Commit graph

4 commits

Author SHA1 Message Date
Sven Eckelmann
b1d57dadb2 ar71xx: disable 40Mhz refclk for QCA953x
The "QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms"
datasheet (80-Y7991-1 Rev. C - October 2014) doesn't specify support for a
40 Mhz reference clock. The register description for "Bootstrap Options"
(page 31) defines following states for the bit 4 (REF_CLK):

* 0 - CLK25 (default)
* 1 - (reserved)

Devices like the TP-Link CPE210 v2 has this bit set to 1 but is using a 25
Mhz reference clock. OpenWrt is still interpreted this bit as 40 Mhz and
then break the bootup of the system due to this incorrect interpretation.

Signed-off-by: Sven Eckelmann <sven@narfation.org>
[refreshed patches]
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
2018-02-22 18:53:22 +01:00
Stijn Tintel
f80963d4d1 kernel: update kernel 4.4 to 4.4.74
Refresh patches.
Compile-tested on ar71xx.
Runtime-tested on ar71xx.

Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
2017-06-27 07:42:50 +02:00
Felix Fietkau
837285b832 ar71xx: fold 641-MIPS-ath79-fix-AR934x-OTP-offsets.patch into the patch that it fixes
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2017-04-26 10:29:45 +02:00
Felix Fietkau
2530640f07 ar71xx: add support for linux 4.4
Signed-off-by: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 48563
2016-01-30 13:19:53 +00:00