DB149 is a IPQ8064 based platform. This patch adds the init scripts to
detect it, configure the network accordingly, and generate a flashable
image for it.
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
SVN-Revision: 45537
DB149 is an IPQ806x based development platform. This patch adds the dts
files to support it.
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
SVN-Revision: 45536
Certain IPQ806x based platforms are making use of this PHY. So we'll
enable it so it gets detected as such.
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
SVN-Revision: 45535
-removed symbol because it should be handled by wpan.mk
-add missing FAKEHARD symbol (this symbol is removed in Kernel 4.0)
Signed-off-by: Dirk Neukirchen <dirkneukirchen@web.de>
SVN-Revision: 45530
It was reported that OM5P-AN needs not only a delay setting of 1 for RXD/RDV
but 2. These was found when testing with a NetGear GS752TP POE switch with a
cable length of 50ft and 250ft.
Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
SVN-Revision: 45524
The ETH_RXDV_DELAY (17:16) and ETH_RXD_DELAY (15:14) are currently not cleared
by the function ath79_setup_ar934x_eth_cfg. Clearing these in the
ath79_setup_ar934x_eth_cfg may cause problems on some hardware because they
rely on the preset value by the bootloader.
Instead another function is introduced which also works on ETH_CFG on AR934x.
It can be used to safely clear and set ETH_RXDV_DELAY and ETH_RXD_DELAY on
machines which require special settings.
Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
SVN-Revision: 45523
The commit r38948 ("ag71xx: add F1E specific feature bit definitions to AR934X
register file") introduced definitions for some bits in the RDV/RXD part of the
ETH_CFG register of AR934x. These are incomplete because ETH_RXDV_DELAY is
specified as 17:16 and ETH_RXD_DELAY is specified 15:14. The original commit
only specified the lower bits. The upper bits also have to be unset when the
lower bits should only be set.
Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
SVN-Revision: 45522
The tx/rx delay bits in the ETH_XMII_CONTROL register have to be unset when the
enable_rgmii_rx_delay/enable_rgmii_tx_delay will be set in the AT803x PHY.
Othwise the throughput in gigabit mode is heavily reduced.
Signed-off-by: Sven Eckelmann <sven@open-mesh.org>
SVN-Revision: 45521
Profile definitions need to be checked and fixed before this patch can
be applied again.
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45511
Refresh patches to remove the trailing whitespaces caused by an old
diffutils version on osx.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45506
This should rather be done by passing appropriate platform_data/OF, but
should suffice for now.
Fixes e.g. GbE ports on BCM963268BU_P300.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45505
At least the third rgmii port is available on 63169, so assume all are
available. Simplifies cpu vs. variant handling.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45504
The new building code included the rootfs twice when building tplink initramfs images.
To make it more readable move initramfs into an own build step
Build/mktplinkfw-initramfs.
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
SVN-Revision: 45491
The new image size is verified by a running tplink device and checked
against mktplinkfw source code.
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
SVN-Revision: 45488
The mips74k subtarget of brcm47xx configures gcc to compile for mips32r2;
however, the generated kernel config for 3.14 and later kernels ends up
with CPU_MIPS32_R1 and CPU_MIPSR1 selected. The generated kernel config
for the 3.10 kernel (Barrier Breaker) properly selected CPU_MIPS32_R2 and
CPU_MIPSR2. Modify the default kernel config for mips74k to explicitly
select CPU_MIPS32_R2 and CPU_MIPSR2.
Signed-off-by: Nathan Hintz <nlhintz@hotmail.com>
Tested-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 45469
Open-Mesh OM5P-AN use a AT8035 (F1E) behind one of the ethernet ports. This PHY
requires special flags to work correctly. Otherwise massive packet loss happens
with active POE or when switching the link speed from gigabit ethernet to fast
ethernet. The generic PHY doesn't have support to change these settings.
Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
SVN-Revision: 45439
The OM5P-AN boards are suffering from ethernet packet loss when booting with
some active POE setups or when switching to Fast Ethernet when previously
booted with Gigabit ethernet attached.
The cause of the problem is that the AR8035 PHYs requires special register
settings to work reliably on these boards. Enable the RGMII TX, RX delays and
disable SmartEE functionality of the AR8035 PHYs. Also enable the RXD and RDV
delay in the ETH_CFG register to fix the issue.
Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
SVN-Revision: 45438
