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ramips: implement clock API for RT288x

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SVN-Revision: 25125
This commit is contained in:
Gabor Juhos 2011-01-26 20:48:39 +00:00
parent b0ffa70248
commit f38367fcb4
7 changed files with 152 additions and 45 deletions
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6
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x.h
View file

@ -1,7 +1,7 @@
/*
* Ralink RT288x SoC specific definitions
*
* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Parts of this file are based on Ralink's 2.6.21 BSP
@ -18,10 +18,6 @@
#include <linux/io.h>
void rt288x_detect_sys_type(void);
void rt288x_detect_sys_freq(void);
extern unsigned long rt288x_cpu_freq;
extern unsigned long rt288x_sys_freq;
#define RT288X_CPU_IRQ_BASE 0
#define RT288X_INTC_IRQ_BASE 8

2
target/linux/ramips/files/arch/mips/ralink/rt288x/Makefile
View file

@ -9,7 +9,7 @@
# under the terms of the GNU General Public License version 2 as published
# by the Free Software Foundation.
obj-y := irq.o setup.o rt288x.o devices.o
obj-y := irq.o setup.o rt288x.o devices.o clock.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o

99
target/linux/ramips/files/arch/mips/ralink/rt288x/clock.c Normal file
View file

@ -0,0 +1,99 @@
/*
* Ralink RT288X clock API
*
* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <asm/mach-ralink/common.h>
#include <asm/mach-ralink/rt288x.h>
#include <asm/mach-ralink/rt288x_regs.h>
#include "common.h"
struct clk {
unsigned long rate;
};
static struct clk rt288x_cpu_clk;
static struct clk rt288x_sys_clk;
static struct clk rt288x_wdt_clk;
static struct clk rt288x_uart_clk;
void __init rt288x_clocks_init(void)
{
u32 t;
t = rt288x_sysc_rr(SYSC_REG_SYSTEM_CONFIG);
t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
switch (t) {
case SYSTEM_CONFIG_CPUCLK_250:
rt288x_cpu_clk.rate = 250000000;
break;
case SYSTEM_CONFIG_CPUCLK_266:
rt288x_cpu_clk.rate = 266666667;
break;
case SYSTEM_CONFIG_CPUCLK_280:
rt288x_cpu_clk.rate = 280000000;
break;
case SYSTEM_CONFIG_CPUCLK_300:
rt288x_cpu_clk.rate = 300000000;
break;
}
rt288x_sys_clk.rate = rt288x_cpu_clk.rate / 2;
rt288x_uart_clk.rate = rt288x_sys_clk.rate;
rt288x_wdt_clk.rate = rt288x_sys_clk.rate;
}
/*
* Linux clock API
*/
struct clk *clk_get(struct device *dev, const char *id)
{
if (!strcmp(id, "sys"))
return &rt288x_sys_clk;
if (!strcmp(id, "cpu"))
return &rt288x_cpu_clk;
if (!strcmp(id, "wdt"))
return &rt288x_wdt_clk;
if (!strcmp(id, "uart"))
return &rt288x_uart_clk;
return ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL(clk_get);
int clk_enable(struct clk *clk)
{
return 0;
}
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
return clk->rate;
}
EXPORT_SYMBOL(clk_get_rate);
void clk_put(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_put);

16
target/linux/ramips/files/arch/mips/ralink/rt288x/common.h Normal file
View file

@ -0,0 +1,16 @@
/*
* Ralink RT288X SoC common defines
*
* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef _RT288X_COMMON_H
#define _RT288X_COMMON_H
void rt288x_clocks_init(void);
#endif /* _RT288X_COMMON_H */

12
target/linux/ramips/files/arch/mips/ralink/rt288x/devices.c
View file

@ -1,7 +1,7 @@
/*
* Ralink RT288x SoC platform device registration
*
* Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
@ -14,6 +14,8 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/physmap.h>
#include <linux/etherdevice.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <asm/addrspace.h>
@ -154,7 +156,13 @@ static struct platform_device rt288x_eth_device = {
void __init rt288x_register_ethernet(void)
{
rt288x_eth_data.sys_freq = rt288x_sys_freq;
struct clk *clk;
clk = clk_get(NULL, "sys");
if (IS_ERR(clk))
panic("unable to get SYS clock, err=%ld", PTR_ERR(clk));
rt288x_eth_data.sys_freq = clk_get_rate(clk);
rt288x_eth_data.reset_fe = rt288x_fe_reset;
rt288x_eth_data.min_pkt_len = 64;

31
target/linux/ramips/files/arch/mips/ralink/rt288x/rt288x.c
View file

@ -20,12 +20,6 @@
#include <asm/mach-ralink/rt288x.h>
#include <asm/mach-ralink/rt288x_regs.h>
unsigned long rt288x_cpu_freq;
EXPORT_SYMBOL_GPL(rt288x_cpu_freq);
unsigned long rt288x_sys_freq;
EXPORT_SYMBOL_GPL(rt288x_sys_freq);
void __iomem * rt288x_sysc_base;
void __iomem * rt288x_memc_base;
@ -49,31 +43,6 @@ void __init rt288x_detect_sys_type(void)
(id & CHIP_ID_REV_MASK));
}
void __init rt288x_detect_sys_freq(void)
{
u32 t;
t = rt288x_sysc_rr(SYSC_REG_SYSTEM_CONFIG);
t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
switch (t) {
case SYSTEM_CONFIG_CPUCLK_250:
rt288x_cpu_freq = 250000000;
break;
case SYSTEM_CONFIG_CPUCLK_266:
rt288x_cpu_freq = 266666667;
break;
case SYSTEM_CONFIG_CPUCLK_280:
rt288x_cpu_freq = 280000000;
break;
case SYSTEM_CONFIG_CPUCLK_300:
rt288x_cpu_freq = 300000000;
break;
}
rt288x_sys_freq = rt288x_cpu_freq / 2;
}
static void rt288x_gpio_reserve(int first, int last)
{
for (; first <= last; first++)

31
target/linux/ramips/files/arch/mips/ralink/rt288x/setup.c
View file

@ -14,6 +14,8 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <asm/mips_machine.h>
#include <asm/reboot.h>
@ -22,6 +24,7 @@
#include <asm/mach-ralink/common.h>
#include <asm/mach-ralink/rt288x.h>
#include <asm/mach-ralink/rt288x_regs.h>
#include "common.h"
static void rt288x_restart(char *command)
{
@ -44,27 +47,43 @@ unsigned int __cpuinit get_c0_compare_irq(void)
void __init ramips_soc_setup(void)
{
struct clk *clk;
rt288x_sysc_base = ioremap_nocache(RT2880_SYSC_BASE, RT2880_SYSC_SIZE);
rt288x_memc_base = ioremap_nocache(RT2880_MEMC_BASE, RT2880_MEMC_SIZE);
rt288x_detect_sys_type();
rt288x_detect_sys_freq();
rt288x_clocks_init();
clk = clk_get(NULL, "cpu");
if (IS_ERR(clk))
panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
printk(KERN_INFO "%s running at %lu.%02lu MHz\n", ramips_sys_type,
rt288x_cpu_freq / 1000000,
(rt288x_cpu_freq % 1000000) * 100 / 1000000);
clk_get_rate(clk) / 1000000,
(clk_get_rate(clk) % 1000000) * 100 / 1000000);
_machine_restart = rt288x_restart;
_machine_halt = rt288x_halt;
pm_power_off = rt288x_halt;
ramips_early_serial_setup(0, RT2880_UART0_BASE, rt288x_sys_freq,
clk = clk_get(NULL, "uart");
if (IS_ERR(clk))
panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
ramips_early_serial_setup(0, RT2880_UART0_BASE, clk_get_rate(clk),
RT2880_INTC_IRQ_UART0);
ramips_early_serial_setup(1, RT2880_UART1_BASE, rt288x_sys_freq,
ramips_early_serial_setup(1, RT2880_UART1_BASE, clk_get_rate(clk),
RT2880_INTC_IRQ_UART1);
}
void __init plat_time_init(void)
{
mips_hpt_frequency = rt288x_cpu_freq / 2;
struct clk *clk;
clk = clk_get(NULL, "cpu");
if (IS_ERR(clk))
panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
mips_hpt_frequency = clk_get_rate(clk) / 2;
}