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lantiq: fix ath_pci_fixup hang on bridged devices

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Port of r41856.

In contrast to the brcm63xx target, it isn't sufficient to enable/disable
the bridge. The device needs to be enabled/disabled to fix the hang. The
bridge will be automatically enabled by the time the connected device is
enabled.

Fixes boot on TD-W8980.

Signed-off-by: Mathias Kresin <openwrt@kresin.me>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 47129
This commit is contained in:
John Crispin 2015-10-05 10:28:12 +00:00
parent c5cc3d9610
commit f2f50ad762
2 changed files with 20 additions and 2 deletions
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11
target/linux/lantiq/patches-3.18/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch
View file

@ -415,7 +415,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+device_initcall(of_eth_mac_init); +device_initcall(of_eth_mac_init);
--- /dev/null --- /dev/null
+++ b/arch/mips/lantiq/xway/pci-ath-fixup.c +++ b/arch/mips/lantiq/xway/pci-ath-fixup.c
@@ -0,0 +1,109 @@ @@ -0,0 +1,118 @@
+/* +/*
+ * Atheros AP94 reference board PCI initialization + * Atheros AP94 reference board PCI initialization
+ * + *
@ -442,6 +442,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+static void ath_pci_fixup(struct pci_dev *dev) +static void ath_pci_fixup(struct pci_dev *dev)
+{ +{
+ void __iomem *mem; + void __iomem *mem;
+ struct pci_dev *bridge = pci_upstream_bridge(dev);
+ u16 *cal_data = NULL; + u16 *cal_data = NULL;
+ u16 cmd; + u16 cmd;
+ u32 bar0; + u32 bar0;
@ -477,6 +478,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ return; + return;
+ } + }
+ +
+ if (bridge) {
+ pci_enable_device(dev);
+ }
+
+ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, base); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, base);
+ pci_read_config_word(dev, PCI_COMMAND, &cmd); + pci_read_config_word(dev, PCI_COMMAND, &cmd);
@ -512,6 +517,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ +
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
+ +
+ if (bridge) {
+ pci_disable_device(dev);
+ }
+
+ iounmap(mem); + iounmap(mem);
+} +}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath_pci_fixup); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath_pci_fixup);

11
target/linux/lantiq/patches-4.1/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch
View file

@ -415,7 +415,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+device_initcall(of_eth_mac_init); +device_initcall(of_eth_mac_init);
--- /dev/null --- /dev/null
+++ b/arch/mips/lantiq/xway/pci-ath-fixup.c +++ b/arch/mips/lantiq/xway/pci-ath-fixup.c
@@ -0,0 +1,109 @@ @@ -0,0 +1,118 @@
+/* +/*
+ * Atheros AP94 reference board PCI initialization + * Atheros AP94 reference board PCI initialization
+ * + *
@ -442,6 +442,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+static void ath_pci_fixup(struct pci_dev *dev) +static void ath_pci_fixup(struct pci_dev *dev)
+{ +{
+ void __iomem *mem; + void __iomem *mem;
+ struct pci_dev *bridge = pci_upstream_bridge(dev);
+ u16 *cal_data = NULL; + u16 *cal_data = NULL;
+ u16 cmd; + u16 cmd;
+ u32 bar0; + u32 bar0;
@ -477,6 +478,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ return; + return;
+ } + }
+ +
+ if (bridge) {
+ pci_enable_device(dev);
+ }
+
+ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, base); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, base);
+ pci_read_config_word(dev, PCI_COMMAND, &cmd); + pci_read_config_word(dev, PCI_COMMAND, &cmd);
@ -512,6 +517,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ +
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
+ +
+ if (bridge) {
+ pci_disable_device(dev);
+ }
+
+ iounmap(mem); + iounmap(mem);
+} +}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath_pci_fixup); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath_pci_fixup);