From f025215422689dbbcf65d8366f3fad3bec58cad4 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Sat, 13 Jun 2009 20:36:48 +0000 Subject: [PATCH] also apply gcc4.4.0 specific patches to 2.6.27 (#5318) SVN-Revision: 16439 --- .../022-mips_div64_gcc4.4.0.patch | 171 ++++++++++++++++++ .../023-mips_delay_gcc4.4.0.patch | 163 +++++++++++++++++ 2 files changed, 334 insertions(+) create mode 100644 target/linux/generic-2.6/patches-2.6.27/022-mips_div64_gcc4.4.0.patch create mode 100644 target/linux/generic-2.6/patches-2.6.27/023-mips_delay_gcc4.4.0.patch diff --git a/target/linux/generic-2.6/patches-2.6.27/022-mips_div64_gcc4.4.0.patch b/target/linux/generic-2.6/patches-2.6.27/022-mips_div64_gcc4.4.0.patch new file mode 100644 index 0000000000..c01765d8f1 --- /dev/null +++ b/target/linux/generic-2.6/patches-2.6.27/022-mips_div64_gcc4.4.0.patch @@ -0,0 +1,171 @@ +From: Ralf Baechle +Date: Thu, 30 Apr 2009 16:14:56 +0000 (+0200) +Subject: MIPS: Rewrite to work with gcc 4.4.0. +X-Git-Url: http://www.linux-mips.org/git?p=linux.git;a=commitdiff_plain;h=a1b68289997030df64cba8478d5767fe10e42a58 + +MIPS: Rewrite to work with gcc 4.4.0. + +The inline assembler used on 32-bit kernels was using the "h" constraint +which was considered dangerous and removed for gcc 4.4.0. + +Signed-off-by: Ralf Baechle +--- + +--- a/include/asm-mips/div64.h ++++ b/include/asm-mips/div64.h +@@ -6,105 +6,63 @@ + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +-#ifndef _ASM_DIV64_H +-#define _ASM_DIV64_H ++#ifndef __ASM_DIV64_H ++#define __ASM_DIV64_H + +-#include ++#include + +-#if (_MIPS_SZLONG == 32) ++#if BITS_PER_LONG == 64 + +-#include ++#include + + /* + * No traps on overflows for any of these... + */ + +-#define do_div64_32(res, high, low, base) ({ \ +- unsigned long __quot32, __mod32; \ +- unsigned long __cf, __tmp, __tmp2, __i; \ +- \ +- __asm__(".set push\n\t" \ +- ".set noat\n\t" \ +- ".set noreorder\n\t" \ +- "move %2, $0\n\t" \ +- "move %3, $0\n\t" \ +- "b 1f\n\t" \ +- " li %4, 0x21\n" \ +- "0:\n\t" \ +- "sll $1, %0, 0x1\n\t" \ +- "srl %3, %0, 0x1f\n\t" \ +- "or %0, $1, %5\n\t" \ +- "sll %1, %1, 0x1\n\t" \ +- "sll %2, %2, 0x1\n" \ +- "1:\n\t" \ +- "bnez %3, 2f\n\t" \ +- " sltu %5, %0, %z6\n\t" \ +- "bnez %5, 3f\n" \ +- "2:\n\t" \ +- " addiu %4, %4, -1\n\t" \ +- "subu %0, %0, %z6\n\t" \ +- "addiu %2, %2, 1\n" \ +- "3:\n\t" \ +- "bnez %4, 0b\n\t" \ +- " srl %5, %1, 0x1f\n\t" \ +- ".set pop" \ +- : "=&r" (__mod32), "=&r" (__tmp), \ +- "=&r" (__quot32), "=&r" (__cf), \ +- "=&r" (__i), "=&r" (__tmp2) \ +- : "Jr" (base), "0" (high), "1" (low)); \ +- \ +- (res) = __quot32; \ +- __mod32; }) +- +-#define do_div(n, base) ({ \ +- unsigned long long __quot; \ +- unsigned long __mod; \ +- unsigned long long __div; \ +- unsigned long __upper, __low, __high, __base; \ +- \ +- __div = (n); \ +- __base = (base); \ +- \ +- __high = __div >> 32; \ +- __low = __div; \ +- __upper = __high; \ +- \ +- if (__high) \ +- __asm__("divu $0, %z2, %z3" \ +- : "=h" (__upper), "=l" (__high) \ +- : "Jr" (__high), "Jr" (__base) \ +- : GCC_REG_ACCUM); \ +- \ +- __mod = do_div64_32(__low, __upper, __low, __base); \ +- \ +- __quot = __high; \ +- __quot = __quot << 32 | __low; \ +- (n) = __quot; \ +- __mod; }) +- +-#endif /* (_MIPS_SZLONG == 32) */ +- +-#if (_MIPS_SZLONG == 64) +- +-/* +- * Hey, we're already 64-bit, no +- * need to play games.. +- */ +-#define do_div(n, base) ({ \ +- unsigned long __quot; \ +- unsigned int __mod; \ +- unsigned long __div; \ +- unsigned int __base; \ +- \ +- __div = (n); \ +- __base = (base); \ +- \ +- __mod = __div % __base; \ +- __quot = __div / __base; \ +- \ +- (n) = __quot; \ +- __mod; }) ++#define __div64_32(n, base) \ ++({ \ ++ unsigned long __cf, __tmp, __tmp2, __i; \ ++ unsigned long __quot32, __mod32; \ ++ unsigned long __high, __low; \ ++ unsigned long long __n; \ ++ \ ++ __high = *__n >> 32; \ ++ __low = __n; \ ++ __asm__( \ ++ " .set push \n" \ ++ " .set noat \n" \ ++ " .set noreorder \n" \ ++ " move %2, $0 \n" \ ++ " move %3, $0 \n" \ ++ " b 1f \n" \ ++ " li %4, 0x21 \n" \ ++ "0: \n" \ ++ " sll $1, %0, 0x1 \n" \ ++ " srl %3, %0, 0x1f \n" \ ++ " or %0, $1, %5 \n" \ ++ " sll %1, %1, 0x1 \n" \ ++ " sll %2, %2, 0x1 \n" \ ++ "1: \n" \ ++ " bnez %3, 2f \n" \ ++ " sltu %5, %0, %z6 \n" \ ++ " bnez %5, 3f \n" \ ++ "2: \n" \ ++ " addiu %4, %4, -1 \n" \ ++ " subu %0, %0, %z6 \n" \ ++ " addiu %2, %2, 1 \n" \ ++ "3: \n" \ ++ " bnez %4, 0b\n\t" \ ++ " srl %5, %1, 0x1f\n\t" \ ++ " .set pop" \ ++ : "=&r" (__mod32), "=&r" (__tmp), \ ++ "=&r" (__quot32), "=&r" (__cf), \ ++ "=&r" (__i), "=&r" (__tmp2) \ ++ : "Jr" (base), "0" (__high), "1" (__low)); \ ++ \ ++ (__n) = __quot32; \ ++ __mod32; \ ++}) + +-#endif /* (_MIPS_SZLONG == 64) */ ++#endif /* BITS_PER_LONG == 64 */ + +-#endif /* _ASM_DIV64_H */ ++#endif /* __ASM_DIV64_H */ diff --git a/target/linux/generic-2.6/patches-2.6.27/023-mips_delay_gcc4.4.0.patch b/target/linux/generic-2.6/patches-2.6.27/023-mips_delay_gcc4.4.0.patch new file mode 100644 index 0000000000..f001b81e10 --- /dev/null +++ b/target/linux/generic-2.6/patches-2.6.27/023-mips_delay_gcc4.4.0.patch @@ -0,0 +1,163 @@ +From: Wu Zhangjin + +the gcc 4.4 support for MIPS mostly refer to this PATCH: +http://www.nabble.com/-PATCH--MIPS:-Handle-removal-of-%27h%27-constraint-in-GCC-4.4-td22192768.html +but have been tuned a little. + +because only gcc 4.4 have loongson-specific support, so, we need to +choose the suitable -march argument for gcc <= 4.3 and gcc >= 4.4, and +we also need to consider use -march=loongson2e and -march=loongson2f for +loongson2e and loongson2f respectively. this is handled by adding two +new kernel options: CPU_LOONGSON2E and CPU_LOONGSON2F(thanks for the +solutin provided by ZhangLe). + +I have tested it on FuLoong(2f) in 32bit and 64bit with gcc-4.4 and +gcc-4.3. so, basically, it works. + +Signed-off-by: Wu Zhangjin +--- + arch/mips/Makefile | 9 +++++- + arch/mips/include/asm/compiler.h | 10 ++++++ + arch/mips/include/asm/delay.h | 58 +++++++++++++++++++++++++------------ + 3 files changed, 57 insertions(+), 20 deletions(-) + +diff --git a/arch/mips/Makefile b/arch/mips/Makefile +index a25c2e5..1ee5504 100644 +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -120,7 +120,14 @@ cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap + cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap + cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap + cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap +-cflags-$(CONFIG_CPU_LOONGSON2) += -march=r4600 -Wa,--trap ++ ++# only gcc >= 4.4 have the loongson-specific support ++cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap ++cflags-$(CONFIG_CPU_LOONGSON2E) += $(shell if [ $(call cc-version) -lt 0440 ] ; then \ ++ echo $(call cc-option,-march=r4600); else echo $(call cc-option,-march=loongson2e); fi ;) ++cflags-$(CONFIG_CPU_LOONGSON2F) += $(shell if [ $(call cc-version) -lt 0440 ] ; then \ ++ echo $(call cc-option,-march=r4600); else echo $(call cc-option,-march=loongson2f); fi ;) ++ + cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ + -Wa,-mips32 -Wa,--trap + cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ +diff --git a/include/asm-mips/compiler.h b/include/asm-mips/compiler.h +index 71f5c5c..95256a8 100644 +--- a/include/asm-mips/compiler.h ++++ b/include/asm-mips/compiler.h +@@ -1,5 +1,6 @@ + /* + * Copyright (C) 2004, 2007 Maciej W. Rozycki ++ * Copyright (C) 2009 Wu Zhangjin, wuzj@lemote.com + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive +@@ -16,4 +17,13 @@ + #define GCC_REG_ACCUM "accum" + #endif + ++#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 4) ++#define GCC_NO_H_CONSTRAINT ++#ifdef CONFIG_64BIT ++typedef unsigned int uintx_t __attribute__((mode(TI))); ++#else ++typedef u64 uintx_t; ++#endif ++#endif ++ + #endif /* _ASM_COMPILER_H */ +diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h +index b0bccd2..00d7969 100644 +--- a/include/asm-mips/delay.h ++++ b/include/asm-mips/delay.h +@@ -7,6 +7,7 @@ + * Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * Copyright (C) 2007 Maciej W. Rozycki ++ * Copyright (C) 2009 Wu Zhangjin, wuzj@lemote.com + */ + #ifndef _ASM_DELAY_H + #define _ASM_DELAY_H +@@ -48,6 +49,43 @@ static inline void __delay(unsigned long loops) + : "0" (loops), "r" (1)); + } + ++/* ++ * convert usecs to loops ++ * ++ * handle removal of 'h' constraint in GCC 4.4 ++ */ ++ ++#ifndef GCC_NO_H_CONSTRAINT /* gcc <= 4.3 */ ++static inline unsigned long __usecs_to_loops(unsigned long usecs, ++ unsigned long lpj) ++{ ++ unsigned long hi, lo; ++ ++ if (sizeof(long) == 4) ++ __asm__("multu\t%2, %3" ++ : "=h" (usecs), "=l" (lo) ++ : "r" (usecs), "r" (lpj) ++ : GCC_REG_ACCUM); ++ else if (sizeof(long) == 8 && !R4000_WAR) ++ __asm__("dmultu\t%2, %3" ++ : "=h" (usecs), "=l" (lo) ++ : "r" (usecs), "r" (lpj) ++ : GCC_REG_ACCUM); ++ else if (sizeof(long) == 8 && R4000_WAR) ++ __asm__("dmultu\t%3, %4\n\tmfhi\t%0" ++ : "=r" (usecs), "=h" (hi), "=l" (lo) ++ : "r" (usecs), "r" (lpj) ++ : GCC_REG_ACCUM); ++ ++ return usecs; ++} ++#else /* GCC_NO_H_CONSTRAINT, gcc >= 4.4 */ ++static inline unsigned long __usecs_to_loops(unsigned long usecs, ++ unsigned long lpj) ++{ ++ return ((uintx_t)usecs * lpj) >> BITS_PER_LONG; ++} ++#endif + + /* + * Division by multiplication: you don't have to worry about +@@ -62,8 +100,6 @@ static inline void __delay(unsigned long loops) + + static inline void __udelay(unsigned long usecs, unsigned long lpj) + { +- unsigned long hi, lo; +- + /* + * The rates of 128 is rounded wrongly by the catchall case + * for 64-bit. Excessive precission? Probably ... +@@ -77,23 +113,7 @@ static inline void __udelay(unsigned long usecs, unsigned long lpj) + 0x80000000ULL) >> 32); + #endif + +- if (sizeof(long) == 4) +- __asm__("multu\t%2, %3" +- : "=h" (usecs), "=l" (lo) +- : "r" (usecs), "r" (lpj) +- : GCC_REG_ACCUM); +- else if (sizeof(long) == 8 && !R4000_WAR) +- __asm__("dmultu\t%2, %3" +- : "=h" (usecs), "=l" (lo) +- : "r" (usecs), "r" (lpj) +- : GCC_REG_ACCUM); +- else if (sizeof(long) == 8 && R4000_WAR) +- __asm__("dmultu\t%3, %4\n\tmfhi\t%0" +- : "=r" (usecs), "=h" (hi), "=l" (lo) +- : "r" (usecs), "r" (lpj) +- : GCC_REG_ACCUM); +- +- __delay(usecs); ++ __delay(__usecs_to_loops(usecs, lpj)); + } + + #define __udelay_val cpu_data[raw_smp_processor_id()].udelay_val +-- +1.6.0.4 + + +