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GPIO code updates, make the cf-mips driver compile against this gpio version

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SVN-Revision: 10768
This commit is contained in:
Florian Fainelli 2008-04-07 21:49:05 +00:00
parent 5798590c7c
commit d835b0e42e
4 changed files with 103 additions and 163 deletions
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91
target/linux/rb532/files/arch/mips/rb500/gpio.c
View file

@ -39,11 +39,11 @@
#include <asm/rc32434/rb.h>
#define GPIO_BADDR 0xb8050000
#define GPIO_BADDR 0x18050000
static volatile unsigned char *devCtl3Base;
static unsigned char latchU5State;
static spinlock_t clu5Lock = SPIN_LOCK_UNLOCKED;
static spinlock_t clu5Lock;
struct rb500_gpio_reg __iomem *rb500_gpio_reg0;
EXPORT_SYMBOL(rb500_gpio_reg0);
@ -73,7 +73,6 @@ void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val)
*(volatile unsigned *) (IDT434_REG_BASE + regOffs) = data;
spin_unlock_irqrestore(&clu5Lock, flags);
}
EXPORT_SYMBOL(set434Reg);
void changeLatchU5(unsigned char orMask, unsigned char nandMask)
@ -89,66 +88,105 @@ void changeLatchU5(unsigned char orMask, unsigned char nandMask)
*devCtl3Base = latchU5State;
spin_unlock_irqrestore(&clu5Lock, flags);
}
EXPORT_SYMBOL(changeLatchU5);
unsigned char getLatchU5State(void)
{
return latchU5State;
}
EXPORT_SYMBOL(getLatchU5State);
int rb500_gpio_get_value(unsigned gpio)
{
u32 reg;
reg = readl(&rb500_gpio_reg0->gpiod);
return (reg & (1 << gpio));
return readl(&rb500_gpio_reg0->gpiod) & (1 << gpio);
}
EXPORT_SYMBOL(rb500_gpio_get_value);
void rb500_gpio_set_value(unsigned gpio, int value)
{
u32 reg;
unsigned tmp;
reg = (u32)&rb500_gpio_reg0->gpiod;
tmp = readl(&rb500_gpio_reg0->gpiod) & ~(1 << gpio);
if (value)
tmp |= 1 << gpio;
writel(value, (void *)(reg & (1 << gpio)));
writel(tmp, (void *)&rb500_gpio_reg0->gpiod);
}
EXPORT_SYMBOL(rb500_gpio_set_value);
int rb500_gpio_direction_input(unsigned gpio)
{
u32 reg;
reg = (u32)&rb500_gpio_reg0->gpiocfg;
writel(0, (void *)(reg & (1 << gpio)));
writel(readl(&rb500_gpio_reg0->gpiocfg) | (1 << gpio), (void *)&rb500_gpio_reg0->gpiocfg);
return 0;
}
EXPORT_SYMBOL(rb500_gpio_direction_input);
int rb500_gpio_direction_output(unsigned gpio, int value)
{
u32 reg;
reg = (u32)&rb500_gpio_reg0->gpiocfg;
if (value)
writel(1, (void *)(reg & (1 << gpio)));
gpio_set_value(gpio, value);
writel(readl(&rb500_gpio_reg0->gpiocfg) & ~(1 << gpio), (void *)&rb500_gpio_reg0->gpiocfg);
return 0;
}
EXPORT_SYMBOL(rb500_gpio_direction_output);
void rb500_gpio_set_int_level(unsigned gpio, int value)
{
unsigned tmp;
tmp = readl(&rb500_gpio_reg0->gpioilevel) & ~(1 << gpio);
if (value)
tmp |= 1 << gpio;
writel(tmp, (void *)&rb500_gpio_reg0->gpioilevel);
}
EXPORT_SYMBOL(rb500_gpio_set_int_level);
int rb500_gpio_get_int_level(unsigned gpio)
{
return readl(&rb500_gpio_reg0->gpioilevel) & (1 << gpio);
}
EXPORT_SYMBOL(rb500_gpio_get_int_level);
void rb500_gpio_set_int_status(unsigned gpio, int value)
{
unsigned tmp;
tmp = readl(&rb500_gpio_reg0->gpioistat);
if (value)
tmp |= 1 << gpio;
writel(tmp, (void *)&rb500_gpio_reg0->gpioistat);
}
EXPORT_SYMBOL(rb500_gpio_set_int_status);
int rb500_gpio_get_int_status(unsigned gpio)
{
return readl(&rb500_gpio_reg0->gpioistat) & (1 << gpio);
}
EXPORT_SYMBOL(rb500_gpio_get_int_status);
void rb500_gpio_set_func(unsigned gpio, int value)
{
unsigned tmp;
tmp = readl(&rb500_gpio_reg0->gpiofunc);
if (value)
tmp |= 1 << gpio;
writel(tmp, (void *)&rb500_gpio_reg0->gpiofunc);
}
EXPORT_SYMBOL(rb500_gpio_set_func);
int rb500_gpio_get_func(unsigned gpio)
{
return readl(&rb500_gpio_reg0->gpiofunc) & (1 << gpio);
}
EXPORT_SYMBOL(rb500_gpio_get_func);
int __init rb500_gpio_init(void)
{
rb500_gpio_reg0 = ioremap_nocache(rb500_gpio_reg0_res[0].start,
rb500_gpio_reg0_res[0].end - rb500_gpio_reg0_res[0].start);
rb500_gpio_reg0_res[0].end -
rb500_gpio_reg0_res[0].start);
if (!rb500_gpio_reg0) {
printk(KERN_ERR "rb500: cannot remap GPIO register 0\n");
@ -157,3 +195,4 @@ int __init rb500_gpio_init(void)
return 0;
}
arch_initcall(rb500_gpio_init);

30
target/linux/rb532/files/drivers/block/rb500/ata.c
View file

@ -15,6 +15,8 @@
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/ioport.h> /* request_mem_region() */
#include <asm/gpio.h>
#include <asm/unaligned.h> /* ioremap() */
#include <asm/io.h> /* ioremap() */
#include <asm/rc32434/rb.h>
@ -55,25 +57,15 @@ static inline u8 rareg(unsigned reg, struct cf_mips_dev* dev)
return readb(dev->baddr + ATA_REG_OFFSET + reg);
}
static inline int get_gpio_bit(gpio_func ofs, struct cf_mips_dev *dev)
{
return (gpio_get(ofs) >> dev->pin) & 1;
}
static inline void set_gpio_bit(int bit, gpio_func ofs, struct cf_mips_dev *dev)
{
gpio_set(ofs, (1 << dev->pin), ((bit & 1) << dev->pin));
}
static inline int cfrdy(struct cf_mips_dev *dev)
{
return get_gpio_bit(DATA, dev);
return gpio_get_value(dev->pin);
}
static inline void prepare_cf_irq(struct cf_mips_dev *dev)
{
set_gpio_bit(1, ILEVEL, dev); /* interrupt on cf ready (not busy) */
set_gpio_bit(0, ISTAT, dev); /* clear interrupt status */
rb500_gpio_set_int_level(1, dev->pin); /* interrupt on cf ready (not busy) */
rb500_gpio_set_int_status(0, dev->pin); /* clear interrupt status */
}
static inline int cf_present(struct cf_mips_dev* dev)
@ -85,8 +77,8 @@ static inline int cf_present(struct cf_mips_dev* dev)
int i;
/* setup CFRDY GPIO as input */
set_gpio_bit(0, FUNC, dev);
set_gpio_bit(0, CFG, dev);
rb500_gpio_set_func(dev->pin, 0);
gpio_direction_input(dev->pin);
for (i = 0; i < 0x10; ++i) {
if (rareg(i,dev) != 0xff)
@ -151,9 +143,9 @@ static irqreturn_t cf_irq_handler(int irq, void *dev_id)
* To avoid this, we change ILEVEL to 0.
*/
struct cf_mips_dev *dev=dev_id;
set_gpio_bit(0, ILEVEL, dev);
set_gpio_bit(0, ISTAT, dev);
rb500_gpio_set_int_level(0, dev->pin);
rb500_gpio_set_int_status(0, dev->pin);
del_timer(&dev->to_timer);
tasklet_schedule(&dev->tasklet);
@ -393,7 +385,7 @@ static int do_identify(struct cf_mips_dev *dev)
tstr[16]=0;
printk(KERN_INFO "cf-mips: %s detected, C/H/S=%d/%d/%d sectors=%u (%uMB) Serial=%s\n",
(sbuf[0] == 0x848A ? "CF card" : "ATA drive"), dev->cyl, dev->head,
dev->spt, dev->sectors, dev->sectors >> 11,tstr);
dev->spt, dev->sectors, dev->sectors >> 11, tstr);
return 1;
}

3
target/linux/rb532/files/drivers/block/rb500/bdev.c
View file

@ -23,6 +23,7 @@
#include <asm/uaccess.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/rc32434/rb.h>
@ -242,7 +243,7 @@ static int cf_open(struct inode *inode, struct file *filp)
/* dirty workaround to set CFRDY GPIO as an input when some other
program sets it as an output */
gpio_set(CFG, (1 << dev->pin), 0);
gpio_set_value(dev->pin, 0);
return 0; /* success */
}

142
target/linux/rb532/files/include/asm-mips/rc32434/gpio.h
View file

@ -37,132 +37,40 @@ struct rb500_gpio_reg {
u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
};
enum gpio_regs
{
GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
GPIO_alt_v = 1, // gpiofunc use pin as alt.
GPIO_input_v = 0, // gpiocfg use pin as input.
GPIO_output_v = 1, // gpiocfg use pin as output.
GPIO_pin0_b = 0,
GPIO_pin0_m = 0x00000001,
GPIO_pin1_b = 1,
GPIO_pin1_m = 0x00000002,
GPIO_pin2_b = 2,
GPIO_pin2_m = 0x00000004,
GPIO_pin3_b = 3,
GPIO_pin3_m = 0x00000008,
GPIO_pin4_b = 4,
GPIO_pin4_m = 0x00000010,
GPIO_pin5_b = 5,
GPIO_pin5_m = 0x00000020,
GPIO_pin6_b = 6,
GPIO_pin6_m = 0x00000040,
GPIO_pin7_b = 7,
GPIO_pin7_m = 0x00000080,
GPIO_pin8_b = 8,
GPIO_pin8_m = 0x00000100,
GPIO_pin9_b = 9,
GPIO_pin9_m = 0x00000200,
GPIO_pin10_b = 10,
GPIO_pin10_m = 0x00000400,
GPIO_pin11_b = 11,
GPIO_pin11_m = 0x00000800,
GPIO_pin12_b = 12,
GPIO_pin12_m = 0x00001000,
GPIO_pin13_b = 13,
GPIO_pin13_m = 0x00002000,
GPIO_pin14_b = 14,
GPIO_pin14_m = 0x00004000,
GPIO_pin15_b = 15,
GPIO_pin15_m = 0x00008000,
GPIO_pin16_b = 16,
GPIO_pin16_m = 0x00010000,
GPIO_pin17_b = 17,
GPIO_pin17_m = 0x00020000,
GPIO_pin18_b = 18,
GPIO_pin18_m = 0x00040000,
GPIO_pin19_b = 19,
GPIO_pin19_m = 0x00080000,
GPIO_pin20_b = 20,
GPIO_pin20_m = 0x00100000,
GPIO_pin21_b = 21,
GPIO_pin21_m = 0x00200000,
GPIO_pin22_b = 22,
GPIO_pin22_m = 0x00400000,
GPIO_pin23_b = 23,
GPIO_pin23_m = 0x00800000,
GPIO_pin24_b = 24,
GPIO_pin24_m = 0x01000000,
GPIO_pin25_b = 25,
GPIO_pin25_m = 0x02000000,
GPIO_pin26_b = 26,
GPIO_pin26_m = 0x04000000,
GPIO_pin27_b = 27,
GPIO_pin27_m = 0x08000000,
GPIO_pin28_b = 28,
GPIO_pin28_m = 0x10000000,
GPIO_pin29_b = 29,
GPIO_pin29_m = 0x20000000,
GPIO_pin30_b = 30,
GPIO_pin30_m = 0x40000000,
GPIO_pin31_b = 31,
GPIO_pin31_m = 0x80000000,
/* UART GPIO signals */
#define RC32434_UART0_SOUT (1 << 0)
#define RC32434_UART0_SIN (1 << 1)
#define RC32434_UART0_RTS (1 << 2)
#define RC32434_UART0_CTS (1 << 3)
// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
/* M & P bus GPIO signals */
#define RC32434_MP_BIT_22 (1 << 4)
#define RC32434_MP_BIT_23 (1 << 5)
#define RC32434_MP_BIT_24 (1 << 6)
#define RC32434_MP_BIT_25 (1 << 7)
GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
GPIO_u0sout_m = GPIO_pin0_m,
GPIO_u0sout_cfg_v = GPIO_output_v,
GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
GPIO_u0sinp_m = GPIO_pin1_m,
GPIO_u0sinp_cfg_v = GPIO_input_v,
GPIO_u0rtsn_b = GPIO_pin2_b, // UART 0 req. to send.
GPIO_u0rtsn_m = GPIO_pin2_m,
GPIO_u0rtsn_cfg_v = GPIO_output_v,
GPIO_u0ctsn_b = GPIO_pin3_b, // UART 0 clear to send.
GPIO_u0ctsn_m = GPIO_pin3_m,
GPIO_u0ctsn_cfg_v = GPIO_input_v,
GPIO_maddr22_b = GPIO_pin4_b, // M&P bus bit 22.
GPIO_maddr22_m = GPIO_pin4_m,
GPIO_maddr22_cfg_v = GPIO_output_v,
/* CPU GPIO signals */
#define RC32434_CPU_GPIO (1 << 8)
GPIO_maddr23_b = GPIO_pin5_b, // M&P bus bit 23.
GPIO_maddr23_m = GPIO_pin5_m,
GPIO_maddr23_cfg_v = GPIO_output_v,
/* Reserved GPIO signals */
#define RC32434_AF_SPARE_6 (1 << 9)
#define RC32434_AF_SPARE_4 (1 << 10)
#define RC32434_AF_SPARE_3 (1 << 11)
#define RC32434_AF_SPARE_2 (1 << 12)
GPIO_maddr24_b = GPIO_pin6_b, // M&P bus bit 24.
GPIO_maddr24_m = GPIO_pin6_m,
GPIO_maddr24_cfg_v = GPIO_output_v,
GPIO_maddr25_b = GPIO_pin7_b, // M&P bus bit 25.
GPIO_maddr25_m = GPIO_pin7_m,
GPIO_maddr25_cfg_v = GPIO_output_v,
GPIO_cpu_b = GPIO_pin8_b, // M&P bus bit 25.
GPIO_cpu_m = GPIO_pin8_m,
GPIO_cpu_cfg_v = GPIO_output_v,
GPIO_afspare6_b = GPIO_pin9_b, // reserved.
GPIO_afspare6_m = GPIO_pin9_m,
GPIO_afspare6_cfg_v = GPIO_input_v,
GPIO_afspare4_b = GPIO_pin10_b, // reserved.
GPIO_afspare4_m = GPIO_pin10_m,
GPIO_afspare4_cfg_v = GPIO_input_v,
GPIO_afspare3_b = GPIO_pin11_b, // reserved.
GPIO_afspare3_m = GPIO_pin11_m,
GPIO_afspare3_cfg_v = GPIO_input_v,
GPIO_afspare2_b = GPIO_pin12_b, // reserved.
GPIO_afspare2_m = GPIO_pin12_m,
GPIO_afspare2_cfg_v = GPIO_input_v,
GPIO_pcimuintn_b = GPIO_pin13_b, // PCI messaging int.
GPIO_pcimuintn_m = GPIO_pin13_m,
GPIO_pcimuintn_cfg_v = GPIO_output_v,
};
/* PCI messaging unit */
#define RC32434_PCI_MSU_GPIO (1 << 13)
extern int rb500_gpio_get_value(unsigned gpio);
extern void rb500_gpio_set_value(unsigned gpio, int value);
extern int rb500_gpio_direction_input(unsigned gpio);
extern int rb500_gpio_direction_output(unsigned gpio, int value);
extern void rb500_gpio_set_int_level(unsigned gpio, int value);
extern int rb500_gpio_get_int_level(unsigned gpio);
extern void rb500_gpio_set_int_status(unsigned gpio, int value);
extern int rb500_gpio_get_int_status(unsigned gpio);
extern void rb500_gpio_set_func(unsigned gpio, int value);
extern int rb500_gpio_get_func(unsigned gpio);
/* Wrappers for the arch-neutral GPIO API */