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ipq806x: add NAND flash controller support

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These patches add support for ipq806x NAND flash controller. Most of
these are cherry-picked & backported from LKML:
*https://lkml.org/lkml/2015/8/3/16

This patch just modifies the kernel code, but doesn't change the config.
It should be harmless.

Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>

SVN-Revision: 46568
This commit is contained in:
Felix Fietkau 2015-08-07 08:36:31 +00:00
parent c7bf2accc9
commit d523866eb3
16 changed files with 4739 additions and 26 deletions
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74
target/linux/ipq806x/patches-3.18/160-clk-qcom-Add-EBI2-clocks-for-IPQ806x.patch Normal file
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@ -0,0 +1,74 @@
From 4c385b25fab119144bffb255ad77712fe586ac10 Mon Sep 17 00:00:00 2001
From: Archit Taneja <architt@codeaurora.org>
Date: Thu, 2 Apr 2015 11:20:41 +0530
Subject: [PATCH] clk: qcom: Add EBI2 clocks for IPQ806x
The NAND controller within EBI2 requires EBI2_CLK and
EBI2_ALWAYS_ON_CLK clocks. Create structs for these clocks so
that they can be used by the NAND controller driver. Add an entry
for EBI2_AON_CLK in the gcc-ipq806x DT binding document.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq806x.c | 32 ++++++++++++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-ipq806x.h | 1 +
2 files changed, 33 insertions(+)
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -2239,6 +2239,36 @@ static struct clk_branch usb_fs1_h_clk =
},
};
+static struct clk_branch ebi2_clk = {
+ .hwcg_reg = 0x3b00,
+ .hwcg_bit = 6,
+ .halt_reg = 0x2fcc,
+ .halt_bit = 1,
+ .clkr = {
+ .enable_reg = 0x3b00,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "ebi2_clk",
+ .ops = &clk_branch_ops,
+ .flags = CLK_IS_ROOT,
+ },
+ },
+};
+
+static struct clk_branch ebi2_aon_clk = {
+ .halt_reg = 0x2fcc,
+ .halt_bit = 0,
+ .clkr = {
+ .enable_reg = 0x3b00,
+ .enable_mask = BIT(8),
+ .hw.init = &(struct clk_init_data){
+ .name = "ebi2_always_on_clk",
+ .ops = &clk_branch_ops,
+ .flags = CLK_IS_ROOT,
+ },
+ },
+};
+
static struct clk_regmap *gcc_ipq806x_clks[] = {
[PLL0] = &pll0.clkr,
[PLL0_VOTE] = &pll0_vote,
@@ -2341,6 +2371,8 @@ static struct clk_regmap *gcc_ipq806x_cl
[USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
[USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
[USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
+ [EBI2_CLK] = &ebi2_clk.clkr,
+ [EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
[PLL9] = &hfpll0.clkr,
[PLL10] = &hfpll1.clkr,
[PLL12] = &hfpll_l2.clkr,
--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
@@ -289,5 +289,6 @@
#define UBI32_CORE2_CLK_SRC 278
#define UBI32_CORE1_CLK 279
#define UBI32_CORE2_CLK 280
+#define EBI2_AON_CLK 281
#endif

84
target/linux/ipq806x/patches-3.18/161-mtd-nand-Create-a-BBT-flag-to-access-bad-block-markers-in-raw-mode.patch Normal file
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Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [v3,
1/5] mtd: nand: Create a BBT flag to access bad block markers in raw
mode
From: Archit Taneja <architt@codeaurora.org>
X-Patchwork-Id: 6927081
Message-Id: <1438578498-32254-2-git-send-email-architt@codeaurora.org>
To: linux-mtd@lists.infradead.org, dehrenberg@google.com,
cernekee@gmail.com, computersforpeace@gmail.com
Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org,
sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
Archit Taneja <architt@codeaurora.org>
Date: Mon, 3 Aug 2015 10:38:14 +0530
Some controllers can access the factory bad block marker from OOB only
when they read it in raw mode. When ECC is enabled, these controllers
discard reading/writing bad block markers, preventing access to them
altogether.
The bbt driver assumes MTD_OPS_PLACE_OOB when scanning for bad blocks.
This results in the nand driver's ecc->read_oob() op to be called, which
works with ECC enabled.
Create a new BBT option flag that tells nand_bbt to force the mode to
MTD_OPS_RAW. This would result in the correct op being called for the
underlying nand controller driver.
Reviewed-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
drivers/mtd/nand/nand_base.c | 6 +++++-
drivers/mtd/nand/nand_bbt.c | 6 +++++-
include/linux/mtd/bbm.h | 7 +++++++
3 files changed, 17 insertions(+), 2 deletions(-)
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -396,7 +396,11 @@ static int nand_default_block_markbad(st
} else {
ops.len = ops.ooblen = 1;
}
- ops.mode = MTD_OPS_PLACE_OOB;
+
+ if (unlikely(chip->bbt_options & NAND_BBT_ACCESS_BBM_RAW))
+ ops.mode = MTD_OPS_RAW;
+ else
+ ops.mode = MTD_OPS_PLACE_OOB;
/* Write to first/last page(s) if necessary */
if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
@@ -423,7 +423,11 @@ static int scan_block_fast(struct mtd_in
ops.oobbuf = buf;
ops.ooboffs = 0;
ops.datbuf = NULL;
- ops.mode = MTD_OPS_PLACE_OOB;
+
+ if (unlikely(bd->options & NAND_BBT_ACCESS_BBM_RAW))
+ ops.mode = MTD_OPS_RAW;
+ else
+ ops.mode = MTD_OPS_PLACE_OOB;
for (j = 0; j < numpages; j++) {
/*
--- a/include/linux/mtd/bbm.h
+++ b/include/linux/mtd/bbm.h
@@ -116,6 +116,13 @@ struct nand_bbt_descr {
#define NAND_BBT_NO_OOB_BBM 0x00080000
/*
+ * Force MTD_OPS_RAW mode when trying to access bad block markes from OOB. To
+ * be used by controllers which can access BBM only when ECC is disabled, i.e,
+ * when in RAW access mode
+ */
+#define NAND_BBT_ACCESS_BBM_RAW 0x00100000
+
+/*
* Flag set by nand_create_default_bbt_descr(), marking that the nand_bbt_descr
* was allocated dynamicaly and must be freed in nand_release(). Has no meaning
* in nand_chip.bbt_options.

2024
target/linux/ipq806x/patches-3.18/162-mtd-nand-Qualcomm-NAND-controller-driver.patch Normal file
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82
target/linux/ipq806x/patches-3.18/163-dt-bindings-qcom_nandc-Add-DT-bindings.patch Normal file
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Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [v3,3/5] dt/bindings: qcom_nandc: Add DT bindings
From: Archit Taneja <architt@codeaurora.org>
X-Patchwork-Id: 6927141
Message-Id: <1438578498-32254-4-git-send-email-architt@codeaurora.org>
To: linux-mtd@lists.infradead.org, dehrenberg@google.com,
cernekee@gmail.com, computersforpeace@gmail.com
Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org,
sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
Archit Taneja <architt@codeaurora.org>, devicetree@vger.kernel.org
Date: Mon, 3 Aug 2015 10:38:16 +0530
Add DT bindings document for the Qualcomm NAND controller driver.
Cc: devicetree@vger.kernel.org
v3:
- Don't use '0x' when specifying nand controller address space
- Add optional property for on-flash bbt usage
Acked-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
.../devicetree/bindings/mtd/qcom_nandc.txt | 49 ++++++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -0,0 +1,49 @@
+* Qualcomm NAND controller
+
+Required properties:
+- compatible: should be "qcom,ebi2-nand" for IPQ806x
+- reg: MMIO address range
+- clocks: must contain core clock and always on clock
+- clock-names: must contain "core" for the core clock and "aon" for the
+ always on clock
+- dmas: DMA specifier, consisting of a phandle to the ADM DMA
+ controller node and the channel number to be used for
+ NAND. Refer to dma.txt and qcom_adm.txt for more details
+- dma-names: must be "rxtx"
+- qcom,cmd-crci: must contain the ADM command type CRCI block instance
+ number specified for the NAND controller on the given
+ platform
+- qcom,data-crci: must contain the ADM data type CRCI block instance
+ number specified for the NAND controller on the given
+ platform
+
+Optional properties:
+- nand-bus-width: bus width. Must be 8 or 16. If not present, 8 is chosen
+ as default
+
+- nand-ecc-strength: number of bits to correct per ECC step. Must be 4 or 8
+ bits. If not present, 4 is chosen as default
+- nand-on-flash-bbt: Create/use on-flash bad block table
+
+The device tree may optionally contain sub-nodes describing partitions of the
+address space. See partition.txt for more detail.
+
+Example:
+
+nand@1ac00000 {
+ compatible = "qcom,ebi2-nandc";
+ reg = <0x1ac00000 0x800>;
+
+ clocks = <&gcc EBI2_CLK>,
+ <&gcc EBI2_AON_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&adm_dma 3>;
+ dma-names = "rxtx";
+ qcom,cmd-crci = <15>;
+ qcom,data-crci = <3>;
+
+ partition@0 {
+ ...
+ };
+};

50
target/linux/ipq806x/patches-3.18/164-arm-qcom-dts-Add-NAND-controller-node-for-ipq806x.patch Normal file
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@ -0,0 +1,50 @@
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [v3,4/5] arm: qcom: dts: Add NAND controller node for ipq806x
From: Archit Taneja <architt@codeaurora.org>
X-Patchwork-Id: 6927121
Message-Id: <1438578498-32254-5-git-send-email-architt@codeaurora.org>
To: linux-mtd@lists.infradead.org, dehrenberg@google.com,
cernekee@gmail.com, computersforpeace@gmail.com
Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org,
sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
Archit Taneja <architt@codeaurora.org>, devicetree@vger.kernel.org
Date: Mon, 3 Aug 2015 10:38:17 +0530
The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding
compatible string.
Cc: devicetree@vger.kernel.org
Reviewed-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -677,5 +677,21 @@
status = "disabled";
};
+ nand@1ac00000 {
+ compatible = "qcom,ebi2-nandc";
+ reg = <0x1ac00000 0x800>;
+
+ clocks = <&gcc EBI2_CLK>,
+ <&gcc EBI2_AON_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&adm_dma 3>;
+ dma-names = "rxtx";
+ qcom,cmd-crci = <15>;
+ qcom,data-crci = <3>;
+
+ status = "disabled";
+ };
+
};
};

79
target/linux/ipq806x/patches-3.18/165-arm-qcom-dts-Enable-NAND-node-on-IPQ8064-AP148-platform.patch Normal file
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@ -0,0 +1,79 @@
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [v3,5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform
From: Archit Taneja <architt@codeaurora.org>
X-Patchwork-Id: 6927091
Message-Id: <1438578498-32254-6-git-send-email-architt@codeaurora.org>
To: linux-mtd@lists.infradead.org, dehrenberg@google.com,
cernekee@gmail.com, computersforpeace@gmail.com
Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org,
sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
Archit Taneja <architt@codeaurora.org>, devicetree@vger.kernel.org
Date: Mon, 3 Aug 2015 10:38:18 +0530
Enable the NAND controller node on the AP148 platform. Provide pinmux
information.
Cc: devicetree@vger.kernel.org
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -61,6 +61,31 @@
bias-none;
};
};
+
+ nand_pins: nand_pins {
+ mux {
+ pins = "gpio34", "gpio35", "gpio36",
+ "gpio37", "gpio38", "gpio39",
+ "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45",
+ "gpio46", "gpio47";
+ function = "nand";
+ drive-strength = <10>;
+ bias-disable;
+ };
+
+ pullups {
+ pins = "gpio39";
+ bias-pull-up;
+ };
+
+ hold {
+ pins = "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45",
+ "gpio46", "gpio47";
+ bias-bus-hold;
+ };
+ };
};
gsbi@16300000 {
@@ -174,5 +199,19 @@
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
};
+
+ nand@1ac00000 {
+ status = "ok";
+
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+
+ nand-ecc-strength = <4>;
+ nand-bus-width = <8>;
+ };
};
};
+
+&adm_dma {
+ status = "ok";
+};

20
target/linux/ipq806x/patches-3.18/700-clk-qcom-Add-support-for-NSS-GMAC-clocks-and-resets.patch
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@ -86,7 +86,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
static struct freq_tbl clk_tbl_gsbi_uart[] = {
{ 1843200, P_PLL8, 2, 6, 625 },
{ 3686400, P_PLL8, 2, 12, 625 },
@@ -2239,6 +2290,472 @@ static struct clk_branch usb_fs1_h_clk =
@@ -2269,6 +2320,472 @@ static struct clk_branch ebi2_aon_clk =
},
};
@ -559,7 +559,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
static struct clk_regmap *gcc_ipq806x_clks[] = {
[PLL0] = &pll0.clkr,
[PLL0_VOTE] = &pll0_vote,
@@ -2247,6 +2764,7 @@ static struct clk_regmap *gcc_ipq806x_cl
@@ -2277,6 +2794,7 @@ static struct clk_regmap *gcc_ipq806x_cl
[PLL8_VOTE] = &pll8_vote,
[PLL14] = &pll14.clkr,
[PLL14_VOTE] = &pll14_vote,
@ -567,7 +567,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
[GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
[GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
@@ -2344,6 +2862,18 @@ static struct clk_regmap *gcc_ipq806x_cl
@@ -2376,6 +2894,18 @@ static struct clk_regmap *gcc_ipq806x_cl
[PLL9] = &hfpll0.clkr,
[PLL10] = &hfpll1.clkr,
[PLL12] = &hfpll_l2.clkr,
@ -586,7 +586,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
};
static const struct qcom_reset_map gcc_ipq806x_resets[] = {
@@ -2462,6 +2992,48 @@ static const struct qcom_reset_map gcc_i
@@ -2494,6 +3024,48 @@ static const struct qcom_reset_map gcc_i
[USB30_1_PHY_RESET] = { 0x3b58, 0 },
[NSSFB0_RESET] = { 0x3b60, 6 },
[NSSFB1_RESET] = { 0x3b60, 7 },
@ -635,7 +635,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
};
static const struct regmap_config gcc_ipq806x_regmap_config = {
@@ -2490,6 +3062,8 @@ static int gcc_ipq806x_probe(struct plat
@@ -2522,6 +3094,8 @@ static int gcc_ipq806x_probe(struct plat
{
struct clk *clk;
struct device *dev = &pdev->dev;
@ -644,7 +644,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
/* Temporary until RPM clocks supported */
clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 25000000);
@@ -2500,7 +3074,25 @@ static int gcc_ipq806x_probe(struct plat
@@ -2532,7 +3106,25 @@ static int gcc_ipq806x_probe(struct plat
if (IS_ERR(clk))
return PTR_ERR(clk);
@ -673,12 +673,12 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
static int gcc_ipq806x_remove(struct platform_device *pdev)
--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
@@ -289,5 +289,7 @@
#define UBI32_CORE2_CLK_SRC 278
@@ -290,5 +290,7 @@
#define UBI32_CORE1_CLK 279
#define UBI32_CORE2_CLK 280
+#define NSSTCM_CLK_SRC 281
+#define NSSTCM_CLK 282
#define EBI2_AON_CLK 281
+#define NSSTCM_CLK_SRC 282
+#define NSSTCM_CLK 283
#endif
--- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h

11
target/linux/ipq806x/patches-3.18/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch
View file

@ -22,8 +22,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
};
chosen {
@@ -61,6 +62,15 @@
bias-none;
@@ -86,6 +87,15 @@
bias-bus-hold;
};
};
+
@ -38,9 +38,9 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
};
gsbi@16300000 {
@@ -174,5 +184,33 @@
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
@@ -209,6 +219,34 @@
nand-ecc-strength = <4>;
nand-bus-width = <8>;
};
+
+ mdio0: mdio {
@ -72,6 +72,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ };
};
};
--- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
@@ -16,6 +16,7 @@

7
target/linux/ipq806x/patches-3.18/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch
View file

@ -12,7 +12,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -71,6 +71,16 @@
@@ -96,6 +96,16 @@
bias-disable;
};
};
@ -29,7 +29,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
};
gsbi@16300000 {
@@ -212,5 +222,26 @@
@@ -247,6 +257,27 @@
reg = <4>;
};
};
@ -56,6 +56,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ };
};
};
--- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
@@ -75,6 +75,14 @@
@ -116,7 +117,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
};
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -677,5 +677,91 @@
@@ -693,5 +693,91 @@
status = "disabled";
};

84
target/linux/ipq806x/patches-4.1/161-mtd-nand-Create-a-BBT-flag-to-access-bad-block-markers-in-raw-mode.patch Normal file
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@ -0,0 +1,84 @@
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [v3,
1/5] mtd: nand: Create a BBT flag to access bad block markers in raw
mode
From: Archit Taneja <architt@codeaurora.org>
X-Patchwork-Id: 6927081
Message-Id: <1438578498-32254-2-git-send-email-architt@codeaurora.org>
To: linux-mtd@lists.infradead.org, dehrenberg@google.com,
cernekee@gmail.com, computersforpeace@gmail.com
Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org,
sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
Archit Taneja <architt@codeaurora.org>
Date: Mon, 3 Aug 2015 10:38:14 +0530
Some controllers can access the factory bad block marker from OOB only
when they read it in raw mode. When ECC is enabled, these controllers
discard reading/writing bad block markers, preventing access to them
altogether.
The bbt driver assumes MTD_OPS_PLACE_OOB when scanning for bad blocks.
This results in the nand driver's ecc->read_oob() op to be called, which
works with ECC enabled.
Create a new BBT option flag that tells nand_bbt to force the mode to
MTD_OPS_RAW. This would result in the correct op being called for the
underlying nand controller driver.
Reviewed-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
drivers/mtd/nand/nand_base.c | 6 +++++-
drivers/mtd/nand/nand_bbt.c | 6 +++++-
include/linux/mtd/bbm.h | 7 +++++++
3 files changed, 17 insertions(+), 2 deletions(-)
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -395,7 +395,11 @@ static int nand_default_block_markbad(st
} else {
ops.len = ops.ooblen = 1;
}
- ops.mode = MTD_OPS_PLACE_OOB;
+
+ if (unlikely(chip->bbt_options & NAND_BBT_ACCESS_BBM_RAW))
+ ops.mode = MTD_OPS_RAW;
+ else
+ ops.mode = MTD_OPS_PLACE_OOB;
/* Write to first/last page(s) if necessary */
if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
@@ -423,7 +423,11 @@ static int scan_block_fast(struct mtd_in
ops.oobbuf = buf;
ops.ooboffs = 0;
ops.datbuf = NULL;
- ops.mode = MTD_OPS_PLACE_OOB;
+
+ if (unlikely(bd->options & NAND_BBT_ACCESS_BBM_RAW))
+ ops.mode = MTD_OPS_RAW;
+ else
+ ops.mode = MTD_OPS_PLACE_OOB;
for (j = 0; j < numpages; j++) {
/*
--- a/include/linux/mtd/bbm.h
+++ b/include/linux/mtd/bbm.h
@@ -116,6 +116,13 @@ struct nand_bbt_descr {
#define NAND_BBT_NO_OOB_BBM 0x00080000
/*
+ * Force MTD_OPS_RAW mode when trying to access bad block markes from OOB. To
+ * be used by controllers which can access BBM only when ECC is disabled, i.e,
+ * when in RAW access mode
+ */
+#define NAND_BBT_ACCESS_BBM_RAW 0x00100000
+
+/*
* Flag set by nand_create_default_bbt_descr(), marking that the nand_bbt_descr
* was allocated dynamicaly and must be freed in nand_release(). Has no meaning
* in nand_chip.bbt_options.

2024
target/linux/ipq806x/patches-4.1/162-mtd-nand-Qualcomm-NAND-controller-driver.patch Normal file
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File diff suppressed because it is too large Load diff

82
target/linux/ipq806x/patches-4.1/163-dt-bindings-qcom_nandc-Add-DT-bindings.patch Normal file
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@ -0,0 +1,82 @@
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [v3,3/5] dt/bindings: qcom_nandc: Add DT bindings
From: Archit Taneja <architt@codeaurora.org>
X-Patchwork-Id: 6927141
Message-Id: <1438578498-32254-4-git-send-email-architt@codeaurora.org>
To: linux-mtd@lists.infradead.org, dehrenberg@google.com,
cernekee@gmail.com, computersforpeace@gmail.com
Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org,
sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
Archit Taneja <architt@codeaurora.org>, devicetree@vger.kernel.org
Date: Mon, 3 Aug 2015 10:38:16 +0530
Add DT bindings document for the Qualcomm NAND controller driver.
Cc: devicetree@vger.kernel.org
v3:
- Don't use '0x' when specifying nand controller address space
- Add optional property for on-flash bbt usage
Acked-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
.../devicetree/bindings/mtd/qcom_nandc.txt | 49 ++++++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -0,0 +1,49 @@
+* Qualcomm NAND controller
+
+Required properties:
+- compatible: should be "qcom,ebi2-nand" for IPQ806x
+- reg: MMIO address range
+- clocks: must contain core clock and always on clock
+- clock-names: must contain "core" for the core clock and "aon" for the
+ always on clock
+- dmas: DMA specifier, consisting of a phandle to the ADM DMA
+ controller node and the channel number to be used for
+ NAND. Refer to dma.txt and qcom_adm.txt for more details
+- dma-names: must be "rxtx"
+- qcom,cmd-crci: must contain the ADM command type CRCI block instance
+ number specified for the NAND controller on the given
+ platform
+- qcom,data-crci: must contain the ADM data type CRCI block instance
+ number specified for the NAND controller on the given
+ platform
+
+Optional properties:
+- nand-bus-width: bus width. Must be 8 or 16. If not present, 8 is chosen
+ as default
+
+- nand-ecc-strength: number of bits to correct per ECC step. Must be 4 or 8
+ bits. If not present, 4 is chosen as default
+- nand-on-flash-bbt: Create/use on-flash bad block table
+
+The device tree may optionally contain sub-nodes describing partitions of the
+address space. See partition.txt for more detail.
+
+Example:
+
+nand@1ac00000 {
+ compatible = "qcom,ebi2-nandc";
+ reg = <0x1ac00000 0x800>;
+
+ clocks = <&gcc EBI2_CLK>,
+ <&gcc EBI2_AON_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&adm_dma 3>;
+ dma-names = "rxtx";
+ qcom,cmd-crci = <15>;
+ qcom,data-crci = <3>;
+
+ partition@0 {
+ ...
+ };
+};

50
target/linux/ipq806x/patches-4.1/164-arm-qcom-dts-Add-NAND-controller-node-for-ipq806x.patch Normal file
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@ -0,0 +1,50 @@
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [v3,4/5] arm: qcom: dts: Add NAND controller node for ipq806x
From: Archit Taneja <architt@codeaurora.org>
X-Patchwork-Id: 6927121
Message-Id: <1438578498-32254-5-git-send-email-architt@codeaurora.org>
To: linux-mtd@lists.infradead.org, dehrenberg@google.com,
cernekee@gmail.com, computersforpeace@gmail.com
Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org,
sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
Archit Taneja <architt@codeaurora.org>, devicetree@vger.kernel.org
Date: Mon, 3 Aug 2015 10:38:17 +0530
The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding
compatible string.
Cc: devicetree@vger.kernel.org
Reviewed-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -615,5 +615,21 @@
status = "disabled";
};
+
+ nand@1ac00000 {
+ compatible = "qcom,ebi2-nandc";
+ reg = <0x1ac00000 0x800>;
+
+ clocks = <&gcc EBI2_CLK>,
+ <&gcc EBI2_AON_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&adm_dma 3>;
+ dma-names = "rxtx";
+ qcom,cmd-crci = <15>;
+ qcom,data-crci = <3>;
+
+ status = "disabled";
+ };
};
};

76
target/linux/ipq806x/patches-4.1/165-arm-qcom-dts-Enable-NAND-node-on-IPQ8064-AP148-platform.patch Normal file
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@ -0,0 +1,76 @@
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [v3,5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform
From: Archit Taneja <architt@codeaurora.org>
X-Patchwork-Id: 6927091
Message-Id: <1438578498-32254-6-git-send-email-architt@codeaurora.org>
To: linux-mtd@lists.infradead.org, dehrenberg@google.com,
cernekee@gmail.com, computersforpeace@gmail.com
Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org,
sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
Archit Taneja <architt@codeaurora.org>, devicetree@vger.kernel.org
Date: Mon, 3 Aug 2015 10:38:18 +0530
Enable the NAND controller node on the AP148 platform. Provide pinmux
information.
Cc: devicetree@vger.kernel.org
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -61,6 +61,28 @@
bias-none;
};
};
+ nand_pins: nand_pins {
+ mux {
+ pins = "gpio34", "gpio35", "gpio36",
+ "gpio37", "gpio38", "gpio39",
+ "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45",
+ "gpio46", "gpio47";
+ function = "nand";
+ drive-strength = <10>;
+ bias-disable;
+ };
+ pullups {
+ pins = "gpio39";
+ bias-pull-up;
+ };
+ hold {
+ pins = "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45",
+ "gpio46", "gpio47";
+ bias-bus-hold;
+ };
+ };
};
gsbi@16300000 {
@@ -150,5 +172,19 @@
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
};
+
+ nand@1ac00000 {
+ status = "ok";
+
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+
+ nand-ecc-strength = <4>;
+ nand-bus-width = <8>;
+ };
};
};
+
+&adm_dma {
+ status = "ok";
+};

11
target/linux/ipq806x/patches-4.1/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch
View file

@ -22,8 +22,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
};
chosen {
@@ -61,6 +62,15 @@
bias-none;
@@ -83,6 +84,15 @@
bias-bus-hold;
};
};
+
@ -38,9 +38,9 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
};
gsbi@16300000 {
@@ -150,5 +160,33 @@
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
@@ -182,6 +192,34 @@
nand-ecc-strength = <4>;
nand-bus-width = <8>;
};
+
+ mdio0: mdio {
@ -72,6 +72,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ };
};
};
--- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
@@ -16,6 +16,7 @@

7
target/linux/ipq806x/patches-4.1/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch
View file

@ -12,7 +12,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -71,6 +71,16 @@
@@ -93,6 +93,16 @@
bias-disable;
};
};
@ -29,7 +29,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
};
gsbi@16300000 {
@@ -188,5 +198,26 @@
@@ -220,6 +230,27 @@
reg = <4>;
};
};
@ -56,6 +56,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ };
};
};
--- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
@@ -75,6 +75,14 @@
@ -116,7 +117,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
};
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -615,5 +615,91 @@
@@ -631,5 +631,91 @@
status = "disabled";
};