From ccf95fe93855bb16bc3c0b555930725b6c617d9f Mon Sep 17 00:00:00 2001
From: Gabor Juhos <juhosg@openwrt.org>
Date: Fri, 3 May 2013 19:00:58 +0000
Subject: [PATCH] ar71xx: Fix AP135 PCI

AP135 has a pluggable PCIE slot unlike AP136.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 36541
---
 .../609-MIPS-ath79-ap136-fixes.patch          | 24 ++++++++++++++-----
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/target/linux/ar71xx/patches-3.8/609-MIPS-ath79-ap136-fixes.patch b/target/linux/ar71xx/patches-3.8/609-MIPS-ath79-ap136-fixes.patch
index 0a8fe0e4b8..4b530a7b5a 100644
--- a/target/linux/ar71xx/patches-3.8/609-MIPS-ath79-ap136-fixes.patch
+++ b/target/linux/ar71xx/patches-3.8/609-MIPS-ath79-ap136-fixes.patch
@@ -1,6 +1,6 @@
 --- a/arch/mips/ath79/mach-ap136.c
 +++ b/arch/mips/ath79/mach-ap136.c
-@@ -18,23 +18,28 @@
+@@ -18,23 +18,29 @@
   *
   */
  
@@ -13,6 +13,7 @@
 +#include <asm/mach-ath79/ar71xx_regs.h>
 +
 +#include "common.h"
++#include "pci.h"
 +#include "dev-ap9x-pci.h"
  #include "dev-gpio-buttons.h"
 +#include "dev-eth.h"
@@ -37,7 +38,7 @@
  #define AP136_GPIO_LED_WPS_GREEN	20
  
  #define AP136_GPIO_BTN_WPS		16
-@@ -43,37 +48,39 @@
+@@ -43,37 +49,39 @@
  #define AP136_KEYS_POLL_INTERVAL	20	/* msecs */
  #define AP136_KEYS_DEBOUNCE_INTERVAL	(3 * AP136_KEYS_POLL_INTERVAL)
  
@@ -85,7 +86,7 @@
  		.gpio		= AP136_GPIO_LED_USB,
  		.active_low	= 1,
  	}
-@@ -98,65 +105,158 @@ static struct gpio_keys_button ap136_gpi
+@@ -98,65 +106,169 @@ static struct gpio_keys_button ap136_gpi
  	},
  };
  
@@ -188,7 +189,6 @@
 +	ath79_register_nfc();
 +
 +	ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
-+	ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
 +
 +	ap136_gmac_setup();
 +
@@ -216,6 +216,8 @@
 +
 +static void __init ap136_010_setup(void)
 +{
++	u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
++
 +	/* GMAC0 of the AR8327 switch is connected to GMAC0 via RGMII */
 +	ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII;
 +	ap136_ar8327_pad0_cfg.txclk_delay_en = true;
@@ -232,6 +234,7 @@
 +	ath79_eth1_pll_data.pll_1000 = 0x03000101;
 +
 +	ap136_common_setup();
++	ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
  }
  
  MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
@@ -239,7 +242,7 @@
 -	     ap136_setup);
 +	     ap136_010_setup);
 +
-+static void __init ap136_020_setup(void)
++static void __init ap136_020_common_setup(void)
 +{
 +	/* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */
 +	ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII;
@@ -258,6 +261,14 @@
 +	ap136_common_setup();
 +}
 +
++static void __init ap136_020_setup(void)
++{
++	u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
++
++	ap136_020_common_setup();
++	ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
++}
++
 +MIPS_MACHINE(ATH79_MACH_AP136_020, "AP136-020",
 +	     "Atheros AP136-020 reference board",
 +	     ap136_020_setup);
@@ -275,7 +286,8 @@
 +	ap136_leds_gpio[4].name = "ap135:red:wlan-2g";
 +	ap136_leds_gpio[5].name = "ap135:red:usb";
 +
-+	ap136_020_setup();
++	ap136_020_common_setup();
++	ath79_register_pci();
 +}
 +
 +MIPS_MACHINE(ATH79_MACH_AP135_020, "AP135-020",