cleaned up amazon serial and prom code
SVN-Revision: 8344
This commit is contained in:
John Crispin
parent
049dc2925b
commit
cb3d2ae6e2
3 changed files with 183 additions and 236 deletions
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@ -1,6 +1,21 @@
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/*
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* copyright 2007 john crispin <blogic@openwrt.org>
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright 2007 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/init.h>
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#include <linux/string.h>
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#include <linux/ctype.h>
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@ -17,11 +32,11 @@
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void prom_putchar(char c)
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{
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/* Wait for FIFO to empty */
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while (((*AMAZON_ASC_FSTAT) >> 8) != 0x00) ;
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while ((amazon_readl(AMAZON_ASC_FSTAT) >> 8) != 0x00) ;
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/* Crude cr/nl handling is better than none */
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if(c == '\n')
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*AMAZON_ASC_TBUF=('\r');
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*AMAZON_ASC_TBUF=(c);
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amazon_writel('\r', AMAZON_ASC_TBUF);
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amazon_writel(c, AMAZON_ASC_TBUF);
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}
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void prom_printf(const char * fmt, ...)
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@ -32,7 +47,8 @@ void prom_printf(const char * fmt, ...)
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char buf[1024];
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va_start(args, fmt);
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l = vsprintf(buf, fmt, args); /* hopefully i < sizeof(buf) */
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/* FIXME - hopefully i < sizeof(buf) */
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l = vsprintf(buf, fmt, args);
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va_end(args);
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buf_end = buf + l;
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@ -1,12 +1,6 @@
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/*
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* linux/drivers/char/amazon_asc.c
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*
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* Driver for AMAZONASC serial ports
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*
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* Copyright (C) 2004 Infineon IFAP DC COM CPE
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* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
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*
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* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
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* Based on drivers/serial/serial_s3c2400.c
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*
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@ -24,9 +18,9 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* $Id: amazon_asc.c,v 1.2 2005/04/01 02:40:48 pliu Exp $
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*
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* This is a generic driver for AMAZONASC-type serial ports.
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* Copyright (C) 2004 Infineon IFAP DC COM CPE
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* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/module.h>
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@ -61,46 +55,23 @@
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#define PORT_AMAZONASC 111
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#if defined(CONFIG_SERIAL_AMAZONASC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
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#define SUPPORT_SYSRQ
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#endif
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#include <linux/serial_core.h>
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#define UART_NR 1
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#define UART_DUMMY_UER_RX 1
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#define SERIAL_AMAZONASC_MAJOR TTY_MAJOR
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#define CALLOUT_AMAZONASC_MAJOR TTYAUX_MAJOR
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#define SERIAL_AMAZONASC_MINOR 64
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#define SERIAL_AMAZONASC_NR UART_NR
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static void amazonasc_tx_chars(struct uart_port *port);
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extern void prom_printf(const char * fmt, ...);
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static struct uart_port amazonasc_ports[UART_NR];
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static struct uart_driver amazonasc_reg;
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#ifdef CONFIG_SERIAL_AMAZONASC_CONSOLE /*SUPPORT_SYSRQ*/
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static struct console amazonasc_console;
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#endif
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static unsigned int uartclk = 0;
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#define SET_BIT(reg, mask) *reg |= (mask)
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#define CLEAR_BIT(reg, mask) *reg &= (~mask)
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#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
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#define SET_BITS(reg, mask) SET_BIT(reg, mask)
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#define SET_BITFIELD(reg, mask, off, val) \
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{*reg &= (~mask); *reg |= (val << off);}
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static void amazonasc_tx_chars(struct uart_port *port);
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/* fake flag to indicate CREAD was not set -> throw away all bytes */
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#define UART_DUMMY_UER_RX 1
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/* macro to set the bit corresponding to an interrupt number */
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#define BIT_NO(irq) (1 << (irq - 64))
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#define SERIAL_DEBUG
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extern unsigned int amazon_get_fpi_hz(void);
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static int tx_enabled = 0;
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static void amazonasc_stop_tx(struct uart_port *port)
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{
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@ -122,7 +93,7 @@ static void amazonasc_start_tx(struct uart_port *port)
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static void amazonasc_stop_rx(struct uart_port *port)
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{
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/* clear the RX enable bit */
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*AMAZON_ASC_WHBCON = ASCWHBCON_CLRREN;
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amazon_writel(ASCWHBCON_CLRREN, AMAZON_ASC_WHBCON);
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}
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static void amazonasc_enable_ms(struct uart_port *port)
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@ -136,14 +107,13 @@ amazonasc_rx_chars(struct uart_port *port)
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{
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struct tty_struct *tty = port->info->tty;
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unsigned int ch = 0, rsr = 0, fifocnt;
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unsigned long flags;
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fifocnt = *AMAZON_ASC_FSTAT & ASCFSTAT_RXFFLMASK;
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fifocnt = amazon_readl(AMAZON_ASC_FSTAT) & ASCFSTAT_RXFFLMASK;
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while (fifocnt--)
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{
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u8 flag = TTY_NORMAL;
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ch = *AMAZON_ASC_RBUF;
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rsr = (*AMAZON_ASC_CON & ASCCON_ANY) | UART_DUMMY_UER_RX;
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ch = amazon_readl(AMAZON_ASC_RBUF);
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rsr = (amazon_readl(AMAZON_ASC_CON) & ASCCON_ANY) | UART_DUMMY_UER_RX;
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tty_flip_buffer_push(tty);
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port->icount.rx++;
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@ -154,14 +124,14 @@ amazonasc_rx_chars(struct uart_port *port)
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if (rsr & ASCCON_ANY) {
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if (rsr & ASCCON_PE) {
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port->icount.parity++;
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SET_BIT(AMAZON_ASC_WHBCON, ASCWHBCON_CLRPE);
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amazon_writel_masked(AMAZON_ASC_WHBCON, ASCWHBCON_CLRPE, ASCWHBCON_CLRPE);
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} else if (rsr & ASCCON_FE) {
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port->icount.frame++;
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SET_BIT(AMAZON_ASC_WHBCON, ASCWHBCON_CLRFE);
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amazon_writel_masked(AMAZON_ASC_WHBCON, ASCWHBCON_CLRFE, ASCWHBCON_CLRFE);
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}
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if (rsr & ASCCON_OE) {
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port->icount.overrun++;
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SET_BIT(AMAZON_ASC_WHBCON, ASCWHBCON_CLROE);
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amazon_writel_masked(AMAZON_ASC_WHBCON, ASCWHBCON_CLROE, ASCWHBCON_CLROE);
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}
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rsr &= port->read_status_mask;
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@ -199,11 +169,11 @@ static void amazonasc_tx_chars(struct uart_port *port)
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return;
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}
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while (((*AMAZON_ASC_FSTAT & ASCFSTAT_TXFFLMASK)
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while (((amazon_readl(AMAZON_ASC_FSTAT) & ASCFSTAT_TXFFLMASK)
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>> ASCFSTAT_TXFFLOFF) != AMAZONASC_TXFIFO_FULL)
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{
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if (port->x_char) {
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*AMAZON_ASC_TBUF = port->x_char;
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amazon_writel(port->x_char, AMAZON_ASC_TBUF);
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port->icount.tx++;
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port->x_char = 0;
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continue;
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@ -212,7 +182,7 @@ static void amazonasc_tx_chars(struct uart_port *port)
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if (uart_circ_empty(xmit))
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break;
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*AMAZON_ASC_TBUF = xmit->buf[xmit->tail];
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amazon_writel(xmit->buf[xmit->tail], AMAZON_ASC_TBUF);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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}
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@ -223,13 +193,13 @@ static void amazonasc_tx_chars(struct uart_port *port)
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static irqreturn_t amazonasc_tx_int(int irq, void *port)
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{
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*(AMAZON_ASC_IRNCR1) = ASC_IRNCR_TIR;
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amazon_writel(ASC_IRNCR_TIR, AMAZON_ASC_IRNCR1);
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amazonasc_start_tx(port);
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/* clear any pending interrupts */
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SET_BIT(AMAZON_ASC_WHBCON, ASCWHBCON_CLRPE);
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SET_BIT(AMAZON_ASC_WHBCON, ASCWHBCON_CLRFE);
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SET_BIT(AMAZON_ASC_WHBCON, ASCWHBCON_CLROE);
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amazon_writel_masked(AMAZON_ASC_WHBCON,
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(ASCWHBCON_CLRPE | ASCWHBCON_CLRFE | ASCWHBCON_CLROE),
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(ASCWHBCON_CLRPE | ASCWHBCON_CLRFE | ASCWHBCON_CLROE));
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return IRQ_HANDLED;
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}
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@ -237,15 +207,16 @@ static irqreturn_t amazonasc_tx_int(int irq, void *port)
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static irqreturn_t amazonasc_er_int(int irq, void *port)
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{
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/* clear any pending interrupts */
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SET_BIT(AMAZON_ASC_WHBCON, ASCWHBCON_CLRPE);
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SET_BIT(AMAZON_ASC_WHBCON, ASCWHBCON_CLRFE);
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SET_BIT(AMAZON_ASC_WHBCON, ASCWHBCON_CLROE);
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amazon_writel_masked(AMAZON_ASC_WHBCON,
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(ASCWHBCON_CLRPE | ASCWHBCON_CLRFE | ASCWHBCON_CLROE),
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(ASCWHBCON_CLRPE | ASCWHBCON_CLRFE | ASCWHBCON_CLROE));
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return IRQ_HANDLED;
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}
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static irqreturn_t amazonasc_rx_int(int irq, void *port)
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{
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*(AMAZON_ASC_IRNCR1) = ASC_IRNCR_RIR;
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amazon_writel(ASC_IRNCR_RIR, AMAZON_ASC_IRNCR1);
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amazonasc_rx_chars((struct uart_port *) port);
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return IRQ_HANDLED;
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}
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@ -260,7 +231,7 @@ static u_int amazonasc_tx_empty(struct uart_port *port)
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* 16 bytes to be transmitted before reporting that the
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* transmitter is empty.
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*/
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status = *AMAZON_ASC_FSTAT & ASCFSTAT_TXFFLMASK;
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status = amazon_readl(AMAZON_ASC_FSTAT) & ASCFSTAT_TXFFLMASK;
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return status ? 0 : TIOCSER_TEMT;
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}
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@ -294,7 +265,6 @@ static int amazonasc_startup(struct uart_port *port)
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amazonasc_ports[0].uartclk = uartclk;
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/* block the IRQs */
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local_irq_save(flags);
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/* this setup was probably already done in u-boot */
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@ -302,61 +272,45 @@ static int amazonasc_startup(struct uart_port *port)
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* P1.3 (RX) in, Alternate 10
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* P1.4 (TX) in, Alternate 10
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*/
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SET_BITFIELD((AMAZON_GPIO_P1_DIR), 0x8, 4, 1); //P1.4 output, P1.3 input
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SET_BIT((AMAZON_GPIO_P1_ALTSEL0), 0x18); //ALTSETL0 11
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CLEAR_BIT((AMAZON_GPIO_P1_ALTSEL1), 0x18); //ALTSETL1 00
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SET_BITFIELD((AMAZON_GPIO_P1_OD), 0x8, 4, 1);
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amazon_writel_masked(AMAZON_GPIO_P1_DIR, 0x18, 0x10); //P1.4 output, P1.3 input
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amazon_writel_masked(AMAZON_GPIO_P1_ALTSEL0, 0x18, 0x18); //ALTSETL0 11
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amazon_writel_masked(AMAZON_GPIO_P1_ALTSEL1, 0x18, 0); //ALTSETL1 00
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amazon_writel_masked(AMAZON_GPIO_P1_OD, 0x18, 0x10);
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/* set up the CLC */
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CLEAR_BIT(AMAZON_ASC_CLC, AMAZON_ASC_CLC_DISS);
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SET_BITFIELD(AMAZON_ASC_CLC, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 1);
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/* asynchronous mode */
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con = ASCCON_M_8ASYNC;
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/* set error signals - framing and overrun */
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con |= ASCCON_FEN;
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con |= ASCCON_OEN;
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con |= ASCCON_PEN;
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/* choose the line - there's only one */
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*AMAZON_ASC_PISEL = 0;
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#if 1
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*AMAZON_ASC_TXFCON = (((AMAZONASC_TXFIFO_FL<<ASCTXFCON_TXFITLOFF)&ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN |ASCTXFCON_TXFFLU);
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*AMAZON_ASC_RXFCON = (((AMAZONASC_RXFIFO_FL<<ASCRXFCON_RXFITLOFF)&ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN |ASCRXFCON_RXFFLU);
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wmb();
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#else
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/* TXFIFO's fill level */
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SET_BITFIELD(AMAZON_ASC_TXFCON, ASCTXFCON_TXFITLMASK,
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ASCTXFCON_TXFITLOFF, AMAZONASC_TXFIFO_FL);
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/* enable TXFIFO */
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SET_BIT(AMAZON_ASC_TXFCON, ASCTXFCON_TXFEN);
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/* RXFIFO's fill level */
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SET_BITFIELD(AMAZON_ASC_RXFCON, ASCRXFCON_RXFITLMASK,
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ASCRXFCON_RXFITLOFF, AMAZONASC_RXFIFO_FL);
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/* enable RXFIFO */
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SET_BIT(AMAZON_ASC_RXFCON, ASCRXFCON_RXFEN);
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/* now really set CON */
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#endif
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SET_BIT(AMAZON_ASC_CON,con);
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amazon_writel_masked(AMAZON_ASC_CLC, AMAZON_ASC_CLC_DISS, 0);
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amazon_writel_masked(AMAZON_ASC_CLC, ASCCLC_RMCMASK, 1 << ASCCLC_RMCOFFSET);
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/* asynchronous mode */
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con = ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_OEN | ASCCON_PEN;
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/* choose the line - there's only one */
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amazon_writel(0, AMAZON_ASC_PISEL);
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amazon_writel(((AMAZONASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU,
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AMAZON_ASC_TXFCON);
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amazon_writel(((AMAZONASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU,
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AMAZON_ASC_RXFCON);
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wmb();
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amazon_writel_masked(AMAZON_ASC_CON, con, con);
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/*
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* Allocate the IRQs
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*/
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retval = request_irq(AMAZONASC_RIR, amazonasc_rx_int, 0, "asc_rx", port);
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if (retval){
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printk("-------req1 failed\n");
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printk("failed to request amazonasc_rx_int\n");
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return retval;
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}
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retval = request_irq(AMAZONASC_TIR, amazonasc_tx_int, 0, "asc_tx", port);
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if (retval){
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printk("----------req2 failed\n");
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printk("failed to request amazonasc_tx_int\n");
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goto err1;
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}
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retval = request_irq(AMAZONASC_EIR, amazonasc_er_int, 0, "asc_er", port);
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if (retval){
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printk("---------req3 failed\n");
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printk("failed to request amazonasc_er_int\n");
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goto err2;
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}
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/* unblock the IRQs */
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local_irq_restore(flags);
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return 0;
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@ -371,22 +325,19 @@ err1:
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static void amazonasc_shutdown(struct uart_port *port)
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{
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/*
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* Free the interrupts
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*/
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free_irq(AMAZONASC_RIR, port);
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free_irq(AMAZONASC_TIR, port);
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free_irq(AMAZONASC_EIR, port);
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/*
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* disable the baudrate generator to disable the ASC
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*/
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*AMAZON_ASC_CON = 0;
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amazon_writel(0, AMAZON_ASC_CON);
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/* flush and then disable the fifos */
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SET_BIT(AMAZON_ASC_RXFCON, ASCRXFCON_RXFFLU);
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CLEAR_BIT(AMAZON_ASC_RXFCON, ASCRXFCON_RXFEN);
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SET_BIT(AMAZON_ASC_TXFCON, ASCTXFCON_TXFFLU);
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CLEAR_BIT(AMAZON_ASC_TXFCON, ASCTXFCON_TXFEN);
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amazon_writel_masked(AMAZON_ASC_RXFCON, ASCRXFCON_RXFFLU, ASCRXFCON_RXFFLU);
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amazon_writel_masked(AMAZON_ASC_RXFCON, ASCRXFCON_RXFEN, 0);
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amazon_writel_masked(AMAZON_ASC_TXFCON, ASCTXFCON_TXFFLU, ASCTXFCON_TXFFLU);
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amazon_writel_masked(AMAZON_ASC_TXFCON, ASCTXFCON_TXFEN, 0);
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}
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static void amazonasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old)
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@ -426,23 +377,12 @@ static void amazonasc_set_termios(struct uart_port *port, struct ktermios *new,
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port->read_status_mask = ASCCON_OE;
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if (iflag & INPCK)
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port->read_status_mask |= ASCCON_FE | ASCCON_PE;
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/* the ASC can't really detect or generate a BREAK */
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#if 0
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if (iflag & (BRKINT | PARMRK))
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port->read_status_mask |= UERSTAT_BREAK;
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#endif
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||||
/*
|
||||
* Characters to ignore
|
||||
*/
|
||||
|
||||
port->ignore_status_mask = 0;
|
||||
if (iflag & IGNPAR)
|
||||
port->ignore_status_mask |= ASCCON_FE | ASCCON_PE;
|
||||
#if 0
|
||||
/* always ignore breaks - the ASC can't handle them XXXX */
|
||||
port->ignore_status_mask |= UERSTAT_BREAK;
|
||||
#endif
|
||||
|
||||
if (iflag & IGNBRK) {
|
||||
/*port->ignore_status_mask |= UERSTAT_BREAK;*/
|
||||
/*
|
||||
* If we're ignoring parity and break indicators,
|
||||
* ignore overruns too (for real raw support).
|
||||
|
|
@ -468,7 +408,7 @@ static void amazonasc_set_termios(struct uart_port *port, struct ktermios *new,
|
|||
local_irq_save(flags);
|
||||
|
||||
/* set up CON */
|
||||
*AMAZON_ASC_CON = con;
|
||||
amazon_writel(con, AMAZON_ASC_CON);
|
||||
|
||||
/* Set baud rate - take a divider of 2 into account */
|
||||
baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16);
|
||||
|
|
@ -477,17 +417,16 @@ static void amazonasc_set_termios(struct uart_port *port, struct ktermios *new,
|
|||
|
||||
/* the next 3 probably already happened when we set CON above */
|
||||
/* disable the baudrate generator */
|
||||
CLEAR_BIT(AMAZON_ASC_CON, ASCCON_R);
|
||||
amazon_writel_masked(AMAZON_ASC_CON, ASCCON_R, 0);
|
||||
/* make sure the fractional divider is off */
|
||||
CLEAR_BIT(AMAZON_ASC_CON, ASCCON_FDE);
|
||||
amazon_writel_masked(AMAZON_ASC_CON, ASCCON_FDE, 0);
|
||||
/* set up to use divisor of 2 */
|
||||
CLEAR_BIT(AMAZON_ASC_CON, ASCCON_BRS);
|
||||
amazon_writel_masked(AMAZON_ASC_CON, ASCCON_BRS, 0);
|
||||
/* now we can write the new baudrate into the register */
|
||||
*AMAZON_ASC_BTR = quot;
|
||||
amazon_writel(quot, AMAZON_ASC_BTR);
|
||||
/* turn the baudrate generator back on */
|
||||
SET_BIT(AMAZON_ASC_CON, ASCCON_R);
|
||||
amazon_writel_masked(AMAZON_ASC_CON, ASCCON_R, ASCCON_R);
|
||||
|
||||
/* unblock the IRQs */
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
|
|
@ -572,45 +511,36 @@ static struct uart_port amazonasc_ports[UART_NR] = {
|
|||
},
|
||||
};
|
||||
|
||||
|
||||
|
||||
static void amazonasc_console_write(struct console *co, const char *s, u_int count)
|
||||
{
|
||||
int i, fifocnt;
|
||||
unsigned long flags;
|
||||
/* block the IRQ */
|
||||
local_irq_save(flags);
|
||||
/*
|
||||
* Now, do each character
|
||||
*/
|
||||
for (i = 0; i < count;)
|
||||
{
|
||||
/* wait until the FIFO is not full */
|
||||
do
|
||||
{
|
||||
fifocnt = (*AMAZON_ASC_FSTAT & ASCFSTAT_TXFFLMASK)
|
||||
fifocnt = (amazon_readl(AMAZON_ASC_FSTAT) & ASCFSTAT_TXFFLMASK)
|
||||
>> ASCFSTAT_TXFFLOFF;
|
||||
} while (fifocnt == AMAZONASC_TXFIFO_FULL);
|
||||
#if 1
|
||||
if (s[i] == '\0')
|
||||
{
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
if (s[i] == '\n')
|
||||
{
|
||||
*AMAZON_ASC_TBUF = '\r';
|
||||
amazon_writel('\r', AMAZON_ASC_TBUF);
|
||||
do
|
||||
{
|
||||
fifocnt = (*AMAZON_ASC_FSTAT &
|
||||
fifocnt = (amazon_readl(AMAZON_ASC_FSTAT) &
|
||||
ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF;
|
||||
} while (fifocnt == AMAZONASC_TXFIFO_FULL);
|
||||
}
|
||||
*AMAZON_ASC_TBUF = s[i];
|
||||
amazon_writel(s[i], AMAZON_ASC_TBUF);
|
||||
i++;
|
||||
} /* for */
|
||||
}
|
||||
|
||||
/* restore the IRQ */
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
|
|
@ -619,7 +549,7 @@ amazonasc_console_get_options(struct uart_port *port, int *baud, int *parity, in
|
|||
{
|
||||
u_int lcr_h;
|
||||
|
||||
lcr_h = *AMAZON_ASC_CON;
|
||||
lcr_h = amazon_readl(AMAZON_ASC_CON);
|
||||
/* do this only if the ASC is turned on */
|
||||
if (lcr_h & ASCCON_R) {
|
||||
u_int quot, div, fdiv, frac;
|
||||
|
|
@ -638,13 +568,13 @@ amazonasc_console_get_options(struct uart_port *port, int *baud, int *parity, in
|
|||
else
|
||||
*bits = 8;
|
||||
|
||||
quot = *AMAZON_ASC_BTR + 1;
|
||||
quot = amazon_readl(AMAZON_ASC_BTR) + 1;
|
||||
|
||||
/* this gets hairy if the fractional divider is used */
|
||||
if (lcr_h & ASCCON_FDE)
|
||||
{
|
||||
div = 1;
|
||||
fdiv = *AMAZON_ASC_FDV;
|
||||
fdiv = amazon_readl(AMAZON_ASC_FDV);
|
||||
if (fdiv == 0)
|
||||
fdiv = 512;
|
||||
frac = 512;
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@
|
|||
|
||||
#define amazon_readl(a) readl(((u32*)(a)))
|
||||
#define amazon_writel(a,b) writel(a, ((u32*)(b)))
|
||||
#define amazon_writel_masked(a,b,c) writel((readl(((u32*)(a))) & ~b) | (c & b), ((u32*)(a)))
|
||||
|
||||
/* check ADSL link status */
|
||||
#define AMAZON_CHECK_LINK
|
||||
|
|
@ -625,11 +626,11 @@ If set and clear bit are written concurrently with 1, the associated bit is not
|
|||
|
||||
|
||||
/***ASC Port Input Select Register***/
|
||||
#define AMAZON_ASC_PISEL ((volatile u32*)(AMAZON_ASC+ 0x0004))
|
||||
#define AMAZON_ASC_PISEL (AMAZON_ASC+ 0x0004)
|
||||
#define AMAZON_ASC_PISEL_RIS (1 << 0)
|
||||
|
||||
/***ASC Control Register***/
|
||||
#define AMAZON_ASC_CON ((volatile u32*)(AMAZON_ASC+ 0x0010))
|
||||
#define AMAZON_ASC_CON (AMAZON_ASC+ 0x0010)
|
||||
#define AMAZON_ASC_CON_R (1 << 15)
|
||||
#define AMAZON_ASC_CON_LB (1 << 14)
|
||||
#define AMAZON_ASC_CON_BRS (1 << 13)
|
||||
|
|
@ -646,7 +647,7 @@ If set and clear bit are written concurrently with 1, the associated bit is not
|
|||
#define AMAZON_ASC_CON_M(value) (((( 1 << 3) - 1) & (value)) << 0)
|
||||
|
||||
/***ASC Write Hardware Modified Control Register***/
|
||||
#define AMAZON_ASC_WHBCON ((volatile u32*)(AMAZON_ASC+ 0x0050))
|
||||
#define AMAZON_ASC_WHBCON (AMAZON_ASC+ 0x0050)
|
||||
#define AMAZON_ASC_WHBCON_SETOE (1 << 13)
|
||||
#define AMAZON_ASC_WHBCON_SETFE (1 << 12)
|
||||
#define AMAZON_ASC_WHBCON_SETPE (1 << 11)
|
||||
|
|
@ -657,28 +658,28 @@ If set and clear bit are written concurrently with 1, the associated bit is not
|
|||
#define AMAZON_ASC_WHBCON_CLRREN (1 << 4)
|
||||
|
||||
/***ASC Baudrate Timer/Reload Register***/
|
||||
#define AMAZON_ASC_BTR ((volatile u32*)(AMAZON_ASC+ 0x0014))
|
||||
#define AMAZON_ASC_BTR (AMAZON_ASC+ 0x0014)
|
||||
#define AMAZON_ASC_BTR_BR_VALUE(value) (((( 1 << 13) - 1) & (value)) << 0)
|
||||
|
||||
/***ASC Fractional Divider Register***/
|
||||
#define AMAZON_ASC_FDV ((volatile u32*)(AMAZON_ASC+ 0x0018))
|
||||
#define AMAZON_ASC_FDV (AMAZON_ASC+ 0x0018)
|
||||
#define AMAZON_ASC_FDV_FD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0)
|
||||
|
||||
/***ASC IrDA Pulse Mode/Width Register***/
|
||||
#define AMAZON_ASC_PMW ((volatile u32*)(AMAZON_ASC+ 0x001C))
|
||||
#define AMAZON_ASC_PMW (AMAZON_ASC+ 0x001C)
|
||||
#define AMAZON_ASC_PMW_IRPW (1 << 8)
|
||||
#define AMAZON_ASC_PMW_PW_VALUE(value) (((( 1 << 8) - 1) & (value)) << 0)
|
||||
|
||||
/***ASC Transmit Buffer Register***/
|
||||
#define AMAZON_ASC_TBUF ((volatile u32*)(AMAZON_ASC+ 0x0020))
|
||||
#define AMAZON_ASC_TBUF (AMAZON_ASC+ 0x0020)
|
||||
#define AMAZON_ASC_TBUF_TD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0)
|
||||
|
||||
/***ASC Receive Buffer Register***/
|
||||
#define AMAZON_ASC_RBUF ((volatile u32*)(AMAZON_ASC+ 0x0024))
|
||||
#define AMAZON_ASC_RBUF (AMAZON_ASC+ 0x0024)
|
||||
#define AMAZON_ASC_RBUF_RD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0)
|
||||
|
||||
/***ASC Autobaud Control Register***/
|
||||
#define AMAZON_ASC_ABCON ((volatile u32*)(AMAZON_ASC+ 0x0030))
|
||||
#define AMAZON_ASC_ABCON (AMAZON_ASC+ 0x0030)
|
||||
#define AMAZON_ASC_ABCON_RXINV (1 << 11)
|
||||
#define AMAZON_ASC_ABCON_TXINV (1 << 10)
|
||||
#define AMAZON_ASC_ABCON_ABEM(value) (((( 1 << 2) - 1) & (value)) << 8)
|
||||
|
|
@ -689,31 +690,31 @@ If set and clear bit are written concurrently with 1, the associated bit is not
|
|||
#define AMAZON_ASC_ABCON_ABEN (1 << 0)
|
||||
|
||||
/***Receive FIFO Control Register***/
|
||||
#define AMAZON_ASC_RXFCON ((volatile u32*)(AMAZON_ASC+ 0x0040))
|
||||
#define AMAZON_ASC_RXFCON (AMAZON_ASC+ 0x0040)
|
||||
#define AMAZON_ASC_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8)
|
||||
#define AMAZON_ASC_RXFCON_RXTMEN (1 << 2)
|
||||
#define AMAZON_ASC_RXFCON_RXFFLU (1 << 1)
|
||||
#define AMAZON_ASC_RXFCON_RXFEN (1 << 0)
|
||||
|
||||
/***Transmit FIFO Control Register***/
|
||||
#define AMAZON_ASC_TXFCON ((volatile u32*)(AMAZON_ASC+ 0x0044))
|
||||
#define AMAZON_ASC_TXFCON (AMAZON_ASC+ 0x0044)
|
||||
#define AMAZON_ASC_TXFCON_TXFITL(value) (((( 1 << 6) - 1) & (value)) << 8)
|
||||
#define AMAZON_ASC_TXFCON_TXTMEN (1 << 2)
|
||||
#define AMAZON_ASC_TXFCON_TXFFLU (1 << 1)
|
||||
#define AMAZON_ASC_TXFCON_TXFEN (1 << 0)
|
||||
|
||||
/***FIFO Status Register***/
|
||||
#define AMAZON_ASC_FSTAT ((volatile u32*)(AMAZON_ASC+ 0x0048))
|
||||
#define AMAZON_ASC_FSTAT (AMAZON_ASC+ 0x0048)
|
||||
#define AMAZON_ASC_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8)
|
||||
#define AMAZON_ASC_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0)
|
||||
|
||||
/***ASC Write HW Modified Autobaud Control Register***/
|
||||
#define AMAZON_ASC_WHBABCON ((volatile u32*)(AMAZON_ASC+ 0x0054))
|
||||
#define AMAZON_ASC_WHBABCON (AMAZON_ASC+ 0x0054)
|
||||
#define AMAZON_ASC_WHBABCON_SETABEN (1 << 1)
|
||||
#define AMAZON_ASC_WHBABCON_CLRABEN (1 << 0)
|
||||
|
||||
/***ASC Autobaud Status Register***/
|
||||
#define AMAZON_ASC_ABSTAT ((volatile u32*)(AMAZON_ASC+ 0x0034))
|
||||
#define AMAZON_ASC_ABSTAT (AMAZON_ASC+ 0x0034)
|
||||
#define AMAZON_ASC_ABSTAT_DETWAIT (1 << 4)
|
||||
#define AMAZON_ASC_ABSTAT_SCCDET (1 << 3)
|
||||
#define AMAZON_ASC_ABSTAT_SCSDET (1 << 2)
|
||||
|
|
@ -721,7 +722,7 @@ If set and clear bit are written concurrently with 1, the associated bit is not
|
|||
#define AMAZON_ASC_ABSTAT_FCSDET (1 << 0)
|
||||
|
||||
/***ASC Write HW Modified Autobaud Status Register***/
|
||||
#define AMAZON_ASC_WHBABSTAT ((volatile u32*)(AMAZON_ASC+ 0x0058))
|
||||
#define AMAZON_ASC_WHBABSTAT (AMAZON_ASC+ 0x0058)
|
||||
#define AMAZON_ASC_WHBABSTAT_SETDETWAIT (1 << 9)
|
||||
#define AMAZON_ASC_WHBABSTAT_CLRDETWAIT (1 << 8)
|
||||
#define AMAZON_ASC_WHBABSTAT_SETSCCDET (1 << 7)
|
||||
|
|
@ -734,15 +735,15 @@ If set and clear bit are written concurrently with 1, the associated bit is not
|
|||
#define AMAZON_ASC_WHBABSTAT_CLRFCSDET (1 << 0)
|
||||
|
||||
/***ASC Clock Control Register***/
|
||||
#define AMAZON_ASC_CLC ((volatile u32*)(AMAZON_ASC+ 0x0000))
|
||||
#define AMAZON_ASC_CLC (AMAZON_ASC+ 0x0000)
|
||||
#define AMAZON_ASC_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8)
|
||||
#define AMAZON_ASC_CLC_DISS (1 << 1)
|
||||
#define AMAZON_ASC_CLC_DISR (1 << 0)
|
||||
|
||||
/***ASC IRNCR0 **/
|
||||
#define AMAZON_ASC_IRNCR0 ((volatile u32*)(AMAZON_ASC+ 0x00FC))
|
||||
#define AMAZON_ASC_IRNCR0 (AMAZON_ASC+ 0x00FC)
|
||||
/***ASC IRNCR1 **/
|
||||
#define AMAZON_ASC_IRNCR1 ((volatile u32*)(AMAZON_ASC+ 0x00F8))
|
||||
#define AMAZON_ASC_IRNCR1 (AMAZON_ASC+ 0x00F8)
|
||||
#define ASC_IRNCR_TIR 0x1
|
||||
#define ASC_IRNCR_RIR 0x2
|
||||
#define ASC_IRNCR_EIR 0x4
|
||||
|
|
|
|||
Loading…
Reference in a new issue