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mpc83xx: add support for 3.6

Browse source 
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 34889
This commit is contained in:
Gabor Juhos 2012-12-26 10:40:48 +00:00
parent e537b8a093
commit c4c8307ca1
11 changed files with 4535 additions and 0 deletions
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399
target/linux/mpc83xx/config-3.6 Normal file
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@ -0,0 +1,399 @@
# CONFIG_40x is not set
# CONFIG_44x is not set
CONFIG_6xx=y
CONFIG_8xxx_WDT=y
# CONFIG_ADVANCED_OPTIONS is not set
# CONFIG_ALTIVEC is not set
# CONFIG_AMIGAONE is not set
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
CONFIG_ARCH_HAS_ILOG2_U32=y
CONFIG_ARCH_HAS_WALK_MEMORY=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_SUPPORTS_MSI=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
# CONFIG_ARPD is not set
# CONFIG_ASP834x is not set
CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
CONFIG_ATA=y
CONFIG_AUDIT_ARCH=y
CONFIG_BLK_DEV_SD=y
# CONFIG_BOOTX_TEXT is not set
CONFIG_BOUNCE=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_CMDLINE="console=ttyS0,115200 rootfstype=squashfs,yaffs2,jffs2"
CONFIG_CMDLINE_BOOL=y
CONFIG_COMPAT_BRK=y
CONFIG_CONFIGFS_FS=m
CONFIG_CRC16=m
CONFIG_CRC7=m
CONFIG_CRC_CCITT=y
CONFIG_CRC_ITU_T=m
CONFIG_CRC_T10DIF=m
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_BLKCIPHER2=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_DEFLATE=m
CONFIG_CRYPTO_DES=m
CONFIG_CRYPTO_DEV_TALITOS=y
CONFIG_CRYPTO_GF128MUL=m
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_HMAC=m
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_MD5=m
CONFIG_CRYPTO_PCOMP2=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_SHA1=m
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_DEADLINE is not set
CONFIG_DEFAULT_IOSCHED="cfq"
CONFIG_DEFAULT_UIMAGE=y
CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
CONFIG_DMADEVICES=y
CONFIG_DMA_ENGINE=y
CONFIG_DTC=y
# CONFIG_DW_DMAC is not set
# CONFIG_E200 is not set
CONFIG_EARLY_PRINTK=y
# CONFIG_EMBEDDED6xx is not set
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_EPAPR_BOOT is not set
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_FIXED_PHY=y
CONFIG_FSL_DMA=y
CONFIG_FSL_EMB_PERFMON=y
CONFIG_FSL_GTM=y
CONFIG_FSL_LBC=y
CONFIG_FSL_PCI=y
CONFIG_FSL_PQ_MDIO=y
CONFIG_FSL_SOC=y
# CONFIG_FSL_ULI1575 is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_GENERIC_ACL=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_IO=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_ISA_DMA=y
CONFIG_GENERIC_NVRAM=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
# CONFIG_GENERIC_TBSYNC is not set
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GEN_RTC=y
# CONFIG_GEN_RTC_X is not set
# CONFIG_GE_FPGA is not set
CONFIG_GIANFAR=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_MPC8XXX=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HAMRADIO is not set
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
# CONFIG_HAS_RAPIDIO is not set
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_DMA_ATTRS=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_HAVE_GENERIC_HARDIRQS=y
CONFIG_HAVE_IDE=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_IRQ_WORK=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HW_RANDOM=y
CONFIG_HZ=250
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
CONFIG_INET_AH=m
CONFIG_INET_DIAG=m
CONFIG_INET_ESP=m
CONFIG_INET_IPCOMP=m
CONFIG_INET_LRO=y
CONFIG_INET_TCP_DIAG=m
CONFIG_INET_TUNNEL=m
CONFIG_INET_XFRM_MODE_BEET=m
CONFIG_INET_XFRM_MODE_TRANSPORT=m
CONFIG_INET_XFRM_MODE_TUNNEL=m
CONFIG_INET_XFRM_TUNNEL=m
CONFIG_INITRAMFS_SOURCE=""
CONFIG_INPUT=y
# CONFIG_INPUT_MISC is not set
# CONFIG_IOMMU_HELPER is not set
CONFIG_IOSCHED_CFQ=y
CONFIG_IPIC=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_IP_ROUTE_CLASSID=y
CONFIG_IP_SCTP=m
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_ISA_DMA_API=y
# CONFIG_ISDN is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
# CONFIG_JFFS2_LZMA is not set
# CONFIG_JFFS2_SUMMARY is not set
CONFIG_JFFS2_ZLIB=y
CONFIG_KERNEL_START=0xc0000000
# CONFIG_KMETER1 is not set
# CONFIG_LBDAF is not set
# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
# CONFIG_LEDS_TRIGGER_NETDEV is not set
# CONFIG_LEDS_TRIGGER_TIMER is not set
CONFIG_LIBCRC32C=y
CONFIG_LOG_BUF_SHIFT=15
CONFIG_LOWMEM_SIZE=0x30000000
# CONFIG_MATH_EMULATION is not set
CONFIG_MAX_ACTIVE_REGIONS=32
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BOARDINFO=y
CONFIG_MDIO_GPIO=y
# CONFIG_MMIO_NVRAM is not set
# CONFIG_MPC512X_DMA is not set
CONFIG_MPC830x_RDB=y
CONFIG_MPC831x_RDB=y
CONFIG_MPC832x_MDS=y
CONFIG_MPC832x_RDB=y
CONFIG_MPC834x_ITX=y
CONFIG_MPC834x_MDS=y
CONFIG_MPC836x_MDS=y
CONFIG_MPC836x_RDK=y
CONFIG_MPC837x_MDS=y
CONFIG_MPC837x_RDB=y
# CONFIG_MPIC is not set
# CONFIG_MPIC_U3_HT_IRQS is not set
# CONFIG_MPIC_WEIRD is not set
CONFIG_MTD_BLOCK2MTD=y
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_FSL_ELBC=y
# CONFIG_MTD_NAND_FSL_IFC is not set
CONFIG_MTD_NAND_FSL_UPM=y
CONFIG_MTD_NAND_RB_PPC=y
CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_PHYSMAP_OF=y
# CONFIG_MTD_SM_COMMON is not set
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_RESERVE=1
# CONFIG_MTD_UBI_GLUEBI is not set
CONFIG_MTD_UBI_WL_THRESHOLD=4096
# CONFIG_NEED_DMA_MAP_STATE is not set
# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set
CONFIG_NEED_PER_CPU_KM=y
CONFIG_NEED_SG_DMA_LENGTH=y
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_FLOW=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_RSVP=m
CONFIG_NET_CLS_RSVP6=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_U32=m
# CONFIG_NET_DMA is not set
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_CMP=m
CONFIG_NET_EMATCH_META=m
CONFIG_NET_EMATCH_NBYTE=m
CONFIG_NET_EMATCH_TEXT=m
CONFIG_NET_EMATCH_U32=m
CONFIG_NET_IPIP=m
CONFIG_NET_SCH_CBQ=m
CONFIG_NET_SCH_DSMARK=m
CONFIG_NET_SCH_GRED=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFQ=m
CONFIG_NET_SCH_TBF=m
CONFIG_NET_SCH_TEQL=m
# CONFIG_NONSTATIC_KERNEL is not set
CONFIG_NR_IRQS=512
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_DEVICE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_MDIO=y
CONFIG_OF_MTD=y
CONFIG_OF_NET=y
CONFIG_OF_PCI=y
CONFIG_OF_PCI_IRQ=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_PAGE_OFFSET=0xc0000000
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_PATA_RB_PPC=y
CONFIG_PCI=y
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_MSI=y
CONFIG_PHYLIB=y
CONFIG_PHYSICAL_START=0x00000000
CONFIG_PPC=y
CONFIG_PPC32=y
# CONFIG_PPC64 is not set
# CONFIG_PPC_82xx is not set
CONFIG_PPC_83xx=y
# CONFIG_PPC_85xx is not set
# CONFIG_PPC_86xx is not set
# CONFIG_PPC_8xx is not set
# CONFIG_PPC_970_NAP is not set
CONFIG_PPC_BOOK3S=y
CONFIG_PPC_BOOK3S_32=y
# CONFIG_PPC_CELL is not set
# CONFIG_PPC_CELL_NATIVE is not set
# CONFIG_PPC_CHRP is not set
CONFIG_PPC_CLOCK=y
# CONFIG_PPC_DCR_MMIO is not set
# CONFIG_PPC_DCR_NATIVE is not set
CONFIG_PPC_DISABLE_WERROR=y
# CONFIG_PPC_EARLY_DEBUG is not set
# CONFIG_PPC_EPAPR_HV_PIC is not set
CONFIG_PPC_FPU=y
CONFIG_PPC_HAVE_PMU_SUPPORT=y
# CONFIG_PPC_I8259 is not set
# CONFIG_PPC_ICP_HV is not set
# CONFIG_PPC_ICP_NATIVE is not set
# CONFIG_PPC_ICS_RTAS is not set
CONFIG_PPC_INDIRECT_PCI=y
CONFIG_PPC_LIB_RHEAP=y
# CONFIG_PPC_MM_SLICES is not set
# CONFIG_PPC_MPC106 is not set
# CONFIG_PPC_MPC512x is not set
# CONFIG_PPC_MPC52xx is not set
CONFIG_PPC_MPC831x=y
CONFIG_PPC_MPC832x=y
CONFIG_PPC_MPC834x=y
CONFIG_PPC_MPC837x=y
CONFIG_PPC_MSI_BITMAP=y
CONFIG_PPC_OF=y
CONFIG_PPC_OF_BOOT_TRAMPOLINE=y
# CONFIG_PPC_P7_NAP is not set
CONFIG_PPC_PCI_CHOICE=y
# CONFIG_PPC_PMAC is not set
# CONFIG_PPC_RTAS is not set
CONFIG_PPC_STD_MMU=y
CONFIG_PPC_STD_MMU_32=y
CONFIG_PPC_UDBG_16550=y
# CONFIG_PPC_WSP is not set
# CONFIG_PPC_XICS is not set
# CONFIG_PQ2ADS is not set
# CONFIG_PREEMPT_RCU is not set
CONFIG_PROC_DEVICETREE=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_QE_GPIO=y
CONFIG_QUICC_ENGINE=y
CONFIG_RB_IOMAP=y
CONFIG_RB_PPC=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
# CONFIG_SBC834x is not set
CONFIG_SCHED_HRTICK=y
CONFIG_SCSI=y
# CONFIG_SCSI_LOWLEVEL is not set
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_PROC_FS is not set
# CONFIG_SCTP_DBG_MSG is not set
# CONFIG_SCTP_DBG_OBJCNT is not set
CONFIG_SCTP_HMAC_MD5=y
# CONFIG_SCTP_HMAC_NONE is not set
# CONFIG_SCTP_HMAC_SHA1 is not set
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_PCI=y
CONFIG_SERIAL_QE=y
CONFIG_SERIO=y
CONFIG_SERIO_I8042=y
CONFIG_SERIO_PCIPS2=y
CONFIG_SERIO_RAW=y
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_XILINX_XPS_PS2 is not set
CONFIG_SIMPLE_GPIO=y
# CONFIG_SLAB is not set
CONFIG_SLOB=y
CONFIG_SOCK_DIAG=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_MASTER=y
# CONFIG_SWAP is not set
# CONFIG_SWIOTLB is not set
CONFIG_TASK_SIZE=0xc0000000
# CONFIG_TAU is not set
CONFIG_TEXTSEARCH_BM=m
CONFIG_TEXTSEARCH_FSM=m
CONFIG_TEXTSEARCH_KMP=m
CONFIG_TMPFS_POSIX_ACL=y
# CONFIG_UBIFS_FS is not set
CONFIG_UCC=y
CONFIG_UCC_FAST=y
CONFIG_UCC_GETH=y
CONFIG_UCC_SLOW=y
# CONFIG_UCC_TDM is not set
# CONFIG_UGETH_TX_ON_DEMAND is not set
CONFIG_USB_ARCH_HAS_XHCI=y
CONFIG_VIA_VELOCITY=y
CONFIG_VITESSE_PHY=y
CONFIG_VITESSE_PHY_8601_SKEW=y
CONFIG_WAN_ROUTER=m
CONFIG_WORD_SIZE=32
CONFIG_XFRM_ALGO=m
CONFIG_XFRM_IPCOMP=m
CONFIG_YAFFS_9BYTE_TAGS=y
# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
CONFIG_YAFFS_AUTO_YAFFS2=y
# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
CONFIG_YAFFS_DISABLE_TAGS_ECC=y
# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
CONFIG_YAFFS_FS=y
CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
CONFIG_YAFFS_XATTR=y
CONFIG_YAFFS_YAFFS1=y
CONFIG_YAFFS_YAFFS2=y

85
target/linux/mpc83xx/patches-3.6/100-powerpc_create_fit_uImages.patch Normal file
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@ -0,0 +1,85 @@
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -155,7 +155,9 @@ all: zImage
# With make 3.82 we cannot mix normal and wildcard targets
BOOT_TARGETS1 := zImage zImage.initrd uImage
-BOOT_TARGETS2 := zImage% dtbImage% treeImage.% cuImage.% simpleImage.% uImage.%
+BOOT_TARGETS2 := uImage.fit.% zImage% dtbImage% treeImage.% cuImage.% \
+ simpleImage.% uImage.%
+
PHONY += $(BOOT_TARGETS1) $(BOOT_TARGETS2)
@@ -188,6 +190,7 @@ define archhelp
@echo '* zImage - Build default images selected by kernel config'
@echo ' zImage.* - Compressed kernel image (arch/$(ARCH)/boot/zImage.*)'
@echo ' uImage - U-Boot native image format'
+ @echo ' uImage.fit.<dt> - U-Boot Flattened Image Tree image format'
@echo ' cuImage.<dt> - Backwards compatible U-Boot image for older'
@echo ' versions which do not support device trees'
@echo ' dtbImage.<dt> - zImage with an embedded device tree blob'
--- a/arch/powerpc/boot/.gitignore
+++ b/arch/powerpc/boot/.gitignore
@@ -18,6 +18,7 @@ kernel-vmlinux.strip.c
kernel-vmlinux.strip.gz
mktree
uImage
+uImage.fit.*
cuImage.*
dtbImage.*
treeImage.*
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -337,6 +337,9 @@ $(obj)/uImage.initrd.%: vmlinux $(obj)/%
$(obj)/uImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
$(call if_changed,wrap,uboot-$*,,$(obj)/$*.dtb)
+$(obj)/uImage.fit.%: vmlinux $(obj)/%.dtb $(wrapperbits)
+ $(call if_changed,wrap,uboot.fit,,$(obj)/$*.dtb)
+
$(obj)/cuImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
$(call if_changed,wrap,cuboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
@@ -374,6 +377,7 @@ install: $(CONFIGURE) $(addprefix $(obj)
# anything not in $(targets)
clean-files += $(image-) $(initrd-) cuImage.* dtbImage.* treeImage.* \
+ uImage.* \
zImage zImage.initrd zImage.chrp zImage.coff zImage.holly \
zImage.miboot zImage.pmac zImage.pseries \
zImage.maple simpleImage.* otheros.bld *.dtb
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -47,6 +47,9 @@ CROSS=
# mkimage wrapper script
MKIMAGE=$srctree/scripts/mkuboot.sh
+# script to generate an .its file for uImage.fit.* images
+MKITS=$srctree/scripts/mkits.sh
+
# directory for object and other files used by this script
object=arch/powerpc/boot
objbin=$object
@@ -336,6 +339,21 @@ uboot-obs600)
if [ -z "$cacheit" ]; then
rm -f "$vmz"
fi
+ exit 0
+ ;;
+uboot.fit)
+ rm -f "$ofile"
+ ${MKITS} -A ppc -C gzip -a $membase -e $membase -v $version \
+ -d "$srctree/$dtb" -k "$srctree/$vmz" -o "$object/uImage.its"
+
+ # mkimage calls dtc for FIT images so use kernel dtc if necessary
+ export PATH=$PATH:$srctree/scripts/dtc
+
+ ${MKIMAGE} -f "$object/uImage.its" "$ofile"
+ rm "$object/uImage.its"
+ if [ -z "$cacheit" ]; then
+ rm -f "$vmz"
+ fi
exit 0
;;
esac

21
target/linux/mpc83xx/patches-3.6/101-mpc8377_wlan-dts-add-gpio-leds.patch Normal file
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@ -0,0 +1,21 @@
--- a/arch/powerpc/boot/dts/mpc8377_wlan.dts
+++ b/arch/powerpc/boot/dts/mpc8377_wlan.dts
@@ -462,4 +462,18 @@
0 0x00800000>;
};
};
+
+ leds {
+ compatible = "gpio-leds";
+
+ diag {
+ gpios = <&gpio1 9 1>;
+ default-state = "off";
+ };
+
+ wireless {
+ gpios = <&gpio1 10 1>;
+ default-state = "off";
+ };
+ };
};

93
target/linux/mpc83xx/patches-3.6/110-vitesse_8601.patch Normal file
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@ -0,0 +1,93 @@
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -64,6 +64,12 @@ config VITESSE_PHY
---help---
Currently supports the vsc8244
+config VITESSE_PHY_8601_SKEW
+ bool "Enable skew timing to vsc8601"
+ depends on VITESSE_PHY
+ ---help---
+ Apply clock timing adjustments for vsc8601
+
config SMSC_PHY
tristate "Drivers for SMSC PHYs"
---help---
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -26,6 +26,11 @@
#define MII_VSC8244_EXTCON1_TX_SKEW 0x0800
#define MII_VSC8244_EXTCON1_RX_SKEW 0x0200
+/* EXT_CON1 Register values for VSC8601 */
+#define MII_VSC8601_EXTCON1_INIT 0x0000
+#define MII_VSC8601_EXTCON1_SKEW 0x0100
+#define MII_VSC8601_EXTCON1_ACTIPHY 0x0020
+
/* Vitesse Interrupt Mask Register */
#define MII_VSC8244_IMASK 0x19
#define MII_VSC8244_IMASK_IEN 0x8000
@@ -56,6 +61,7 @@
#define PHY_ID_VSC8244 0x000fc6c0
#define PHY_ID_VSC8221 0x000fc550
+#define PHY_ID_VSC8601 0x00070420
MODULE_DESCRIPTION("Vitesse PHY driver");
MODULE_AUTHOR("Kriston Carson");
@@ -98,10 +104,34 @@ static int vsc824x_config_init(struct ph
return err;
}
+static int vsc8601_config_init(struct phy_device *phydev)
+{
+ int err;
+ int extcon;
+
+ err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
+ MII_VSC8244_AUXCONSTAT_INIT);
+
+ if (err < 0)
+ return err;
+
+#ifdef CONFIG_VITESSE_PHY_8601_SKEW
+ extcon = phy_read(phydev, MII_VSC8244_EXT_CON1);
+ if (err < 0)
+ return err;
+
+ extcon |= MII_VSC8601_EXTCON1_SKEW;
+
+ err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);
+#endif
+
+ return err;
+}
+
static int vsc824x_ack_interrupt(struct phy_device *phydev)
{
int err = 0;
-
+
/*
* Don't bother to ACK the interrupts if interrupts
* are disabled. The 824x cannot clear the interrupts
@@ -177,6 +207,19 @@ static struct phy_driver vsc82xx_driver[
.ack_interrupt = &vsc824x_ack_interrupt,
.config_intr = &vsc82xx_config_intr,
.driver = { .owner = THIS_MODULE,},
+}, {
+ /* Vitesse 8601 */
+ .phy_id = PHY_ID_VSC8601,
+ .name = "Vitesse VSC8601",
+ .phy_id_mask = 0x000ffff8,
+ .features = PHY_GBIT_FEATURES,
+ .flags = PHY_HAS_INTERRUPT,
+ .config_init = &vsc8601_config_init,
+ .config_aneg = &genphy_config_aneg,
+ .read_status = &genphy_read_status,
+ .ack_interrupt = &vsc824x_ack_interrupt,
+ .config_intr = &vsc82xx_config_intr,
+ .driver = { .owner = THIS_MODULE,},
} };
static int __init vsc82xx_init(void)

20
target/linux/mpc83xx/patches-3.6/111-etsec27_war.patch Normal file
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@ -0,0 +1,20 @@
--- a/drivers/net/ethernet/freescale/gianfar.c
+++ b/drivers/net/ethernet/freescale/gianfar.c
@@ -1004,7 +1004,16 @@ static int gfar_probe(struct platform_de
/* We need to delay at least 3 TX clocks */
udelay(2);
- tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
+ if ((mfspr(SPRN_SVR) & 0xffff) >= 0x0011) {
+ tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
+ } else {
+ /*
+ * Do not enable flow control on chips earlier than rev 1.1,
+ * because of the eTSEC27 erratum
+ */
+ tempval = 0;
+ }
+
gfar_write(&regs->maccfg1, tempval);
/* Initialize MACCFG2. */

1307
target/linux/mpc83xx/patches-3.6/120-ucc_tdm.patch Normal file
View file

File diff suppressed because it is too large Load diff

1318
target/linux/mpc83xx/patches-3.6/200-powerpc-add-rbppc-support.patch Normal file
View file

File diff suppressed because it is too large Load diff

263
target/linux/mpc83xx/patches-3.6/201-powerpc-add-rb_iomap.patch Normal file
View file

@ -0,0 +1,263 @@
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -117,9 +117,11 @@ obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.
obj-$(CONFIG_8XX_MINIMAL_FPEMU) += softemu8xx.o
+ifneq ($(CONFIG_RB_IOMAP),y)
ifneq ($(CONFIG_PPC_INDIRECT_IO),y)
obj-y += iomap.o
endif
+endif
obj-$(CONFIG_PPC64) += $(obj64-y)
obj-$(CONFIG_PPC32) += $(obj32-y)
--- a/arch/powerpc/platforms/83xx/Makefile
+++ b/arch/powerpc/platforms/83xx/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_MCU_MPC8349EMITX) += mcu_mp
obj-$(CONFIG_MPC830x_RDB) += mpc830x_rdb.o
obj-$(CONFIG_MPC831x_RDB) += mpc831x_rdb.o
obj-$(CONFIG_MPC832x_RDB) += mpc832x_rdb.o
+obj-$(CONFIG_RB_PPC) += rbppc.o
obj-$(CONFIG_MPC834x_MDS) += mpc834x_mds.o
obj-$(CONFIG_MPC834x_ITX) += mpc834x_itx.o
obj-$(CONFIG_MPC836x_MDS) += mpc836x_mds.o
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -191,6 +191,10 @@ config PPC_INDIRECT_MMIO
config PPC_IO_WORKAROUNDS
bool
+config RB_IOMAP
+ bool
+ default y if RB_PPC
+
source "drivers/cpufreq/Kconfig"
menu "CPU Frequency drivers"
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -69,3 +69,6 @@ subdir-ccflags-$(CONFIG_PPC_WERROR) := -
obj-$(CONFIG_PPC_XICS) += xics/
obj-$(CONFIG_GE_FPGA) += ge/
+
+obj-$(CONFIG_RB_IOMAP) += rb_iomap.o
+
--- /dev/null
+++ b/arch/powerpc/sysdev/rb_iomap.c
@@ -0,0 +1,204 @@
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/mm.h>
+#include <asm/io.h>
+
+#define LOCALBUS_START 0x40000000
+#define LOCALBUS_MASK 0x007fffff
+#define LOCALBUS_REGMASK 0x001fffff
+
+static void __iomem *localbus_base;
+
+static inline int is_localbus(void __iomem *addr)
+{
+ return ((unsigned) addr & ~LOCALBUS_MASK) == LOCALBUS_START;
+}
+
+static inline unsigned localbus_regoff(unsigned reg) {
+ return (reg << 16) | (((reg ^ 8) & 8) << 17);
+}
+
+static inline void __iomem *localbus_addr(void __iomem *addr)
+{
+ return localbus_base
+ + ((unsigned) addr & LOCALBUS_MASK & ~LOCALBUS_REGMASK)
+ + localbus_regoff((unsigned) addr & LOCALBUS_REGMASK);
+}
+
+unsigned int ioread8(void __iomem *addr)
+{
+ if (is_localbus(addr))
+ return in_be16(localbus_addr(addr)) >> 8;
+ return readb(addr);
+}
+EXPORT_SYMBOL(ioread8);
+
+unsigned int ioread16(void __iomem *addr)
+{
+ if (is_localbus(addr))
+ return le16_to_cpu(in_be16(localbus_addr(addr)));
+ return readw(addr);
+}
+EXPORT_SYMBOL(ioread16);
+
+unsigned int ioread16be(void __iomem *addr)
+{
+ return in_be16(addr);
+}
+EXPORT_SYMBOL(ioread16be);
+
+unsigned int ioread32(void __iomem *addr)
+{
+ return readl(addr);
+}
+EXPORT_SYMBOL(ioread32);
+
+unsigned int ioread32be(void __iomem *addr)
+{
+ return in_be32(addr);
+}
+EXPORT_SYMBOL(ioread32be);
+
+void iowrite8(u8 val, void __iomem *addr)
+{
+ if (is_localbus(addr))
+ out_be16(localbus_addr(addr), ((u16) val) << 8);
+ else
+ writeb(val, addr);
+}
+EXPORT_SYMBOL(iowrite8);
+
+void iowrite16(u16 val, void __iomem *addr)
+{
+ if (is_localbus(addr))
+ out_be16(localbus_addr(addr), cpu_to_le16(val));
+ else
+ writew(val, addr);
+}
+EXPORT_SYMBOL(iowrite16);
+
+void iowrite16be(u16 val, void __iomem *addr)
+{
+ out_be16(addr, val);
+}
+EXPORT_SYMBOL(iowrite16be);
+
+void iowrite32(u32 val, void __iomem *addr)
+{
+ writel(val, addr);
+}
+EXPORT_SYMBOL(iowrite32);
+
+void iowrite32be(u32 val, void __iomem *addr)
+{
+ out_be32(addr, val);
+}
+EXPORT_SYMBOL(iowrite32be);
+
+void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
+{
+ if (is_localbus(addr)) {
+ unsigned i;
+ void *laddr = localbus_addr(addr);
+ u8 *buf = dst;
+
+ for (i = 0; i < count; ++i) {
+ *buf++ = in_be16(laddr) >> 8;
+ }
+ } else {
+ _insb((u8 __iomem *) addr, dst, count);
+ }
+}
+EXPORT_SYMBOL(ioread8_rep);
+
+void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
+{
+ if (is_localbus(addr)) {
+ unsigned i;
+ void *laddr = localbus_addr(addr);
+ u16 *buf = dst;
+
+ for (i = 0; i < count; ++i) {
+ *buf++ = in_be16(laddr);
+ }
+ } else {
+ _insw_ns((u16 __iomem *) addr, dst, count);
+ }
+}
+EXPORT_SYMBOL(ioread16_rep);
+
+void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
+{
+ _insl_ns((u32 __iomem *) addr, dst, count);
+}
+EXPORT_SYMBOL(ioread32_rep);
+
+void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
+{
+ if (is_localbus(addr)) {
+ unsigned i;
+ void *laddr = localbus_addr(addr);
+ const u8 *buf = src;
+
+ for (i = 0; i < count; ++i) {
+ out_be16(laddr, ((u16) *buf++) << 8);
+ }
+ } else {
+ _outsb((u8 __iomem *) addr, src, count);
+ }
+}
+EXPORT_SYMBOL(iowrite8_rep);
+
+void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
+{
+ if (is_localbus(addr)) {
+ unsigned i;
+ void *laddr = localbus_addr(addr);
+ const u16 *buf = src;
+
+ for (i = 0; i < count; ++i) {
+ out_be16(laddr, *buf++);
+ }
+ } else {
+ _outsw_ns((u16 __iomem *) addr, src, count);
+ }
+}
+EXPORT_SYMBOL(iowrite16_rep);
+
+void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
+{
+ _outsl_ns((u32 __iomem *) addr, src, count);
+}
+EXPORT_SYMBOL(iowrite32_rep);
+
+void __iomem *ioport_map(unsigned long port, unsigned int len)
+{
+ return (void __iomem *) (port + _IO_BASE);
+}
+EXPORT_SYMBOL(ioport_unmap);
+
+void ioport_unmap(void __iomem *addr)
+{
+ /* Nothing to do */
+}
+EXPORT_SYMBOL(ioport_map);
+
+void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
+{
+ /* Nothing to do */
+}
+EXPORT_SYMBOL(pci_iounmap);
+
+void __iomem *localbus_map(unsigned long addr, unsigned int len)
+{
+ if (!localbus_base)
+ localbus_base = ioremap(addr & ~LOCALBUS_MASK,
+ LOCALBUS_MASK + 1);
+ return (void *) (LOCALBUS_START + (addr & LOCALBUS_MASK));
+}
+EXPORT_SYMBOL(localbus_map);
+
+void localbus_unmap(void __iomem *addr)
+{
+}
+EXPORT_SYMBOL(localbus_unmap);
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -44,6 +44,7 @@ config RB_PPC
select QUICC_ENGINE
select PPC_MPC832x
select PPC_MPC834x
+ select RB_IOMAP
help
This option enables support for MikroTik RouterBOARD 333/600 series boards.

727
target/linux/mpc83xx/patches-3.6/202-ata-add-pata_rbppc_cf-driver.patch Normal file
View file

@ -0,0 +1,727 @@
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -908,5 +908,12 @@ config PATA_LEGACY
If unsure, say N.
+config PATA_RB_PPC
+ tristate "MikroTik RB600 PATA support"
+ depends on RB_PPC
+ help
+ This option enables support for PATA devices on MikroTik RouterBOARD
+ 600 series boards.
+
endif # ATA_SFF
endif # ATA
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -90,6 +90,7 @@ obj-$(CONFIG_PATA_PALMLD) += pata_palmld
obj-$(CONFIG_PATA_PLATFORM) += pata_platform.o
obj-$(CONFIG_PATA_OF_PLATFORM) += pata_of_platform.o
obj-$(CONFIG_PATA_RB532) += pata_rb532_cf.o
+obj-$(CONFIG_PATA_RB_PPC) += pata_rbppc_cf.o
obj-$(CONFIG_PATA_RZ1000) += pata_rz1000.o
obj-$(CONFIG_PATA_SAMSUNG_CF) += pata_samsung_cf.o
--- /dev/null
+++ b/drivers/ata/pata_rbppc_cf.c
@@ -0,0 +1,699 @@
+/*
+ * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org>
+ * Copyright (C) Mikrotik 2007
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <scsi/scsi_host.h>
+#include <linux/libata.h>
+#include <linux/of_platform.h>
+#include <linux/ata_platform.h>
+#include <linux/slab.h>
+
+#define DEBUG_UPM 0
+
+#define DRV_NAME "pata_rbppc_cf"
+#define DRV_VERSION "0.0.2"
+
+#define DEV2SEL_OFFSET 0x00100000
+
+#define IMMR_LBCFG_OFFSET 0x00005000
+#define IMMR_LBCFG_SIZE 0x00001000
+
+#define LOCAL_BUS_MCMR 0x00000078
+#define MxMR_OP_MASK 0x30000000
+#define MxMR_OP_NORMAL 0x00000000
+#define MxMR_OP_WRITE 0x10000000
+#define MxMR_OP_READ 0x20000000
+#define MxMR_OP_RUN 0x30000000
+#define MxMR_LUPWAIT_LOW 0x08000000
+#define MxMR_LUPWAIT_HIGH 0x00000000
+#define MxMR_LUPWAIT_ENABLE 0x00040000
+#define MxMR_RLF_MASK 0x0003c000
+#define MxMR_RLF_SHIFT 14
+#define MxMR_WLF_MASK 0x00003c00
+#define MxMR_WLF_SHIFT 10
+#define MxMR_MAD_MASK 0x0000003f
+#define LOCAL_BUS_MDR 0x00000088
+#define LOCAL_BUS_LCRR 0x000000D4
+#define LCRR_CLKDIV_MASK 0x0000000f
+
+#define LOOP_SIZE 4
+
+#define UPM_READ_SINGLE_OFFSET 0x00
+#define UPM_WRITE_SINGLE_OFFSET 0x18
+#define UPM_DATA_SIZE 0x40
+
+#define LBT_CPUIN_MIN 0
+#define LBT_CPUOUT_MIN 1
+#define LBT_CPUOUT_MAX 2
+#define LBT_EXTDEL_MIN 3
+#define LBT_EXTDEL_MAX 4
+#define LBT_SIZE 5
+
+/* UPM machine configuration bits */
+#define N_BASE 0x00f00000
+#define N_CS 0xf0000000
+#define N_CS_H1 0xc0000000
+#define N_CS_H2 0x30000000
+#define N_WE 0x0f000000
+#define N_WE_H1 0x0c000000
+#define N_WE_H2 0x03000000
+#define N_OE 0x00030000
+#define N_OE_H1 0x00020000
+#define N_OE_H2 0x00010000
+#define WAEN 0x00001000
+#define REDO_2 0x00000100
+#define REDO_3 0x00000200
+#define REDO_4 0x00000300
+#define LOOP 0x00000080
+#define NA 0x00000008
+#define UTA 0x00000004
+#define LAST 0x00000001
+
+#define REDO_VAL(mult) (REDO_2 * ((mult) - 1))
+#define REDO_MAX_MULT 4
+
+#define READ_BASE (N_BASE | N_WE)
+#define WRITE_BASE (N_BASE | N_OE)
+#define EMPTY (N_BASE | N_CS | N_OE | N_WE | LAST)
+
+#define EOF_UPM_SETTINGS 0
+#define ANOTHER_TIMING 1
+
+#define OA_CPUIN_MIN 0x01
+#define OA_CPUOUT_MAX 0x02
+#define OD_CPUOUT_MIN 0x04
+#define OA_CPUOUT_DELTA 0x06
+#define OA_EXTDEL_MAX 0x08
+#define OD_EXTDEL_MIN 0x10
+#define OA_EXTDEL_DELTA 0x18
+#define O_MIN_CYCLE_TIME 0x20
+#define O_MINUS_PREV 0x40
+#define O_HALF_CYCLE 0x80
+
+extern void __iomem *localbus_map(unsigned long addr, unsigned int len);
+extern void localbus_unmap(void __iomem *addr);
+
+struct rbppc_cf_info {
+ unsigned lbcfg_addr;
+ unsigned clk_time_ps;
+ int cur_mode;
+ u32 lb_timings[LBT_SIZE];
+};
+static struct rbppc_cf_info *rbinfo = NULL;
+
+struct upm_setting {
+ unsigned value;
+ unsigned ns[7];
+ unsigned clk_minus;
+ unsigned group_size;
+ unsigned options;
+};
+
+static const struct upm_setting cfUpmReadSingle[] = {
+ { READ_BASE | N_OE,
+ /* t1 - ADDR setup time */
+ { 70, 50, 30, 30, 25, 15, 10 }, 0, 0, (OA_CPUOUT_DELTA |
+ OA_EXTDEL_MAX) },
+ { READ_BASE | N_OE_H1,
+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
+ { READ_BASE,
+ /* t2 - OE0 time */
+ { 290, 290, 290, 80, 70, 65, 55 }, 0, 2, (OA_CPUOUT_MAX |
+ OA_CPUIN_MIN) },
+ { READ_BASE | WAEN,
+ { 1, 1, 1, 1, 1, 0, 0 }, 0, 0, 0 },
+ { READ_BASE | UTA,
+ { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 },
+ { READ_BASE | N_OE,
+ /* t9 - ADDR hold time */
+ { 20, 15, 10, 10, 10, 10, 10 }, 0, 0, (OA_CPUOUT_DELTA |
+ OD_EXTDEL_MIN) },
+ { READ_BASE | N_OE | N_CS_H2,
+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
+ { READ_BASE | N_OE | N_CS,
+ /* t6Z -IORD data tristate */
+ { 30, 30, 30, 30, 30, 20, 20 }, 1, 1, O_MINUS_PREV },
+ { ANOTHER_TIMING,
+ /* t2i -IORD recovery time */
+ { 0, 0, 0, 70, 25, 25, 20 }, 2, 0, 0 },
+ { ANOTHER_TIMING,
+ /* CS 0 -> 1 MAX */
+ { 0, 0, 0, 0, 0, 0, 0 }, 1, 0, (OA_CPUOUT_DELTA |
+ OA_EXTDEL_MAX) },
+ { READ_BASE | N_OE | N_CS | LAST,
+ { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 },
+ { EOF_UPM_SETTINGS,
+ /* min total cycle time - includes turnaround and ALE cycle */
+ { 600, 383, 240, 180, 120, 100, 80 }, 2, 0, O_MIN_CYCLE_TIME },
+};
+
+static const struct upm_setting cfUpmWriteSingle[] = {
+ { WRITE_BASE | N_WE,
+ /* t1 - ADDR setup time */
+ { 70, 50, 30, 30, 25, 15, 10 }, 0, 0, (OA_CPUOUT_DELTA |
+ OA_EXTDEL_MAX) },
+ { WRITE_BASE | N_WE_H1,
+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
+ { WRITE_BASE,
+ /* t2 - WE0 time */
+ { 290, 290, 290, 80, 70, 65, 55 }, 0, 1, OA_CPUOUT_DELTA },
+ { WRITE_BASE | WAEN,
+ { 1, 1, 1, 1, 1, 0, 0 }, 0, 0, 0 },
+ { WRITE_BASE | N_WE,
+ /* t9 - ADDR hold time */
+ { 20, 15, 10, 10, 10, 10, 10 }, 0, 0, (OA_CPUOUT_DELTA |
+ OD_EXTDEL_MIN) },
+ { WRITE_BASE | N_WE | N_CS_H2,
+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
+ { WRITE_BASE | N_WE | N_CS,
+ /* t4 - DATA hold time */
+ { 30, 20, 15, 10, 10, 10, 10 }, 0, 1, O_MINUS_PREV },
+ { ANOTHER_TIMING,
+ /* t2i -IOWR recovery time */
+ { 0, 0, 0, 70, 25, 25, 20 }, 1, 0, 0 },
+ { ANOTHER_TIMING,
+ /* CS 0 -> 1 MAX */
+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, (OA_CPUOUT_DELTA |
+ OA_EXTDEL_MAX) },
+ { WRITE_BASE | N_WE | N_CS | UTA | LAST,
+ { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 },
+ /* min total cycle time - includes ALE cycle */
+ { EOF_UPM_SETTINGS,
+ { 600, 383, 240, 180, 120, 100, 80 }, 1, 0, O_MIN_CYCLE_TIME },
+};
+
+static u8 rbppc_cf_check_status(struct ata_port *ap) {
+ u8 val = ioread8(ap->ioaddr.status_addr);
+ if (val == 0xF9)
+ val = 0x7F;
+ return val;
+}
+
+static u8 rbppc_cf_check_altstatus(struct ata_port *ap) {
+ u8 val = ioread8(ap->ioaddr.altstatus_addr);
+ if (val == 0xF9)
+ val = 0x7F;
+ return val;
+}
+
+static void rbppc_cf_dummy_noret(struct ata_port *ap) { }
+static int rbppc_cf_dummy_ret0(struct ata_port *ap) { return 0; }
+
+static int ps2clk(int ps, unsigned clk_time_ps) {
+ int psMaxOver;
+ if (ps <= 0) return 0;
+
+ /* round down if <= 2% over clk border, but no more than 1/4 clk cycle */
+ psMaxOver = ps * 2 / 100;
+ if (4 * psMaxOver > clk_time_ps) {
+ psMaxOver = clk_time_ps / 4;
+ }
+ return (ps + clk_time_ps - 1 - psMaxOver) / clk_time_ps;
+}
+
+static int upm_gen_ps_table(const struct upm_setting *upm,
+ int mode, struct rbppc_cf_info *info,
+ int *psFinal) {
+ int uidx;
+ int lastUpmValIdx = 0;
+ int group_start_idx = -1;
+ int group_left_num = -1;
+ int clk_time_ps = info->clk_time_ps;
+
+ for (uidx = 0; upm[uidx].value != EOF_UPM_SETTINGS; ++uidx) {
+ const struct upm_setting *us = upm + uidx;
+ unsigned opt = us->options;
+ int ps = us->ns[mode] * 1000 - us->clk_minus * clk_time_ps;
+
+ if (opt & OA_CPUIN_MIN) ps += info->lb_timings[LBT_CPUIN_MIN];
+ if (opt & OD_CPUOUT_MIN) ps -= info->lb_timings[LBT_CPUOUT_MIN];
+ if (opt & OA_CPUOUT_MAX) ps += info->lb_timings[LBT_CPUOUT_MAX];
+ if (opt & OD_EXTDEL_MIN) ps -= info->lb_timings[LBT_EXTDEL_MIN];
+ if (opt & OA_EXTDEL_MAX) ps += info->lb_timings[LBT_EXTDEL_MAX];
+
+ if (us->value == ANOTHER_TIMING) {
+ /* use longest timing from alternatives */
+ if (psFinal[lastUpmValIdx] < ps) {
+ psFinal[lastUpmValIdx] = ps;
+ }
+ ps = 0;
+ }
+ else {
+ if (us->group_size) {
+ group_start_idx = uidx;
+ group_left_num = us->group_size;
+ }
+ else if (group_left_num > 0) {
+ /* group time is divided on all group members */
+ int clk = ps2clk(ps, clk_time_ps);
+ psFinal[group_start_idx] -= clk * clk_time_ps;
+ --group_left_num;
+ }
+ if ((opt & O_MINUS_PREV) && lastUpmValIdx > 0) {
+ int clk = ps2clk(psFinal[lastUpmValIdx],
+ clk_time_ps);
+ ps -= clk * clk_time_ps;
+ }
+ lastUpmValIdx = uidx;
+ }
+ psFinal[uidx] = ps;
+ }
+ return uidx;
+}
+
+static int free_half(int ps, int clk, int clk_time_ps) {
+ if (clk < 2) return 0;
+ return (clk * clk_time_ps - ps) * 2 >= clk_time_ps;
+}
+
+static void upm_gen_clk_table(const struct upm_setting *upm,
+ int mode, int clk_time_ps,
+ int max_uidx, const int *psFinal, int *clkFinal) {
+ int clk_cycle_time;
+ int clk_total;
+ int uidx;
+
+ /* convert picoseconds to clocks */
+ clk_total = 0;
+ for (uidx = 0; uidx < max_uidx; ++uidx) {
+ int clk = ps2clk(psFinal[uidx], clk_time_ps);
+ clkFinal[uidx] = clk;
+ clk_total += clk;
+ }
+
+ /* check possibility of half cycle usage */
+ for (uidx = 1; uidx < max_uidx - 1; ++uidx) {
+ if ((upm[uidx].options & O_HALF_CYCLE) &&
+ free_half(psFinal[uidx - 1], clkFinal[uidx - 1],
+ clk_time_ps) &&
+ free_half(psFinal[uidx + 1], clkFinal[uidx + 1],
+ clk_time_ps)) {
+ ++clkFinal[uidx];
+ --clkFinal[uidx - 1];
+ --clkFinal[uidx + 1];
+ }
+ }
+
+ if ((upm[max_uidx].options & O_MIN_CYCLE_TIME) == 0) return;
+
+ /* check cycle time, adjust timings if needed */
+ clk_cycle_time = (ps2clk(upm[max_uidx].ns[mode] * 1000, clk_time_ps) -
+ upm[max_uidx].clk_minus);
+ uidx = 0;
+ while (clk_total < clk_cycle_time) {
+ /* extend all timings in round-robin to match cycle time */
+ if (clkFinal[uidx]) {
+#if DEBUG_UPM
+ printk(KERN_INFO "extending %u by 1 clk\n", uidx);
+#endif
+ ++clkFinal[uidx];
+ ++clk_total;
+ }
+ ++uidx;
+ if (uidx == max_uidx) uidx = 0;
+ }
+}
+
+static void add_data_val(unsigned val, int *clkLeft, int maxClk,
+ unsigned *data, int *dataIdx) {
+ if (*clkLeft == 0) return;
+
+ if (maxClk == 0 && *clkLeft >= LOOP_SIZE * 2) {
+ int times;
+ int times1;
+ int times2;
+
+ times = *clkLeft / LOOP_SIZE;
+ if (times > REDO_MAX_MULT * 2) times = REDO_MAX_MULT * 2;
+ times1 = times / 2;
+ times2 = times - times1;
+
+ val |= LOOP;
+ data[*dataIdx] = val | REDO_VAL(times1);
+ ++(*dataIdx);
+ data[*dataIdx] = val | REDO_VAL(times2);
+ ++(*dataIdx);
+
+ *clkLeft -= times * LOOP_SIZE;
+ return;
+ }
+
+ if (maxClk < 1 || maxClk > REDO_MAX_MULT) maxClk = REDO_MAX_MULT;
+ if (*clkLeft < maxClk) maxClk = *clkLeft;
+
+ *clkLeft -= maxClk;
+ val |= REDO_VAL(maxClk);
+
+ data[*dataIdx] = val;
+ ++(*dataIdx);
+}
+
+static int upm_gen_final_data(const struct upm_setting *upm,
+ int max_uidx, int *clkFinal, unsigned *data) {
+ int dataIdx;
+ int uidx;
+
+ dataIdx = 0;
+ for (uidx = 0; uidx < max_uidx; ++uidx) {
+ int clk = clkFinal[uidx];
+ while (clk > 0) {
+ add_data_val(upm[uidx].value, &clk, 0,
+ data, &dataIdx);
+ }
+ }
+ return dataIdx;
+}
+
+static int conv_upm_table(const struct upm_setting *upm,
+ int mode, struct rbppc_cf_info *info,
+ unsigned *data) {
+#if DEBUG_UPM
+ int uidx;
+#endif
+ int psFinal[32];
+ int clkFinal[32];
+ int max_uidx;
+ int data_len;
+
+ max_uidx = upm_gen_ps_table(upm, mode, info, psFinal);
+
+ upm_gen_clk_table(upm, mode, info->clk_time_ps, max_uidx,
+ psFinal, clkFinal);
+
+#if DEBUG_UPM
+ /* dump out debug info */
+ for (uidx = 0; uidx < max_uidx; ++uidx) {
+ if (clkFinal[uidx]) {
+ printk(KERN_INFO "idx %d val %08x clk %d ps %d\n",
+ uidx, upm[uidx].value,
+ clkFinal[uidx], psFinal[uidx]);
+ }
+ }
+#endif
+
+ data_len = upm_gen_final_data(upm, max_uidx, clkFinal, data);
+
+#if DEBUG_UPM
+ for (uidx = 0; uidx < data_len; ++uidx) {
+ printk(KERN_INFO "cf UPM x result: idx %d val %08x\n",
+ uidx, data[uidx]);
+ }
+#endif
+ return 0;
+}
+
+static int gen_upm_data(int mode, struct rbppc_cf_info *info, unsigned *data) {
+ int i;
+
+ for (i = 0; i < UPM_DATA_SIZE; ++i) {
+ data[i] = EMPTY;
+ }
+
+ if (conv_upm_table(cfUpmReadSingle, mode, info, data + UPM_READ_SINGLE_OFFSET)) {
+ return -1;
+ }
+ if (conv_upm_table(cfUpmWriteSingle, mode, info, data + UPM_WRITE_SINGLE_OFFSET)) {
+ return -1;
+ }
+ return 0;
+}
+
+static void rbppc_cf_program_upm(void *upmMemAddr, volatile void *lbcfg_mxmr, volatile void *lbcfg_mdr, const unsigned *upmData, unsigned offset, unsigned len) {
+ unsigned i;
+ unsigned mxmr;
+
+ mxmr = in_be32(lbcfg_mxmr);
+ mxmr &= ~(MxMR_OP_MASK | MxMR_MAD_MASK);
+ mxmr |= (MxMR_OP_WRITE | offset);
+ out_be32(lbcfg_mxmr, mxmr);
+ in_be32(lbcfg_mxmr); /* flush MxMR write */
+
+ for (i = 0; i < len; ++i) {
+ int to;
+ unsigned data = upmData[i + offset];
+ out_be32(lbcfg_mdr, data);
+ in_be32(lbcfg_mdr); /* flush MDR write */
+
+ iowrite8(1, upmMemAddr); /* dummy write to any CF addr */
+
+ /* wait for dummy write to complete */
+ for (to = 10000; to >= 0; --to) {
+ mxmr = in_be32(lbcfg_mxmr);
+ if (((mxmr ^ (i + 1)) & MxMR_MAD_MASK) == 0) {
+ break;
+ }
+ if (to == 0) {
+ printk(KERN_ERR "rbppc_cf_program_upm: UPMx program error at 0x%x: Timeout\n", i);
+ }
+ }
+ }
+ mxmr &= ~(MxMR_OP_MASK | MxMR_RLF_MASK | MxMR_WLF_MASK);
+ mxmr |= (MxMR_OP_NORMAL | (LOOP_SIZE << MxMR_RLF_SHIFT) | (LOOP_SIZE << MxMR_WLF_SHIFT));
+ out_be32(lbcfg_mxmr, mxmr);
+}
+
+static int rbppc_cf_update_piomode(struct ata_port *ap, int mode) {
+ struct rbppc_cf_info *info = (struct rbppc_cf_info *)ap->host->private_data;
+ void *lbcfgBase;
+ unsigned upmData[UPM_DATA_SIZE];
+
+ if (gen_upm_data(mode, info, upmData)) {
+ return -1;
+ }
+
+ lbcfgBase = ioremap_nocache(info->lbcfg_addr, IMMR_LBCFG_SIZE);
+
+ rbppc_cf_program_upm(ap->ioaddr.cmd_addr, ((char *)lbcfgBase) + LOCAL_BUS_MCMR, ((char *)lbcfgBase) + LOCAL_BUS_MDR, upmData, 0, UPM_DATA_SIZE);
+ iounmap(lbcfgBase);
+ return 0;
+}
+
+static void rbppc_cf_set_piomode(struct ata_port *ap, struct ata_device *adev)
+{
+ struct rbppc_cf_info *info = (struct rbppc_cf_info *)ap->host->private_data;
+ int mode = adev->pio_mode - XFER_PIO_0;
+
+ DPRINTK("rbppc_cf_set_piomode: PIO %d\n", mode);
+ if (mode < 0) mode = 0;
+ if (mode > 6) mode = 6;
+
+ if (info->cur_mode < 0 || info->cur_mode > mode) {
+ if (rbppc_cf_update_piomode(ap, mode) == 0) {
+ printk(KERN_INFO "rbppc_cf_set_piomode: PIO mode changed to %d\n", mode);
+ info->cur_mode = mode;
+ }
+ }
+}
+
+static struct scsi_host_template rbppc_cf_sht = {
+ ATA_BASE_SHT(DRV_NAME),
+};
+
+static struct ata_port_operations rbppc_cf_port_ops = {
+ .inherits = &ata_bmdma_port_ops,
+
+ .sff_check_status = rbppc_cf_check_status,
+ .sff_check_altstatus = rbppc_cf_check_altstatus,
+
+ .set_piomode = rbppc_cf_set_piomode,
+
+ .port_start = rbppc_cf_dummy_ret0,
+
+ .sff_irq_clear = rbppc_cf_dummy_noret,
+};
+
+static int rbppc_cf_init_info(struct platform_device *pdev, struct rbppc_cf_info *info) {
+ struct device_node *np;
+ struct resource res;
+ const u32 *u32ptr;
+ void *lbcfgBase;
+ void *lbcfg_lcrr;
+ unsigned lbc_clk_khz;
+ unsigned lbc_extra_divider = 1;
+ unsigned ccb_freq_hz;
+ unsigned lb_div;
+
+ u32ptr = of_get_property(pdev->dev.of_node, "lbc_extra_divider", NULL);
+ if (u32ptr && *u32ptr) {
+ lbc_extra_divider = *u32ptr;
+#if DEBUG_UPM
+ printk(KERN_INFO "rbppc_cf_init_info: LBC extra divider %u\n",
+ lbc_extra_divider);
+#endif
+ }
+
+ np = of_find_node_by_type(NULL, "serial");
+ if (!np) {
+ printk(KERN_ERR "rbppc_cf_init_info: No serial node found\n");
+ return -1;
+ }
+ u32ptr = of_get_property(np, "clock-frequency", NULL);
+ if (u32ptr == 0 || *u32ptr == 0) {
+ printk(KERN_ERR "rbppc_cf_init_info: Serial does not have clock-frequency\n");
+ of_node_put(np);
+ return -1;
+ }
+ ccb_freq_hz = *u32ptr;
+ of_node_put(np);
+
+ np = of_find_node_by_type(NULL, "soc");
+ if (!np) {
+ printk(KERN_ERR "rbppc_cf_init_info: No soc node found\n");
+ return -1;
+ }
+ if (of_address_to_resource(np, 0, &res)) {
+ printk(KERN_ERR "rbppc_cf_init_info: soc does not have resource\n");
+ of_node_put(np);
+ return -1;
+ }
+ info->lbcfg_addr = res.start + IMMR_LBCFG_OFFSET;
+ of_node_put(np);
+
+ lbcfgBase = ioremap_nocache(info->lbcfg_addr, IMMR_LBCFG_SIZE);
+ lbcfg_lcrr = ((char*)lbcfgBase) + LOCAL_BUS_LCRR;
+ lb_div = (in_be32(lbcfg_lcrr) & LCRR_CLKDIV_MASK) * lbc_extra_divider;
+ iounmap(lbcfgBase);
+
+ lbc_clk_khz = ccb_freq_hz / (1000 * lb_div);
+ info->clk_time_ps = 1000000000 / lbc_clk_khz;
+ printk(KERN_INFO "rbppc_cf_init_info: Using Local-Bus clock %u kHz %u ps\n",
+ lbc_clk_khz, info->clk_time_ps);
+
+ u32ptr = of_get_property(pdev->dev.of_node, "lb-timings", NULL);
+ if (u32ptr) {
+ memcpy(info->lb_timings, u32ptr, LBT_SIZE * sizeof(*u32ptr));
+#if DEBUG_UPM
+ printk(KERN_INFO "rbppc_cf_init_info: Got LB timings <%u %u %u %u %u>\n",
+ u32ptr[0], u32ptr[1], u32ptr[2], u32ptr[3], u32ptr[4]);
+#endif
+ }
+ info->cur_mode = -1;
+ return 0;
+}
+
+static int rbppc_cf_probe(struct platform_device *pdev)
+{
+ struct ata_host *host;
+ struct ata_port *ap;
+ struct rbppc_cf_info *info = NULL;
+ struct resource res;
+ void *baddr;
+ const u32 *u32ptr;
+ int irq_level = 0;
+ int err = -ENOMEM;
+
+ printk(KERN_INFO "rbppc_cf_probe: MikroTik RouterBOARD 600 series Compact Flash PATA driver, version " DRV_VERSION "\n");
+
+ if (rbinfo == NULL) {
+ info = kmalloc(sizeof(*info), GFP_KERNEL);
+ if (info == NULL) {
+ printk(KERN_ERR "rbppc_cf_probe: Out of memory\n");
+ goto err_info;
+ }
+ memset(info, 0, sizeof(*info));
+
+ if (rbppc_cf_init_info(pdev, info)) {
+ goto err_info;
+ }
+ rbinfo = info;
+ }
+
+ u32ptr = of_get_property(pdev->dev.of_node, "interrupt-at-level", NULL);
+ if (u32ptr) {
+ irq_level = *u32ptr;
+ printk(KERN_INFO "rbppc_cf_probe: IRQ level %u\n", irq_level);
+ }
+
+ if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
+ printk(KERN_ERR "rbppc_cf_probe: No reg property found\n");
+ goto err_info;
+ }
+
+ host = ata_host_alloc(&pdev->dev, 1);
+ if (!host)
+ goto err_info;
+
+ baddr = localbus_map(res.start, res.end - res.start + 1);
+ host->iomap = baddr;
+ host->private_data = rbinfo;
+
+ ap = host->ports[0];
+ ap->ops = &rbppc_cf_port_ops;
+ ap->pio_mask = 0x7F; /* PIO modes 0-6 */
+ ap->mwdma_mask = 0;
+
+ ap->ioaddr.cmd_addr = baddr;
+ ata_sff_std_ports(&ap->ioaddr);
+ ap->ioaddr.ctl_addr = ap->ioaddr.cmd_addr + 14;
+ ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
+ ap->ioaddr.bmdma_addr = 0;
+
+ err = ata_host_activate(
+ host,
+ irq_of_parse_and_map(pdev->dev.of_node, 0), ata_sff_interrupt,
+ irq_level ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW,
+ &rbppc_cf_sht);
+ if (!err) return 0;
+
+ localbus_unmap(baddr);
+err_info:
+ if (info) {
+ kfree(info);
+ rbinfo = NULL;
+ }
+ return err;
+}
+
+static int rbppc_cf_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct ata_host *host = dev_get_drvdata(dev);
+
+ if (host == NULL) return -1;
+
+ ata_host_detach(host);
+ return 0;
+}
+
+static struct of_device_id rbppc_cf_ids[] = {
+ { .name = "cf", },
+ { },
+};
+
+static struct platform_driver rbppc_cf_driver = {
+ .probe = rbppc_cf_probe,
+ .remove = rbppc_cf_remove,
+ .driver = {
+ .name = "rbppc-cf",
+ .owner = THIS_MODULE,
+ .of_match_table = rbppc_cf_ids,
+ },
+};
+
+static int __init rbppc_init(void)
+{
+ return platform_driver_register(&rbppc_cf_driver);
+}
+
+static void __exit rbppc_exit(void)
+{
+ platform_driver_unregister(&rbppc_cf_driver);
+}
+
+MODULE_AUTHOR("Mikrotikls SIA");
+MODULE_AUTHOR("Noah Fontes");
+MODULE_DESCRIPTION("MikroTik RouterBOARD 600 series Compact Flash PATA driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
+
+module_init(rbppc_init);
+module_exit(rbppc_exit);

279
target/linux/mpc83xx/patches-3.6/203-mtd-add-rbppc_nand-driver.patch Normal file
View file

@ -0,0 +1,279 @@
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -497,6 +497,13 @@ config MTD_NAND_PLATFORM
devices. You will need to provide platform-specific functions
via platform_data.
+config MTD_NAND_RB_PPC
+ tristate "MikroTik RB333/600 NAND support"
+ depends on RB_PPC
+ help
+ This option enables support for the NAND device on MikroTik
+ RouterBOARD 333/600 series boards.
+
config MTD_ALAUDA
tristate "MTD driver for Olympus MAUSB-10 and Fujifilm DPC-R1"
depends on USB
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx27
obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o
obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
+obj-$(CONFIG_MTD_NAND_RB_PPC) += rbppc_nand.o
obj-$(CONFIG_MTD_ALAUDA) += alauda.o
obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
--- /dev/null
+++ b/drivers/mtd/nand/rbppc_nand.c
@@ -0,0 +1,250 @@
+/*
+ * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org>
+ * Copyright (C) 2009 Michael Guntsche <mike@it-loops.com>
+ * Copyright (C) Mikrotik 2007
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/of_platform.h>
+#include <linux/of_device.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+
+#define DRV_NAME "rbppc_nand"
+#define DRV_VERSION "0.0.2"
+
+static struct mtd_info rmtd;
+static struct nand_chip rnand;
+
+struct rbppc_nand_info {
+ void *gpi;
+ void *gpo;
+ void *localbus;
+
+ unsigned gpio_rdy;
+ unsigned gpio_nce;
+ unsigned gpio_cle;
+ unsigned gpio_ale;
+ unsigned gpio_ctrls;
+};
+
+/* We must use the OOB layout from yaffs 1 if we want this to be recognized
+ * properly. Borrowed from the OpenWRT patches for the RB532.
+ *
+ * See <https://dev.openwrt.org/browser/trunk/target/linux/rb532/
+ * patches-2.6.28/025-rb532_nand_fixup.patch> for more details.
+ */
+static struct nand_ecclayout rbppc_nand_oob_16 = {
+ .eccbytes = 6,
+ .eccpos = { 8, 9, 10, 13, 14, 15 },
+ .oobavail = 9,
+ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
+};
+
+static struct mtd_partition rbppc_nand_partition_info[] = {
+ {
+ name: "kernel",
+ offset: 0,
+ size: 4 * 1024 * 1024,
+ },
+ {
+ name: "rootfs",
+ offset: MTDPART_OFS_NXTBLK,
+ size: MTDPART_SIZ_FULL,
+ },
+};
+
+static int rbppc_nand_dev_ready(struct mtd_info *mtd) {
+ struct nand_chip *chip = mtd->priv;
+ struct rbppc_nand_info *priv = chip->priv;
+
+ return in_be32(priv->gpi) & priv->gpio_rdy;
+}
+
+static void rbppc_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) {
+ struct nand_chip *chip = mtd->priv;
+ struct rbppc_nand_info *priv = chip->priv;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ unsigned val = in_be32(priv->gpo);
+ if (!(val & priv->gpio_nce)) {
+ /* make sure Local Bus has done NAND operations */
+ readb(priv->localbus);
+ }
+
+ if (ctrl & NAND_CLE) {
+ val |= priv->gpio_cle;
+ } else {
+ val &= ~priv->gpio_cle;
+ }
+ if (ctrl & NAND_ALE) {
+ val |= priv->gpio_ale;
+ } else {
+ val &= ~priv->gpio_ale;
+ }
+ if (!(ctrl & NAND_NCE)) {
+ val |= priv->gpio_nce;
+ } else {
+ val &= ~priv->gpio_nce;
+ }
+ out_be32(priv->gpo, val);
+
+ /* make sure GPIO output has changed */
+ val ^= in_be32(priv->gpo);
+ if (val & priv->gpio_ctrls) {
+ printk(KERN_ERR "rbppc_nand_hwcontrol: NAND GPO change failed 0x%08x\n", val);
+ }
+ }
+
+ if (cmd != NAND_CMD_NONE) writeb(cmd, chip->IO_ADDR_W);
+}
+
+static void rbppc_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ struct nand_chip *chip = mtd->priv;
+ memcpy(buf, chip->IO_ADDR_R, len);
+}
+
+static unsigned init_ok = 0;
+
+static int __devinit rbppc_nand_probe(struct platform_device *pdev)
+{
+ struct device_node *gpio;
+ struct device_node *nnand;
+ struct resource res;
+ struct rbppc_nand_info *info;
+ void *baddr;
+ const unsigned *rdy, *nce, *cle, *ale;
+
+ printk(KERN_INFO "rbppc_nand_probe: MikroTik RouterBOARD 333/600 series NAND driver, version " DRV_VERSION "\n");
+
+ info = kmalloc(sizeof(*info), GFP_KERNEL);
+
+ rdy = of_get_property(pdev->dev.of_node, "rdy", NULL);
+ nce = of_get_property(pdev->dev.of_node, "nce", NULL);
+ cle = of_get_property(pdev->dev.of_node, "cle", NULL);
+ ale = of_get_property(pdev->dev.of_node, "ale", NULL);
+
+ if (!rdy || !nce || !cle || !ale) {
+ printk(KERN_ERR "rbppc_nand_probe: GPIO properties are missing\n");
+ goto err;
+ }
+ if (rdy[0] != nce[0] || rdy[0] != cle[0] || rdy[0] != ale[0]) {
+ printk(KERN_ERR "rbppc_nand_probe: Different GPIOs are not supported\n");
+ goto err;
+ }
+
+ gpio = of_find_node_by_phandle(rdy[0]);
+ if (!gpio) {
+ printk(KERN_ERR "rbppc_nand_probe: No GPIO<%x> node found\n", *rdy);
+ goto err;
+ }
+ if (of_address_to_resource(gpio, 0, &res)) {
+ printk(KERN_ERR "rbppc_nand_probe: No reg property in GPIO found\n");
+ goto err;
+ }
+ info->gpo = ioremap_nocache(res.start, res.end - res.start + 1);
+
+ if (!of_address_to_resource(gpio, 1, &res)) {
+ info->gpi = ioremap_nocache(res.start, res.end - res.start + 1);
+ } else {
+ info->gpi = info->gpo;
+ }
+ of_node_put(gpio);
+
+ info->gpio_rdy = 1 << (31 - rdy[1]);
+ info->gpio_nce = 1 << (31 - nce[1]);
+ info->gpio_cle = 1 << (31 - cle[1]);
+ info->gpio_ale = 1 << (31 - ale[1]);
+ info->gpio_ctrls = info->gpio_nce | info->gpio_cle | info->gpio_ale;
+
+ nnand = of_find_node_by_name(NULL, "nnand");
+ if (!nnand) {
+ printk("rbppc_nand_probe: No nNAND found\n");
+ goto err;
+ }
+ if (of_address_to_resource(nnand, 0, &res)) {
+ printk("rbppc_nand_probe: No reg property in nNAND found\n");
+ goto err;
+ }
+ of_node_put(nnand);
+ info->localbus = ioremap_nocache(res.start, res.end - res.start + 1);
+
+ if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
+ printk("rbppc_nand_probe: No reg property found\n");
+ goto err;
+ }
+ baddr = ioremap_nocache(res.start, res.end - res.start + 1);
+
+ memset(&rnand, 0, sizeof(rnand));
+ rnand.cmd_ctrl = rbppc_nand_cmd_ctrl;
+ rnand.dev_ready = rbppc_nand_dev_ready;
+ rnand.read_buf = rbppc_nand_read_buf;
+ rnand.IO_ADDR_W = baddr;
+ rnand.IO_ADDR_R = baddr;
+ rnand.priv = info;
+
+ memset(&rmtd, 0, sizeof(rmtd));
+ rnand.ecc.mode = NAND_ECC_SOFT;
+ rnand.ecc.layout = &rbppc_nand_oob_16;
+ rnand.chip_delay = 25;
+ rmtd.priv = &rnand;
+ rmtd.owner = THIS_MODULE;
+
+ if (nand_scan(&rmtd, 1) && nand_scan(&rmtd, 1) && nand_scan(&rmtd, 1) && nand_scan(&rmtd, 1)) {
+ printk(KERN_ERR "rbppc_nand_probe: RouterBOARD NAND device not found\n");
+ return -ENXIO;
+ }
+
+ mtd_device_parse_register(&rmtd, NULL, 0, rbppc_nand_partition_info, 2);
+ init_ok = 1;
+ return 0;
+
+err:
+ kfree(info);
+ return -1;
+}
+
+static struct of_device_id rbppc_nand_ids[] = {
+ { .name = "nand", },
+ { },
+};
+
+static struct platform_driver rbppc_nand_driver = {
+ .probe = rbppc_nand_probe,
+ .driver = {
+ .name = "rbppc-nand",
+ .owner = THIS_MODULE,
+ .of_match_table = rbppc_nand_ids,
+ },
+};
+
+static int __init rbppc_nand_init(void)
+{
+ return platform_driver_register(&rbppc_nand_driver);
+}
+
+static void __exit rbppc_nand_exit(void)
+{
+ platform_driver_unregister(&rbppc_nand_driver);
+}
+
+MODULE_AUTHOR("Mikrotikls SIA");
+MODULE_AUTHOR("Noah Fontes");
+MODULE_AUTHOR("Michael Guntsche");
+MODULE_DESCRIPTION("MikroTik RouterBOARD 333/600 series NAND driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
+
+module_init(rbppc_nand_init);
+module_exit(rbppc_nand_exit);

23
target/linux/mpc83xx/patches-3.6/300-mpc8377_wlan-dts-add-openwrt-hacks.patch Normal file
View file

@ -0,0 +1,23 @@
--- a/arch/powerpc/boot/dts/mpc8377_wlan.dts
+++ b/arch/powerpc/boot/dts/mpc8377_wlan.dts
@@ -81,6 +81,11 @@
reg = <0x3a0000 0x3c60000>;
label = "rootfs";
};
+
+ partition1@a0000 {
+ reg = <0xa0000 0x3f60000>;
+ label = "firmware";
+ };
};
};
@@ -476,4 +481,8 @@
default-state = "off";
};
};
+
+ chosen {
+ bootargs = "console=ttyS0,115200 rootfstype=squashfs noinitrd";
+ };
};