brcm47xx: add patches for kernel 2.6.36
SVN-Revision: 23278
This commit is contained in:
Hauke Mehrtens
parent
8c33c86021
commit
badd8ffee3
27 changed files with 3329 additions and 0 deletions
160
target/linux/brcm47xx/config-2.6.36
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160
target/linux/brcm47xx/config-2.6.36
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@ -0,0 +1,160 @@
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CONFIG_32BIT=y
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# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
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# CONFIG_AR7 is not set
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# CONFIG_ARCH_HAS_ILOG2_U32 is not set
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# CONFIG_ARCH_HAS_ILOG2_U64 is not set
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
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CONFIG_ARCH_POPULATES_NODE_MAP=y
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# CONFIG_ARCH_SUPPORTS_MSI is not set
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CONFIG_ARCH_SUPPORTS_OPROFILE=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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# CONFIG_ARPD is not set
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CONFIG_B44=y
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CONFIG_B44_PCI=y
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CONFIG_B44_PCICORE_AUTOSELECT=y
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CONFIG_B44_PCI_AUTOSELECT=y
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CONFIG_BCM47XX=y
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CONFIG_BCM47XX_WDT=y
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# CONFIG_BCM63XX is not set
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CONFIG_BITREVERSE=y
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# CONFIG_BSD_PROCESS_ACCT is not set
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# CONFIG_BUG is not set
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# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
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# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
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CONFIG_CC_OPTIMIZE_FOR_SIZE=y
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CONFIG_CEVT_R4K=y
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CONFIG_CEVT_R4K_LIB=y
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CONFIG_CFE=y
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CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200"
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CONFIG_CMDLINE_BOOL=y
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# CONFIG_CMDLINE_OVERRIDE is not set
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CONFIG_CPU_HAS_PREFETCH=y
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CONFIG_CPU_HAS_SYNC=y
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CONFIG_CPU_LITTLE_ENDIAN=y
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CONFIG_CPU_MIPS32=y
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CONFIG_CPU_MIPS32_R1=y
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CONFIG_CPU_MIPSR1=y
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CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
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CONFIG_CPU_SUPPORTS_HIGHMEM=y
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CONFIG_CSRC_R4K=y
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CONFIG_CSRC_R4K_LIB=y
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CONFIG_DECOMPRESS_LZMA=y
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CONFIG_DEVPORT=y
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# CONFIG_DM9000 is not set
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CONFIG_DMA_NONCOHERENT=y
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# CONFIG_FSNOTIFY is not set
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
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CONFIG_GENERIC_CMOS_UPDATE=y
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CONFIG_GENERIC_FIND_LAST_BIT=y
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CONFIG_GENERIC_FIND_NEXT_BIT=y
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CONFIG_GENERIC_GPIO=y
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CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
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# CONFIG_HAMRADIO is not set
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# CONFIG_HARDLOCKUP_DETECTOR is not set
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CONFIG_HARDWARE_WATCHPOINTS=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT=y
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CONFIG_HAVE_ARCH_KGDB=y
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CONFIG_HAVE_DYNAMIC_FTRACE=y
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CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
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CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
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CONFIG_HAVE_GENERIC_DMA_COHERENT=y
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CONFIG_HAVE_IDE=y
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CONFIG_HAVE_KPROBES=y
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CONFIG_HAVE_KRETPROBES=y
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CONFIG_HAVE_OPROFILE=y
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CONFIG_HW_HAS_PCI=y
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CONFIG_HW_RANDOM=y
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CONFIG_HZ=250
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# CONFIG_HZ_100 is not set
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CONFIG_HZ_250=y
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CONFIG_IMAGE_CMDLINE_HACK=y
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CONFIG_INITRAMFS_SOURCE=""
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# CONFIG_IP_ROUTE_VERBOSE is not set
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CONFIG_IRQ_CPU=y
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CONFIG_KALLSYMS=y
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CONFIG_LEDS_GPIO=y
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# CONFIG_LOONGSON_MC146818 is not set
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CONFIG_LOONGSON_UART_BASE=y
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# CONFIG_MACH_DECSTATION is not set
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# CONFIG_MACH_JAZZ is not set
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# CONFIG_MACH_JZ4740 is not set
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# CONFIG_MACH_LOONGSON is not set
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# CONFIG_MACH_TX39XX is not set
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# CONFIG_MACH_TX49XX is not set
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# CONFIG_MACH_VR41XX is not set
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# CONFIG_MIKROTIK_RB532 is not set
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CONFIG_MIPS=y
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# CONFIG_MIPS_ALCHEMY is not set
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# CONFIG_MIPS_COBALT is not set
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CONFIG_MIPS_L1_CACHE_SHIFT=5
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# CONFIG_MIPS_MACHINE is not set
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# CONFIG_MIPS_MALTA is not set
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CONFIG_MIPS_MT_DISABLED=y
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# CONFIG_MIPS_SIM is not set
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CONFIG_MTD_BCM47XX=y
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CONFIG_NEED_DMA_MAP_STATE=y
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CONFIG_NO_HZ=y
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# CONFIG_NO_IOPORT is not set
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# CONFIG_NXP_STB220 is not set
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# CONFIG_NXP_STB225 is not set
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CONFIG_PAGEFLAGS_EXTENDED=y
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CONFIG_PCI=y
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CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
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CONFIG_PCI_DOMAINS=y
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CONFIG_PHYLIB=y
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# CONFIG_PMC_MSP is not set
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# CONFIG_PMC_YOSEMITE is not set
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# CONFIG_PNX8550_JBS is not set
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# CONFIG_PNX8550_STB810 is not set
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# CONFIG_POWERTV is not set
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# CONFIG_PROC_KCORE is not set
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CONFIG_SCHED_OMIT_FRAME_POINTER=y
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# CONFIG_SCSI_DMA is not set
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CONFIG_SCSI_MOD=y
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# CONFIG_SERIAL_8250_DETECT_IRQ is not set
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CONFIG_SERIAL_8250_EXTENDED=y
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# CONFIG_SERIAL_8250_MANY_PORTS is not set
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# CONFIG_SERIAL_8250_RSA is not set
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CONFIG_SERIAL_8250_SHARE_IRQ=y
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# CONFIG_SERIAL_MFD_HSU is not set
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# CONFIG_SGI_IP22 is not set
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# CONFIG_SGI_IP27 is not set
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# CONFIG_SGI_IP28 is not set
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# CONFIG_SGI_IP32 is not set
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# CONFIG_SIBYTE_BIGSUR is not set
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# CONFIG_SIBYTE_CARMEL is not set
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# CONFIG_SIBYTE_CRHINE is not set
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# CONFIG_SIBYTE_CRHONE is not set
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# CONFIG_SIBYTE_LITTLESUR is not set
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# CONFIG_SIBYTE_RHONE is not set
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# CONFIG_SIBYTE_SENTOSA is not set
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# CONFIG_SIBYTE_SWARM is not set
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CONFIG_SSB=y
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CONFIG_SSB_B43_PCI_BRIDGE=y
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CONFIG_SSB_BLOCKIO=y
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CONFIG_SSB_DRIVER_EXTIF=y
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CONFIG_SSB_DRIVER_GIGE=y
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CONFIG_SSB_DRIVER_MIPS=y
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CONFIG_SSB_DRIVER_PCICORE=y
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CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
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CONFIG_SSB_EMBEDDED=y
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CONFIG_SSB_PCICORE_HOSTMODE=y
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CONFIG_SSB_PCIHOST=y
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CONFIG_SSB_PCIHOST_POSSIBLE=y
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CONFIG_SSB_SERIAL=y
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CONFIG_SSB_SPROM=y
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CONFIG_SYS_HAS_CPU_MIPS32_R1=y
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CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
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CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
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CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
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# CONFIG_TC35815 is not set
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CONFIG_TRAD_SIGNALS=y
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CONFIG_USB_SUPPORT=y
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CONFIG_WATCHDOG_NOWAYOUT=y
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CONFIG_ZONE_DMA_FLAG=0
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@ -0,0 +1,559 @@
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/*
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* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
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* Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
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*
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* original functions for finding root filesystem from Mike Baker
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Copyright 2001-2003, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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* Flash mapping for BCM947XX boards
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/wait.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/map.h>
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#ifdef CONFIG_MTD_PARTITIONS
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#include <linux/mtd/partitions.h>
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#endif
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#include <linux/crc32.h>
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#ifdef CONFIG_SSB
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#include <linux/ssb/ssb.h>
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#endif
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#include <asm/io.h>
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#include <asm/mach-bcm47xx/nvram.h>
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#include <asm/fw/cfe/cfe_api.h>
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#define TRX_MAGIC 0x30524448 /* "HDR0" */
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#define TRX_VERSION 1
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#define TRX_MAX_LEN 0x3A0000
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#define TRX_NO_HEADER 1 /* Do not write TRX header */
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#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
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#define TRX_MAX_OFFSET 3
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struct trx_header {
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u32 magic; /* "HDR0" */
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u32 len; /* Length of file including header */
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u32 crc32; /* 32-bit CRC from flag_version to end of file */
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u32 flag_version; /* 0:15 flags, 16:31 version */
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u32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
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};
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#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
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#define NVRAM_SPACE 0x8000
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#define WINDOW_ADDR 0x1fc00000
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#define WINDOW_SIZE 0x400000
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#define BUSWIDTH 2
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#define ROUTER_NETGEAR_WGR614L 1
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#define ROUTER_NETGEAR_WNR834B 2
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#define ROUTER_NETGEAR_WNDR3300 3
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#define ROUTER_NETGEAR_WNR3500L 4
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#ifdef CONFIG_SSB
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extern struct ssb_bus ssb_bcm47xx;
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#endif
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static struct mtd_info *bcm47xx_mtd;
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static void bcm47xx_map_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
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{
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if (len==1) {
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memcpy_fromio(to, map->virt + from, len);
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} else {
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int i;
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u16 *dest = (u16 *) to;
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u16 *src = (u16 *) (map->virt + from);
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for (i = 0; i < (len / 2); i++) {
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dest[i] = src[i];
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}
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if (len & 1)
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*((u8 *)dest+len-1) = src[i] & 0xff;
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}
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}
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static struct map_info bcm47xx_map = {
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name: "Physically mapped flash",
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size: WINDOW_SIZE,
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bankwidth: BUSWIDTH,
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phys: WINDOW_ADDR,
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};
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#ifdef CONFIG_MTD_PARTITIONS
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static struct mtd_partition bcm47xx_parts[] = {
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{ name: "cfe", offset: 0, size: 0, mask_flags: MTD_WRITEABLE, },
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{ name: "linux", offset: 0, size: 0, },
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{ name: "rootfs", offset: 0, size: 0, },
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{ name: "nvram", offset: 0, size: 0, },
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{ name: NULL, },
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};
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static int __init
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find_cfe_size(struct mtd_info *mtd, size_t size)
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{
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struct trx_header *trx;
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unsigned char buf[512];
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int off;
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size_t len;
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int blocksize;
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trx = (struct trx_header *) buf;
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blocksize = mtd->erasesize;
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if (blocksize < 0x10000)
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blocksize = 0x10000;
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for (off = (128*1024); off < size; off += blocksize) {
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memset(buf, 0xe5, sizeof(buf));
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/*
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* Read into buffer
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*/
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if (mtd->read(mtd, off, sizeof(buf), &len, buf) ||
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len != sizeof(buf))
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continue;
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/* found a TRX header */
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if (le32_to_cpu(trx->magic) == TRX_MAGIC) {
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goto found;
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}
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}
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printk(KERN_NOTICE
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"%s: Couldn't find bootloader size\n",
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mtd->name);
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return -1;
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found:
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printk(KERN_NOTICE "bootloader size: %d\n", off);
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return off;
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}
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/*
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* Copied from mtdblock.c
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*
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* Cache stuff...
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*
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* Since typical flash erasable sectors are much larger than what Linux's
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* buffer cache can handle, we must implement read-modify-write on flash
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* sectors for each block write requests. To avoid over-erasing flash sectors
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* and to speed things up, we locally cache a whole flash sector while it is
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* being written to until a different sector is required.
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*/
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static void erase_callback(struct erase_info *done)
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{
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wait_queue_head_t *wait_q = (wait_queue_head_t *)done->priv;
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wake_up(wait_q);
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}
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static int erase_write (struct mtd_info *mtd, unsigned long pos,
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int len, const char *buf)
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{
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struct erase_info erase;
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|
DECLARE_WAITQUEUE(wait, current);
|
||||||
|
wait_queue_head_t wait_q;
|
||||||
|
size_t retlen;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* First, let's erase the flash block.
|
||||||
|
*/
|
||||||
|
|
||||||
|
init_waitqueue_head(&wait_q);
|
||||||
|
erase.mtd = mtd;
|
||||||
|
erase.callback = erase_callback;
|
||||||
|
erase.addr = pos;
|
||||||
|
erase.len = len;
|
||||||
|
erase.priv = (u_long)&wait_q;
|
||||||
|
|
||||||
|
set_current_state(TASK_INTERRUPTIBLE);
|
||||||
|
add_wait_queue(&wait_q, &wait);
|
||||||
|
|
||||||
|
ret = mtd->erase(mtd, &erase);
|
||||||
|
if (ret) {
|
||||||
|
set_current_state(TASK_RUNNING);
|
||||||
|
remove_wait_queue(&wait_q, &wait);
|
||||||
|
printk (KERN_WARNING "erase of region [0x%lx, 0x%x] "
|
||||||
|
"on \"%s\" failed\n",
|
||||||
|
pos, len, mtd->name);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
schedule(); /* Wait for erase to finish. */
|
||||||
|
remove_wait_queue(&wait_q, &wait);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Next, writhe data to flash.
|
||||||
|
*/
|
||||||
|
|
||||||
|
ret = mtd->write (mtd, pos, len, &retlen, buf);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
if (retlen != len)
|
||||||
|
return -EIO;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
static int __init
|
||||||
|
find_dual_image_off (struct mtd_info *mtd, size_t size)
|
||||||
|
{
|
||||||
|
struct trx_header trx;
|
||||||
|
int off, blocksize;
|
||||||
|
size_t len;
|
||||||
|
|
||||||
|
blocksize = mtd->erasesize;
|
||||||
|
if (blocksize < 0x10000)
|
||||||
|
blocksize = 0x10000;
|
||||||
|
|
||||||
|
for (off = (128*1024); off < size; off += blocksize) {
|
||||||
|
memset(&trx, 0xe5, sizeof(trx));
|
||||||
|
/*
|
||||||
|
* Read into buffer
|
||||||
|
*/
|
||||||
|
if (mtd->read(mtd, off, sizeof(trx), &len, (char *) &trx) ||
|
||||||
|
len != sizeof(trx))
|
||||||
|
continue;
|
||||||
|
/* found last TRX header */
|
||||||
|
if (le32_to_cpu(trx.magic) == TRX_MAGIC){
|
||||||
|
if (le32_to_cpu(trx.flag_version >> 16)==2){
|
||||||
|
printk("dual image TRX header found\n");
|
||||||
|
return size/2;
|
||||||
|
} else {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
static int __init
|
||||||
|
find_root(struct mtd_info *mtd, size_t size, struct mtd_partition *part)
|
||||||
|
{
|
||||||
|
struct trx_header trx, *trx2;
|
||||||
|
unsigned char buf[512], *block;
|
||||||
|
int off, blocksize;
|
||||||
|
u32 i, crc = ~0;
|
||||||
|
size_t len;
|
||||||
|
|
||||||
|
blocksize = mtd->erasesize;
|
||||||
|
if (blocksize < 0x10000)
|
||||||
|
blocksize = 0x10000;
|
||||||
|
|
||||||
|
for (off = (128*1024); off < size; off += blocksize) {
|
||||||
|
memset(&trx, 0xe5, sizeof(trx));
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Read into buffer
|
||||||
|
*/
|
||||||
|
if (mtd->read(mtd, off, sizeof(trx), &len, (char *) &trx) ||
|
||||||
|
len != sizeof(trx))
|
||||||
|
continue;
|
||||||
|
|
||||||
|
/* found a TRX header */
|
||||||
|
if (le32_to_cpu(trx.magic) == TRX_MAGIC) {
|
||||||
|
part->offset = le32_to_cpu(trx.offsets[2]) ? :
|
||||||
|
le32_to_cpu(trx.offsets[1]);
|
||||||
|
part->size = le32_to_cpu(trx.len);
|
||||||
|
|
||||||
|
part->size -= part->offset;
|
||||||
|
part->offset += off;
|
||||||
|
|
||||||
|
goto found;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
printk(KERN_NOTICE
|
||||||
|
"%s: Couldn't find root filesystem\n",
|
||||||
|
mtd->name);
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
found:
|
||||||
|
if (part->size == 0)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
if (mtd->read(mtd, part->offset, sizeof(buf), &len, buf) || len != sizeof(buf))
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
/* Move the fs outside of the trx */
|
||||||
|
part->size = 0;
|
||||||
|
|
||||||
|
if (trx.len != part->offset + part->size - off) {
|
||||||
|
/* Update the trx offsets and length */
|
||||||
|
trx.len = part->offset + part->size - off;
|
||||||
|
|
||||||
|
/* Update the trx crc32 */
|
||||||
|
for (i = (u32) &(((struct trx_header *)NULL)->flag_version); i <= trx.len; i += sizeof(buf)) {
|
||||||
|
if (mtd->read(mtd, off + i, sizeof(buf), &len, buf) || len != sizeof(buf))
|
||||||
|
return 0;
|
||||||
|
crc = crc32_le(crc, buf, min(sizeof(buf), trx.len - i));
|
||||||
|
}
|
||||||
|
trx.crc32 = crc;
|
||||||
|
|
||||||
|
/* read first eraseblock from the trx */
|
||||||
|
block = kmalloc(mtd->erasesize, GFP_KERNEL);
|
||||||
|
trx2 = (struct trx_header *) block;
|
||||||
|
if (mtd->read(mtd, off, mtd->erasesize, &len, block) || len != mtd->erasesize) {
|
||||||
|
printk("Error accessing the first trx eraseblock\n");
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
printk("Updating TRX offsets and length:\n");
|
||||||
|
printk("old trx = [0x%08x, 0x%08x, 0x%08x], len=0x%08x crc32=0x%08x\n", trx2->offsets[0], trx2->offsets[1], trx2->offsets[2], trx2->len, trx2->crc32);
|
||||||
|
printk("new trx = [0x%08x, 0x%08x, 0x%08x], len=0x%08x crc32=0x%08x\n", trx.offsets[0], trx.offsets[1], trx.offsets[2], trx.len, trx.crc32);
|
||||||
|
|
||||||
|
/* Write updated trx header to the flash */
|
||||||
|
memcpy(block, &trx, sizeof(trx));
|
||||||
|
if (mtd->unlock)
|
||||||
|
mtd->unlock(mtd, off, mtd->erasesize);
|
||||||
|
erase_write(mtd, off, mtd->erasesize, block);
|
||||||
|
if (mtd->sync)
|
||||||
|
mtd->sync(mtd);
|
||||||
|
kfree(block);
|
||||||
|
printk("Done\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
return part->size;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int get_router(void)
|
||||||
|
{
|
||||||
|
char buf[20];
|
||||||
|
u32 boardnum = 0;
|
||||||
|
u16 boardtype = 0;
|
||||||
|
u16 boardrev = 0;
|
||||||
|
u32 boardflags = 0;
|
||||||
|
u16 sdram_init = 0;
|
||||||
|
u16 cardbus = 0;
|
||||||
|
|
||||||
|
if (nvram_getenv("boardnum", buf, sizeof(buf)) >= 0 ||
|
||||||
|
cfe_getenv("boardnum", buf, sizeof(buf)) >= 0)
|
||||||
|
boardnum = simple_strtoul(buf, NULL, 0);
|
||||||
|
if (nvram_getenv("boardtype", buf, sizeof(buf)) >= 0 ||
|
||||||
|
cfe_getenv("boardtype", buf, sizeof(buf)) >= 0)
|
||||||
|
boardtype = simple_strtoul(buf, NULL, 0);
|
||||||
|
if (nvram_getenv("boardrev", buf, sizeof(buf)) >= 0 ||
|
||||||
|
cfe_getenv("boardrev", buf, sizeof(buf)) >= 0)
|
||||||
|
boardrev = simple_strtoul(buf, NULL, 0);
|
||||||
|
if (nvram_getenv("boardflags", buf, sizeof(buf)) >= 0 ||
|
||||||
|
cfe_getenv("boardflags", buf, sizeof(buf)) >= 0)
|
||||||
|
boardflags = simple_strtoul(buf, NULL, 0);
|
||||||
|
if (nvram_getenv("sdram_init", buf, sizeof(buf)) >= 0 ||
|
||||||
|
cfe_getenv("sdram_init", buf, sizeof(buf)) >= 0)
|
||||||
|
sdram_init = simple_strtoul(buf, NULL, 0);
|
||||||
|
if (nvram_getenv("cardbus", buf, sizeof(buf)) >= 0 ||
|
||||||
|
cfe_getenv("cardbus", buf, sizeof(buf)) >= 0)
|
||||||
|
cardbus = simple_strtoul(buf, NULL, 0);
|
||||||
|
|
||||||
|
if ((boardnum == 8 || boardnum == 01)
|
||||||
|
&& boardtype == 0x0472 && cardbus == 1) {
|
||||||
|
/* Netgear WNR834B, Netgear WNR834Bv2 */
|
||||||
|
return ROUTER_NETGEAR_WNR834B;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (boardnum == 01 && boardtype == 0x0472 && boardrev == 0x23) {
|
||||||
|
/* Netgear WNDR-3300 */
|
||||||
|
return ROUTER_NETGEAR_WNDR3300;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((boardnum == 83258 || boardnum == 01)
|
||||||
|
&& boardtype == 0x048e
|
||||||
|
&& (boardrev == 0x11 || boardrev == 0x10)
|
||||||
|
&& boardflags == 0x750
|
||||||
|
&& sdram_init == 0x000A) {
|
||||||
|
/* Netgear WGR614v8/L/WW 16MB ram, cfe v1.3 or v1.5 */
|
||||||
|
return ROUTER_NETGEAR_WGR614L;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((boardnum == 1 || boardnum == 3500)
|
||||||
|
&& boardtype == 0x04CF
|
||||||
|
&& (boardrev == 0x1213 || boardrev == 02)) {
|
||||||
|
/* Netgear WNR3500v2/U/L */
|
||||||
|
return ROUTER_NETGEAR_WNR3500L;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
struct mtd_partition * __init
|
||||||
|
init_mtd_partitions(struct mtd_info *mtd, size_t size)
|
||||||
|
{
|
||||||
|
int cfe_size;
|
||||||
|
int dual_image_offset = 0;
|
||||||
|
/* e.g Netgear 0x003e0000-0x003f0000 : "board_data", we exclude this
|
||||||
|
* part from our mapping to prevent overwriting len/checksum on e.g.
|
||||||
|
* Netgear WGR614v8/L/WW
|
||||||
|
*/
|
||||||
|
int board_data_size = 0;
|
||||||
|
|
||||||
|
switch (get_router()) {
|
||||||
|
case ROUTER_NETGEAR_WGR614L:
|
||||||
|
case ROUTER_NETGEAR_WNR834B:
|
||||||
|
case ROUTER_NETGEAR_WNDR3300:
|
||||||
|
case ROUTER_NETGEAR_WNR3500L:
|
||||||
|
/* Netgear: checksum is @ 0x003AFFF8 for 4M flash or checksum
|
||||||
|
* is @ 0x007AFFF8 for 8M flash
|
||||||
|
*/
|
||||||
|
board_data_size = 4 * mtd->erasesize;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((cfe_size = find_cfe_size(mtd,size)) < 0)
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
/* boot loader */
|
||||||
|
bcm47xx_parts[0].offset = 0;
|
||||||
|
bcm47xx_parts[0].size = cfe_size;
|
||||||
|
|
||||||
|
/* nvram */
|
||||||
|
if (cfe_size != 384 * 1024) {
|
||||||
|
bcm47xx_parts[3].offset = size - ROUNDUP(NVRAM_SPACE, mtd->erasesize);
|
||||||
|
bcm47xx_parts[3].size = ROUNDUP(NVRAM_SPACE, mtd->erasesize);
|
||||||
|
} else {
|
||||||
|
/* nvram (old 128kb config partition on netgear wgt634u) */
|
||||||
|
bcm47xx_parts[3].offset = bcm47xx_parts[0].size;
|
||||||
|
bcm47xx_parts[3].size = ROUNDUP(NVRAM_SPACE, mtd->erasesize);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* dual image offset*/
|
||||||
|
printk("Looking for dual image\n");
|
||||||
|
dual_image_offset=find_dual_image_off(mtd,size);
|
||||||
|
/* linux (kernel and rootfs) */
|
||||||
|
if (cfe_size != 384 * 1024) {
|
||||||
|
bcm47xx_parts[1].offset = bcm47xx_parts[0].size;
|
||||||
|
bcm47xx_parts[1].size = bcm47xx_parts[3].offset - dual_image_offset -
|
||||||
|
bcm47xx_parts[1].offset - board_data_size;
|
||||||
|
} else {
|
||||||
|
/* do not count the elf loader, which is on one block */
|
||||||
|
bcm47xx_parts[1].offset = bcm47xx_parts[0].size +
|
||||||
|
bcm47xx_parts[3].size + mtd->erasesize;
|
||||||
|
bcm47xx_parts[1].size = size -
|
||||||
|
bcm47xx_parts[0].size -
|
||||||
|
(2*bcm47xx_parts[3].size) -
|
||||||
|
mtd->erasesize - board_data_size;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* find and size rootfs */
|
||||||
|
find_root(mtd,size,&bcm47xx_parts[2]);
|
||||||
|
bcm47xx_parts[2].size = size - dual_image_offset -
|
||||||
|
bcm47xx_parts[2].offset -
|
||||||
|
bcm47xx_parts[3].size - board_data_size;
|
||||||
|
|
||||||
|
return bcm47xx_parts;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
int __init init_bcm47xx_map(void)
|
||||||
|
{
|
||||||
|
#ifdef CONFIG_SSB
|
||||||
|
struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore;
|
||||||
|
#endif
|
||||||
|
size_t size;
|
||||||
|
int ret = 0;
|
||||||
|
#ifdef CONFIG_MTD_PARTITIONS
|
||||||
|
struct mtd_partition *parts;
|
||||||
|
int i;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_SSB
|
||||||
|
u32 window = mcore->flash_window;
|
||||||
|
u32 window_size = mcore->flash_window_size;
|
||||||
|
|
||||||
|
printk("flash init: 0x%08x 0x%08x\n", window, window_size);
|
||||||
|
bcm47xx_map.phys = window;
|
||||||
|
bcm47xx_map.size = window_size;
|
||||||
|
bcm47xx_map.bankwidth = mcore->flash_buswidth;
|
||||||
|
bcm47xx_map.virt = ioremap_nocache(window, window_size);
|
||||||
|
#else
|
||||||
|
printk("flash init: 0x%08x 0x%08x\n", WINDOW_ADDR, WINDOW_SIZE);
|
||||||
|
bcm47xx_map.virt = ioremap_nocache(WINDOW_ADDR, WINDOW_SIZE);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
if (!bcm47xx_map.virt) {
|
||||||
|
printk("Failed to ioremap\n");
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
simple_map_init(&bcm47xx_map);
|
||||||
|
|
||||||
|
if (!(bcm47xx_mtd = do_map_probe("cfi_probe", &bcm47xx_map))) {
|
||||||
|
printk("Failed to do_map_probe\n");
|
||||||
|
iounmap((void *)bcm47xx_map.virt);
|
||||||
|
return -ENXIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* override copy_from routine */
|
||||||
|
bcm47xx_map.copy_from = bcm47xx_map_copy_from;
|
||||||
|
|
||||||
|
bcm47xx_mtd->owner = THIS_MODULE;
|
||||||
|
|
||||||
|
size = bcm47xx_mtd->size;
|
||||||
|
|
||||||
|
printk(KERN_NOTICE "Flash device: 0x%x at 0x%x\n", size, WINDOW_ADDR);
|
||||||
|
|
||||||
|
#ifdef CONFIG_MTD_PARTITIONS
|
||||||
|
parts = init_mtd_partitions(bcm47xx_mtd, size);
|
||||||
|
for (i = 0; parts[i].name; i++);
|
||||||
|
ret = add_mtd_partitions(bcm47xx_mtd, parts, i);
|
||||||
|
if (ret) {
|
||||||
|
printk(KERN_ERR "Flash: add_mtd_partitions failed\n");
|
||||||
|
goto fail;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
fail:
|
||||||
|
if (bcm47xx_mtd)
|
||||||
|
map_destroy(bcm47xx_mtd);
|
||||||
|
if (bcm47xx_map.virt)
|
||||||
|
iounmap((void *)bcm47xx_map.virt);
|
||||||
|
bcm47xx_map.virt = 0;
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
void __exit cleanup_bcm47xx_map(void)
|
||||||
|
{
|
||||||
|
#ifdef CONFIG_MTD_PARTITIONS
|
||||||
|
del_mtd_partitions(bcm47xx_mtd);
|
||||||
|
#endif
|
||||||
|
map_destroy(bcm47xx_mtd);
|
||||||
|
iounmap((void *)bcm47xx_map.virt);
|
||||||
|
}
|
||||||
|
|
||||||
|
module_init(init_bcm47xx_map);
|
||||||
|
module_exit(cleanup_bcm47xx_map);
|
||||||
|
|
@ -0,0 +1,170 @@
|
||||||
|
From e5c5828063a55a752e2392d820383dd7a5da3737 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Hauke Mehrtens <hauke@hauke-m.de>
|
||||||
|
Date: Sun, 18 Jul 2010 13:34:32 +0200
|
||||||
|
Subject: [PATCH 2/6] MIPS: BCM47xx: Fill values for b43 into ssb sprom
|
||||||
|
|
||||||
|
Most of the values are stored in the nvram and not in the CFE. At first
|
||||||
|
the nvram should be read and if there is no value it should look into
|
||||||
|
the CFE. Now more values are read out because the b43 and b43legacy
|
||||||
|
drivers needs them.
|
||||||
|
|
||||||
|
Some parts of this patch have been in OpenWRT for a long time and were
|
||||||
|
made by Michael Buesch.
|
||||||
|
|
||||||
|
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
|
||||||
|
---
|
||||||
|
arch/mips/bcm47xx/setup.c | 131 +++++++++++++++++++++++++++++++++-----------
|
||||||
|
1 files changed, 98 insertions(+), 33 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/bcm47xx/setup.c
|
||||||
|
+++ b/arch/mips/bcm47xx/setup.c
|
||||||
|
@@ -74,6 +74,95 @@ static void str2eaddr(char *str, char *d
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
+#define READ_FROM_NVRAM(_outvar, name, buf) \
|
||||||
|
+ if (nvram_getenv(name, buf, sizeof(buf)) >= 0 || \
|
||||||
|
+ cfe_getenv(name, buf, sizeof(buf)) >= 0) \
|
||||||
|
+ sprom->_outvar = simple_strtoul(buf, NULL, 0);
|
||||||
|
+
|
||||||
|
+static void bcm47xx_fill_sprom(struct ssb_sprom *sprom)
|
||||||
|
+{
|
||||||
|
+ char buf[100];
|
||||||
|
+ u32 boardflags;
|
||||||
|
+
|
||||||
|
+ memset(sprom, 0, sizeof(struct ssb_sprom));
|
||||||
|
+
|
||||||
|
+ sprom->revision = 1; /* Fallback: Old hardware does not define this. */
|
||||||
|
+ READ_FROM_NVRAM(revision, "sromrev", buf);
|
||||||
|
+ if (nvram_getenv("il0macaddr", buf, sizeof(buf)) >= 0 ||
|
||||||
|
+ cfe_getenv("il0macaddr", buf, sizeof(buf)) >= 0)
|
||||||
|
+ str2eaddr(buf, sprom->il0mac);
|
||||||
|
+ if (nvram_getenv("et0macaddr", buf, sizeof(buf)) >= 0 ||
|
||||||
|
+ cfe_getenv("et0macaddr", buf, sizeof(buf)) >= 0)
|
||||||
|
+ str2eaddr(buf, sprom->et0mac);
|
||||||
|
+ if (nvram_getenv("et1macaddr", buf, sizeof(buf)) >= 0 ||
|
||||||
|
+ cfe_getenv("et1macaddr", buf, sizeof(buf)) >= 0)
|
||||||
|
+ str2eaddr(buf, sprom->et1mac);
|
||||||
|
+ READ_FROM_NVRAM(et0phyaddr, "et0phyaddr", buf);
|
||||||
|
+ READ_FROM_NVRAM(et1phyaddr, "et1phyaddr", buf);
|
||||||
|
+ READ_FROM_NVRAM(et0mdcport, "et0mdcport", buf);
|
||||||
|
+ READ_FROM_NVRAM(et1mdcport, "et1mdcport", buf);
|
||||||
|
+ READ_FROM_NVRAM(board_rev, "boardrev", buf);
|
||||||
|
+ READ_FROM_NVRAM(country_code, "ccode", buf);
|
||||||
|
+ READ_FROM_NVRAM(ant_available_a, "aa5g", buf);
|
||||||
|
+ READ_FROM_NVRAM(ant_available_bg, "aa2g", buf);
|
||||||
|
+ READ_FROM_NVRAM(pa0b0, "pa0b0", buf);
|
||||||
|
+ READ_FROM_NVRAM(pa0b1, "pa0b1", buf);
|
||||||
|
+ READ_FROM_NVRAM(pa0b2, "pa0b2", buf);
|
||||||
|
+ READ_FROM_NVRAM(pa1b0, "pa1b0", buf);
|
||||||
|
+ READ_FROM_NVRAM(pa1b1, "pa1b1", buf);
|
||||||
|
+ READ_FROM_NVRAM(pa1b2, "pa1b2", buf);
|
||||||
|
+ READ_FROM_NVRAM(pa1lob0, "pa1lob0", buf);
|
||||||
|
+ READ_FROM_NVRAM(pa1lob2, "pa1lob1", buf);
|
||||||
|
+ READ_FROM_NVRAM(pa1lob1, "pa1lob2", buf);
|
||||||
|
+ READ_FROM_NVRAM(pa1hib0, "pa1hib0", buf);
|
||||||
|
+ READ_FROM_NVRAM(pa1hib2, "pa1hib1", buf);
|
||||||
|
+ READ_FROM_NVRAM(pa1hib1, "pa1hib2", buf);
|
||||||
|
+ READ_FROM_NVRAM(gpio0, "wl0gpio0", buf);
|
||||||
|
+ READ_FROM_NVRAM(gpio1, "wl0gpio1", buf);
|
||||||
|
+ READ_FROM_NVRAM(gpio2, "wl0gpio2", buf);
|
||||||
|
+ READ_FROM_NVRAM(gpio3, "wl0gpio3", buf);
|
||||||
|
+ READ_FROM_NVRAM(maxpwr_bg, "pa0maxpwr", buf);
|
||||||
|
+ READ_FROM_NVRAM(maxpwr_al, "pa1lomaxpwr", buf);
|
||||||
|
+ READ_FROM_NVRAM(maxpwr_a, "pa1maxpwr", buf);
|
||||||
|
+ READ_FROM_NVRAM(maxpwr_ah, "pa1himaxpwr", buf);
|
||||||
|
+ READ_FROM_NVRAM(itssi_a, "pa1itssit", buf);
|
||||||
|
+ READ_FROM_NVRAM(itssi_bg, "pa0itssit", buf);
|
||||||
|
+ READ_FROM_NVRAM(tri2g, "tri2g", buf);
|
||||||
|
+ READ_FROM_NVRAM(tri5gl, "tri5gl", buf);
|
||||||
|
+ READ_FROM_NVRAM(tri5g, "tri5g", buf);
|
||||||
|
+ READ_FROM_NVRAM(tri5gh, "tri5gh", buf);
|
||||||
|
+ READ_FROM_NVRAM(rxpo2g, "rxpo2g", buf);
|
||||||
|
+ READ_FROM_NVRAM(rxpo5g, "rxpo5g", buf);
|
||||||
|
+ READ_FROM_NVRAM(rssisav2g, "rssisav2g", buf);
|
||||||
|
+ READ_FROM_NVRAM(rssismc2g, "rssismc2g", buf);
|
||||||
|
+ READ_FROM_NVRAM(rssismf2g, "rssismf2g", buf);
|
||||||
|
+ READ_FROM_NVRAM(bxa2g, "bxa2g", buf);
|
||||||
|
+ READ_FROM_NVRAM(rssisav5g, "rssisav5g", buf);
|
||||||
|
+ READ_FROM_NVRAM(rssismc5g, "rssismc5g", buf);
|
||||||
|
+ READ_FROM_NVRAM(rssismf5g, "rssismf5g", buf);
|
||||||
|
+ READ_FROM_NVRAM(bxa5g, "bxa5g", buf);
|
||||||
|
+ READ_FROM_NVRAM(cck2gpo, "cck2gpo", buf);
|
||||||
|
+ READ_FROM_NVRAM(ofdm2gpo, "ofdm2gpo", buf);
|
||||||
|
+ READ_FROM_NVRAM(ofdm5glpo, "ofdm5glpo", buf);
|
||||||
|
+ READ_FROM_NVRAM(ofdm5gpo, "ofdm5gpo", buf);
|
||||||
|
+ READ_FROM_NVRAM(ofdm5ghpo, "ofdm5ghpo", buf);
|
||||||
|
+
|
||||||
|
+ if (nvram_getenv("boardflags", buf, sizeof(buf)) >= 0 ||
|
||||||
|
+ cfe_getenv("boardflags", buf, sizeof(buf)) >= 0)
|
||||||
|
+ boardflags = simple_strtoul(buf, NULL, 0);
|
||||||
|
+ if (boardflags) {
|
||||||
|
+ sprom->boardflags_lo = (boardflags & 0x0000FFFFU);
|
||||||
|
+ sprom->boardflags_hi = (boardflags & 0xFFFF0000U) >> 16;
|
||||||
|
+ }
|
||||||
|
+ if (nvram_getenv("boardflags2", buf, sizeof(buf)) >= 0 ||
|
||||||
|
+ cfe_getenv("boardflags2", buf, sizeof(buf)) >= 0)
|
||||||
|
+ boardflags = simple_strtoul(buf, NULL, 0);
|
||||||
|
+ if (boardflags) {
|
||||||
|
+ sprom->boardflags2_lo = (boardflags & 0x0000FFFFU);
|
||||||
|
+ sprom->boardflags2_hi = (boardflags & 0xFFFF0000U) >> 16;
|
||||||
|
+ }
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static int bcm47xx_get_invariants(struct ssb_bus *bus,
|
||||||
|
struct ssb_init_invariants *iv)
|
||||||
|
{
|
||||||
|
@@ -82,43 +171,19 @@ static int bcm47xx_get_invariants(struct
|
||||||
|
/* Fill boardinfo structure */
|
||||||
|
memset(&(iv->boardinfo), 0 , sizeof(struct ssb_boardinfo));
|
||||||
|
|
||||||
|
- if (cfe_getenv("boardvendor", buf, sizeof(buf)) >= 0 ||
|
||||||
|
- nvram_getenv("boardvendor", buf, sizeof(buf)) >= 0)
|
||||||
|
+ iv->boardinfo.vendor = SSB_BOARDVENDOR_BCM;
|
||||||
|
+ if (nvram_getenv("boardtype", buf, sizeof(buf)) >= 0 ||
|
||||||
|
+ cfe_getenv("boardtype", buf, sizeof(buf)) >= 0)
|
||||||
|
iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0);
|
||||||
|
- if (cfe_getenv("boardtype", buf, sizeof(buf)) >= 0 ||
|
||||||
|
- nvram_getenv("boardtype", buf, sizeof(buf)) >= 0)
|
||||||
|
- iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0);
|
||||||
|
- if (cfe_getenv("boardrev", buf, sizeof(buf)) >= 0 ||
|
||||||
|
- nvram_getenv("boardrev", buf, sizeof(buf)) >= 0)
|
||||||
|
+ if (nvram_getenv("boardrev", buf, sizeof(buf)) >= 0 ||
|
||||||
|
+ cfe_getenv("boardrev", buf, sizeof(buf)) >= 0)
|
||||||
|
iv->boardinfo.rev = (u16)simple_strtoul(buf, NULL, 0);
|
||||||
|
|
||||||
|
- /* Fill sprom structure */
|
||||||
|
- memset(&(iv->sprom), 0, sizeof(struct ssb_sprom));
|
||||||
|
- iv->sprom.revision = 3;
|
||||||
|
-
|
||||||
|
- if (cfe_getenv("et0macaddr", buf, sizeof(buf)) >= 0 ||
|
||||||
|
- nvram_getenv("et0macaddr", buf, sizeof(buf)) >= 0)
|
||||||
|
- str2eaddr(buf, iv->sprom.et0mac);
|
||||||
|
-
|
||||||
|
- if (cfe_getenv("et1macaddr", buf, sizeof(buf)) >= 0 ||
|
||||||
|
- nvram_getenv("et1macaddr", buf, sizeof(buf)) >= 0)
|
||||||
|
- str2eaddr(buf, iv->sprom.et1mac);
|
||||||
|
-
|
||||||
|
- if (cfe_getenv("et0phyaddr", buf, sizeof(buf)) >= 0 ||
|
||||||
|
- nvram_getenv("et0phyaddr", buf, sizeof(buf)) >= 0)
|
||||||
|
- iv->sprom.et0phyaddr = simple_strtoul(buf, NULL, 0);
|
||||||
|
-
|
||||||
|
- if (cfe_getenv("et1phyaddr", buf, sizeof(buf)) >= 0 ||
|
||||||
|
- nvram_getenv("et1phyaddr", buf, sizeof(buf)) >= 0)
|
||||||
|
- iv->sprom.et1phyaddr = simple_strtoul(buf, NULL, 0);
|
||||||
|
-
|
||||||
|
- if (cfe_getenv("et0mdcport", buf, sizeof(buf)) >= 0 ||
|
||||||
|
- nvram_getenv("et0mdcport", buf, sizeof(buf)) >= 0)
|
||||||
|
- iv->sprom.et0mdcport = simple_strtoul(buf, NULL, 10);
|
||||||
|
-
|
||||||
|
- if (cfe_getenv("et1mdcport", buf, sizeof(buf)) >= 0 ||
|
||||||
|
- nvram_getenv("et1mdcport", buf, sizeof(buf)) >= 0)
|
||||||
|
- iv->sprom.et1mdcport = simple_strtoul(buf, NULL, 10);
|
||||||
|
+ bcm47xx_fill_sprom(&iv->sprom);
|
||||||
|
+
|
||||||
|
+ if (nvram_getenv("cardbus", buf, sizeof(buf)) >= 0 ||
|
||||||
|
+ cfe_getenv("cardbus", buf, sizeof(buf)) >= 0)
|
||||||
|
+ iv->has_cardbus_slot = !!simple_strtoul(buf, NULL, 10);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,75 @@
|
||||||
|
From 9be402f069cc259ad5795b77567d66c4e7f6bef6 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Hauke Mehrtens <hauke@hauke-m.de>
|
||||||
|
Date: Sun, 18 Jul 2010 14:59:24 +0200
|
||||||
|
Subject: [PATCH 4/6] MIPS: BCM47xx: Setup and register serial early
|
||||||
|
|
||||||
|
Swap the first and second serial if console=ttyS1 was set.
|
||||||
|
Set it up and register it for early serial support.
|
||||||
|
|
||||||
|
This patch has been in OpenWRT for a long time.
|
||||||
|
|
||||||
|
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
|
||||||
|
---
|
||||||
|
arch/mips/bcm47xx/setup.c | 39 ++++++++++++++++++++++++++++++++++++++-
|
||||||
|
1 files changed, 38 insertions(+), 1 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/bcm47xx/setup.c
|
||||||
|
+++ b/arch/mips/bcm47xx/setup.c
|
||||||
|
@@ -28,6 +28,8 @@
|
||||||
|
#include <linux/types.h>
|
||||||
|
#include <linux/ssb/ssb.h>
|
||||||
|
#include <linux/ssb/ssb_embedded.h>
|
||||||
|
+#include <linux/serial.h>
|
||||||
|
+#include <linux/serial_8250.h>
|
||||||
|
#include <asm/bootinfo.h>
|
||||||
|
#include <asm/reboot.h>
|
||||||
|
#include <asm/time.h>
|
||||||
|
@@ -190,12 +192,47 @@ static int bcm47xx_get_invariants(struct
|
||||||
|
|
||||||
|
void __init plat_mem_setup(void)
|
||||||
|
{
|
||||||
|
- int err;
|
||||||
|
+ int i, err;
|
||||||
|
+ char buf[100];
|
||||||
|
+ struct ssb_mipscore *mcore;
|
||||||
|
|
||||||
|
err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE,
|
||||||
|
bcm47xx_get_invariants);
|
||||||
|
if (err)
|
||||||
|
panic("Failed to initialize SSB bus (err %d)\n", err);
|
||||||
|
+ mcore = &ssb_bcm47xx.mipscore;
|
||||||
|
+
|
||||||
|
+ if (nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0 ||
|
||||||
|
+ cfe_getenv("kernel_args", buf, sizeof(buf)) >= 0) {
|
||||||
|
+ if (strstr(buf, "console=ttyS1")) {
|
||||||
|
+ struct ssb_serial_port port;
|
||||||
|
+
|
||||||
|
+ printk(KERN_DEBUG "Swapping serial ports!\n");
|
||||||
|
+ /* swap serial ports */
|
||||||
|
+ memcpy(&port, &mcore->serial_ports[0], sizeof(port));
|
||||||
|
+ memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1],
|
||||||
|
+ sizeof(port));
|
||||||
|
+ memcpy(&mcore->serial_ports[1], &port, sizeof(port));
|
||||||
|
+ }
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ for (i = 0; i < mcore->nr_serial_ports; i++) {
|
||||||
|
+ struct ssb_serial_port *port = &(mcore->serial_ports[i]);
|
||||||
|
+ struct uart_port s;
|
||||||
|
+
|
||||||
|
+ memset(&s, 0, sizeof(s));
|
||||||
|
+ s.line = i;
|
||||||
|
+ s.mapbase = (unsigned int) port->regs;
|
||||||
|
+ s.membase = port->regs;
|
||||||
|
+ s.irq = port->irq + 2;
|
||||||
|
+ s.uartclk = port->baud_base;
|
||||||
|
+ s.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
|
||||||
|
+ s.iotype = SERIAL_IO_MEM;
|
||||||
|
+ s.regshift = port->reg_shift;
|
||||||
|
+
|
||||||
|
+ early_serial_setup(&s);
|
||||||
|
+ }
|
||||||
|
+ printk(KERN_DEBUG "Serial init done.\n");
|
||||||
|
|
||||||
|
_machine_restart = bcm47xx_machine_restart;
|
||||||
|
_machine_halt = bcm47xx_machine_halt;
|
||||||
|
|
@ -0,0 +1,141 @@
|
||||||
|
From 5219981646071abb6731634bf47781a53e248764 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Hauke Mehrtens <hauke@hauke-m.de>
|
||||||
|
Date: Sun, 18 Jul 2010 15:11:26 +0200
|
||||||
|
Subject: [PATCH 6/6] MIPS: BCM47xx: Remove CFE console
|
||||||
|
|
||||||
|
Do not use the CFE console. It causes hangs on some devices like the
|
||||||
|
Buffalo WHR-HP-G54.
|
||||||
|
This was reported in https://dev.openwrt.org/ticket/4061 and
|
||||||
|
https://forum.openwrt.org/viewtopic.php?id=17063
|
||||||
|
|
||||||
|
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
|
||||||
|
---
|
||||||
|
arch/mips/Kconfig | 1 -
|
||||||
|
arch/mips/bcm47xx/prom.c | 82 +++------------------------------------------
|
||||||
|
2 files changed, 6 insertions(+), 77 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/Kconfig
|
||||||
|
+++ b/arch/mips/Kconfig
|
||||||
|
@@ -76,7 +76,6 @@ config BCM47XX
|
||||||
|
select SSB_B43_PCI_BRIDGE if PCI
|
||||||
|
select SSB_PCICORE_HOSTMODE if PCI
|
||||||
|
select GENERIC_GPIO
|
||||||
|
- select SYS_HAS_EARLY_PRINTK
|
||||||
|
select CFE
|
||||||
|
help
|
||||||
|
Support for BCM47XX based boards
|
||||||
|
--- a/arch/mips/bcm47xx/prom.c
|
||||||
|
+++ b/arch/mips/bcm47xx/prom.c
|
||||||
|
@@ -31,96 +31,28 @@
|
||||||
|
#include <asm/fw/cfe/cfe_api.h>
|
||||||
|
#include <asm/fw/cfe/cfe_error.h>
|
||||||
|
|
||||||
|
-static int cfe_cons_handle;
|
||||||
|
-
|
||||||
|
const char *get_system_type(void)
|
||||||
|
{
|
||||||
|
return "Broadcom BCM47XX";
|
||||||
|
}
|
||||||
|
|
||||||
|
-void prom_putchar(char c)
|
||||||
|
-{
|
||||||
|
- while (cfe_write(cfe_cons_handle, &c, 1) == 0)
|
||||||
|
- ;
|
||||||
|
-}
|
||||||
|
-
|
||||||
|
-static __init void prom_init_cfe(void)
|
||||||
|
+static __init int prom_init_cfe(void)
|
||||||
|
{
|
||||||
|
uint32_t cfe_ept;
|
||||||
|
uint32_t cfe_handle;
|
||||||
|
uint32_t cfe_eptseal;
|
||||||
|
- int argc = fw_arg0;
|
||||||
|
- char **envp = (char **) fw_arg2;
|
||||||
|
- int *prom_vec = (int *) fw_arg3;
|
||||||
|
-
|
||||||
|
- /*
|
||||||
|
- * Check if a loader was used; if NOT, the 4 arguments are
|
||||||
|
- * what CFE gives us (handle, 0, EPT and EPTSEAL)
|
||||||
|
- */
|
||||||
|
- if (argc < 0) {
|
||||||
|
- cfe_handle = (uint32_t)argc;
|
||||||
|
- cfe_ept = (uint32_t)envp;
|
||||||
|
- cfe_eptseal = (uint32_t)prom_vec;
|
||||||
|
- } else {
|
||||||
|
- if ((int)prom_vec < 0) {
|
||||||
|
- /*
|
||||||
|
- * Old loader; all it gives us is the handle,
|
||||||
|
- * so use the "known" entrypoint and assume
|
||||||
|
- * the seal.
|
||||||
|
- */
|
||||||
|
- cfe_handle = (uint32_t)prom_vec;
|
||||||
|
- cfe_ept = 0xBFC00500;
|
||||||
|
- cfe_eptseal = CFE_EPTSEAL;
|
||||||
|
- } else {
|
||||||
|
- /*
|
||||||
|
- * Newer loaders bundle the handle/ept/eptseal
|
||||||
|
- * Note: prom_vec is in the loader's useg
|
||||||
|
- * which is still alive in the TLB.
|
||||||
|
- */
|
||||||
|
- cfe_handle = prom_vec[0];
|
||||||
|
- cfe_ept = prom_vec[2];
|
||||||
|
- cfe_eptseal = prom_vec[3];
|
||||||
|
- }
|
||||||
|
- }
|
||||||
|
+
|
||||||
|
+ cfe_eptseal = (uint32_t) fw_arg3;
|
||||||
|
+ cfe_handle = (uint32_t) fw_arg0;
|
||||||
|
+ cfe_ept = (uint32_t) fw_arg2;
|
||||||
|
|
||||||
|
if (cfe_eptseal != CFE_EPTSEAL) {
|
||||||
|
- /* too early for panic to do any good */
|
||||||
|
printk(KERN_ERR "CFE's entrypoint seal doesn't match.");
|
||||||
|
- while (1) ;
|
||||||
|
+ return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
cfe_init(cfe_handle, cfe_ept);
|
||||||
|
-}
|
||||||
|
-
|
||||||
|
-static __init void prom_init_console(void)
|
||||||
|
-{
|
||||||
|
- /* Initialize CFE console */
|
||||||
|
- cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
|
||||||
|
-}
|
||||||
|
-
|
||||||
|
-static __init void prom_init_cmdline(void)
|
||||||
|
-{
|
||||||
|
- static char buf[COMMAND_LINE_SIZE] __initdata;
|
||||||
|
-
|
||||||
|
- /* Get the kernel command line from CFE */
|
||||||
|
- if (cfe_getenv("LINUX_CMDLINE", buf, COMMAND_LINE_SIZE) >= 0) {
|
||||||
|
- buf[COMMAND_LINE_SIZE - 1] = 0;
|
||||||
|
- strcpy(arcs_cmdline, buf);
|
||||||
|
- }
|
||||||
|
-
|
||||||
|
- /* Force a console handover by adding a console= argument if needed,
|
||||||
|
- * as CFE is not available anymore later in the boot process. */
|
||||||
|
- if ((strstr(arcs_cmdline, "console=")) == NULL) {
|
||||||
|
- /* Try to read the default serial port used by CFE */
|
||||||
|
- if ((cfe_getenv("BOOT_CONSOLE", buf, COMMAND_LINE_SIZE) < 0)
|
||||||
|
- || (strncmp("uart", buf, 4)))
|
||||||
|
- /* Default to uart0 */
|
||||||
|
- strcpy(buf, "uart0");
|
||||||
|
-
|
||||||
|
- /* Compute the new command line */
|
||||||
|
- snprintf(arcs_cmdline, COMMAND_LINE_SIZE, "%s console=ttyS%c,115200",
|
||||||
|
- arcs_cmdline, buf[4]);
|
||||||
|
- }
|
||||||
|
+ return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static __init void prom_init_mem(void)
|
||||||
|
@@ -161,8 +93,6 @@ static __init void prom_init_mem(void)
|
||||||
|
void __init prom_init(void)
|
||||||
|
{
|
||||||
|
prom_init_cfe();
|
||||||
|
- prom_init_console();
|
||||||
|
- prom_init_cmdline();
|
||||||
|
prom_init_mem();
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,345 @@
|
||||||
|
From ad224c0d5fa0fc05f8aaef3c19fc9b4eb275a5d2 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Hauke Mehrtens <hauke@hauke-m.de>
|
||||||
|
Date: Sun, 18 Jul 2010 21:29:40 +0200
|
||||||
|
Subject: [PATCH 2/2] USB: Add ehci ssb driver
|
||||||
|
|
||||||
|
Support for the Sonics Silicon Backplane (SSB) attached Broadcom USB EHCI core.
|
||||||
|
|
||||||
|
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
|
||||||
|
---
|
||||||
|
drivers/usb/host/Kconfig | 13 ++
|
||||||
|
drivers/usb/host/ehci-hcd.c | 22 ++++-
|
||||||
|
drivers/usb/host/ehci-ssb.c | 255 +++++++++++++++++++++++++++++++++++++++++++
|
||||||
|
3 files changed, 288 insertions(+), 2 deletions(-)
|
||||||
|
create mode 100644 drivers/usb/host/ehci-ssb.c
|
||||||
|
|
||||||
|
--- a/drivers/usb/host/Kconfig
|
||||||
|
+++ b/drivers/usb/host/Kconfig
|
||||||
|
@@ -153,6 +153,19 @@ config USB_OXU210HP_HCD
|
||||||
|
To compile this driver as a module, choose M here: the
|
||||||
|
module will be called oxu210hp-hcd.
|
||||||
|
|
||||||
|
+config USB_EHCI_HCD_SSB
|
||||||
|
+ bool "EHCI support for Broadcom SSB EHCI core"
|
||||||
|
+ depends on USB_EHCI_HCD && (SSB = y || SSB = USB_EHCI_HCD) && EXPERIMENTAL
|
||||||
|
+ default n
|
||||||
|
+ ---help---
|
||||||
|
+ Support for the Sonics Silicon Backplane (SSB) attached
|
||||||
|
+ Broadcom USB EHCI core.
|
||||||
|
+
|
||||||
|
+ This device is present in some embedded devices with
|
||||||
|
+ Broadcom based SSB bus.
|
||||||
|
+
|
||||||
|
+ If unsure, say N.
|
||||||
|
+
|
||||||
|
config USB_ISP116X_HCD
|
||||||
|
tristate "ISP116X HCD support"
|
||||||
|
depends on USB
|
||||||
|
--- a/drivers/usb/host/ehci-hcd.c
|
||||||
|
+++ b/drivers/usb/host/ehci-hcd.c
|
||||||
|
@@ -1197,9 +1197,14 @@ MODULE_LICENSE ("GPL");
|
||||||
|
#define PLATFORM_DRIVER ehci_atmel_driver
|
||||||
|
#endif
|
||||||
|
|
||||||
|
+#ifdef CONFIG_USB_EHCI_HCD_SSB
|
||||||
|
+#include "ehci-ssb.c"
|
||||||
|
+#define SSB_EHCI_DRIVER ssb_ehci_driver
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
|
||||||
|
!defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
|
||||||
|
- !defined(XILINX_OF_PLATFORM_DRIVER)
|
||||||
|
+ !defined(XILINX_OF_PLATFORM_DRIVER) && !defined(SSB_EHCI_DRIVER)
|
||||||
|
#error "missing bus glue for ehci-hcd"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
@@ -1259,10 +1264,20 @@ static int __init ehci_hcd_init(void)
|
||||||
|
if (retval < 0)
|
||||||
|
goto clean4;
|
||||||
|
#endif
|
||||||
|
+
|
||||||
|
+#ifdef SSB_EHCI_DRIVER
|
||||||
|
+ retval = ssb_driver_register(&SSB_EHCI_DRIVER);
|
||||||
|
+ if (retval < 0)
|
||||||
|
+ goto clean5;
|
||||||
|
+#endif
|
||||||
|
return retval;
|
||||||
|
|
||||||
|
+#ifdef SSB_EHCI_DRIVER
|
||||||
|
+ /* ssb_driver_unregister(&SSB_EHCI_DRIVER); */
|
||||||
|
+clean5:
|
||||||
|
+#endif
|
||||||
|
#ifdef XILINX_OF_PLATFORM_DRIVER
|
||||||
|
- /* of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER); */
|
||||||
|
+ of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER);
|
||||||
|
clean4:
|
||||||
|
#endif
|
||||||
|
#ifdef OF_PLATFORM_DRIVER
|
||||||
|
@@ -1293,6 +1308,9 @@ module_init(ehci_hcd_init);
|
||||||
|
|
||||||
|
static void __exit ehci_hcd_cleanup(void)
|
||||||
|
{
|
||||||
|
+#ifdef SSB_EHCI_DRIVER
|
||||||
|
+ ssb_driver_unregister(&SSB_EHCI_DRIVER);
|
||||||
|
+#endif
|
||||||
|
#ifdef XILINX_OF_PLATFORM_DRIVER
|
||||||
|
of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER);
|
||||||
|
#endif
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/drivers/usb/host/ehci-ssb.c
|
||||||
|
@@ -0,0 +1,255 @@
|
||||||
|
+/*
|
||||||
|
+ * Sonics Silicon Backplane
|
||||||
|
+ * Broadcom USB-core EHCI driver (SSB bus glue)
|
||||||
|
+ *
|
||||||
|
+ * Copyright 2007 Steven Brown <sbrown@cortland.com>
|
||||||
|
+ * Copyright 2010 Hauke Mehrtens <hauke@hauke-m.de>
|
||||||
|
+ *
|
||||||
|
+ * Derived from the OHCI-SSB driver
|
||||||
|
+ * Copyright 2007 Michael Buesch <mb@bu3sch.de>
|
||||||
|
+ *
|
||||||
|
+ * Derived from the EHCI-PCI driver
|
||||||
|
+ * Copyright (c) 2000-2004 by David Brownell
|
||||||
|
+ *
|
||||||
|
+ * Derived from the OHCI-PCI driver
|
||||||
|
+ * Copyright 1999 Roman Weissgaerber
|
||||||
|
+ * Copyright 2000-2002 David Brownell
|
||||||
|
+ * Copyright 1999 Linus Torvalds
|
||||||
|
+ * Copyright 1999 Gregory P. Smith
|
||||||
|
+ *
|
||||||
|
+ * Derived from the USBcore related parts of Broadcom-SB
|
||||||
|
+ * Copyright 2005 Broadcom Corporation
|
||||||
|
+ *
|
||||||
|
+ * Licensed under the GNU/GPL. See COPYING for details.
|
||||||
|
+ */
|
||||||
|
+#include <linux/ssb/ssb.h>
|
||||||
|
+
|
||||||
|
+
|
||||||
|
+struct ssb_ehci_device {
|
||||||
|
+ struct ehci_hcd ehci; /* _must_ be at the beginning. */
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static inline
|
||||||
|
+struct ssb_ehci_device *hcd_to_ssb_ehci(struct usb_hcd *hcd)
|
||||||
|
+{
|
||||||
|
+ return (struct ssb_ehci_device *)(hcd->hcd_priv);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int ssb_ehci_reset(struct usb_hcd *hcd)
|
||||||
|
+{
|
||||||
|
+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
|
||||||
|
+ int err;
|
||||||
|
+
|
||||||
|
+ ehci->caps = hcd->regs;
|
||||||
|
+ ehci->regs = hcd->regs +
|
||||||
|
+ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
|
||||||
|
+
|
||||||
|
+ dbg_hcs_params(ehci, "reset");
|
||||||
|
+ dbg_hcc_params(ehci, "reset");
|
||||||
|
+
|
||||||
|
+ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
|
||||||
|
+
|
||||||
|
+ err = ehci_halt(ehci);
|
||||||
|
+
|
||||||
|
+ if (err)
|
||||||
|
+ return err;
|
||||||
|
+
|
||||||
|
+ err = ehci_init(hcd);
|
||||||
|
+
|
||||||
|
+ if (err)
|
||||||
|
+ return err;
|
||||||
|
+
|
||||||
|
+ ehci_reset(ehci);
|
||||||
|
+
|
||||||
|
+ return err;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static const struct hc_driver ssb_ehci_hc_driver = {
|
||||||
|
+ .description = "ssb-usb-ehci",
|
||||||
|
+ .product_desc = "SSB EHCI Controller",
|
||||||
|
+ .hcd_priv_size = sizeof(struct ssb_ehci_device),
|
||||||
|
+
|
||||||
|
+ .irq = ehci_irq,
|
||||||
|
+ .flags = HCD_MEMORY | HCD_USB2,
|
||||||
|
+
|
||||||
|
+ .reset = ssb_ehci_reset,
|
||||||
|
+ .start = ehci_run,
|
||||||
|
+ .stop = ehci_stop,
|
||||||
|
+ .shutdown = ehci_shutdown,
|
||||||
|
+
|
||||||
|
+ .urb_enqueue = ehci_urb_enqueue,
|
||||||
|
+ .urb_dequeue = ehci_urb_dequeue,
|
||||||
|
+ .endpoint_disable = ehci_endpoint_disable,
|
||||||
|
+ .endpoint_reset = ehci_endpoint_reset,
|
||||||
|
+
|
||||||
|
+ .get_frame_number = ehci_get_frame,
|
||||||
|
+
|
||||||
|
+ .hub_status_data = ehci_hub_status_data,
|
||||||
|
+ .hub_control = ehci_hub_control,
|
||||||
|
+#if defined(CONFIG_PM)
|
||||||
|
+ .bus_suspend = ehci_bus_suspend,
|
||||||
|
+ .bus_resume = ehci_bus_resume,
|
||||||
|
+#endif
|
||||||
|
+ .relinquish_port = ehci_relinquish_port,
|
||||||
|
+ .port_handed_over = ehci_port_handed_over,
|
||||||
|
+
|
||||||
|
+ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static void ssb_ehci_detach(struct ssb_device *dev)
|
||||||
|
+{
|
||||||
|
+ struct usb_hcd *hcd = ssb_get_drvdata(dev);
|
||||||
|
+
|
||||||
|
+ if (hcd->driver->shutdown)
|
||||||
|
+ hcd->driver->shutdown(hcd);
|
||||||
|
+ usb_remove_hcd(hcd);
|
||||||
|
+ iounmap(hcd->regs);
|
||||||
|
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
|
||||||
|
+ usb_put_hcd(hcd);
|
||||||
|
+ ssb_device_disable(dev, 0);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int ssb_ehci_attach(struct ssb_device *dev)
|
||||||
|
+{
|
||||||
|
+ struct ssb_ehci_device *ehcidev;
|
||||||
|
+ struct usb_hcd *hcd;
|
||||||
|
+ int err = -ENOMEM;
|
||||||
|
+ u32 tmp;
|
||||||
|
+
|
||||||
|
+ if (dma_set_mask(dev->dma_dev, DMA_BIT_MASK(32)) ||
|
||||||
|
+ dma_set_coherent_mask(dev->dma_dev, DMA_BIT_MASK(32)))
|
||||||
|
+ return -EOPNOTSUPP;
|
||||||
|
+
|
||||||
|
+ /*
|
||||||
|
+ * USB 2.0 special considerations:
|
||||||
|
+ *
|
||||||
|
+ * In addition to the standard SSB reset sequence, the Host Control
|
||||||
|
+ * Register must be programmed to bring the USB core and various phy
|
||||||
|
+ * components out of reset.
|
||||||
|
+ */
|
||||||
|
+ ssb_device_enable(dev, 0);
|
||||||
|
+ ssb_write32(dev, 0x200, 0x7ff);
|
||||||
|
+
|
||||||
|
+ /* Change Flush control reg */
|
||||||
|
+ tmp = ssb_read32(dev, 0x400);
|
||||||
|
+ tmp &= ~8;
|
||||||
|
+ ssb_write32(dev, 0x400, tmp);
|
||||||
|
+ tmp = ssb_read32(dev, 0x400);
|
||||||
|
+
|
||||||
|
+ /* Change Shim control reg */
|
||||||
|
+ tmp = ssb_read32(dev, 0x304);
|
||||||
|
+ tmp &= ~0x100;
|
||||||
|
+ ssb_write32(dev, 0x304, tmp);
|
||||||
|
+ tmp = ssb_read32(dev, 0x304);
|
||||||
|
+
|
||||||
|
+ udelay(1);
|
||||||
|
+
|
||||||
|
+ /* Work around for 5354 failures */
|
||||||
|
+ if (dev->id.revision == 2 && dev->bus->chip_id == 0x5354) {
|
||||||
|
+ /* Change syn01 reg */
|
||||||
|
+ tmp = 0x00fe00fe;
|
||||||
|
+ ssb_write32(dev, 0x894, tmp);
|
||||||
|
+
|
||||||
|
+ /* Change syn03 reg */
|
||||||
|
+ tmp = ssb_read32(dev, 0x89c);
|
||||||
|
+ tmp |= 0x1;
|
||||||
|
+ ssb_write32(dev, 0x89c, tmp);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ hcd = usb_create_hcd(&ssb_ehci_hc_driver, dev->dev,
|
||||||
|
+ dev_name(dev->dev));
|
||||||
|
+ if (!hcd)
|
||||||
|
+ goto err_dev_disable;
|
||||||
|
+
|
||||||
|
+ ehcidev = hcd_to_ssb_ehci(hcd);
|
||||||
|
+ tmp = ssb_read32(dev, SSB_ADMATCH0);
|
||||||
|
+ hcd->rsrc_start = ssb_admatch_base(tmp) + 0x800; /* ehci core offset */
|
||||||
|
+ hcd->rsrc_len = 0x100; /* ehci reg block size */
|
||||||
|
+ /*
|
||||||
|
+ * start & size modified per sbutils.c
|
||||||
|
+ */
|
||||||
|
+ hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len);
|
||||||
|
+ if (!hcd->regs)
|
||||||
|
+ goto err_put_hcd;
|
||||||
|
+ err = usb_add_hcd(hcd, dev->irq, IRQF_DISABLED | IRQF_SHARED);
|
||||||
|
+ if (err)
|
||||||
|
+ goto err_iounmap;
|
||||||
|
+
|
||||||
|
+ ssb_set_drvdata(dev, hcd);
|
||||||
|
+
|
||||||
|
+ return err;
|
||||||
|
+
|
||||||
|
+err_iounmap:
|
||||||
|
+ iounmap(hcd->regs);
|
||||||
|
+err_put_hcd:
|
||||||
|
+ usb_put_hcd(hcd);
|
||||||
|
+err_dev_disable:
|
||||||
|
+ ssb_device_disable(dev, 0);
|
||||||
|
+ return err;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int ssb_ehci_probe(struct ssb_device *dev,
|
||||||
|
+ const struct ssb_device_id *id)
|
||||||
|
+{
|
||||||
|
+ int err;
|
||||||
|
+ u16 chipid_top;
|
||||||
|
+
|
||||||
|
+ /* USBcores are only connected on embedded devices. */
|
||||||
|
+ chipid_top = (dev->bus->chip_id & 0xFF00);
|
||||||
|
+ if (chipid_top != 0x4700 && chipid_top != 0x5300)
|
||||||
|
+ return -ENODEV;
|
||||||
|
+
|
||||||
|
+ /* TODO: Probably need checks here; is the core connected? */
|
||||||
|
+
|
||||||
|
+ if (usb_disabled())
|
||||||
|
+ return -ENODEV;
|
||||||
|
+
|
||||||
|
+ err = ssb_ehci_attach(dev);
|
||||||
|
+
|
||||||
|
+ return err;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void ssb_ehci_remove(struct ssb_device *dev)
|
||||||
|
+{
|
||||||
|
+ ssb_ehci_detach(dev);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+#ifdef CONFIG_PM
|
||||||
|
+
|
||||||
|
+static int ssb_ehci_suspend(struct ssb_device *dev, pm_message_t state)
|
||||||
|
+{
|
||||||
|
+ ssb_device_disable(dev, 0);
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int ssb_ehci_resume(struct ssb_device *dev)
|
||||||
|
+{
|
||||||
|
+ struct usb_hcd *hcd = ssb_get_drvdata(dev);
|
||||||
|
+ struct ssb_ehci_device *ehcidev = hcd_to_ssb_ehci(hcd);
|
||||||
|
+
|
||||||
|
+ ssb_device_enable(dev, 0);
|
||||||
|
+
|
||||||
|
+ ehci_finish_controller_resume(hcd);
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+#else /* !CONFIG_PM */
|
||||||
|
+#define ssb_ehci_suspend NULL
|
||||||
|
+#define ssb_ehci_resume NULL
|
||||||
|
+#endif /* CONFIG_PM */
|
||||||
|
+
|
||||||
|
+static const struct ssb_device_id ssb_ehci_table[] = {
|
||||||
|
+ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV),
|
||||||
|
+ SSB_DEVTABLE_END
|
||||||
|
+};
|
||||||
|
+MODULE_DEVICE_TABLE(ssb, ssb_ehci_table);
|
||||||
|
+
|
||||||
|
+static struct ssb_driver ssb_ehci_driver = {
|
||||||
|
+ .name = KBUILD_MODNAME,
|
||||||
|
+ .id_table = ssb_ehci_table,
|
||||||
|
+ .probe = ssb_ehci_probe,
|
||||||
|
+ .remove = ssb_ehci_remove,
|
||||||
|
+ .suspend = ssb_ehci_suspend,
|
||||||
|
+ .resume = ssb_ehci_resume,
|
||||||
|
+};
|
||||||
188
target/linux/brcm47xx/patches-2.6.36/023-usb_ehci_ohci.patch
Normal file
188
target/linux/brcm47xx/patches-2.6.36/023-usb_ehci_ohci.patch
Normal file
|
|
@ -0,0 +1,188 @@
|
||||||
|
--- a/drivers/usb/host/ohci-ssb.c
|
||||||
|
+++ b/drivers/usb/host/ohci-ssb.c
|
||||||
|
@@ -17,6 +17,8 @@
|
||||||
|
*/
|
||||||
|
#include <linux/ssb/ssb.h>
|
||||||
|
|
||||||
|
+extern int ssb_ehci_attach(struct ssb_device *dev, struct usb_hcd **hcd);
|
||||||
|
+extern void ssb_ehci_detach(struct ssb_device *dev, struct usb_hcd *hcd);
|
||||||
|
|
||||||
|
#define SSB_OHCI_TMSLOW_HOSTMODE (1 << 29)
|
||||||
|
|
||||||
|
@@ -24,6 +26,9 @@ struct ssb_ohci_device {
|
||||||
|
struct ohci_hcd ohci; /* _must_ be at the beginning. */
|
||||||
|
|
||||||
|
u32 enable_flags;
|
||||||
|
+#ifdef CONFIG_USB_EHCI_HCD_SSB
|
||||||
|
+ struct usb_hcd *ehci_hcd;
|
||||||
|
+#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
static inline
|
||||||
|
@@ -92,6 +97,9 @@ static const struct hc_driver ssb_ohci_h
|
||||||
|
static void ssb_ohci_detach(struct ssb_device *dev)
|
||||||
|
{
|
||||||
|
struct usb_hcd *hcd = ssb_get_drvdata(dev);
|
||||||
|
+#ifdef CONFIG_USB_EHCI_HCD_SSB
|
||||||
|
+ struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd);
|
||||||
|
+#endif
|
||||||
|
|
||||||
|
if (hcd->driver->shutdown)
|
||||||
|
hcd->driver->shutdown(hcd);
|
||||||
|
@@ -99,6 +107,14 @@ static void ssb_ohci_detach(struct ssb_d
|
||||||
|
iounmap(hcd->regs);
|
||||||
|
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
|
||||||
|
usb_put_hcd(hcd);
|
||||||
|
+
|
||||||
|
+#ifdef CONFIG_USB_EHCI_HCD_SSB
|
||||||
|
+ /*
|
||||||
|
+ * Also detach ehci function
|
||||||
|
+ */
|
||||||
|
+ if (dev->id.coreid == SSB_DEV_USB20_HOST)
|
||||||
|
+ ssb_ehci_detach(dev, ohcidev->ehci_hcd);
|
||||||
|
+#endif
|
||||||
|
ssb_device_disable(dev, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
@@ -121,6 +137,9 @@ static int ssb_ohci_attach(struct ssb_de
|
||||||
|
/*
|
||||||
|
* USB 2.0 special considerations:
|
||||||
|
*
|
||||||
|
+ * Since the core supports both OHCI and EHCI functions,
|
||||||
|
+ * it must only be reset once.
|
||||||
|
+ *
|
||||||
|
* In addition to the standard SSB reset sequence, the Host
|
||||||
|
* Control Register must be programmed to bring the USB core
|
||||||
|
* and various phy components out of reset.
|
||||||
|
@@ -175,6 +194,14 @@ static int ssb_ohci_attach(struct ssb_de
|
||||||
|
|
||||||
|
ssb_set_drvdata(dev, hcd);
|
||||||
|
|
||||||
|
+#ifdef CONFIG_USB_EHCI_HCD_SSB
|
||||||
|
+ /*
|
||||||
|
+ * attach ehci function in this core
|
||||||
|
+ */
|
||||||
|
+ if (dev->id.coreid == SSB_DEV_USB20_HOST)
|
||||||
|
+ err = ssb_ehci_attach(dev, &(ohcidev->ehci_hcd));
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
return err;
|
||||||
|
|
||||||
|
err_iounmap:
|
||||||
|
--- a/drivers/usb/host/ehci-ssb.c
|
||||||
|
+++ b/drivers/usb/host/ehci-ssb.c
|
||||||
|
@@ -106,10 +106,18 @@ static void ssb_ehci_detach(struct ssb_d
|
||||||
|
iounmap(hcd->regs);
|
||||||
|
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
|
||||||
|
usb_put_hcd(hcd);
|
||||||
|
+#ifndef CONFIG_USB_OHCI_HCD_SSB
|
||||||
|
+ ssb_device_disable(dev, 0);
|
||||||
|
+#endif
|
||||||
|
ssb_device_disable(dev, 0);
|
||||||
|
}
|
||||||
|
+EXPORT_SYMBOL_GPL(ssb_ehci_detach);
|
||||||
|
|
||||||
|
+#ifndef CONFIG_USB_OHCI_HCD_SSB
|
||||||
|
static int ssb_ehci_attach(struct ssb_device *dev)
|
||||||
|
+#else
|
||||||
|
+static int ssb_ehci_attach(struct ssb_device *dev, struct usb_hcd **ehci_hcd)
|
||||||
|
+#endif
|
||||||
|
{
|
||||||
|
struct ssb_ehci_device *ehcidev;
|
||||||
|
struct usb_hcd *hcd;
|
||||||
|
@@ -120,6 +128,7 @@ static int ssb_ehci_attach(struct ssb_de
|
||||||
|
dma_set_coherent_mask(dev->dma_dev, DMA_BIT_MASK(32)))
|
||||||
|
return -EOPNOTSUPP;
|
||||||
|
|
||||||
|
+#ifndef CONFIG_USB_OHCI_HCD_SSB
|
||||||
|
/*
|
||||||
|
* USB 2.0 special considerations:
|
||||||
|
*
|
||||||
|
@@ -155,6 +164,7 @@ static int ssb_ehci_attach(struct ssb_de
|
||||||
|
tmp |= 0x1;
|
||||||
|
ssb_write32(dev, 0x89c, tmp);
|
||||||
|
}
|
||||||
|
+#endif
|
||||||
|
|
||||||
|
hcd = usb_create_hcd(&ssb_ehci_hc_driver, dev->dev,
|
||||||
|
dev_name(dev->dev));
|
||||||
|
@@ -175,7 +185,11 @@ static int ssb_ehci_attach(struct ssb_de
|
||||||
|
if (err)
|
||||||
|
goto err_iounmap;
|
||||||
|
|
||||||
|
+#ifndef CONFIG_USB_OHCI_HCD_SSB
|
||||||
|
ssb_set_drvdata(dev, hcd);
|
||||||
|
+#else
|
||||||
|
+ *ehci_hcd = hcd;
|
||||||
|
+#endif
|
||||||
|
|
||||||
|
return err;
|
||||||
|
|
||||||
|
@@ -187,7 +201,9 @@ err_dev_disable:
|
||||||
|
ssb_device_disable(dev, 0);
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
+EXPORT_SYMBOL_GPL(ssb_ehci_attach);
|
||||||
|
|
||||||
|
+#ifndef CONFIG_USB_OHCI_HCD_SSB
|
||||||
|
static int ssb_ehci_probe(struct ssb_device *dev,
|
||||||
|
const struct ssb_device_id *id)
|
||||||
|
{
|
||||||
|
@@ -238,6 +254,7 @@ static int ssb_ehci_resume(struct ssb_de
|
||||||
|
#define ssb_ehci_suspend NULL
|
||||||
|
#define ssb_ehci_resume NULL
|
||||||
|
#endif /* CONFIG_PM */
|
||||||
|
+#endif /* !CONFIG_USB_OHCI_HCD_SSB */
|
||||||
|
|
||||||
|
static const struct ssb_device_id ssb_ehci_table[] = {
|
||||||
|
SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV),
|
||||||
|
@@ -245,6 +262,8 @@ static const struct ssb_device_id ssb_eh
|
||||||
|
};
|
||||||
|
MODULE_DEVICE_TABLE(ssb, ssb_ehci_table);
|
||||||
|
|
||||||
|
+
|
||||||
|
+#ifndef CONFIG_USB_OHCI_HCD_SSB
|
||||||
|
static struct ssb_driver ssb_ehci_driver = {
|
||||||
|
.name = KBUILD_MODNAME,
|
||||||
|
.id_table = ssb_ehci_table,
|
||||||
|
@@ -253,3 +272,4 @@ static struct ssb_driver ssb_ehci_driver
|
||||||
|
.suspend = ssb_ehci_suspend,
|
||||||
|
.resume = ssb_ehci_resume,
|
||||||
|
};
|
||||||
|
+#endif
|
||||||
|
--- a/drivers/usb/host/ehci-hcd.c
|
||||||
|
+++ b/drivers/usb/host/ehci-hcd.c
|
||||||
|
@@ -1265,17 +1265,21 @@ static int __init ehci_hcd_init(void)
|
||||||
|
goto clean4;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
+#ifndef CONFIG_USB_OHCI_HCD_SSB
|
||||||
|
#ifdef SSB_EHCI_DRIVER
|
||||||
|
retval = ssb_driver_register(&SSB_EHCI_DRIVER);
|
||||||
|
if (retval < 0)
|
||||||
|
goto clean5;
|
||||||
|
#endif
|
||||||
|
+#endif /* !CONFIG_USB_OHCI_HCD_SSB */
|
||||||
|
return retval;
|
||||||
|
|
||||||
|
+#ifndef CONFIG_USB_OHCI_HCD_SSB
|
||||||
|
#ifdef SSB_EHCI_DRIVER
|
||||||
|
/* ssb_driver_unregister(&SSB_EHCI_DRIVER); */
|
||||||
|
clean5:
|
||||||
|
#endif
|
||||||
|
+#endif /* !CONFIG_USB_OHCI_HCD_SSB */
|
||||||
|
#ifdef XILINX_OF_PLATFORM_DRIVER
|
||||||
|
of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER);
|
||||||
|
clean4:
|
||||||
|
@@ -1308,9 +1312,11 @@ module_init(ehci_hcd_init);
|
||||||
|
|
||||||
|
static void __exit ehci_hcd_cleanup(void)
|
||||||
|
{
|
||||||
|
+#ifndef CONFIG_USB_OHCI_HCD_SSB
|
||||||
|
#ifdef SSB_EHCI_DRIVER
|
||||||
|
ssb_driver_unregister(&SSB_EHCI_DRIVER);
|
||||||
|
#endif
|
||||||
|
+#endif /* !CONFIG_USB_OHCI_HCD_SSB */
|
||||||
|
#ifdef XILINX_OF_PLATFORM_DRIVER
|
||||||
|
of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER);
|
||||||
|
#endif
|
||||||
25
target/linux/brcm47xx/patches-2.6.36/110-flash_map.patch
Normal file
25
target/linux/brcm47xx/patches-2.6.36/110-flash_map.patch
Normal file
|
|
@ -0,0 +1,25 @@
|
||||||
|
--- a/drivers/mtd/maps/Kconfig
|
||||||
|
+++ b/drivers/mtd/maps/Kconfig
|
||||||
|
@@ -319,6 +319,12 @@ config MTD_CFI_FLAGADM
|
||||||
|
Mapping for the Flaga digital module. If you don't have one, ignore
|
||||||
|
this setting.
|
||||||
|
|
||||||
|
+config MTD_BCM47XX
|
||||||
|
+ tristate "BCM47xx flash device"
|
||||||
|
+ depends on MIPS && MTD_CFI && BCM47XX
|
||||||
|
+ help
|
||||||
|
+ Support for the flash chips on the BCM947xx board.
|
||||||
|
+
|
||||||
|
config MTD_SOLUTIONENGINE
|
||||||
|
tristate "CFI Flash device mapped on Hitachi SolutionEngine"
|
||||||
|
depends on SUPERH && SOLUTION_ENGINE && MTD_CFI && MTD_REDBOOT_PARTS
|
||||||
|
--- a/drivers/mtd/maps/Makefile
|
||||||
|
+++ b/drivers/mtd/maps/Makefile
|
||||||
|
@@ -29,6 +29,7 @@ obj-$(CONFIG_MTD_PMC_MSP_EVM) += pmcms
|
||||||
|
obj-$(CONFIG_MTD_PCMCIA) += pcmciamtd.o
|
||||||
|
obj-$(CONFIG_MTD_RPXLITE) += rpxlite.o
|
||||||
|
obj-$(CONFIG_MTD_TQM8XXL) += tqm8xxl.o
|
||||||
|
+obj-$(CONFIG_MTD_BCM47XX) += bcm47xx-flash.o
|
||||||
|
obj-$(CONFIG_MTD_SA1100) += sa1100-flash.o
|
||||||
|
obj-$(CONFIG_MTD_SBC_GXX) += sbc_gxx.o
|
||||||
|
obj-$(CONFIG_MTD_SC520CDP) += sc520cdp.o
|
||||||
367
target/linux/brcm47xx/patches-2.6.36/150-cpu_fixes.patch
Normal file
367
target/linux/brcm47xx/patches-2.6.36/150-cpu_fixes.patch
Normal file
|
|
@ -0,0 +1,367 @@
|
||||||
|
--- a/arch/mips/include/asm/r4kcache.h
|
||||||
|
+++ b/arch/mips/include/asm/r4kcache.h
|
||||||
|
@@ -17,6 +17,20 @@
|
||||||
|
#include <asm/cpu-features.h>
|
||||||
|
#include <asm/mipsmtregs.h>
|
||||||
|
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+#include <asm/paccess.h>
|
||||||
|
+#include <linux/ssb/ssb.h>
|
||||||
|
+#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE)))
|
||||||
|
+
|
||||||
|
+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
|
||||||
|
+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
|
||||||
|
+#else
|
||||||
|
+#define BCM4710_DUMMY_RREG()
|
||||||
|
+
|
||||||
|
+#define BCM4710_FILL_TLB(addr)
|
||||||
|
+#define BCM4710_PROTECTED_FILL_TLB(addr)
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
/*
|
||||||
|
* This macro return a properly sign-extended address suitable as base address
|
||||||
|
* for indexed cache operations. Two issues here:
|
||||||
|
@@ -150,6 +164,7 @@ static inline void flush_icache_line_ind
|
||||||
|
static inline void flush_dcache_line_indexed(unsigned long addr)
|
||||||
|
{
|
||||||
|
__dflush_prologue
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
cache_op(Index_Writeback_Inv_D, addr);
|
||||||
|
__dflush_epilogue
|
||||||
|
}
|
||||||
|
@@ -169,6 +184,7 @@ static inline void flush_icache_line(uns
|
||||||
|
static inline void flush_dcache_line(unsigned long addr)
|
||||||
|
{
|
||||||
|
__dflush_prologue
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
cache_op(Hit_Writeback_Inv_D, addr);
|
||||||
|
__dflush_epilogue
|
||||||
|
}
|
||||||
|
@@ -176,6 +192,7 @@ static inline void flush_dcache_line(uns
|
||||||
|
static inline void invalidate_dcache_line(unsigned long addr)
|
||||||
|
{
|
||||||
|
__dflush_prologue
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
cache_op(Hit_Invalidate_D, addr);
|
||||||
|
__dflush_epilogue
|
||||||
|
}
|
||||||
|
@@ -208,6 +225,7 @@ static inline void flush_scache_line(uns
|
||||||
|
*/
|
||||||
|
static inline void protected_flush_icache_line(unsigned long addr)
|
||||||
|
{
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
protected_cache_op(Hit_Invalidate_I, addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
@@ -219,6 +237,7 @@ static inline void protected_flush_icach
|
||||||
|
*/
|
||||||
|
static inline void protected_writeback_dcache_line(unsigned long addr)
|
||||||
|
{
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
protected_cache_op(Hit_Writeback_Inv_D, addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
@@ -339,8 +358,52 @@ static inline void invalidate_tcache_pag
|
||||||
|
: "r" (base), \
|
||||||
|
"i" (op));
|
||||||
|
|
||||||
|
+static inline void blast_dcache(void)
|
||||||
|
+{
|
||||||
|
+ unsigned long start = KSEG0;
|
||||||
|
+ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
|
||||||
|
+ unsigned long end = (start + dcache_size);
|
||||||
|
+
|
||||||
|
+ do {
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
+ cache_op(Index_Writeback_Inv_D, start);
|
||||||
|
+ start += current_cpu_data.dcache.linesz;
|
||||||
|
+ } while(start < end);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static inline void blast_dcache_page(unsigned long page)
|
||||||
|
+{
|
||||||
|
+ unsigned long start = page;
|
||||||
|
+ unsigned long end = start + PAGE_SIZE;
|
||||||
|
+
|
||||||
|
+ BCM4710_FILL_TLB(start);
|
||||||
|
+ do {
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
+ cache_op(Hit_Writeback_Inv_D, start);
|
||||||
|
+ start += current_cpu_data.dcache.linesz;
|
||||||
|
+ } while(start < end);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static inline void blast_dcache_page_indexed(unsigned long page)
|
||||||
|
+{
|
||||||
|
+ unsigned long start = page;
|
||||||
|
+ unsigned long end = start + PAGE_SIZE;
|
||||||
|
+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
|
||||||
|
+ unsigned long ws_end = current_cpu_data.dcache.ways <<
|
||||||
|
+ current_cpu_data.dcache.waybit;
|
||||||
|
+ unsigned long ws, addr;
|
||||||
|
+ for (ws = 0; ws < ws_end; ws += ws_inc) {
|
||||||
|
+ start = page + ws;
|
||||||
|
+ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
+ cache_op(Index_Writeback_Inv_D, addr);
|
||||||
|
+ }
|
||||||
|
+ }
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+
|
||||||
|
/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
|
||||||
|
-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
|
||||||
|
+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, war) \
|
||||||
|
static inline void blast_##pfx##cache##lsize(void) \
|
||||||
|
{ \
|
||||||
|
unsigned long start = INDEX_BASE; \
|
||||||
|
@@ -352,6 +415,7 @@ static inline void blast_##pfx##cache##l
|
||||||
|
\
|
||||||
|
__##pfx##flush_prologue \
|
||||||
|
\
|
||||||
|
+ war \
|
||||||
|
for (ws = 0; ws < ws_end; ws += ws_inc) \
|
||||||
|
for (addr = start; addr < end; addr += lsize * 32) \
|
||||||
|
cache##lsize##_unroll32(addr|ws, indexop); \
|
||||||
|
@@ -366,6 +430,7 @@ static inline void blast_##pfx##cache##l
|
||||||
|
\
|
||||||
|
__##pfx##flush_prologue \
|
||||||
|
\
|
||||||
|
+ war \
|
||||||
|
do { \
|
||||||
|
cache##lsize##_unroll32(start, hitop); \
|
||||||
|
start += lsize * 32; \
|
||||||
|
@@ -384,6 +449,8 @@ static inline void blast_##pfx##cache##l
|
||||||
|
current_cpu_data.desc.waybit; \
|
||||||
|
unsigned long ws, addr; \
|
||||||
|
\
|
||||||
|
+ war \
|
||||||
|
+ \
|
||||||
|
__##pfx##flush_prologue \
|
||||||
|
\
|
||||||
|
for (ws = 0; ws < ws_end; ws += ws_inc) \
|
||||||
|
@@ -393,36 +460,38 @@ static inline void blast_##pfx##cache##l
|
||||||
|
__##pfx##flush_epilogue \
|
||||||
|
}
|
||||||
|
|
||||||
|
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
|
||||||
|
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
|
||||||
|
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
|
||||||
|
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
|
||||||
|
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
|
||||||
|
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
|
||||||
|
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64)
|
||||||
|
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
|
||||||
|
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
|
||||||
|
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
|
||||||
|
-
|
||||||
|
-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
|
||||||
|
-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
|
||||||
|
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
|
||||||
|
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
|
||||||
|
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
|
||||||
|
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
|
||||||
|
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
|
||||||
|
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);)
|
||||||
|
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
|
||||||
|
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
|
||||||
|
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, BCM4710_FILL_TLB(start);)
|
||||||
|
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
|
||||||
|
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
|
||||||
|
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);)
|
||||||
|
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
|
||||||
|
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
|
||||||
|
+
|
||||||
|
+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
|
||||||
|
+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
|
||||||
|
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
|
||||||
|
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
|
||||||
|
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
|
||||||
|
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
|
||||||
|
|
||||||
|
/* build blast_xxx_range, protected_blast_xxx_range */
|
||||||
|
-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
|
||||||
|
+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war, war2) \
|
||||||
|
static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
|
||||||
|
unsigned long end) \
|
||||||
|
{ \
|
||||||
|
unsigned long lsize = cpu_##desc##_line_size(); \
|
||||||
|
unsigned long addr = start & ~(lsize - 1); \
|
||||||
|
unsigned long aend = (end - 1) & ~(lsize - 1); \
|
||||||
|
+ war \
|
||||||
|
\
|
||||||
|
__##pfx##flush_prologue \
|
||||||
|
\
|
||||||
|
while (1) { \
|
||||||
|
+ war2 \
|
||||||
|
prot##cache_op(hitop, addr); \
|
||||||
|
if (addr == aend) \
|
||||||
|
break; \
|
||||||
|
@@ -432,13 +501,13 @@ static inline void prot##blast_##pfx##ca
|
||||||
|
__##pfx##flush_epilogue \
|
||||||
|
}
|
||||||
|
|
||||||
|
-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
|
||||||
|
-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
|
||||||
|
-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
|
||||||
|
-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
|
||||||
|
-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
|
||||||
|
+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
|
||||||
|
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_,, )
|
||||||
|
+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_,, )
|
||||||
|
+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D,, BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
|
||||||
|
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD,,, )
|
||||||
|
/* blast_inv_dcache_range */
|
||||||
|
-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
|
||||||
|
-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
|
||||||
|
+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D,,,BCM4710_DUMMY_RREG();)
|
||||||
|
+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
|
||||||
|
|
||||||
|
#endif /* _ASM_R4KCACHE_H */
|
||||||
|
--- a/arch/mips/include/asm/stackframe.h
|
||||||
|
+++ b/arch/mips/include/asm/stackframe.h
|
||||||
|
@@ -449,6 +449,10 @@
|
||||||
|
.macro RESTORE_SP_AND_RET
|
||||||
|
LONG_L sp, PT_R29(sp)
|
||||||
|
.set mips3
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+ nop
|
||||||
|
+ nop
|
||||||
|
+#endif
|
||||||
|
eret
|
||||||
|
.set mips0
|
||||||
|
.endm
|
||||||
|
--- a/arch/mips/kernel/genex.S
|
||||||
|
+++ b/arch/mips/kernel/genex.S
|
||||||
|
@@ -52,6 +52,10 @@ NESTED(except_vec1_generic, 0, sp)
|
||||||
|
NESTED(except_vec3_generic, 0, sp)
|
||||||
|
.set push
|
||||||
|
.set noat
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+ nop
|
||||||
|
+ nop
|
||||||
|
+#endif
|
||||||
|
#if R5432_CP0_INTERRUPT_WAR
|
||||||
|
mfc0 k0, CP0_INDEX
|
||||||
|
#endif
|
||||||
|
--- a/arch/mips/mm/c-r4k.c
|
||||||
|
+++ b/arch/mips/mm/c-r4k.c
|
||||||
|
@@ -35,6 +35,9 @@
|
||||||
|
#include <asm/cacheflush.h> /* for run_uncached() */
|
||||||
|
|
||||||
|
|
||||||
|
+/* For enabling BCM4710 cache workarounds */
|
||||||
|
+int bcm4710 = 0;
|
||||||
|
+
|
||||||
|
/*
|
||||||
|
* Special Variant of smp_call_function for use by cache functions:
|
||||||
|
*
|
||||||
|
@@ -111,6 +114,9 @@ static void __cpuinit r4k_blast_dcache_p
|
||||||
|
{
|
||||||
|
unsigned long dc_lsize = cpu_dcache_line_size();
|
||||||
|
|
||||||
|
+ if (bcm4710)
|
||||||
|
+ r4k_blast_dcache_page = blast_dcache_page;
|
||||||
|
+ else
|
||||||
|
if (dc_lsize == 0)
|
||||||
|
r4k_blast_dcache_page = (void *)cache_noop;
|
||||||
|
else if (dc_lsize == 16)
|
||||||
|
@@ -127,6 +133,9 @@ static void __cpuinit r4k_blast_dcache_p
|
||||||
|
{
|
||||||
|
unsigned long dc_lsize = cpu_dcache_line_size();
|
||||||
|
|
||||||
|
+ if (bcm4710)
|
||||||
|
+ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
|
||||||
|
+ else
|
||||||
|
if (dc_lsize == 0)
|
||||||
|
r4k_blast_dcache_page_indexed = (void *)cache_noop;
|
||||||
|
else if (dc_lsize == 16)
|
||||||
|
@@ -143,6 +152,9 @@ static void __cpuinit r4k_blast_dcache_s
|
||||||
|
{
|
||||||
|
unsigned long dc_lsize = cpu_dcache_line_size();
|
||||||
|
|
||||||
|
+ if (bcm4710)
|
||||||
|
+ r4k_blast_dcache = blast_dcache;
|
||||||
|
+ else
|
||||||
|
if (dc_lsize == 0)
|
||||||
|
r4k_blast_dcache = (void *)cache_noop;
|
||||||
|
else if (dc_lsize == 16)
|
||||||
|
@@ -680,6 +692,8 @@ static void local_r4k_flush_cache_sigtra
|
||||||
|
unsigned long addr = (unsigned long) arg;
|
||||||
|
|
||||||
|
R4600_HIT_CACHEOP_WAR_IMPL;
|
||||||
|
+ BCM4710_PROTECTED_FILL_TLB(addr);
|
||||||
|
+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
|
||||||
|
if (dc_lsize)
|
||||||
|
protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
|
||||||
|
if (!cpu_icache_snoops_remote_store && scache_size)
|
||||||
|
@@ -1311,6 +1325,17 @@ static void __cpuinit coherency_setup(vo
|
||||||
|
* silly idea of putting something else there ...
|
||||||
|
*/
|
||||||
|
switch (current_cpu_type()) {
|
||||||
|
+ case CPU_BCM3302:
|
||||||
|
+ {
|
||||||
|
+ u32 cm;
|
||||||
|
+ cm = read_c0_diag();
|
||||||
|
+ /* Enable icache */
|
||||||
|
+ cm |= (1 << 31);
|
||||||
|
+ /* Enable dcache */
|
||||||
|
+ cm |= (1 << 30);
|
||||||
|
+ write_c0_diag(cm);
|
||||||
|
+ }
|
||||||
|
+ break;
|
||||||
|
case CPU_R4000PC:
|
||||||
|
case CPU_R4000SC:
|
||||||
|
case CPU_R4000MC:
|
||||||
|
@@ -1367,6 +1392,15 @@ void __cpuinit r4k_cache_init(void)
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
+ /* Check if special workarounds are required */
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+ if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
|
||||||
|
+ printk("Enabling BCM4710A0 cache workarounds.\n");
|
||||||
|
+ bcm4710 = 1;
|
||||||
|
+ } else
|
||||||
|
+#endif
|
||||||
|
+ bcm4710 = 0;
|
||||||
|
+
|
||||||
|
probe_pcache();
|
||||||
|
setup_scache();
|
||||||
|
|
||||||
|
@@ -1425,5 +1459,13 @@ void __cpuinit r4k_cache_init(void)
|
||||||
|
#if !defined(CONFIG_MIPS_CMP)
|
||||||
|
local_r4k___flush_cache_all(NULL);
|
||||||
|
#endif
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+ {
|
||||||
|
+ static void (*_coherency_setup)(void);
|
||||||
|
+ _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
|
||||||
|
+ _coherency_setup();
|
||||||
|
+ }
|
||||||
|
+#else
|
||||||
|
coherency_setup();
|
||||||
|
+#endif
|
||||||
|
}
|
||||||
|
--- a/arch/mips/mm/tlbex.c
|
||||||
|
+++ b/arch/mips/mm/tlbex.c
|
||||||
|
@@ -873,6 +873,9 @@ static void __cpuinit build_r4000_tlb_re
|
||||||
|
/* No need for uasm_i_nop */
|
||||||
|
}
|
||||||
|
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+ uasm_i_nop(&p);
|
||||||
|
+#endif
|
||||||
|
#ifdef CONFIG_64BIT
|
||||||
|
build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
|
||||||
|
#else
|
||||||
|
@@ -1323,6 +1326,9 @@ build_r4000_tlbchange_handler_head(u32 *
|
||||||
|
struct uasm_reloc **r, unsigned int pte,
|
||||||
|
unsigned int ptr)
|
||||||
|
{
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+ uasm_i_nop(p);
|
||||||
|
+#endif
|
||||||
|
#ifdef CONFIG_64BIT
|
||||||
|
build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
|
||||||
|
#else
|
||||||
77
target/linux/brcm47xx/patches-2.6.36/160-kmap_coherent.patch
Normal file
77
target/linux/brcm47xx/patches-2.6.36/160-kmap_coherent.patch
Normal file
|
|
@ -0,0 +1,77 @@
|
||||||
|
--- a/arch/mips/include/asm/cpu-features.h
|
||||||
|
+++ b/arch/mips/include/asm/cpu-features.h
|
||||||
|
@@ -110,6 +110,9 @@
|
||||||
|
#ifndef cpu_has_pindexed_dcache
|
||||||
|
#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
|
||||||
|
#endif
|
||||||
|
+#ifndef cpu_use_kmap_coherent
|
||||||
|
+#define cpu_use_kmap_coherent 1
|
||||||
|
+#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
|
||||||
|
@@ -0,0 +1,13 @@
|
||||||
|
+/*
|
||||||
|
+ * This file is subject to the terms and conditions of the GNU General Public
|
||||||
|
+ * License. See the file "COPYING" in the main directory of this archive
|
||||||
|
+ * for more details.
|
||||||
|
+ *
|
||||||
|
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
|
||||||
|
+ */
|
||||||
|
+#ifndef __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
|
||||||
|
+#define __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
|
||||||
|
+
|
||||||
|
+#define cpu_use_kmap_coherent 0
|
||||||
|
+
|
||||||
|
+#endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */
|
||||||
|
--- a/arch/mips/mm/c-r4k.c
|
||||||
|
+++ b/arch/mips/mm/c-r4k.c
|
||||||
|
@@ -507,7 +507,7 @@ static inline void local_r4k_flush_cache
|
||||||
|
*/
|
||||||
|
map_coherent = (cpu_has_dc_aliases &&
|
||||||
|
page_mapped(page) && !Page_dcache_dirty(page));
|
||||||
|
- if (map_coherent)
|
||||||
|
+ if (map_coherent && cpu_use_kmap_coherent)
|
||||||
|
vaddr = kmap_coherent(page, addr);
|
||||||
|
else
|
||||||
|
vaddr = kmap_atomic(page, KM_USER0);
|
||||||
|
@@ -530,7 +530,7 @@ static inline void local_r4k_flush_cache
|
||||||
|
}
|
||||||
|
|
||||||
|
if (vaddr) {
|
||||||
|
- if (map_coherent)
|
||||||
|
+ if (map_coherent && cpu_use_kmap_coherent)
|
||||||
|
kunmap_coherent();
|
||||||
|
else
|
||||||
|
kunmap_atomic(vaddr, KM_USER0);
|
||||||
|
--- a/arch/mips/mm/init.c
|
||||||
|
+++ b/arch/mips/mm/init.c
|
||||||
|
@@ -210,7 +210,7 @@ void copy_user_highpage(struct page *to,
|
||||||
|
void *vfrom, *vto;
|
||||||
|
|
||||||
|
vto = kmap_atomic(to, KM_USER1);
|
||||||
|
- if (cpu_has_dc_aliases &&
|
||||||
|
+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
|
||||||
|
page_mapped(from) && !Page_dcache_dirty(from)) {
|
||||||
|
vfrom = kmap_coherent(from, vaddr);
|
||||||
|
copy_page(vto, vfrom);
|
||||||
|
@@ -232,7 +232,7 @@ void copy_to_user_page(struct vm_area_st
|
||||||
|
struct page *page, unsigned long vaddr, void *dst, const void *src,
|
||||||
|
unsigned long len)
|
||||||
|
{
|
||||||
|
- if (cpu_has_dc_aliases &&
|
||||||
|
+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
|
||||||
|
page_mapped(page) && !Page_dcache_dirty(page)) {
|
||||||
|
void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
|
||||||
|
memcpy(vto, src, len);
|
||||||
|
@@ -250,7 +250,7 @@ void copy_from_user_page(struct vm_area_
|
||||||
|
struct page *page, unsigned long vaddr, void *dst, const void *src,
|
||||||
|
unsigned long len)
|
||||||
|
{
|
||||||
|
- if (cpu_has_dc_aliases &&
|
||||||
|
+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
|
||||||
|
page_mapped(page) && !Page_dcache_dirty(page)) {
|
||||||
|
void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
|
||||||
|
memcpy(dst, vfrom, len);
|
||||||
92
target/linux/brcm47xx/patches-2.6.36/210-b44_phy_fix.patch
Normal file
92
target/linux/brcm47xx/patches-2.6.36/210-b44_phy_fix.patch
Normal file
|
|
@ -0,0 +1,92 @@
|
||||||
|
--- a/drivers/net/b44.c
|
||||||
|
+++ b/drivers/net/b44.c
|
||||||
|
@@ -381,11 +381,12 @@ static void b44_set_flow_ctrl(struct b44
|
||||||
|
__b44_set_flow_ctrl(bp, pause_enab);
|
||||||
|
}
|
||||||
|
|
||||||
|
-#ifdef SSB_DRIVER_MIPS
|
||||||
|
-extern char *nvram_get(char *name);
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+
|
||||||
|
+#include <asm/mach-bcm47xx/nvram.h>
|
||||||
|
static void b44_wap54g10_workaround(struct b44 *bp)
|
||||||
|
{
|
||||||
|
- const char *str;
|
||||||
|
+ char buf[20];
|
||||||
|
u32 val;
|
||||||
|
int err;
|
||||||
|
|
||||||
|
@@ -394,10 +395,9 @@ static void b44_wap54g10_workaround(stru
|
||||||
|
* see https://dev.openwrt.org/ticket/146
|
||||||
|
* check and reset bit "isolate"
|
||||||
|
*/
|
||||||
|
- str = nvram_get("boardnum");
|
||||||
|
- if (!str)
|
||||||
|
+ if (nvram_getenv("boardnum", buf, sizeof(buf)) > 0)
|
||||||
|
return;
|
||||||
|
- if (simple_strtoul(str, NULL, 0) == 2) {
|
||||||
|
+ if (simple_strtoul(buf, NULL, 0) == 2) {
|
||||||
|
err = __b44_readphy(bp, 0, MII_BMCR, &val);
|
||||||
|
if (err)
|
||||||
|
goto error;
|
||||||
|
@@ -412,10 +412,43 @@ static void b44_wap54g10_workaround(stru
|
||||||
|
error:
|
||||||
|
pr_warning("PHY: cannot reset MII transceiver isolate bit\n");
|
||||||
|
}
|
||||||
|
+
|
||||||
|
+static inline int startswith (const char *source, const char *cmp)
|
||||||
|
+{
|
||||||
|
+ return !strncmp(source,cmp,strlen(cmp));
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static inline void b44_bcm47xx_workarounds(struct b44 *bp)
|
||||||
|
+{
|
||||||
|
+ char buf[20];
|
||||||
|
+ /* Toshiba WRC-1000, Siemens SE505 v1, Askey RT-210W, RT-220W */
|
||||||
|
+ if (nvram_getenv("boardnum", buf, sizeof(buf)) > 0)
|
||||||
|
+ return;
|
||||||
|
+ if (simple_strtoul(buf, NULL, 0) == 100) {
|
||||||
|
+ bp->phy_addr = B44_PHY_ADDR_NO_PHY;
|
||||||
|
+ } else {
|
||||||
|
+ /* WL-HDD */
|
||||||
|
+ struct ssb_device *sdev = bp->sdev;
|
||||||
|
+ if (nvram_getenv("hardware_version", buf, sizeof(buf)) > 0)
|
||||||
|
+ return;
|
||||||
|
+ if (startswith(buf, "WL300-")) {
|
||||||
|
+ if (sdev->bus->sprom.et0phyaddr == 0 &&
|
||||||
|
+ sdev->bus->sprom.et1phyaddr == 1)
|
||||||
|
+ bp->phy_addr = B44_PHY_ADDR_NO_PHY;
|
||||||
|
+ }
|
||||||
|
+ }
|
||||||
|
+ return;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
#else
|
||||||
|
+
|
||||||
|
static inline void b44_wap54g10_workaround(struct b44 *bp)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
+
|
||||||
|
+static inline void b44_bcm47xx_workarounds(struct b44 *bp)
|
||||||
|
+{
|
||||||
|
+}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static int b44_setup_phy(struct b44 *bp)
|
||||||
|
@@ -424,6 +457,7 @@ static int b44_setup_phy(struct b44 *bp)
|
||||||
|
int err;
|
||||||
|
|
||||||
|
b44_wap54g10_workaround(bp);
|
||||||
|
+ b44_bcm47xx_workarounds(bp);
|
||||||
|
|
||||||
|
if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
|
||||||
|
return 0;
|
||||||
|
@@ -2089,6 +2123,8 @@ static int __devinit b44_get_invariants(
|
||||||
|
* valid PHY address. */
|
||||||
|
bp->phy_addr &= 0x1F;
|
||||||
|
|
||||||
|
+ b44_bcm47xx_workarounds(bp);
|
||||||
|
+
|
||||||
|
memcpy(bp->dev->dev_addr, addr, 6);
|
||||||
|
|
||||||
|
if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
|
||||||
|
|
@ -0,0 +1,15 @@
|
||||||
|
--- a/drivers/net/b44.c
|
||||||
|
+++ b/drivers/net/b44.c
|
||||||
|
@@ -188,10 +188,11 @@ static int b44_wait_bit(struct b44 *bp,
|
||||||
|
udelay(10);
|
||||||
|
}
|
||||||
|
if (i == timeout) {
|
||||||
|
+#if 0
|
||||||
|
if (net_ratelimit())
|
||||||
|
netdev_err(bp->dev, "BUG! Timeout waiting for bit %08x of register %lx to %s\n",
|
||||||
|
bit, reg, clear ? "clear" : "set");
|
||||||
|
-
|
||||||
|
+#endif
|
||||||
|
return -ENODEV;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
42
target/linux/brcm47xx/patches-2.6.36/220-bcm5354.patch
Normal file
42
target/linux/brcm47xx/patches-2.6.36/220-bcm5354.patch
Normal file
|
|
@ -0,0 +1,42 @@
|
||||||
|
--- a/drivers/ssb/driver_chipcommon.c
|
||||||
|
+++ b/drivers/ssb/driver_chipcommon.c
|
||||||
|
@@ -285,6 +285,8 @@ void ssb_chipco_resume(struct ssb_chipco
|
||||||
|
void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
|
||||||
|
u32 *plltype, u32 *n, u32 *m)
|
||||||
|
{
|
||||||
|
+ if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
|
||||||
|
+ return;
|
||||||
|
*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
|
||||||
|
*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
|
||||||
|
switch (*plltype) {
|
||||||
|
@@ -308,6 +310,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
|
||||||
|
void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
|
||||||
|
u32 *plltype, u32 *n, u32 *m)
|
||||||
|
{
|
||||||
|
+ if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
|
||||||
|
+ return;
|
||||||
|
*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
|
||||||
|
*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
|
||||||
|
switch (*plltype) {
|
||||||
|
--- a/drivers/ssb/driver_mipscore.c
|
||||||
|
+++ b/drivers/ssb/driver_mipscore.c
|
||||||
|
@@ -217,6 +217,8 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
|
||||||
|
|
||||||
|
if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
|
||||||
|
rate = 200000000;
|
||||||
|
+ } else if (bus->chip_id == 0x5354) {
|
||||||
|
+ rate = 240000000;
|
||||||
|
} else {
|
||||||
|
rate = ssb_calc_clock_rate(pll_type, n, m);
|
||||||
|
}
|
||||||
|
--- a/drivers/ssb/main.c
|
||||||
|
+++ b/drivers/ssb/main.c
|
||||||
|
@@ -1074,6 +1074,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
|
||||||
|
|
||||||
|
if (bus->chip_id == 0x5365) {
|
||||||
|
rate = 100000000;
|
||||||
|
+ } else if (bus->chip_id == 0x5354) {
|
||||||
|
+ rate = 120000000;
|
||||||
|
} else {
|
||||||
|
rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
|
||||||
|
if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
|
||||||
|
|
@ -0,0 +1,16 @@
|
||||||
|
This prevents the options from being delete with make kernel_oldconfig.
|
||||||
|
---
|
||||||
|
drivers/ssb/Kconfig | 2 ++
|
||||||
|
1 file changed, 2 insertions(+)
|
||||||
|
|
||||||
|
--- a/drivers/ssb/Kconfig
|
||||||
|
+++ b/drivers/ssb/Kconfig
|
||||||
|
@@ -141,6 +141,8 @@ config SSB_DRIVER_MIPS
|
||||||
|
config SSB_EMBEDDED
|
||||||
|
bool
|
||||||
|
depends on SSB_DRIVER_MIPS
|
||||||
|
+ select USB_EHCI_HCD_SSB if USB_EHCI_HCD
|
||||||
|
+ select USB_OHCI_HCD_SSB if USB_OHCI_HCD
|
||||||
|
default y
|
||||||
|
|
||||||
|
config SSB_DRIVER_EXTIF
|
||||||
|
|
@ -0,0 +1,11 @@
|
||||||
|
--- a/arch/mips/include/asm/cacheflush.h
|
||||||
|
+++ b/arch/mips/include/asm/cacheflush.h
|
||||||
|
@@ -32,7 +32,7 @@
|
||||||
|
extern void (*flush_cache_all)(void);
|
||||||
|
extern void (*__flush_cache_all)(void);
|
||||||
|
extern void (*flush_cache_mm)(struct mm_struct *mm);
|
||||||
|
-#define flush_cache_dup_mm(mm) do { (void) (mm); } while (0)
|
||||||
|
+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
|
||||||
|
extern void (*flush_cache_range)(struct vm_area_struct *vma,
|
||||||
|
unsigned long start, unsigned long end);
|
||||||
|
extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
|
||||||
|
|
@ -0,0 +1,32 @@
|
||||||
|
--- a/arch/mips/mm/c-r4k.c
|
||||||
|
+++ b/arch/mips/mm/c-r4k.c
|
||||||
|
@@ -373,7 +373,7 @@ static inline void local_r4k___flush_cac
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
-static void r4k___flush_cache_all(void)
|
||||||
|
+void r4k___flush_cache_all(void)
|
||||||
|
{
|
||||||
|
r4k_on_each_cpu(local_r4k___flush_cache_all, NULL, 1);
|
||||||
|
}
|
||||||
|
@@ -537,7 +537,7 @@ static inline void local_r4k_flush_cache
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
-static void r4k_flush_cache_page(struct vm_area_struct *vma,
|
||||||
|
+void r4k_flush_cache_page(struct vm_area_struct *vma,
|
||||||
|
unsigned long addr, unsigned long pfn)
|
||||||
|
{
|
||||||
|
struct flush_cache_page_args args;
|
||||||
|
@@ -1469,3 +1469,11 @@ void __cpuinit r4k_cache_init(void)
|
||||||
|
coherency_setup();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
+
|
||||||
|
+/* fuse package DCACHE BUG patch exports */
|
||||||
|
+void (*fuse_flush_cache_all)(void) = r4k___flush_cache_all;
|
||||||
|
+EXPORT_SYMBOL(fuse_flush_cache_all);
|
||||||
|
+
|
||||||
|
+void (*fuse_flush_cache_page)(struct vm_area_struct *vma, unsigned long page,
|
||||||
|
+ unsigned long pfn) = r4k_flush_cache_page;
|
||||||
|
+EXPORT_SYMBOL(fuse_flush_cache_page);
|
||||||
66
target/linux/brcm47xx/patches-2.6.36/310-no_highpage.patch
Normal file
66
target/linux/brcm47xx/patches-2.6.36/310-no_highpage.patch
Normal file
|
|
@ -0,0 +1,66 @@
|
||||||
|
--- a/arch/mips/include/asm/page.h
|
||||||
|
+++ b/arch/mips/include/asm/page.h
|
||||||
|
@@ -43,6 +43,7 @@
|
||||||
|
#ifndef __ASSEMBLY__
|
||||||
|
|
||||||
|
#include <linux/pfn.h>
|
||||||
|
+#include <asm/cpu-features.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
|
||||||
|
extern void build_clear_page(void);
|
||||||
|
@@ -78,13 +79,16 @@ static inline void clear_user_page(void
|
||||||
|
flush_data_cache_page((unsigned long)addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
-extern void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
|
||||||
|
- struct page *to);
|
||||||
|
-struct vm_area_struct;
|
||||||
|
-extern void copy_user_highpage(struct page *to, struct page *from,
|
||||||
|
- unsigned long vaddr, struct vm_area_struct *vma);
|
||||||
|
+static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
|
||||||
|
+ struct page *to)
|
||||||
|
+{
|
||||||
|
+ extern void (*flush_data_cache_page)(unsigned long addr);
|
||||||
|
|
||||||
|
-#define __HAVE_ARCH_COPY_USER_HIGHPAGE
|
||||||
|
+ copy_page(vto, vfrom);
|
||||||
|
+ if (!cpu_has_ic_fills_f_dc ||
|
||||||
|
+ pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
|
||||||
|
+ flush_data_cache_page((unsigned long)vto);
|
||||||
|
+}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* These are used to make use of C type-checking..
|
||||||
|
--- a/arch/mips/mm/init.c
|
||||||
|
+++ b/arch/mips/mm/init.c
|
||||||
|
@@ -204,30 +204,6 @@ void kunmap_coherent(void)
|
||||||
|
preempt_check_resched();
|
||||||
|
}
|
||||||
|
|
||||||
|
-void copy_user_highpage(struct page *to, struct page *from,
|
||||||
|
- unsigned long vaddr, struct vm_area_struct *vma)
|
||||||
|
-{
|
||||||
|
- void *vfrom, *vto;
|
||||||
|
-
|
||||||
|
- vto = kmap_atomic(to, KM_USER1);
|
||||||
|
- if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
|
||||||
|
- page_mapped(from) && !Page_dcache_dirty(from)) {
|
||||||
|
- vfrom = kmap_coherent(from, vaddr);
|
||||||
|
- copy_page(vto, vfrom);
|
||||||
|
- kunmap_coherent();
|
||||||
|
- } else {
|
||||||
|
- vfrom = kmap_atomic(from, KM_USER0);
|
||||||
|
- copy_page(vto, vfrom);
|
||||||
|
- kunmap_atomic(vfrom, KM_USER0);
|
||||||
|
- }
|
||||||
|
- if ((!cpu_has_ic_fills_f_dc) ||
|
||||||
|
- pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
|
||||||
|
- flush_data_cache_page((unsigned long)vto);
|
||||||
|
- kunmap_atomic(vto, KM_USER1);
|
||||||
|
- /* Make sure this page is cleared on other CPU's too before using it */
|
||||||
|
- smp_wmb();
|
||||||
|
-}
|
||||||
|
-
|
||||||
|
void copy_to_user_page(struct vm_area_struct *vma,
|
||||||
|
struct page *page, unsigned long vaddr, void *dst, const void *src,
|
||||||
|
unsigned long len)
|
||||||
56
target/linux/brcm47xx/patches-2.6.36/400-arch-bcm47xx.patch
Normal file
56
target/linux/brcm47xx/patches-2.6.36/400-arch-bcm47xx.patch
Normal file
|
|
@ -0,0 +1,56 @@
|
||||||
|
--- a/arch/mips/bcm47xx/nvram.c
|
||||||
|
+++ b/arch/mips/bcm47xx/nvram.c
|
||||||
|
@@ -92,3 +92,30 @@ int nvram_getenv(char *name, char *val,
|
||||||
|
return NVRAM_ERR_ENVNOTFOUND;
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(nvram_getenv);
|
||||||
|
+
|
||||||
|
+char *nvram_get(const char *name)
|
||||||
|
+{
|
||||||
|
+ char *var, *value, *end, *eq;
|
||||||
|
+
|
||||||
|
+ if (!name)
|
||||||
|
+ return NULL;
|
||||||
|
+
|
||||||
|
+ if (!nvram_buf[0])
|
||||||
|
+ early_nvram_init();
|
||||||
|
+
|
||||||
|
+ /* Look for name=value and return value */
|
||||||
|
+ var = &nvram_buf[sizeof(struct nvram_header)];
|
||||||
|
+ end = nvram_buf + sizeof(nvram_buf) - 2;
|
||||||
|
+ end[0] = end[1] = '\0';
|
||||||
|
+ for (; *var; var = value + strlen(value) + 1) {
|
||||||
|
+ eq = strchr(var, '=');
|
||||||
|
+ if (!eq)
|
||||||
|
+ break;
|
||||||
|
+ value = eq + 1;
|
||||||
|
+ if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
|
||||||
|
+ return value;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ return NULL;
|
||||||
|
+}
|
||||||
|
+EXPORT_SYMBOL(nvram_get);
|
||||||
|
--- a/arch/mips/bcm47xx/setup.c
|
||||||
|
+++ b/arch/mips/bcm47xx/setup.c
|
||||||
|
@@ -238,3 +238,20 @@ void __init plat_mem_setup(void)
|
||||||
|
_machine_halt = bcm47xx_machine_halt;
|
||||||
|
pm_power_off = bcm47xx_machine_halt;
|
||||||
|
}
|
||||||
|
+
|
||||||
|
+static int __init bcm47xx_register_gpiodev(void)
|
||||||
|
+{
|
||||||
|
+ static struct resource res = {
|
||||||
|
+ .start = 0xFFFFFFFF,
|
||||||
|
+ };
|
||||||
|
+ struct platform_device *pdev;
|
||||||
|
+
|
||||||
|
+ pdev = platform_device_register_simple("GPIODEV", 0, &res, 1);
|
||||||
|
+ if (!pdev) {
|
||||||
|
+ printk(KERN_ERR "bcm47xx: GPIODEV init failed\n");
|
||||||
|
+ return -ENODEV;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+device_initcall(bcm47xx_register_gpiodev);
|
||||||
|
|
@ -0,0 +1,18 @@
|
||||||
|
--- a/arch/mips/pci/pci.c
|
||||||
|
+++ b/arch/mips/pci/pci.c
|
||||||
|
@@ -185,12 +185,10 @@ static int pcibios_enable_resources(stru
|
||||||
|
if ((idx == PCI_ROM_RESOURCE) &&
|
||||||
|
(!(r->flags & IORESOURCE_ROM_ENABLE)))
|
||||||
|
continue;
|
||||||
|
- if (!r->start && r->end) {
|
||||||
|
- printk(KERN_ERR "PCI: Device %s not available "
|
||||||
|
- "because of resource collisions\n",
|
||||||
|
+ if (!r->start && r->end)
|
||||||
|
+ printk(KERN_WARNING "PCI: Device %s resource"
|
||||||
|
+ "collisions detected. Ignoring...\n",
|
||||||
|
pci_name(dev));
|
||||||
|
- return -EINVAL;
|
||||||
|
- }
|
||||||
|
if (r->flags & IORESOURCE_IO)
|
||||||
|
cmd |= PCI_COMMAND_IO;
|
||||||
|
if (r->flags & IORESOURCE_MEM)
|
||||||
14
target/linux/brcm47xx/patches-2.6.36/610-pci_ide_fix.patch
Normal file
14
target/linux/brcm47xx/patches-2.6.36/610-pci_ide_fix.patch
Normal file
|
|
@ -0,0 +1,14 @@
|
||||||
|
--- a/include/linux/ide.h
|
||||||
|
+++ b/include/linux/ide.h
|
||||||
|
@@ -195,7 +195,11 @@ static inline void ide_std_init_ports(st
|
||||||
|
hw->io_ports.ctl_addr = ctl_addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
+#if defined CONFIG_BCM47XX
|
||||||
|
+# define MAX_HWIFS 2
|
||||||
|
+#else
|
||||||
|
#define MAX_HWIFS 10
|
||||||
|
+#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Now for the data we need to maintain per-drive: ide_drive_t
|
||||||
|
|
@ -0,0 +1,328 @@
|
||||||
|
--- a/drivers/net/tg3.c
|
||||||
|
+++ b/drivers/net/tg3.c
|
||||||
|
@@ -42,6 +42,7 @@
|
||||||
|
#include <linux/prefetch.h>
|
||||||
|
#include <linux/dma-mapping.h>
|
||||||
|
#include <linux/firmware.h>
|
||||||
|
+#include <linux/ssb/ssb_driver_gige.h>
|
||||||
|
|
||||||
|
#include <net/checksum.h>
|
||||||
|
#include <net/ip.h>
|
||||||
|
@@ -494,8 +495,9 @@ static void _tw32_flush(struct tg3 *tp,
|
||||||
|
static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
|
||||||
|
{
|
||||||
|
tp->write32_mbox(tp, off, val);
|
||||||
|
- if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
|
||||||
|
- !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
|
||||||
|
+ if ((tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) ||
|
||||||
|
+ (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
|
||||||
|
+ !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)))
|
||||||
|
tp->read32_mbox(tp, off);
|
||||||
|
}
|
||||||
|
|
||||||
|
@@ -505,7 +507,7 @@ static void tg3_write32_tx_mbox(struct t
|
||||||
|
writel(val, mbox);
|
||||||
|
if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
|
||||||
|
writel(val, mbox);
|
||||||
|
- if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
|
||||||
|
+ if ((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) || (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES))
|
||||||
|
readl(mbox);
|
||||||
|
}
|
||||||
|
|
||||||
|
@@ -824,7 +826,7 @@ static void tg3_switch_clocks(struct tg3
|
||||||
|
|
||||||
|
#define PHY_BUSY_LOOPS 5000
|
||||||
|
|
||||||
|
-static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
|
||||||
|
+static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val)
|
||||||
|
{
|
||||||
|
u32 frame_val;
|
||||||
|
unsigned int loops;
|
||||||
|
@@ -838,7 +840,7 @@ static int tg3_readphy(struct tg3 *tp, i
|
||||||
|
|
||||||
|
*val = 0x0;
|
||||||
|
|
||||||
|
- frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
|
||||||
|
+ frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
|
||||||
|
MI_COM_PHY_ADDR_MASK);
|
||||||
|
frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
|
||||||
|
MI_COM_REG_ADDR_MASK);
|
||||||
|
@@ -873,7 +875,12 @@ static int tg3_readphy(struct tg3 *tp, i
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
-static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
|
||||||
|
+static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
|
||||||
|
+{
|
||||||
|
+ return __tg3_readphy(tp, tp->phy_addr, reg, val);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val)
|
||||||
|
{
|
||||||
|
u32 frame_val;
|
||||||
|
unsigned int loops;
|
||||||
|
@@ -889,7 +896,7 @@ static int tg3_writephy(struct tg3 *tp,
|
||||||
|
udelay(80);
|
||||||
|
}
|
||||||
|
|
||||||
|
- frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
|
||||||
|
+ frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
|
||||||
|
MI_COM_PHY_ADDR_MASK);
|
||||||
|
frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
|
||||||
|
MI_COM_REG_ADDR_MASK);
|
||||||
|
@@ -922,6 +929,11 @@ static int tg3_writephy(struct tg3 *tp,
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
+static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
|
||||||
|
+{
|
||||||
|
+ return __tg3_writephy(tp, tp->phy_addr, reg, val);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static int tg3_bmcr_reset(struct tg3 *tp)
|
||||||
|
{
|
||||||
|
u32 phy_control;
|
||||||
|
@@ -2426,6 +2438,9 @@ static int tg3_nvram_read(struct tg3 *tp
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
|
||||||
|
+ return -ENODEV;
|
||||||
|
+
|
||||||
|
if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
|
||||||
|
return tg3_nvram_read_using_eeprom(tp, offset, val);
|
||||||
|
|
||||||
|
@@ -2757,8 +2772,10 @@ static int tg3_set_power_state(struct tg
|
||||||
|
tg3_frob_aux_power(tp);
|
||||||
|
|
||||||
|
/* Workaround for unstable PLL clock */
|
||||||
|
- if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
|
||||||
|
- (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
|
||||||
|
+ if ((tp->phy_id & TG3_PHY_ID_MASK) != TG3_PHY_ID_BCM5750_2 &&
|
||||||
|
+ /* !!! FIXME !!! */
|
||||||
|
+ ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
|
||||||
|
+ (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
|
||||||
|
u32 val = tr32(0x7d00);
|
||||||
|
|
||||||
|
val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
|
||||||
|
@@ -3242,6 +3259,14 @@ relink:
|
||||||
|
|
||||||
|
tg3_phy_copper_begin(tp);
|
||||||
|
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_ROBOSWITCH) {
|
||||||
|
+ current_link_up = 1;
|
||||||
|
+ current_speed = SPEED_1000; /* FIXME */
|
||||||
|
+ current_duplex = DUPLEX_FULL;
|
||||||
|
+ tp->link_config.active_speed = current_speed;
|
||||||
|
+ tp->link_config.active_duplex = current_duplex;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
tg3_readphy(tp, MII_BMSR, &tmp);
|
||||||
|
if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
|
||||||
|
(tmp & BMSR_LSTATUS))
|
||||||
|
@@ -6760,6 +6785,11 @@ static int tg3_poll_fw(struct tg3 *tp)
|
||||||
|
int i;
|
||||||
|
u32 val;
|
||||||
|
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
|
||||||
|
+ /* We don't use firmware. */
|
||||||
|
+ return 0;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
|
||||||
|
/* Wait up to 20ms for init done. */
|
||||||
|
for (i = 0; i < 200; i++) {
|
||||||
|
@@ -7050,6 +7080,14 @@ static int tg3_chip_reset(struct tg3 *tp
|
||||||
|
tw32(0x5000, 0x400);
|
||||||
|
}
|
||||||
|
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
|
||||||
|
+ /* BCM4785: In order to avoid repercussions from using potentially
|
||||||
|
+ * defective internal ROM, stop the Rx RISC CPU, which is not
|
||||||
|
+ * required. */
|
||||||
|
+ tg3_stop_fw(tp);
|
||||||
|
+ tg3_halt_cpu(tp, RX_CPU_BASE);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
tw32(GRC_MODE, tp->grc_mode);
|
||||||
|
|
||||||
|
if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
|
||||||
|
@@ -7202,9 +7240,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
|
||||||
|
return -ENODEV;
|
||||||
|
}
|
||||||
|
|
||||||
|
- /* Clear firmware's nvram arbitration. */
|
||||||
|
- if (tp->tg3_flags & TG3_FLAG_NVRAM)
|
||||||
|
- tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
|
||||||
|
+ if (!(tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)) {
|
||||||
|
+ /* Clear firmware's nvram arbitration. */
|
||||||
|
+ if (tp->tg3_flags & TG3_FLAG_NVRAM)
|
||||||
|
+ tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
@@ -7267,6 +7308,11 @@ static int tg3_load_5701_a0_firmware_fix
|
||||||
|
const __be32 *fw_data;
|
||||||
|
int err, i;
|
||||||
|
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
|
||||||
|
+ /* We don't use firmware. */
|
||||||
|
+ return 0;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
fw_data = (void *)tp->fw->data;
|
||||||
|
|
||||||
|
/* Firmware blob starts with version numbers, followed by
|
||||||
|
@@ -7325,6 +7371,11 @@ static int tg3_load_tso_firmware(struct
|
||||||
|
unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
|
||||||
|
int err, i;
|
||||||
|
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
|
||||||
|
+ /* We don't use firmware. */
|
||||||
|
+ return 0;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
@@ -8474,6 +8525,11 @@ static void tg3_timer(unsigned long __op
|
||||||
|
|
||||||
|
spin_lock(&tp->lock);
|
||||||
|
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
|
||||||
|
+ /* BCM4785: Flush posted writes from GbE to host memory. */
|
||||||
|
+ tr32(HOSTCC_MODE);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
|
||||||
|
/* All of this garbage is because when using non-tagged
|
||||||
|
* IRQ status the mailbox/status_block protocol the chip
|
||||||
|
@@ -10131,6 +10187,11 @@ static int tg3_test_nvram(struct tg3 *tp
|
||||||
|
if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
|
||||||
|
+ /* We don't have NVRAM. */
|
||||||
|
+ return 0;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
if (tg3_nvram_read(tp, 0, &magic) != 0)
|
||||||
|
return -EIO;
|
||||||
|
|
||||||
|
@@ -10951,7 +11012,7 @@ static int tg3_ioctl(struct net_device *
|
||||||
|
return -EAGAIN;
|
||||||
|
|
||||||
|
spin_lock_bh(&tp->lock);
|
||||||
|
- err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
|
||||||
|
+ err = __tg3_readphy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
|
||||||
|
spin_unlock_bh(&tp->lock);
|
||||||
|
|
||||||
|
data->val_out = mii_regval;
|
||||||
|
@@ -10967,7 +11028,7 @@ static int tg3_ioctl(struct net_device *
|
||||||
|
return -EAGAIN;
|
||||||
|
|
||||||
|
spin_lock_bh(&tp->lock);
|
||||||
|
- err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
|
||||||
|
+ err = __tg3_writephy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
|
||||||
|
spin_unlock_bh(&tp->lock);
|
||||||
|
|
||||||
|
return err;
|
||||||
|
@@ -11612,6 +11673,12 @@ static void __devinit tg3_get_5717_nvram
|
||||||
|
/* Chips other than 5700/5701 use the NVRAM for fetching info. */
|
||||||
|
static void __devinit tg3_nvram_init(struct tg3 *tp)
|
||||||
|
{
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
|
||||||
|
+ /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
|
||||||
|
+ tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
|
||||||
|
+ return;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
tw32_f(GRC_EEPROM_ADDR,
|
||||||
|
(EEPROM_ADDR_FSM_RESET |
|
||||||
|
(EEPROM_DEFAULT_CLOCK_PERIOD <<
|
||||||
|
@@ -11875,6 +11942,9 @@ static int tg3_nvram_write_block(struct
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
|
||||||
|
+ return -ENODEV;
|
||||||
|
+
|
||||||
|
if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
|
||||||
|
tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
|
||||||
|
~GRC_LCLCTRL_GPIO_OUTPUT1);
|
||||||
|
@@ -13267,6 +13337,11 @@ static int __devinit tg3_get_invariants(
|
||||||
|
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
|
||||||
|
tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
|
||||||
|
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
|
||||||
|
+ tp->write32_tx_mbox = tg3_write_flush_reg32;
|
||||||
|
+ tp->write32_rx_mbox = tg3_write_flush_reg32;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
/* Get eeprom hw config before calling tg3_set_power_state().
|
||||||
|
* In particular, the TG3_FLG2_IS_NIC flag must be
|
||||||
|
* determined before calling tg3_set_power_state() so that
|
||||||
|
@@ -13665,6 +13740,10 @@ static int __devinit tg3_get_device_addr
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!is_valid_ether_addr(&dev->dev_addr[0])) {
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
|
||||||
|
+ ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
|
||||||
|
+ }
|
||||||
|
+ if (!is_valid_ether_addr(&dev->dev_addr[0])) {
|
||||||
|
#ifdef CONFIG_SPARC
|
||||||
|
if (!tg3_get_default_macaddr_sparc(tp))
|
||||||
|
return 0;
|
||||||
|
@@ -14181,6 +14260,7 @@ static char * __devinit tg3_phy_string(s
|
||||||
|
case TG3_PHY_ID_BCM5704: return "5704";
|
||||||
|
case TG3_PHY_ID_BCM5705: return "5705";
|
||||||
|
case TG3_PHY_ID_BCM5750: return "5750";
|
||||||
|
+ case TG3_PHY_ID_BCM5750_2: return "5750-2";
|
||||||
|
case TG3_PHY_ID_BCM5752: return "5752";
|
||||||
|
case TG3_PHY_ID_BCM5714: return "5714";
|
||||||
|
case TG3_PHY_ID_BCM5780: return "5780";
|
||||||
|
@@ -14392,6 +14472,13 @@ static int __devinit tg3_init_one(struct
|
||||||
|
tp->msg_enable = tg3_debug;
|
||||||
|
else
|
||||||
|
tp->msg_enable = TG3_DEF_MSG_ENABLE;
|
||||||
|
+ if (pdev_is_ssb_gige_core(pdev)) {
|
||||||
|
+ tp->tg3_flags3 |= TG3_FLG3_IS_SSB_CORE;
|
||||||
|
+ if (ssb_gige_must_flush_posted_writes(pdev))
|
||||||
|
+ tp->tg3_flags3 |= TG3_FLG3_FLUSH_POSTED_WRITES;
|
||||||
|
+ if (ssb_gige_have_roboswitch(pdev))
|
||||||
|
+ tp->tg3_flags3 |= TG3_FLG3_ROBOSWITCH;
|
||||||
|
+ }
|
||||||
|
|
||||||
|
/* The word/byte swap controls here control register access byte
|
||||||
|
* swapping. DMA data byte swapping is controlled in the GRC_MODE
|
||||||
|
--- a/drivers/net/tg3.h
|
||||||
|
+++ b/drivers/net/tg3.h
|
||||||
|
@@ -2020,6 +2020,9 @@
|
||||||
|
#define NIC_SRAM_RGMII_INBAND_DISABLE 0x00000004
|
||||||
|
#define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008
|
||||||
|
#define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010
|
||||||
|
+#define TG3_FLG3_IS_SSB_CORE 0x00000800
|
||||||
|
+#define TG3_FLG3_FLUSH_POSTED_WRITES 0x00001000
|
||||||
|
+#define TG3_FLG3_ROBOSWITCH 0x00002000
|
||||||
|
|
||||||
|
#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
|
||||||
|
|
||||||
|
@@ -2908,6 +2911,7 @@ struct tg3 {
|
||||||
|
#define TG3_PHY_ID_BCM5704 0x60008190
|
||||||
|
#define TG3_PHY_ID_BCM5705 0x600081a0
|
||||||
|
#define TG3_PHY_ID_BCM5750 0x60008180
|
||||||
|
+#define TG3_PHY_ID_BCM5750_2 0xbc050cd0
|
||||||
|
#define TG3_PHY_ID_BCM5752 0x60008100
|
||||||
|
#define TG3_PHY_ID_BCM5714 0x60008340
|
||||||
|
#define TG3_PHY_ID_BCM5780 0x60008350
|
||||||
|
@@ -2944,7 +2948,7 @@ struct tg3 {
|
||||||
|
(X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
|
||||||
|
(X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
|
||||||
|
(X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \
|
||||||
|
- (X) == TG3_PHY_ID_BCM8002)
|
||||||
|
+ (X) == TG3_PHY_ID_BCM8002 || (X) == TG3_PHY_ID_BCM5750_2)
|
||||||
|
|
||||||
|
u32 phy_flags;
|
||||||
|
#define TG3_PHYFLG_IS_LOW_POWER 0x00000001
|
||||||
|
|
@ -0,0 +1,177 @@
|
||||||
|
--- a/arch/mips/bcm47xx/Makefile
|
||||||
|
+++ b/arch/mips/bcm47xx/Makefile
|
||||||
|
@@ -3,4 +3,4 @@
|
||||||
|
# under Linux.
|
||||||
|
#
|
||||||
|
|
||||||
|
-obj-y := gpio.o irq.o nvram.o prom.o serial.o setup.o time.o wgt634u.o
|
||||||
|
+obj-y := gpio.o irq.o nvram.o prom.o serial.o setup.o time.o
|
||||||
|
--- a/arch/mips/bcm47xx/wgt634u.c
|
||||||
|
+++ /dev/null
|
||||||
|
@@ -1,166 +0,0 @@
|
||||||
|
-/*
|
||||||
|
- * This file is subject to the terms and conditions of the GNU General Public
|
||||||
|
- * License. See the file "COPYING" in the main directory of this archive
|
||||||
|
- * for more details.
|
||||||
|
- *
|
||||||
|
- * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
|
||||||
|
- */
|
||||||
|
-
|
||||||
|
-#include <linux/platform_device.h>
|
||||||
|
-#include <linux/module.h>
|
||||||
|
-#include <linux/leds.h>
|
||||||
|
-#include <linux/mtd/physmap.h>
|
||||||
|
-#include <linux/ssb/ssb.h>
|
||||||
|
-#include <linux/interrupt.h>
|
||||||
|
-#include <linux/reboot.h>
|
||||||
|
-#include <linux/gpio.h>
|
||||||
|
-#include <asm/mach-bcm47xx/bcm47xx.h>
|
||||||
|
-
|
||||||
|
-/* GPIO definitions for the WGT634U */
|
||||||
|
-#define WGT634U_GPIO_LED 3
|
||||||
|
-#define WGT634U_GPIO_RESET 2
|
||||||
|
-#define WGT634U_GPIO_TP1 7
|
||||||
|
-#define WGT634U_GPIO_TP2 6
|
||||||
|
-#define WGT634U_GPIO_TP3 5
|
||||||
|
-#define WGT634U_GPIO_TP4 4
|
||||||
|
-#define WGT634U_GPIO_TP5 1
|
||||||
|
-
|
||||||
|
-static struct gpio_led wgt634u_leds[] = {
|
||||||
|
- {
|
||||||
|
- .name = "power",
|
||||||
|
- .gpio = WGT634U_GPIO_LED,
|
||||||
|
- .active_low = 1,
|
||||||
|
- .default_trigger = "heartbeat",
|
||||||
|
- },
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-static struct gpio_led_platform_data wgt634u_led_data = {
|
||||||
|
- .num_leds = ARRAY_SIZE(wgt634u_leds),
|
||||||
|
- .leds = wgt634u_leds,
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-static struct platform_device wgt634u_gpio_leds = {
|
||||||
|
- .name = "leds-gpio",
|
||||||
|
- .id = -1,
|
||||||
|
- .dev = {
|
||||||
|
- .platform_data = &wgt634u_led_data,
|
||||||
|
- }
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-
|
||||||
|
-/* 8MiB flash. The struct mtd_partition matches original Netgear WGT634U
|
||||||
|
- firmware. */
|
||||||
|
-static struct mtd_partition wgt634u_partitions[] = {
|
||||||
|
- {
|
||||||
|
- .name = "cfe",
|
||||||
|
- .offset = 0,
|
||||||
|
- .size = 0x60000, /* 384k */
|
||||||
|
- .mask_flags = MTD_WRITEABLE /* force read-only */
|
||||||
|
- },
|
||||||
|
- {
|
||||||
|
- .name = "config",
|
||||||
|
- .offset = 0x60000,
|
||||||
|
- .size = 0x20000 /* 128k */
|
||||||
|
- },
|
||||||
|
- {
|
||||||
|
- .name = "linux",
|
||||||
|
- .offset = 0x80000,
|
||||||
|
- .size = 0x140000 /* 1280k */
|
||||||
|
- },
|
||||||
|
- {
|
||||||
|
- .name = "jffs",
|
||||||
|
- .offset = 0x1c0000,
|
||||||
|
- .size = 0x620000 /* 6272k */
|
||||||
|
- },
|
||||||
|
- {
|
||||||
|
- .name = "nvram",
|
||||||
|
- .offset = 0x7e0000,
|
||||||
|
- .size = 0x20000 /* 128k */
|
||||||
|
- },
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-static struct physmap_flash_data wgt634u_flash_data = {
|
||||||
|
- .parts = wgt634u_partitions,
|
||||||
|
- .nr_parts = ARRAY_SIZE(wgt634u_partitions)
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-static struct resource wgt634u_flash_resource = {
|
||||||
|
- .flags = IORESOURCE_MEM,
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-static struct platform_device wgt634u_flash = {
|
||||||
|
- .name = "physmap-flash",
|
||||||
|
- .id = 0,
|
||||||
|
- .dev = { .platform_data = &wgt634u_flash_data, },
|
||||||
|
- .resource = &wgt634u_flash_resource,
|
||||||
|
- .num_resources = 1,
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-/* Platform devices */
|
||||||
|
-static struct platform_device *wgt634u_devices[] __initdata = {
|
||||||
|
- &wgt634u_flash,
|
||||||
|
- &wgt634u_gpio_leds,
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-static irqreturn_t gpio_interrupt(int irq, void *ignored)
|
||||||
|
-{
|
||||||
|
- int state;
|
||||||
|
-
|
||||||
|
- /* Interrupts are shared, check if the current one is
|
||||||
|
- a GPIO interrupt. */
|
||||||
|
- if (!ssb_chipco_irq_status(&ssb_bcm47xx.chipco,
|
||||||
|
- SSB_CHIPCO_IRQ_GPIO))
|
||||||
|
- return IRQ_NONE;
|
||||||
|
-
|
||||||
|
- state = gpio_get_value(WGT634U_GPIO_RESET);
|
||||||
|
-
|
||||||
|
- /* Interrupt are level triggered, revert the interrupt polarity
|
||||||
|
- to clear the interrupt. */
|
||||||
|
- gpio_polarity(WGT634U_GPIO_RESET, state);
|
||||||
|
-
|
||||||
|
- if (!state) {
|
||||||
|
- printk(KERN_INFO "Reset button pressed");
|
||||||
|
- ctrl_alt_del();
|
||||||
|
- }
|
||||||
|
-
|
||||||
|
- return IRQ_HANDLED;
|
||||||
|
-}
|
||||||
|
-
|
||||||
|
-static int __init wgt634u_init(void)
|
||||||
|
-{
|
||||||
|
- /* There is no easy way to detect that we are running on a WGT634U
|
||||||
|
- * machine. Use the MAC address as an heuristic. Netgear Inc. has
|
||||||
|
- * been allocated ranges 00:09:5b:xx:xx:xx and 00:0f:b5:xx:xx:xx.
|
||||||
|
- */
|
||||||
|
-
|
||||||
|
- u8 *et0mac = ssb_bcm47xx.sprom.et0mac;
|
||||||
|
-
|
||||||
|
- if (et0mac[0] == 0x00 &&
|
||||||
|
- ((et0mac[1] == 0x09 && et0mac[2] == 0x5b) ||
|
||||||
|
- (et0mac[1] == 0x0f && et0mac[2] == 0xb5))) {
|
||||||
|
- struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore;
|
||||||
|
-
|
||||||
|
- printk(KERN_INFO "WGT634U machine detected.\n");
|
||||||
|
-
|
||||||
|
- if (!request_irq(gpio_to_irq(WGT634U_GPIO_RESET),
|
||||||
|
- gpio_interrupt, IRQF_SHARED,
|
||||||
|
- "WGT634U GPIO", &ssb_bcm47xx.chipco)) {
|
||||||
|
- gpio_direction_input(WGT634U_GPIO_RESET);
|
||||||
|
- gpio_intmask(WGT634U_GPIO_RESET, 1);
|
||||||
|
- ssb_chipco_irq_mask(&ssb_bcm47xx.chipco,
|
||||||
|
- SSB_CHIPCO_IRQ_GPIO,
|
||||||
|
- SSB_CHIPCO_IRQ_GPIO);
|
||||||
|
- }
|
||||||
|
-
|
||||||
|
- wgt634u_flash_data.width = mcore->flash_buswidth;
|
||||||
|
- wgt634u_flash_resource.start = mcore->flash_window;
|
||||||
|
- wgt634u_flash_resource.end = mcore->flash_window
|
||||||
|
- + mcore->flash_window_size
|
||||||
|
- - 1;
|
||||||
|
- return platform_add_devices(wgt634u_devices,
|
||||||
|
- ARRAY_SIZE(wgt634u_devices));
|
||||||
|
- } else
|
||||||
|
- return -ENODEV;
|
||||||
|
-}
|
||||||
|
-
|
||||||
|
-module_init(wgt634u_init);
|
||||||
138
target/linux/brcm47xx/patches-2.6.36/920-cache-wround.patch
Normal file
138
target/linux/brcm47xx/patches-2.6.36/920-cache-wround.patch
Normal file
|
|
@ -0,0 +1,138 @@
|
||||||
|
--- a/arch/mips/include/asm/r4kcache.h
|
||||||
|
+++ b/arch/mips/include/asm/r4kcache.h
|
||||||
|
@@ -20,10 +20,28 @@
|
||||||
|
#ifdef CONFIG_BCM47XX
|
||||||
|
#include <asm/paccess.h>
|
||||||
|
#include <linux/ssb/ssb.h>
|
||||||
|
-#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE)))
|
||||||
|
+#define BCM4710_DUMMY_RREG() bcm4710_dummy_rreg()
|
||||||
|
+
|
||||||
|
+static inline unsigned long bcm4710_dummy_rreg(void)
|
||||||
|
+{
|
||||||
|
+ return *(volatile unsigned long *)(KSEG1ADDR(SSB_ENUM_BASE));
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+#define BCM4710_FILL_TLB(addr) bcm4710_fill_tlb((void *)(addr))
|
||||||
|
+
|
||||||
|
+static inline unsigned long bcm4710_fill_tlb(void *addr)
|
||||||
|
+{
|
||||||
|
+ return *(unsigned long *)addr;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+#define BCM4710_PROTECTED_FILL_TLB(addr) bcm4710_protected_fill_tlb((void *)(addr))
|
||||||
|
+
|
||||||
|
+static inline void bcm4710_protected_fill_tlb(void *addr)
|
||||||
|
+{
|
||||||
|
+ unsigned long x;
|
||||||
|
+ get_dbe(x, (unsigned long *)addr);;
|
||||||
|
+}
|
||||||
|
|
||||||
|
-#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
|
||||||
|
-#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
|
||||||
|
#else
|
||||||
|
#define BCM4710_DUMMY_RREG()
|
||||||
|
|
||||||
|
--- a/arch/mips/mm/tlbex.c
|
||||||
|
+++ b/arch/mips/mm/tlbex.c
|
||||||
|
@@ -712,6 +712,9 @@ build_get_pgde32(u32 **p, unsigned int t
|
||||||
|
#endif
|
||||||
|
uasm_i_addu(p, ptr, tmp, ptr);
|
||||||
|
#else
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+ uasm_i_nop(p);
|
||||||
|
+#endif
|
||||||
|
UASM_i_LA_mostly(p, ptr, pgdc);
|
||||||
|
#endif
|
||||||
|
uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
|
||||||
|
@@ -873,12 +876,12 @@ static void __cpuinit build_r4000_tlb_re
|
||||||
|
/* No need for uasm_i_nop */
|
||||||
|
}
|
||||||
|
|
||||||
|
-#ifdef CONFIG_BCM47XX
|
||||||
|
- uasm_i_nop(&p);
|
||||||
|
-#endif
|
||||||
|
#ifdef CONFIG_64BIT
|
||||||
|
build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
|
||||||
|
#else
|
||||||
|
+# ifdef CONFIG_BCM47XX
|
||||||
|
+ uasm_i_nop(&p);
|
||||||
|
+# endif
|
||||||
|
build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
@@ -890,6 +893,9 @@ static void __cpuinit build_r4000_tlb_re
|
||||||
|
build_update_entries(&p, K0, K1);
|
||||||
|
build_tlb_write_entry(&p, &l, &r, tlb_random);
|
||||||
|
uasm_l_leave(&l, p);
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+ uasm_i_nop(&p);
|
||||||
|
+#endif
|
||||||
|
uasm_i_eret(&p); /* return from trap */
|
||||||
|
|
||||||
|
#ifdef CONFIG_HUGETLB_PAGE
|
||||||
|
@@ -1326,12 +1332,12 @@ build_r4000_tlbchange_handler_head(u32 *
|
||||||
|
struct uasm_reloc **r, unsigned int pte,
|
||||||
|
unsigned int ptr)
|
||||||
|
{
|
||||||
|
-#ifdef CONFIG_BCM47XX
|
||||||
|
- uasm_i_nop(p);
|
||||||
|
-#endif
|
||||||
|
#ifdef CONFIG_64BIT
|
||||||
|
build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
|
||||||
|
#else
|
||||||
|
+# ifdef CONFIG_BCM47XX
|
||||||
|
+ uasm_i_nop(p);
|
||||||
|
+# endif
|
||||||
|
build_get_pgde32(p, pte, ptr); /* get pgd in ptr */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
@@ -1368,6 +1374,9 @@ build_r4000_tlbchange_handler_tail(u32 *
|
||||||
|
build_update_entries(p, tmp, ptr);
|
||||||
|
build_tlb_write_entry(p, l, r, tlb_indexed);
|
||||||
|
uasm_l_leave(l, *p);
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+ uasm_i_nop(p);
|
||||||
|
+#endif
|
||||||
|
uasm_i_eret(p); /* return from trap */
|
||||||
|
|
||||||
|
#ifdef CONFIG_64BIT
|
||||||
|
--- a/arch/mips/kernel/genex.S
|
||||||
|
+++ b/arch/mips/kernel/genex.S
|
||||||
|
@@ -22,6 +22,19 @@
|
||||||
|
#include <asm/page.h>
|
||||||
|
#include <asm/thread_info.h>
|
||||||
|
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+# ifdef eret
|
||||||
|
+# undef eret
|
||||||
|
+# endif
|
||||||
|
+# define eret \
|
||||||
|
+ .set push; \
|
||||||
|
+ .set noreorder; \
|
||||||
|
+ nop; \
|
||||||
|
+ nop; \
|
||||||
|
+ eret; \
|
||||||
|
+ .set pop;
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
#define PANIC_PIC(msg) \
|
||||||
|
.set push; \
|
||||||
|
.set reorder; \
|
||||||
|
@@ -54,7 +67,6 @@ NESTED(except_vec3_generic, 0, sp)
|
||||||
|
.set noat
|
||||||
|
#ifdef CONFIG_BCM47XX
|
||||||
|
nop
|
||||||
|
- nop
|
||||||
|
#endif
|
||||||
|
#if R5432_CP0_INTERRUPT_WAR
|
||||||
|
mfc0 k0, CP0_INDEX
|
||||||
|
@@ -79,6 +91,9 @@ NESTED(except_vec3_r4000, 0, sp)
|
||||||
|
.set push
|
||||||
|
.set mips3
|
||||||
|
.set noat
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+ nop
|
||||||
|
+#endif
|
||||||
|
mfc0 k1, CP0_CAUSE
|
||||||
|
li k0, 31<<2
|
||||||
|
andi k1, k1, 0x7c
|
||||||
46
target/linux/brcm47xx/patches-2.6.36/940-bcm47xx-yenta.patch
Normal file
46
target/linux/brcm47xx/patches-2.6.36/940-bcm47xx-yenta.patch
Normal file
|
|
@ -0,0 +1,46 @@
|
||||||
|
--- a/drivers/pcmcia/yenta_socket.c
|
||||||
|
+++ b/drivers/pcmcia/yenta_socket.c
|
||||||
|
@@ -921,6 +921,8 @@ static unsigned int yenta_probe_irq(stru
|
||||||
|
* Probe for usable interrupts using the force
|
||||||
|
* register to generate bogus card status events.
|
||||||
|
*/
|
||||||
|
+#ifndef CONFIG_BCM47XX
|
||||||
|
+ /* WRT54G3G does not like this */
|
||||||
|
cb_writel(socket, CB_SOCKET_EVENT, -1);
|
||||||
|
cb_writel(socket, CB_SOCKET_MASK, CB_CSTSMASK);
|
||||||
|
reg = exca_readb(socket, I365_CSCINT);
|
||||||
|
@@ -936,6 +938,7 @@ static unsigned int yenta_probe_irq(stru
|
||||||
|
}
|
||||||
|
cb_writel(socket, CB_SOCKET_MASK, 0);
|
||||||
|
exca_writeb(socket, I365_CSCINT, reg);
|
||||||
|
+#endif
|
||||||
|
|
||||||
|
mask = probe_irq_mask(val) & 0xffff;
|
||||||
|
|
||||||
|
@@ -1020,6 +1023,10 @@ static void yenta_get_socket_capabilitie
|
||||||
|
else
|
||||||
|
socket->socket.irq_mask = 0;
|
||||||
|
|
||||||
|
+ /* irq mask probing is broken for the WRT54G3G */
|
||||||
|
+ if (socket->socket.irq_mask == 0)
|
||||||
|
+ socket->socket.irq_mask = 0x6f8;
|
||||||
|
+
|
||||||
|
dev_printk(KERN_INFO, &socket->dev->dev,
|
||||||
|
"ISA IRQ mask 0x%04x, PCI irq %d\n",
|
||||||
|
socket->socket.irq_mask, socket->cb_irq);
|
||||||
|
@@ -1258,6 +1265,15 @@ static int __devinit yenta_probe(struct
|
||||||
|
dev_printk(KERN_INFO, &dev->dev,
|
||||||
|
"Socket status: %08x\n", cb_readl(socket, CB_SOCKET_STATE));
|
||||||
|
|
||||||
|
+ /* Generate an interrupt on card insert/remove */
|
||||||
|
+ config_writew(socket, CB_SOCKET_MASK, CB_CSTSMASK | CB_CDMASK);
|
||||||
|
+
|
||||||
|
+ /* Set up Multifunction Routing Status Register */
|
||||||
|
+ config_writew(socket, 0x8C, 0x1000 /* MFUNC3 to GPIO3 */ | 0x2 /* MFUNC0 to INTA */);
|
||||||
|
+
|
||||||
|
+ /* Switch interrupts to parallelized */
|
||||||
|
+ config_writeb(socket, 0x92, 0x64);
|
||||||
|
+
|
||||||
|
yenta_fixup_parent_bridge(dev->subordinate);
|
||||||
|
|
||||||
|
/* Register it with the pcmcia layer.. */
|
||||||
|
|
@ -0,0 +1,45 @@
|
||||||
|
--- a/drivers/ssb/main.c
|
||||||
|
+++ b/drivers/ssb/main.c
|
||||||
|
@@ -384,6 +384,34 @@ static int ssb_device_uevent(struct devi
|
||||||
|
ssb_dev->id.revision);
|
||||||
|
}
|
||||||
|
|
||||||
|
+#define ssb_config_attr(attrib, field, format_string) \
|
||||||
|
+static ssize_t \
|
||||||
|
+attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
|
||||||
|
+{ \
|
||||||
|
+ return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+ssb_config_attr(core_num, core_index, "%u\n")
|
||||||
|
+ssb_config_attr(coreid, id.coreid, "0x%04x\n")
|
||||||
|
+ssb_config_attr(vendor, id.vendor, "0x%04x\n")
|
||||||
|
+ssb_config_attr(revision, id.revision, "%u\n")
|
||||||
|
+ssb_config_attr(irq, irq, "%u\n")
|
||||||
|
+static ssize_t
|
||||||
|
+name_show(struct device *dev, struct device_attribute *attr, char *buf)
|
||||||
|
+{
|
||||||
|
+ return sprintf(buf, "%s\n", ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static struct device_attribute ssb_device_attrs[] = {
|
||||||
|
+ __ATTR_RO(name),
|
||||||
|
+ __ATTR_RO(core_num),
|
||||||
|
+ __ATTR_RO(coreid),
|
||||||
|
+ __ATTR_RO(vendor),
|
||||||
|
+ __ATTR_RO(revision),
|
||||||
|
+ __ATTR_RO(irq),
|
||||||
|
+ __ATTR_NULL,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
static struct bus_type ssb_bustype = {
|
||||||
|
.name = "ssb",
|
||||||
|
.match = ssb_bus_match,
|
||||||
|
@@ -393,6 +421,7 @@ static struct bus_type ssb_bustype = {
|
||||||
|
.suspend = ssb_device_suspend,
|
||||||
|
.resume = ssb_device_resume,
|
||||||
|
.uevent = ssb_device_uevent,
|
||||||
|
+ .dev_attrs = ssb_device_attrs,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void ssb_buses_lock(void)
|
||||||
104
target/linux/brcm47xx/patches-2.6.36/951-brcm4716-defines.patch
Normal file
104
target/linux/brcm47xx/patches-2.6.36/951-brcm4716-defines.patch
Normal file
|
|
@ -0,0 +1,104 @@
|
||||||
|
--- a/drivers/ssb/scan.c
|
||||||
|
+++ b/drivers/ssb/scan.c
|
||||||
|
@@ -91,6 +91,14 @@ const char *ssb_core_name(u16 coreid)
|
||||||
|
return "ARM 1176";
|
||||||
|
case SSB_DEV_ARM_7TDMI:
|
||||||
|
return "ARM 7TDMI";
|
||||||
|
+ case SSB_DEV_ETHERNET_GBIT2:
|
||||||
|
+ return "Gigabit MAC";
|
||||||
|
+ case SSB_DEV_MIPS_74K:
|
||||||
|
+ return "MIPS 74k";
|
||||||
|
+ case SSB_DEV_DDR_CTRLR:
|
||||||
|
+ return "DDR1/2 memory controller";
|
||||||
|
+ case SSB_DEV_I2S:
|
||||||
|
+ return "I2S";
|
||||||
|
}
|
||||||
|
return "UNKNOWN";
|
||||||
|
}
|
||||||
|
@@ -149,6 +157,7 @@ static u8 chipid_to_nrcores(u16 chipid)
|
||||||
|
case 0x4710:
|
||||||
|
case 0x4610:
|
||||||
|
case 0x4704:
|
||||||
|
+ case 0x4716:
|
||||||
|
return 9;
|
||||||
|
default:
|
||||||
|
ssb_printk(KERN_ERR PFX
|
||||||
|
--- a/include/linux/ssb/ssb.h
|
||||||
|
+++ b/include/linux/ssb/ssb.h
|
||||||
|
@@ -151,9 +151,16 @@ struct ssb_bus_ops {
|
||||||
|
#define SSB_DEV_MINI_MACPHY 0x823
|
||||||
|
#define SSB_DEV_ARM_1176 0x824
|
||||||
|
#define SSB_DEV_ARM_7TDMI 0x825
|
||||||
|
+#define SSB_DEV_ETHERNET_GBIT2 0x82d
|
||||||
|
+#define SSB_DEV_MIPS_74K 0x82c
|
||||||
|
+#define SSB_DEV_DDR_CTRLR 0x82e
|
||||||
|
+#define SSB_DEV_I2S 0x834
|
||||||
|
+#define SSB_DEV_DEFAULT 0xfff
|
||||||
|
|
||||||
|
/* Vendor-ID values */
|
||||||
|
#define SSB_VENDOR_BROADCOM 0x4243
|
||||||
|
+#define SSB_VENDOR_BROADCOM2 0x04BF
|
||||||
|
+#define SSB_VENDOR_ARM 0x43b
|
||||||
|
|
||||||
|
/* Some kernel subsystems poke with dev->drvdata, so we must use the
|
||||||
|
* following ugly workaround to get from struct device to struct ssb_device */
|
||||||
|
--- a/include/linux/ssb/ssb_regs.h
|
||||||
|
+++ b/include/linux/ssb/ssb_regs.h
|
||||||
|
@@ -11,6 +11,7 @@
|
||||||
|
#define SSB_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */
|
||||||
|
#define SSB_ENUM_BASE 0x18000000U /* Enumeration space base */
|
||||||
|
#define SSB_ENUM_LIMIT 0x18010000U /* Enumeration space limit */
|
||||||
|
+#define SSB_AI_BASE 0x18100000 /* base for AI registers */
|
||||||
|
|
||||||
|
#define SSB_FLASH2 0x1c000000U /* Flash Region 2 (region 1 shadowed here) */
|
||||||
|
#define SSB_FLASH2_SZ 0x02000000U /* Size of Flash Region 2 */
|
||||||
|
@@ -26,6 +27,7 @@
|
||||||
|
#define SSB_EUART (SSB_EXTIF_BASE + 0x00800000)
|
||||||
|
#define SSB_LED (SSB_EXTIF_BASE + 0x00900000)
|
||||||
|
|
||||||
|
+#define SSB_EROM_ASD_SZ_BASE 0x00001000
|
||||||
|
|
||||||
|
/* Enumeration space constants */
|
||||||
|
#define SSB_CORE_SIZE 0x1000 /* Size of a core MMIO area */
|
||||||
|
@@ -453,5 +455,41 @@ enum {
|
||||||
|
#define SSB_ADM_BASE2 0xFFFF0000 /* Type2 base address for the core */
|
||||||
|
#define SSB_ADM_BASE2_SHIFT 16
|
||||||
|
|
||||||
|
+/***** EROM defines for AI type busses *****/
|
||||||
|
+#define SSB_EROM_VALID 1
|
||||||
|
+#define SSB_EROM_END 0xe
|
||||||
|
+#define SSB_EROM_TAG 0xe
|
||||||
|
+/* Adress Space Descriptor */
|
||||||
|
+#define SSB_EROM_ASD 0x4
|
||||||
|
+#define SSB_EROM_ASD_SP_MASK 0x00000f00
|
||||||
|
+#define SSB_EROM_ASD_SP_SHIFT 8
|
||||||
|
+#define SSB_EROM_ASD_ST_MASK 0x000000c0
|
||||||
|
+#define SSB_EROM_ASD_ST_SLAVE 0x00000000
|
||||||
|
+#define SSB_EROM_ASD_ST_BRIDGE 0x00000040
|
||||||
|
+#define SSB_EROM_ASD_ST_MWRAP 0x000000c0
|
||||||
|
+#define SSB_EROM_ASD_ST_SWRAP 0x00000080
|
||||||
|
+#define SSB_EROM_ASD_ADDR_MASK 0xfffff000
|
||||||
|
+#define SSB_EROM_ASD_AG32 0x00000008
|
||||||
|
+#define SSB_EROM_ASD_SZ_MASK 0x00000030
|
||||||
|
+#define SSB_EROM_ASD_SZ_SZD 0x00000030
|
||||||
|
+#define SSB_EROM_ASD_SZ_SHIFT 4
|
||||||
|
+#define SSB_EROM_CI 0
|
||||||
|
+#define SSB_EROM_CIA_CID_MASK 0x000fff00
|
||||||
|
+#define SSB_EROM_CIA_CID_SHIFT 8
|
||||||
|
+#define SSB_EROM_CIA_MFG_MASK 0xfff00000
|
||||||
|
+#define SSB_EROM_CIA_MFG_SHIFT 20
|
||||||
|
+#define SSB_EROM_CIB_REV_MASK 0xff000000
|
||||||
|
+#define SSB_EROM_CIB_REV_SHIFT 24
|
||||||
|
+#define SSB_EROM_CIB_NMW_MASK 0x0007c000
|
||||||
|
+#define SSB_EROM_CIB_NSW_MASK 0x00f80000
|
||||||
|
+#define SSB_EROM_CIB_NSP_MASK 0x00003e00
|
||||||
|
+
|
||||||
|
+/***** Registers of AI config space *****/
|
||||||
|
+#define SSB_AI_RESETCTRL 0x800 /* maybe 0x804 for big endian */
|
||||||
|
+#define SSB_AI_RESETCTRL_RESET 1
|
||||||
|
+#define SSB_AI_IOCTRL 0x408 /* maybe 0x40c for big endian */
|
||||||
|
+#define SSB_CF_FGC 0x0002
|
||||||
|
+#define SSB_CF_CLOCK_EN 0x001
|
||||||
|
+#define SSB_AI_oobselouta30 0x100
|
||||||
|
|
||||||
|
#endif /* LINUX_SSB_REGS_H_ */
|
||||||
22
target/linux/brcm47xx/patches-2.6.36/999-wl_exports.patch
Normal file
22
target/linux/brcm47xx/patches-2.6.36/999-wl_exports.patch
Normal file
|
|
@ -0,0 +1,22 @@
|
||||||
|
--- a/arch/mips/bcm47xx/nvram.c
|
||||||
|
+++ b/arch/mips/bcm47xx/nvram.c
|
||||||
|
@@ -20,7 +20,8 @@
|
||||||
|
#include <asm/mach-bcm47xx/nvram.h>
|
||||||
|
#include <asm/mach-bcm47xx/bcm47xx.h>
|
||||||
|
|
||||||
|
-static char nvram_buf[NVRAM_SPACE];
|
||||||
|
+char nvram_buf[NVRAM_SPACE];
|
||||||
|
+EXPORT_SYMBOL(nvram_buf);
|
||||||
|
|
||||||
|
/* Probe for NVRAM header */
|
||||||
|
static void __init early_nvram_init(void)
|
||||||
|
--- a/arch/mips/mm/cache.c
|
||||||
|
+++ b/arch/mips/mm/cache.c
|
||||||
|
@@ -52,6 +52,7 @@ void (*_dma_cache_wback)(unsigned long s
|
||||||
|
void (*_dma_cache_inv)(unsigned long start, unsigned long size);
|
||||||
|
|
||||||
|
EXPORT_SYMBOL(_dma_cache_wback_inv);
|
||||||
|
+EXPORT_SYMBOL(_dma_cache_inv);
|
||||||
|
|
||||||
|
#endif /* CONFIG_DMA_NONCOHERENT */
|
||||||
|
|
||||||
Loading…
Reference in a new issue