ar71xx: boost SPI flash read performance
mtd_speedtest results:
page read speed
old new delta
DB120 929 KiB/s 2597 KiB/s +179.55%
TL-WR1043ND v1 754 KiB/s 2166 KiB/s +187.27%
TL-WR703N v1 745 KiB/s 2176 KiB/s +192.08%
TL-MR3220 v1 752 KiB/s 2154 KiB/s +186.44%
TL-WR2543ND v1 564 KiB/s 2130 KiB/s +277.66%
TL-WR741ND v2 525 KiB/s 1767 KiB/s +236.57%
ALFA-AP96 702 KiB/s 1977 KiB/s +181.62%
WNDR3700 697 KiB/s 1965 KiB/s +181.92%
SVN-Revision: 31118
This commit is contained in:
Gabor Juhos
parent
102c6df148
commit
b77217d963
11 changed files with 504 additions and 1 deletions
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@ -51,6 +51,7 @@ void __init ath79_register_m25p80(struct flash_platform_data *pdata)
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{
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ath79_spi_data.bus_num = 0;
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ath79_spi_data.num_chipselect = 1;
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ath79_spi0_cdata.is_flash = true;
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ath79_spi_info[0].platform_data = pdata;
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ath79_register_spi(&ath79_spi_data, ath79_spi_info, 1);
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}
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@ -62,6 +62,7 @@ static struct mmc_spi_platform_data alfa_ap96_mmc_data = {
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static struct ath79_spi_controller_data ap96_spi0_cdata = {
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.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
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.cs_line = 0,
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.is_flash = true,
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};
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static struct ath79_spi_controller_data ap96_spi1_cdata = {
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@ -40,7 +40,6 @@ static const char *tl_wr2543n_part_probes[] = {
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static struct flash_platform_data tl_wr2543n_flash_data = {
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.part_probes = tl_wr2543n_part_probes,
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.max_read_len = 64,
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};
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static struct gpio_led tl_wr2543n_leds_gpio[] __initdata = {
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@ -0,0 +1,28 @@
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--- a/drivers/spi/spi-bitbang.c
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+++ b/drivers/spi/spi-bitbang.c
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@@ -234,13 +234,14 @@ void spi_bitbang_cleanup(struct spi_devi
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}
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EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);
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-static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
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+int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
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{
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struct spi_bitbang_cs *cs = spi->controller_state;
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unsigned nsecs = cs->nsecs;
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return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t);
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}
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+EXPORT_SYMBOL_GPL(spi_bitbang_bufs);
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/*----------------------------------------------------------------------*/
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--- a/include/linux/spi/spi_bitbang.h
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+++ b/include/linux/spi/spi_bitbang.h
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@@ -44,6 +44,7 @@ extern void spi_bitbang_cleanup(struct s
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extern int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m);
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extern int spi_bitbang_setup_transfer(struct spi_device *spi,
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struct spi_transfer *t);
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+extern int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t);
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/* start or stop queue processing */
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extern int spi_bitbang_start(struct spi_bitbang *spi);
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@ -0,0 +1,23 @@
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--- a/include/linux/spi/spi.h
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+++ b/include/linux/spi/spi.h
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@@ -344,6 +344,12 @@ extern struct spi_master *spi_busnum_to_
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/*---------------------------------------------------------------------------*/
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+enum spi_transfer_type {
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+ SPI_TRANSFER_GENERIC = 0,
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+ SPI_TRANSFER_FLASH_READ_CMD,
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+ SPI_TRANSFER_FLASH_READ_DATA,
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+};
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+
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/*
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* I/O INTERFACE between SPI controller and protocol drivers
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*
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@@ -446,6 +452,7 @@ struct spi_transfer {
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u8 bits_per_word;
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u16 delay_usecs;
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u32 speed_hz;
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+ enum spi_transfer_type type;
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struct list_head transfer_list;
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};
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@ -0,0 +1,15 @@
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--- a/drivers/mtd/devices/m25p80.c
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+++ b/drivers/mtd/devices/m25p80.c
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@@ -372,10 +372,12 @@ static int m25p80_read(struct mtd_info *
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* OPCODE_FAST_READ (if available) is faster.
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* Should add 1 byte DUMMY_BYTE.
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*/
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+ t[0].type = SPI_TRANSFER_FLASH_READ_CMD;
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t[0].tx_buf = flash->command;
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t[0].len = m25p_cmdsz(flash) + FAST_READ_DUMMY_BYTE;
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spi_message_add_tail(&t[0], &m);
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+ t[1].type = SPI_TRANSFER_FLASH_READ_DATA;
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spi_message_add_tail(&t[1], &m);
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/* Byte count starts at zero. */
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@ -0,0 +1,185 @@
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--- a/drivers/spi/spi-ath79.c
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+++ b/drivers/spi/spi-ath79.c
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@@ -37,6 +37,11 @@
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#define ATH79_SPI_CS_LINE_MAX 2
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+enum ath79_spi_state {
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+ ATH79_SPI_STATE_WAIT_CMD = 0,
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+ ATH79_SPI_STATE_WAIT_READ,
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+};
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+
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struct ath79_spi {
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struct spi_bitbang bitbang;
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u32 ioc_base;
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@@ -44,6 +49,11 @@ struct ath79_spi {
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void __iomem *base;
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struct clk *clk;
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unsigned rrw_delay;
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+
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+ enum ath79_spi_state state;
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+ u32 clk_div;
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+ unsigned long read_addr;
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+ unsigned long ahb_rate;
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};
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static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
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@@ -108,9 +118,6 @@ static void ath79_spi_enable(struct ath7
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/* save CTRL register */
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sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
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sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
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-
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- /* TODO: setup speed? */
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- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
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}
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static void ath79_spi_disable(struct ath79_spi *sp)
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@@ -222,6 +229,110 @@ static u32 ath79_spi_txrx_mode0(struct s
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return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
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}
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+static int ath79_spi_do_read_flash_data(struct spi_device *spi,
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+ struct spi_transfer *t)
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+{
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+ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
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+
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+ /* disable GPIO mode */
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+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
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+
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+ memcpy_fromio(t->rx_buf, sp->base + sp->read_addr, t->len);
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+
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+ /* enable GPIO mode */
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+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
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+
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+ /* restore IOC register */
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+ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
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+
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+ return t->len;
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+}
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+
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+static int ath79_spi_do_read_flash_cmd(struct spi_device *spi,
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+ struct spi_transfer *t)
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+{
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+ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
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+ int len;
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+ const u8 *p;
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+
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+ sp->read_addr = 0;
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+
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+ len = t->len - 1;
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+ p = t->tx_buf;
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+
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+ while (len--) {
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+ p++;
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+ sp->read_addr <<= 8;
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+ sp->read_addr |= *p;
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+ }
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+
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+ return t->len;
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+}
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+
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+static bool ath79_spi_is_read_cmd(struct spi_device *spi,
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+ struct spi_transfer *t)
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+{
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+ return t->type == SPI_TRANSFER_FLASH_READ_CMD;
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+}
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+
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+static bool ath79_spi_is_data_read(struct spi_device *spi,
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+ struct spi_transfer *t)
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+{
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+ return t->type == SPI_TRANSFER_FLASH_READ_DATA;
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+}
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+
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+static int ath79_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
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+{
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+ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
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+ int ret;
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+
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+ switch (sp->state) {
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+ case ATH79_SPI_STATE_WAIT_CMD:
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+ if (ath79_spi_is_read_cmd(spi, t)) {
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+ ret = ath79_spi_do_read_flash_cmd(spi, t);
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+ sp->state = ATH79_SPI_STATE_WAIT_READ;
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+ } else {
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+ ret = spi_bitbang_bufs(spi, t);
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+ }
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+ break;
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+
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+ case ATH79_SPI_STATE_WAIT_READ:
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+ if (ath79_spi_is_data_read(spi, t)) {
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+ ret = ath79_spi_do_read_flash_data(spi, t);
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+ } else {
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+ dev_warn(&spi->dev, "flash data read expected\n");
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+ ret = -EIO;
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+ }
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+ sp->state = ATH79_SPI_STATE_WAIT_CMD;
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+ break;
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+
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+ default:
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+ BUG();
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+ }
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+
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+ return ret;
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+}
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+
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+static int ath79_spi_setup_transfer(struct spi_device *spi,
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+ struct spi_transfer *t)
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+{
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+ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
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+ struct ath79_spi_controller_data *cdata;
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+ int ret;
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+
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+ ret = spi_bitbang_setup_transfer(spi, t);
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+ if (ret)
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+ return ret;
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+
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+ cdata = spi->controller_data;
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+ if (cdata->is_flash)
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+ sp->bitbang.txrx_bufs = ath79_spi_txrx_bufs;
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+ else
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+ sp->bitbang.txrx_bufs = spi_bitbang_bufs;
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+
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+ return ret;
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+}
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+
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static __devinit int ath79_spi_probe(struct platform_device *pdev)
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{
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struct spi_master *master;
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@@ -244,6 +355,8 @@ static __devinit int ath79_spi_probe(str
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sp = spi_master_get_devdata(master);
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platform_set_drvdata(pdev, sp);
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+ sp->state = ATH79_SPI_STATE_WAIT_CMD;
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+
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master->setup = ath79_spi_setup;
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master->cleanup = ath79_spi_cleanup;
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master->bus_num = pdata->bus_num;
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@@ -252,7 +365,7 @@ static __devinit int ath79_spi_probe(str
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sp->bitbang.master = spi_master_get(master);
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sp->bitbang.chipselect = ath79_spi_chipselect;
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sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
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- sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
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+ sp->bitbang.setup_transfer = ath79_spi_setup_transfer;
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sp->bitbang.flags = SPI_CS_HIGH;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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@@ -277,7 +390,8 @@ static __devinit int ath79_spi_probe(str
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if (ret)
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goto err_clk_put;
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- rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
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+ sp->ahb_rate = clk_get_rate(sp->clk);
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+ rate = DIV_ROUND_UP(sp->ahb_rate, MHZ);
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if (!rate) {
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ret = -EINVAL;
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goto err_clk_disable;
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--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
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+++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
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@@ -24,6 +24,7 @@ enum ath79_spi_cs_type {
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struct ath79_spi_controller_data {
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enum ath79_spi_cs_type cs_type;
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unsigned cs_line;
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+ bool is_flash;
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};
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#endif /* _ATH79_SPI_PLATFORM_H */
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@ -0,0 +1,28 @@
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--- a/drivers/spi/spi-bitbang.c
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+++ b/drivers/spi/spi-bitbang.c
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@@ -234,13 +234,14 @@ void spi_bitbang_cleanup(struct spi_devi
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}
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EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);
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-static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
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+int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
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{
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struct spi_bitbang_cs *cs = spi->controller_state;
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unsigned nsecs = cs->nsecs;
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return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t);
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}
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+EXPORT_SYMBOL_GPL(spi_bitbang_bufs);
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/*----------------------------------------------------------------------*/
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--- a/include/linux/spi/spi_bitbang.h
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+++ b/include/linux/spi/spi_bitbang.h
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@@ -44,6 +44,7 @@ extern void spi_bitbang_cleanup(struct s
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extern int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m);
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extern int spi_bitbang_setup_transfer(struct spi_device *spi,
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struct spi_transfer *t);
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+extern int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t);
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/* start or stop queue processing */
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extern int spi_bitbang_start(struct spi_bitbang *spi);
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@ -0,0 +1,23 @@
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--- a/include/linux/spi/spi.h
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+++ b/include/linux/spi/spi.h
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@@ -355,6 +355,12 @@ extern struct spi_master *spi_busnum_to_
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/*---------------------------------------------------------------------------*/
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+enum spi_transfer_type {
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+ SPI_TRANSFER_GENERIC = 0,
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+ SPI_TRANSFER_FLASH_READ_CMD,
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+ SPI_TRANSFER_FLASH_READ_DATA,
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+};
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+
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/*
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* I/O INTERFACE between SPI controller and protocol drivers
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*
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@@ -457,6 +463,7 @@ struct spi_transfer {
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u8 bits_per_word;
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u16 delay_usecs;
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u32 speed_hz;
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+ enum spi_transfer_type type;
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struct list_head transfer_list;
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};
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@ -0,0 +1,15 @@
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--- a/drivers/mtd/devices/m25p80.c
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+++ b/drivers/mtd/devices/m25p80.c
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@@ -372,10 +372,12 @@ static int m25p80_read(struct mtd_info *
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* OPCODE_FAST_READ (if available) is faster.
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* Should add 1 byte DUMMY_BYTE.
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*/
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+ t[0].type = SPI_TRANSFER_FLASH_READ_CMD;
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t[0].tx_buf = flash->command;
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t[0].len = m25p_cmdsz(flash) + FAST_READ_DUMMY_BYTE;
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spi_message_add_tail(&t[0], &m);
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+ t[1].type = SPI_TRANSFER_FLASH_READ_DATA;
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spi_message_add_tail(&t[1], &m);
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/* Byte count starts at zero. */
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@ -0,0 +1,185 @@
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--- a/drivers/spi/spi-ath79.c
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+++ b/drivers/spi/spi-ath79.c
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@@ -37,6 +37,11 @@
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#define ATH79_SPI_CS_LINE_MAX 2
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+enum ath79_spi_state {
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+ ATH79_SPI_STATE_WAIT_CMD = 0,
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+ ATH79_SPI_STATE_WAIT_READ,
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+};
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+
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struct ath79_spi {
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struct spi_bitbang bitbang;
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u32 ioc_base;
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@@ -44,6 +49,11 @@ struct ath79_spi {
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void __iomem *base;
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struct clk *clk;
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unsigned rrw_delay;
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+
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+ enum ath79_spi_state state;
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+ u32 clk_div;
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+ unsigned long read_addr;
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+ unsigned long ahb_rate;
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};
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static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
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@@ -108,9 +118,6 @@ static void ath79_spi_enable(struct ath7
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/* save CTRL register */
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sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
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sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
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-
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- /* TODO: setup speed? */
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- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
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}
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static void ath79_spi_disable(struct ath79_spi *sp)
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@@ -222,6 +229,110 @@ static u32 ath79_spi_txrx_mode0(struct s
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return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
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}
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+static int ath79_spi_do_read_flash_data(struct spi_device *spi,
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+ struct spi_transfer *t)
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+{
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+ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
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+
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+ /* disable GPIO mode */
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+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
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+
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+ memcpy_fromio(t->rx_buf, sp->base + sp->read_addr, t->len);
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+
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+ /* enable GPIO mode */
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+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
|
||||
+
|
||||
+ /* restore IOC register */
|
||||
+ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
|
||||
+
|
||||
+ return t->len;
|
||||
+}
|
||||
+
|
||||
+static int ath79_spi_do_read_flash_cmd(struct spi_device *spi,
|
||||
+ struct spi_transfer *t)
|
||||
+{
|
||||
+ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
|
||||
+ int len;
|
||||
+ const u8 *p;
|
||||
+
|
||||
+ sp->read_addr = 0;
|
||||
+
|
||||
+ len = t->len - 1;
|
||||
+ p = t->tx_buf;
|
||||
+
|
||||
+ while (len--) {
|
||||
+ p++;
|
||||
+ sp->read_addr <<= 8;
|
||||
+ sp->read_addr |= *p;
|
||||
+ }
|
||||
+
|
||||
+ return t->len;
|
||||
+}
|
||||
+
|
||||
+static bool ath79_spi_is_read_cmd(struct spi_device *spi,
|
||||
+ struct spi_transfer *t)
|
||||
+{
|
||||
+ return t->type == SPI_TRANSFER_FLASH_READ_CMD;
|
||||
+}
|
||||
+
|
||||
+static bool ath79_spi_is_data_read(struct spi_device *spi,
|
||||
+ struct spi_transfer *t)
|
||||
+{
|
||||
+ return t->type == SPI_TRANSFER_FLASH_READ_DATA;
|
||||
+}
|
||||
+
|
||||
+static int ath79_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
|
||||
+{
|
||||
+ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
|
||||
+ int ret;
|
||||
+
|
||||
+ switch (sp->state) {
|
||||
+ case ATH79_SPI_STATE_WAIT_CMD:
|
||||
+ if (ath79_spi_is_read_cmd(spi, t)) {
|
||||
+ ret = ath79_spi_do_read_flash_cmd(spi, t);
|
||||
+ sp->state = ATH79_SPI_STATE_WAIT_READ;
|
||||
+ } else {
|
||||
+ ret = spi_bitbang_bufs(spi, t);
|
||||
+ }
|
||||
+ break;
|
||||
+
|
||||
+ case ATH79_SPI_STATE_WAIT_READ:
|
||||
+ if (ath79_spi_is_data_read(spi, t)) {
|
||||
+ ret = ath79_spi_do_read_flash_data(spi, t);
|
||||
+ } else {
|
||||
+ dev_warn(&spi->dev, "flash data read expected\n");
|
||||
+ ret = -EIO;
|
||||
+ }
|
||||
+ sp->state = ATH79_SPI_STATE_WAIT_CMD;
|
||||
+ break;
|
||||
+
|
||||
+ default:
|
||||
+ BUG();
|
||||
+ }
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int ath79_spi_setup_transfer(struct spi_device *spi,
|
||||
+ struct spi_transfer *t)
|
||||
+{
|
||||
+ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
|
||||
+ struct ath79_spi_controller_data *cdata;
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = spi_bitbang_setup_transfer(spi, t);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ cdata = spi->controller_data;
|
||||
+ if (cdata->is_flash)
|
||||
+ sp->bitbang.txrx_bufs = ath79_spi_txrx_bufs;
|
||||
+ else
|
||||
+ sp->bitbang.txrx_bufs = spi_bitbang_bufs;
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
static __devinit int ath79_spi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master;
|
||||
@@ -244,6 +355,8 @@ static __devinit int ath79_spi_probe(str
|
||||
sp = spi_master_get_devdata(master);
|
||||
platform_set_drvdata(pdev, sp);
|
||||
|
||||
+ sp->state = ATH79_SPI_STATE_WAIT_CMD;
|
||||
+
|
||||
master->setup = ath79_spi_setup;
|
||||
master->cleanup = ath79_spi_cleanup;
|
||||
master->bus_num = pdata->bus_num;
|
||||
@@ -252,7 +365,7 @@ static __devinit int ath79_spi_probe(str
|
||||
sp->bitbang.master = spi_master_get(master);
|
||||
sp->bitbang.chipselect = ath79_spi_chipselect;
|
||||
sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
|
||||
- sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
|
||||
+ sp->bitbang.setup_transfer = ath79_spi_setup_transfer;
|
||||
sp->bitbang.flags = SPI_CS_HIGH;
|
||||
|
||||
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
@@ -277,7 +390,8 @@ static __devinit int ath79_spi_probe(str
|
||||
if (ret)
|
||||
goto err_clk_put;
|
||||
|
||||
- rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
|
||||
+ sp->ahb_rate = clk_get_rate(sp->clk);
|
||||
+ rate = DIV_ROUND_UP(sp->ahb_rate, MHZ);
|
||||
if (!rate) {
|
||||
ret = -EINVAL;
|
||||
goto err_clk_disable;
|
||||
--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
|
||||
+++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
|
||||
@@ -24,6 +24,7 @@ enum ath79_spi_cs_type {
|
||||
struct ath79_spi_controller_data {
|
||||
enum ath79_spi_cs_type cs_type;
|
||||
unsigned cs_line;
|
||||
+ bool is_flash;
|
||||
};
|
||||
|
||||
#endif /* _ATH79_SPI_PLATFORM_H */
|
||||
Loading…
Reference in a new issue