KumiSystems/openwrtv3
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

fix the PCI byte lane enable generation code, based on a patch by Chris Dearman

Browse source 
SVN-Revision: 12617
This commit is contained in:
Gabor Juhos 2008-09-17 13:29:47 +00:00
parent 954c24c5ed
commit a43e2d5ac6
1 changed files with 6 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
View file

@ -59,17 +59,18 @@ static inline void ar71xx_pcicfg_wr(unsigned int reg, u32 val)
/* Byte lane enable bits */ /* Byte lane enable bits */
static u8 ble_table[4][4] = { static u8 ble_table[4][4] = {
{0xf, 0xe, 0xd, 0xc}, {0x0, 0xf, 0xf, 0xf},
{0xc, 0x9, 0x3, 0x1}, {0xe, 0xd, 0xb, 0x7},
{0x0, 0x0, 0x0, 0x0}, {0xc, 0xf, 0x3, 0xf},
{0x0, 0x0, 0x0, 0x0}, {0xf, 0xf, 0xf, 0xf},
}; };
static inline u32 ar71xx_pci_get_ble(int where, int size, int local) static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
{ {
u32 t; u32 t;
t = ble_table[size][where & 3]; t = ble_table[size & 3][where & 3];
BUG_ON(t == 0xf);
t <<= (local) ? 20 : 4; t <<= (local) ? 20 : 4;
return t; return t;
} }