arc: use patched .dts from sources
Instead of using off-the-tree .dts files for ARC boards we're switching to use in-tree ones. And for that to work properly we apply upstream patch that adds currently missing "model" property. Upstream patch and discussion could be found here: http://lists.infradead.org/pipermail/linux-snps-arc/2016-August/001394.html Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Jonas Gorski <jonas.gorski@gmail.com> Cc: John Crispin <john@phrozen.org>
This commit is contained in:
Alexey Brodkin
John Crispin
parent
c41506625a
commit
a3cde14f5a
13 changed files with 194 additions and 943 deletions
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@ -1,100 +0,0 @@
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/*
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* Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* Device tree for AXC001 770D/EM6/AS221 CPU card
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* Note that this file only supports the 770D CPU
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*/
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/ {
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compatible = "snps,arc";
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clock-frequency = <750000000>; /* 750 MHZ */
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#address-cells = <1>;
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#size-cells = <1>;
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cpu_card {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0xf0000000 0x10000000>;
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cpu_intc: arc700-intc@cpu {
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compatible = "snps,arc700-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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/*
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* this GPIO block ORs all interrupts on CPU card (creg,..)
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* to uplink only 1 IRQ to ARC core intc
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*/
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dw-apb-gpio@0x2000 {
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compatible = "snps,dw-apb-gpio";
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reg = < 0x2000 0x80 >;
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#address-cells = <1>;
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#size-cells = <0>;
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ictl_intc: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <30>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&cpu_intc>;
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interrupts = <15>;
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};
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};
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debug_uart: dw-apb-uart@0x5000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x5000 0x100>;
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clock-frequency = <33333000>;
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interrupt-parent = <&ictl_intc>;
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interrupts = <19 4>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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arcpmu0: pmu {
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compatible = "snps,arc700-pct";
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};
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};
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/*
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* This INTC is actually connected to DW APB GPIO
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* which acts as a wire between MB INTC and CPU INTC.
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* GPIO INTC is configured in platform init code
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* and here we mimic direct connection from MB INTC to
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* CPU INTC, thus we set "interrupts = <7>" instead of
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* "interrupts = <12>"
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*
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* This intc actually resides on MB, but we move it here to
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* avoid duplicating the MB dtsi file given that IRQ from
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* this intc to cpu intc are different for axs101 and axs103
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*/
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mb_intc: dw-apb-ictl@0xe0012000 {
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#interrupt-cells = <1>;
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compatible = "snps,dw-apb-ictl";
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reg = < 0xe0012000 0x200 >;
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interrupt-controller;
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interrupt-parent = <&cpu_intc>;
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interrupts = < 7 >;
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};
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memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x80000000 0x40000000>;
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device_type = "memory";
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reg = <0x80000000 0x20000000>; /* 512MiB */
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};
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};
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@ -1,22 +0,0 @@
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/*
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* Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
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*
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* ARC AXS101 S/W development platform
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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/include/ "axc001.dtsi"
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/include/ "axs10x_mb.dtsi"
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/ {
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model = "Synopsys AXS101 Development Board";
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compatible = "snps,axs101", "snps,arc-sdp";
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chosen {
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bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=ttyS3,115200n8";
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};
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};
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@ -1,225 +0,0 @@
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/*
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* Support for peripherals on the AXS10x mainboard
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*
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* Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/ {
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axs10x_mb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0xe0000000 0x10000000>;
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interrupt-parent = <&mb_intc>;
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clocks {
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i2cclk: i2cclk {
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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#clock-cells = <0>;
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};
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apbclk: apbclk {
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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#clock-cells = <0>;
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};
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mmcclk: mmcclk {
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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#clock-cells = <0>;
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};
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};
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ethernet@0x18000 {
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#interrupt-cells = <1>;
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compatible = "snps,dwmac";
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reg = < 0x18000 0x2000 >;
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interrupts = < 4 >;
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interrupt-names = "macirq";
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phy-mode = "rgmii";
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snps,pbl = < 32 >;
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clocks = <&apbclk>;
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clock-names = "stmmaceth";
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max-speed = <100>;
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};
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ehci@0x40000 {
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compatible = "generic-ehci";
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reg = < 0x40000 0x100 >;
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interrupts = < 8 >;
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};
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ohci@0x60000 {
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compatible = "generic-ohci";
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reg = < 0x60000 0x100 >;
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interrupts = < 8 >;
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};
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/*
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* According to DW Mobile Storage databook it is required
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* to use "Hold Register" if card is enumerated in SDR12 or
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* SDR25 modes.
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*
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* Utilization of "Hold Register" is already implemented via
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* dw_mci_pltfm_prepare_command() which in its turn gets
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* used through dw_mci_drv_data->prepare_command call-back.
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* This call-back is used in Altera Socfpga platform and so
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* we may reuse it saying that we're compatible with their
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* "altr,socfpga-dw-mshc".
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*
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* Most probably "Hold Register" utilization is platform-
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* independent requirement which means that single unified
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* "snps,dw-mshc" should be enough for all users of DW MMC once
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* dw_mci_pltfm_prepare_command() is used in generic platform
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* code.
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*/
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mmc@0x15000 {
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compatible = "altr,socfpga-dw-mshc";
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reg = < 0x15000 0x400 >;
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num-slots = < 1 >;
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fifo-depth = < 16 >;
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card-detect-delay = < 200 >;
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clocks = <&apbclk>, <&mmcclk>;
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clock-names = "biu", "ciu";
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interrupts = < 7 >;
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bus-width = < 4 >;
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};
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uart@0x20000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x20000 0x100>;
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clock-frequency = <33333333>;
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interrupts = <17>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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uart@0x21000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x21000 0x100>;
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clock-frequency = <33333333>;
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interrupts = <18>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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/* UART muxed with USB data port (ttyS3) */
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uart@0x22000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x22000 0x100>;
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clock-frequency = <33333333>;
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interrupts = <19>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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i2c@0x1d000 {
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compatible = "snps,designware-i2c";
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reg = <0x1d000 0x100>;
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clock-frequency = <400000>;
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clocks = <&i2cclk>;
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interrupts = <14>;
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};
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i2c@0x1e000 {
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compatible = "snps,designware-i2c";
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reg = <0x1e000 0x100>;
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clock-frequency = <400000>;
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clocks = <&i2cclk>;
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interrupts = <15>;
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};
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i2c@0x1f000 {
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compatible = "snps,designware-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1f000 0x100>;
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clock-frequency = <400000>;
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clocks = <&i2cclk>;
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interrupts = <16>;
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eeprom@0x54{
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compatible = "24c01";
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reg = <0x54>;
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pagesize = <0x8>;
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};
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eeprom@0x57{
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compatible = "24c04";
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reg = <0x57>;
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pagesize = <0x8>;
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};
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};
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gpio0:gpio@13000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x13000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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gpio0_banka: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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};
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gpio0_bankb: gpio-controller@1 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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reg = <1>;
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};
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gpio0_bankc: gpio-controller@2 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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reg = <2>;
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};
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};
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gpio1:gpio@14000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x14000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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gpio1_banka: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <30>;
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reg = <0>;
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};
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gpio1_bankb: gpio-controller@1 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <10>;
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reg = <1>;
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};
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gpio1_bankc: gpio-controller@2 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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reg = <2>;
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};
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};
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};
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};
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@ -1,71 +0,0 @@
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/*
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* Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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/include/ "skeleton.dtsi"
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/ {
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model = "Synopsys ARC770 nSIM simulator";
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compatible = "snps,nsim";
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clock-frequency = <80000000>; /* 80 MHZ */
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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chosen {
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bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8";
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};
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aliases {
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serial0 = &arcuart0;
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};
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fpga {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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/* child and parent address space 1:1 mapped */
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ranges;
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intc: interrupt-controller {
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compatible = "snps,arc700-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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arcuart0: serial@c0fc1000 {
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compatible = "snps,arc-uart";
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reg = <0xc0fc1000 0x100>;
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interrupts = <5>;
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clock-frequency = <80000000>;
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current-speed = <115200>;
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status = "okay";
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};
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ethernet@c0fc2000 {
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compatible = "snps,arc-emac";
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reg = <0xc0fc2000 0x3c>;
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interrupts = <6>;
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mac-address = [ 00 11 22 33 44 55 ];
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clock-frequency = <80000000>;
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max-speed = <100>;
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phy = <&phy0>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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reg = <1>;
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};
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};
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arcpmu0: pmu {
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compatible = "snps,arc700-pct";
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};
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};
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};
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@ -1,37 +0,0 @@
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/*
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* Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
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* published by the Free Software Foundation.
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*/
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/*
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* Skeleton device tree; the bare minimum needed to boot; just include and
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* add a compatible value.
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*/
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/ {
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compatible = "snps,arc";
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clock-frequency = <80000000>; /* 80 MHZ */
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#address-cells = <1>;
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#size-cells = <1>;
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chosen { };
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aliases { };
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "snps,arc770d";
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reg = <0>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x80000000 0x10000000>; /* 256M */
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};
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};
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@ -15,7 +15,7 @@ define Build/calculate-ep
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endef
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define Build/patch-dtb
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$(call Image/BuildDTB,../dts/$(DEVICE_DTS).dts,$@.dtb)
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$(call Image/BuildDTB,$(DTS_DIR)/$(DEVICE_DTS).dts,$@.dtb)
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$(STAGING_DIR_HOST)/bin/patch-dtb $@ $@.dtb
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endef
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@ -1,126 +0,0 @@
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/*
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* Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
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/*
|
||||
* Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc
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*/
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/ {
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compatible = "snps,arc";
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clock-frequency = <90000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpu_card {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0xf0000000 0x10000000>;
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cpu_intc: archs-intc@cpu {
|
||||
compatible = "snps,archs-intc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
idu_intc: idu-interrupt-controller {
|
||||
compatible = "snps,archs-idu-intc";
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
|
||||
/*
|
||||
* <hwirq distribution>
|
||||
* distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
|
||||
*/
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
/*
|
||||
* upstream irqs to core intc - downstream these are
|
||||
* "COMMON" irq 0,1..
|
||||
*/
|
||||
interrupts = <24 25>;
|
||||
};
|
||||
|
||||
/*
|
||||
* this GPIO block ORs all interrupts on CPU card (creg,..)
|
||||
* to uplink only 1 IRQ to ARC core intc
|
||||
*/
|
||||
dw-apb-gpio@0x2000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = < 0x2000 0x80 >;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ictl_intc: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <30>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&idu_intc>;
|
||||
|
||||
/*
|
||||
* cmn irq 1 -> cpu irq 25
|
||||
* Distribute to cpu0 only
|
||||
*/
|
||||
interrupts = <1 1>;
|
||||
};
|
||||
};
|
||||
|
||||
debug_uart: dw-apb-uart@0x5000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x5000 0x100>;
|
||||
clock-frequency = <33333000>;
|
||||
interrupt-parent = <&ictl_intc>;
|
||||
interrupts = <2 4>;
|
||||
baud = <115200>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
arcpct0: pct {
|
||||
compatible = "snps,archs-pct";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <20>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* This INTC is actually connected to DW APB GPIO
|
||||
* which acts as a wire between MB INTC and CPU INTC.
|
||||
* GPIO INTC is configured in platform init code
|
||||
* and here we mimic direct connection from MB INTC to
|
||||
* CPU INTC, thus we set "interrupts = <0 1>" instead of
|
||||
* "interrupts = <12>"
|
||||
*
|
||||
* This intc actually resides on MB, but we move it here to
|
||||
* avoid duplicating the MB dtsi file given that IRQ from
|
||||
* this intc to cpu intc are different for axs101 and axs103
|
||||
*/
|
||||
mb_intc: dw-apb-ictl@0xe0012000 {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "snps,dw-apb-ictl";
|
||||
reg = < 0xe0012000 0x200 >;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&idu_intc>;
|
||||
interrupts = <0 1>; /* cmn irq 0 -> cpu irq 24
|
||||
distribute to cpu0 only */
|
||||
};
|
||||
|
||||
memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00000000 0x80000000 0x40000000>;
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x20000000>; /* 512MiB */
|
||||
};
|
||||
};
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Device Tree for AXS103 SDP with AXS10X Main Board and
|
||||
* AXC003 FPGA Card (with SMP bitfile)
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "axc003_idu.dtsi"
|
||||
/include/ "axs10x_mb.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Synopsys AXS103 Development Board";
|
||||
compatible = "snps,axs103", "snps,arc-sdp";
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=ttyS3,115200n8";
|
||||
};
|
||||
};
|
||||
|
|
@ -1,225 +0,0 @@
|
|||
/*
|
||||
* Support for peripherals on the AXS10x mainboard
|
||||
*
|
||||
* Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/ {
|
||||
axs10x_mb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00000000 0xe0000000 0x10000000>;
|
||||
interrupt-parent = <&mb_intc>;
|
||||
|
||||
clocks {
|
||||
i2cclk: i2cclk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <50000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
apbclk: apbclk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <50000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
mmcclk: mmcclk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <50000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@0x18000 {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "snps,dwmac";
|
||||
reg = < 0x18000 0x2000 >;
|
||||
interrupts = < 4 >;
|
||||
interrupt-names = "macirq";
|
||||
phy-mode = "rgmii";
|
||||
snps,pbl = < 32 >;
|
||||
clocks = <&apbclk>;
|
||||
clock-names = "stmmaceth";
|
||||
max-speed = <100>;
|
||||
};
|
||||
|
||||
ehci@0x40000 {
|
||||
compatible = "generic-ehci";
|
||||
reg = < 0x40000 0x100 >;
|
||||
interrupts = < 8 >;
|
||||
};
|
||||
|
||||
ohci@0x60000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = < 0x60000 0x100 >;
|
||||
interrupts = < 8 >;
|
||||
};
|
||||
|
||||
/*
|
||||
* According to DW Mobile Storage databook it is required
|
||||
* to use "Hold Register" if card is enumerated in SDR12 or
|
||||
* SDR25 modes.
|
||||
*
|
||||
* Utilization of "Hold Register" is already implemented via
|
||||
* dw_mci_pltfm_prepare_command() which in its turn gets
|
||||
* used through dw_mci_drv_data->prepare_command call-back.
|
||||
* This call-back is used in Altera Socfpga platform and so
|
||||
* we may reuse it saying that we're compatible with their
|
||||
* "altr,socfpga-dw-mshc".
|
||||
*
|
||||
* Most probably "Hold Register" utilization is platform-
|
||||
* independent requirement which means that single unified
|
||||
* "snps,dw-mshc" should be enough for all users of DW MMC once
|
||||
* dw_mci_pltfm_prepare_command() is used in generic platform
|
||||
* code.
|
||||
*/
|
||||
mmc@0x15000 {
|
||||
compatible = "altr,socfpga-dw-mshc";
|
||||
reg = < 0x15000 0x400 >;
|
||||
num-slots = < 1 >;
|
||||
fifo-depth = < 16 >;
|
||||
card-detect-delay = < 200 >;
|
||||
clocks = <&apbclk>, <&mmcclk>;
|
||||
clock-names = "biu", "ciu";
|
||||
interrupts = < 7 >;
|
||||
bus-width = < 4 >;
|
||||
};
|
||||
|
||||
uart@0x20000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x20000 0x100>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <17>;
|
||||
baud = <115200>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
uart@0x21000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x21000 0x100>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <18>;
|
||||
baud = <115200>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
/* UART muxed with USB data port (ttyS3) */
|
||||
uart@0x22000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x22000 0x100>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <19>;
|
||||
baud = <115200>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
i2c@0x1d000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x1d000 0x100>;
|
||||
clock-frequency = <400000>;
|
||||
clocks = <&i2cclk>;
|
||||
interrupts = <14>;
|
||||
};
|
||||
|
||||
i2c@0x1e000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x1e000 0x100>;
|
||||
clock-frequency = <400000>;
|
||||
clocks = <&i2cclk>;
|
||||
interrupts = <15>;
|
||||
};
|
||||
|
||||
i2c@0x1f000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x1f000 0x100>;
|
||||
clock-frequency = <400000>;
|
||||
clocks = <&i2cclk>;
|
||||
interrupts = <16>;
|
||||
|
||||
eeprom@0x54{
|
||||
compatible = "24c01";
|
||||
reg = <0x54>;
|
||||
pagesize = <0x8>;
|
||||
};
|
||||
|
||||
eeprom@0x57{
|
||||
compatible = "24c04";
|
||||
reg = <0x57>;
|
||||
pagesize = <0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio0:gpio@13000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x13000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gpio0_banka: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
gpio0_bankb: gpio-controller@1 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <8>;
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
gpio0_bankc: gpio-controller@2 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <8>;
|
||||
reg = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio1:gpio@14000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x14000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gpio1_banka: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <30>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
gpio1_bankb: gpio-controller@1 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <10>;
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
gpio1_bankc: gpio-controller@2 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <8>;
|
||||
reg = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,73 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Synopsys ARC HS38 nSIM simulator";
|
||||
compatible = "snps,nsim_hs";
|
||||
interrupt-parent = <&core_intc>;
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8";
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &arcuart0;
|
||||
};
|
||||
|
||||
fpga {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* child and parent address space 1:1 mapped */
|
||||
ranges;
|
||||
|
||||
core_intc: core-interrupt-controller {
|
||||
compatible = "snps,archs-intc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
idu_intc: idu-interrupt-controller {
|
||||
compatible = "snps,archs-idu-intc";
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&core_intc>;
|
||||
|
||||
/*
|
||||
* <hwirq distribution>
|
||||
* distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
|
||||
*/
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
/*
|
||||
* upstream irqs to core intc - downstream these are
|
||||
* "COMMON" irq 0,1..
|
||||
*/
|
||||
interrupts = <24 25 26 27 28 29 30 31>;
|
||||
};
|
||||
|
||||
arcuart0: serial@c0fc1000 {
|
||||
compatible = "snps,arc-uart";
|
||||
reg = <0xc0fc1000 0x100>;
|
||||
interrupt-parent = <&idu_intc>;
|
||||
interrupts = <0 0>;
|
||||
clock-frequency = <80000000>;
|
||||
current-speed = <115200>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
arcpct0: pct {
|
||||
compatible = "snps,archs-pct";
|
||||
#interrupt-cells = <1>;
|
||||
interrupts = <20>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,37 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Skeleton device tree; the bare minimum needed to boot; just include and
|
||||
* add a compatible value.
|
||||
*/
|
||||
|
||||
/ {
|
||||
compatible = "snps,arc";
|
||||
clock-frequency = <80000000>; /* 80 MHZ */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
chosen { };
|
||||
aliases { };
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "snps,arc770d";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>; /* 256M */
|
||||
};
|
||||
};
|
||||
|
|
@ -15,7 +15,7 @@ define Build/calculate-ep
|
|||
endef
|
||||
|
||||
define Build/patch-dtb
|
||||
$(call Image/BuildDTB,../dts/$(DEVICE_DTS).dts,$@.dtb)
|
||||
$(call Image/BuildDTB,$(DTS_DIR)/$(DEVICE_DTS).dts,$@.dtb)
|
||||
$(STAGING_DIR_HOST)/bin/patch-dtb $@ $@.dtb
|
||||
endef
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,192 @@
|
|||
From f1e53ac0a99e3754465bd87ae1a6fdbfb8340d15 Mon Sep 17 00:00:00 2001
|
||||
From: Alexey Brodkin <abrodkin@synopsys.com>
|
||||
Date: Mon, 15 Aug 2016 14:42:44 +0300
|
||||
Subject: [PATCH] arc: Add "model" properly in device tree description of all
|
||||
boards
|
||||
|
||||
As it was discussed quite some time ago (see
|
||||
https://lkml.org/lkml/2015/11/5/862) it's a good practice to add
|
||||
"model" property in .dts. Moreover as per ePAPR "model" property is
|
||||
required and should look like "manufacturer,model" so we do here.
|
||||
|
||||
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
|
||||
Cc: Vineet Gupta <vgupta@synopsys.com>
|
||||
Cc: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
Cc: Arnd Bergmann <arnd@arndb.de>
|
||||
Cc: Rob Herring <robh@kernel.org>
|
||||
Cc: Christian Ruppert <christian.ruppert@alitech.com>
|
||||
---
|
||||
arch/arc/boot/dts/abilis_tb100_dvk.dts | 1 +
|
||||
arch/arc/boot/dts/abilis_tb101_dvk.dts | 1 +
|
||||
arch/arc/boot/dts/axs101.dts | 1 +
|
||||
arch/arc/boot/dts/axs103.dts | 1 +
|
||||
arch/arc/boot/dts/axs103_idu.dts | 1 +
|
||||
arch/arc/boot/dts/nsim_700.dts | 1 +
|
||||
arch/arc/boot/dts/nsim_hs.dts | 1 +
|
||||
arch/arc/boot/dts/nsim_hs_idu.dts | 1 +
|
||||
arch/arc/boot/dts/nsimosci.dts | 1 +
|
||||
arch/arc/boot/dts/nsimosci_hs.dts | 1 +
|
||||
arch/arc/boot/dts/nsimosci_hs_idu.dts | 1 +
|
||||
arch/arc/boot/dts/vdk_hs38.dts | 1 +
|
||||
arch/arc/boot/dts/vdk_hs38_smp.dts | 1 +
|
||||
13 files changed, 13 insertions(+)
|
||||
|
||||
diff --git a/arch/arc/boot/dts/abilis_tb100_dvk.dts b/arch/arc/boot/dts/abilis_tb100_dvk.dts
|
||||
index 3dd6ed9..3acf04d 100644
|
||||
--- a/arch/arc/boot/dts/abilis_tb100_dvk.dts
|
||||
+++ b/arch/arc/boot/dts/abilis_tb100_dvk.dts
|
||||
@@ -24,6 +24,7 @@
|
||||
/include/ "abilis_tb100.dtsi"
|
||||
|
||||
/ {
|
||||
+ model = "abilis,tb100";
|
||||
chosen {
|
||||
bootargs = "earlycon=uart8250,mmio32,0xff100000,9600n8 console=ttyS0,9600n8";
|
||||
};
|
||||
diff --git a/arch/arc/boot/dts/abilis_tb101_dvk.dts b/arch/arc/boot/dts/abilis_tb101_dvk.dts
|
||||
index 1cf51c2..37d88c5 100644
|
||||
--- a/arch/arc/boot/dts/abilis_tb101_dvk.dts
|
||||
+++ b/arch/arc/boot/dts/abilis_tb101_dvk.dts
|
||||
@@ -24,6 +24,7 @@
|
||||
/include/ "abilis_tb101.dtsi"
|
||||
|
||||
/ {
|
||||
+ model = "abilis,tb101";
|
||||
chosen {
|
||||
bootargs = "earlycon=uart8250,mmio32,0xff100000,9600n8 console=ttyS0,9600n8";
|
||||
};
|
||||
diff --git a/arch/arc/boot/dts/axs101.dts b/arch/arc/boot/dts/axs101.dts
|
||||
index 3f9b058..d9b9b9d 100644
|
||||
--- a/arch/arc/boot/dts/axs101.dts
|
||||
+++ b/arch/arc/boot/dts/axs101.dts
|
||||
@@ -13,6 +13,7 @@
|
||||
/include/ "axs10x_mb.dtsi"
|
||||
|
||||
/ {
|
||||
+ model = "snps,axs101";
|
||||
compatible = "snps,axs101", "snps,arc-sdp";
|
||||
|
||||
chosen {
|
||||
diff --git a/arch/arc/boot/dts/axs103.dts b/arch/arc/boot/dts/axs103.dts
|
||||
index e6d0e31..ec7fb27 100644
|
||||
--- a/arch/arc/boot/dts/axs103.dts
|
||||
+++ b/arch/arc/boot/dts/axs103.dts
|
||||
@@ -16,6 +16,7 @@
|
||||
/include/ "axs10x_mb.dtsi"
|
||||
|
||||
/ {
|
||||
+ model = "snps,axs103";
|
||||
compatible = "snps,axs103", "snps,arc-sdp";
|
||||
|
||||
chosen {
|
||||
diff --git a/arch/arc/boot/dts/axs103_idu.dts b/arch/arc/boot/dts/axs103_idu.dts
|
||||
index f999fef..070c297 100644
|
||||
--- a/arch/arc/boot/dts/axs103_idu.dts
|
||||
+++ b/arch/arc/boot/dts/axs103_idu.dts
|
||||
@@ -16,6 +16,7 @@
|
||||
/include/ "axs10x_mb.dtsi"
|
||||
|
||||
/ {
|
||||
+ model = "snps,axs103-smp";
|
||||
compatible = "snps,axs103", "snps,arc-sdp";
|
||||
|
||||
chosen {
|
||||
diff --git a/arch/arc/boot/dts/nsim_700.dts b/arch/arc/boot/dts/nsim_700.dts
|
||||
index 105a001..97a9a91 100644
|
||||
--- a/arch/arc/boot/dts/nsim_700.dts
|
||||
+++ b/arch/arc/boot/dts/nsim_700.dts
|
||||
@@ -10,6 +10,7 @@
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
+ model = "snps,nsim";
|
||||
compatible = "snps,nsim";
|
||||
clock-frequency = <80000000>; /* 80 MHZ */
|
||||
#address-cells = <1>;
|
||||
diff --git a/arch/arc/boot/dts/nsim_hs.dts b/arch/arc/boot/dts/nsim_hs.dts
|
||||
index fc81879..1d47b14 100644
|
||||
--- a/arch/arc/boot/dts/nsim_hs.dts
|
||||
+++ b/arch/arc/boot/dts/nsim_hs.dts
|
||||
@@ -10,6 +10,7 @@
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
+ model = "snps,nsim_hs";
|
||||
compatible = "snps,nsim_hs";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
diff --git a/arch/arc/boot/dts/nsim_hs_idu.dts b/arch/arc/boot/dts/nsim_hs_idu.dts
|
||||
index 46ab319..b3a69a8 100644
|
||||
--- a/arch/arc/boot/dts/nsim_hs_idu.dts
|
||||
+++ b/arch/arc/boot/dts/nsim_hs_idu.dts
|
||||
@@ -10,6 +10,7 @@
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
+ model = "snps,nsim_hs-smp";
|
||||
compatible = "snps,nsim_hs";
|
||||
interrupt-parent = <&core_intc>;
|
||||
|
||||
diff --git a/arch/arc/boot/dts/nsimosci.dts b/arch/arc/boot/dts/nsimosci.dts
|
||||
index 1c169dc..80f3c33 100644
|
||||
--- a/arch/arc/boot/dts/nsimosci.dts
|
||||
+++ b/arch/arc/boot/dts/nsimosci.dts
|
||||
@@ -10,6 +10,7 @@
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
+ model = "snps,nsimosci";
|
||||
compatible = "snps,nsimosci";
|
||||
clock-frequency = <20000000>; /* 20 MHZ */
|
||||
#address-cells = <1>;
|
||||
diff --git a/arch/arc/boot/dts/nsimosci_hs.dts b/arch/arc/boot/dts/nsimosci_hs.dts
|
||||
index d64a96f..f680f1e 100644
|
||||
--- a/arch/arc/boot/dts/nsimosci_hs.dts
|
||||
+++ b/arch/arc/boot/dts/nsimosci_hs.dts
|
||||
@@ -10,6 +10,7 @@
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
+ model = "snps,nsimosci_hs";
|
||||
compatible = "snps,nsimosci_hs";
|
||||
clock-frequency = <20000000>; /* 20 MHZ */
|
||||
#address-cells = <1>;
|
||||
diff --git a/arch/arc/boot/dts/nsimosci_hs_idu.dts b/arch/arc/boot/dts/nsimosci_hs_idu.dts
|
||||
index f6bf0ca..6e46b11 100644
|
||||
--- a/arch/arc/boot/dts/nsimosci_hs_idu.dts
|
||||
+++ b/arch/arc/boot/dts/nsimosci_hs_idu.dts
|
||||
@@ -10,6 +10,7 @@
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
+ model = "snps,nsimosci_hs-smp";
|
||||
compatible = "snps,nsimosci_hs";
|
||||
clock-frequency = <5000000>; /* 5 MHZ */
|
||||
#address-cells = <1>;
|
||||
diff --git a/arch/arc/boot/dts/vdk_hs38.dts b/arch/arc/boot/dts/vdk_hs38.dts
|
||||
index 5d803dd..3c51103 100644
|
||||
--- a/arch/arc/boot/dts/vdk_hs38.dts
|
||||
+++ b/arch/arc/boot/dts/vdk_hs38.dts
|
||||
@@ -13,6 +13,7 @@
|
||||
/include/ "vdk_axs10x_mb.dtsi"
|
||||
|
||||
/ {
|
||||
+ model = "snps,vdk_archs";
|
||||
compatible = "snps,axs103";
|
||||
|
||||
chosen {
|
||||
diff --git a/arch/arc/boot/dts/vdk_hs38_smp.dts b/arch/arc/boot/dts/vdk_hs38_smp.dts
|
||||
index 031a5bc..0054684 100644
|
||||
--- a/arch/arc/boot/dts/vdk_hs38_smp.dts
|
||||
+++ b/arch/arc/boot/dts/vdk_hs38_smp.dts
|
||||
@@ -13,6 +13,7 @@
|
||||
/include/ "vdk_axs10x_mb.dtsi"
|
||||
|
||||
/ {
|
||||
+ model = "snps,vdk_archs-smp";
|
||||
compatible = "snps,axs103";
|
||||
|
||||
chosen {
|
||||
--
|
||||
2.7.4
|
||||
|
||||
Loading…
Reference in a new issue