atheros: simplify gpiolib realization
Each SoCs generation has own independent gpiolib realization, so we have no reason to keep these realizations in semiuniversal form. Following modifications are made: * Remove valid_mask field * Remove ar231x_gpio_chip structure * Rename AR2315_GPIO_CR to AR2315_GPIO_DIR * Fix count of AR5312 GPIOs * Simplify gpio_chip methods realization Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> SVN-Revision: 41696
This commit is contained in:
Felix Fietkau
parent
82e4cde1ce
commit
a145d0410b
1 changed files with 62 additions and 182 deletions
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@ -1050,12 +1050,12 @@
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+ */
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+#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
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+#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
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+#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098)
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+#define AR2315_GPIO_DIR (AR2315_DSLBASE + 0x0098)
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+#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
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+
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+#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
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+#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */
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+#define AR2315_GPIO_CR_I(x) (0) /* input */
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+#define AR2315_GPIO_DIR_M(x) (1 << (x)) /* mask for i/o */
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+#define AR2315_GPIO_DIR_O(x) (1 << (x)) /* output */
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+#define AR2315_GPIO_DIR_I(x) (0) /* input */
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+
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+#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
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+#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
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@ -1583,7 +1583,7 @@
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+
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--- /dev/null
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+++ b/arch/mips/ar231x/ar5312.c
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@@ -0,0 +1,596 @@
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@@ -0,0 +1,540 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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@ -1730,100 +1730,46 @@
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+ irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
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+}
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+
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+static u32
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+ar5312_gpio_set_output(u32 mask, u32 val)
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+{
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+ u32 reg;
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+
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+ reg = ar231x_read_reg(AR531X_GPIO_CR);
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+ reg |= mask;
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+ reg &= ~val;
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+ ar231x_write_reg(AR531X_GPIO_CR, reg);
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+ return reg;
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+}
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+
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+static u32
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+ar5312_gpio_get(u32 valid_mask)
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+{
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+ u32 reg;
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+ reg = ar231x_read_reg(AR531X_GPIO_DI);
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+ reg &= valid_mask;
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+ return reg;
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+}
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+
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+static u32
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+ar5312_gpio_set(u32 mask, u32 value)
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+{
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+ u32 reg;
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+ reg = ar231x_read_reg(AR531X_GPIO_DO);
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+ reg &= ~mask;
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+ reg |= value;
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+ ar231x_write_reg(AR531X_GPIO_DO, reg);
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+ return reg;
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+}
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+
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+/*
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+ * gpiolib implementations. Original mask based methods preserved
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+ * gpiolib implementations
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+ */
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+static int
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+ar5312_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
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+{
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+ struct ar231x_gpio_chip *gpch =
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+ container_of(chip, struct ar231x_gpio_chip, chip);
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+ u32 mask = 1 << gpio;
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+ u32 rett;
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+ if (!(gpch->valid_mask & mask))
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+ return 0;
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+ rett = ar5312_gpio_get(gpch->valid_mask);
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+ return !!(rett & mask);
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+ return (ar231x_read_reg(AR531X_GPIO_DI) >> gpio) & 1;
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+}
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+
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+static void
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+ar5312_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
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+{
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+ struct ar231x_gpio_chip *gpch =
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+ container_of(chip, struct ar231x_gpio_chip, chip);
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+ u32 mask = 1 << gpio;
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+ if (!(gpch->valid_mask & mask))
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+ return;
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+ ar5312_gpio_set(mask, (!!value) * mask);
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+ u32 reg = ar231x_read_reg(AR531X_GPIO_DO);
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+ reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
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+ ar231x_write_reg(AR531X_GPIO_DO, reg);
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+}
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+
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+static int
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+ar5312_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
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+{
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+ struct ar231x_gpio_chip *gpch =
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+ container_of(chip, struct ar231x_gpio_chip, chip);
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+ u32 mask = 1 << gpio;
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+ if (!(gpch->valid_mask & mask))
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+ return -ENXIO;
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+ ar5312_gpio_set_output(mask, 0);
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+ return 0;
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+}
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+static int
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+ar5312_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
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+{
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+ struct ar231x_gpio_chip *gpch =
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+ container_of(chip, struct ar231x_gpio_chip, chip);
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+ u32 mask = 1 << gpio;
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+ if (!(gpch->valid_mask & mask))
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+ return -ENXIO;
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+ ar5312_gpio_set_output(mask, mask);
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+ ar5312_gpio_set(mask, (!!value) * mask);
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+ ar231x_mask_reg(AR531X_GPIO_CR, 0, 1 << gpio);
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+ return 0;
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+}
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+
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+static struct ar231x_gpio_chip ar5312_gpio_chip = {
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+ .valid_mask = (1 << 22) - 1,
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+ .chip = {
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+static int
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+ar5312_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
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+{
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+ ar231x_mask_reg(AR531X_GPIO_CR, 1 << gpio, 0);
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+ ar5312_gpio_set_value(chip, gpio, value);
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+ return 0;
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+}
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+
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+static struct gpio_chip ar5312_gpio_chip = {
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+ .label = "ar5312-gpio",
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+ .direction_input = ar5312_gpio_direction_input,
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+ .direction_output = ar5312_gpio_direction_output,
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+ .set = ar5312_gpio_set_value,
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+ .get = ar5312_gpio_get_value,
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+ .base = 0,
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+ .ngpio = AR531X_GPIO_IRQ_COUNT, /* 22 */
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+ }
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+ .ngpio = AR531X_NUM_GPIO, /* 8 */
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+};
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+
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+/* end of gpiolib */
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@ -2123,19 +2069,17 @@
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+ mips_hpt_frequency = ar5312_cpu_frequency() / 2;
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+}
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+
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+int __init
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+static int __init
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+ar5312_gpio_init(void)
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+{
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+ int ret;
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+ struct ar231x_gpio_chip *gpch;
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+ gpch = &ar5312_gpio_chip;
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+ ret = gpiochip_add(&gpch->chip);
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+ ret = gpiochip_add(&ar5312_gpio_chip);
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+ if (ret) {
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+ pr_err("%s: failed to add gpiochip\n", gpch->chip.label);
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+ pr_err("%s: failed to add gpiochip\n", ar5312_gpio_chip.label);
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+ return ret;
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+ }
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+ pr_info("%s: registered %d GPIOs\n", gpch->chip.label,
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+ gpch->chip.ngpio);
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+ pr_info("%s: registered %d GPIOs\n", ar5312_gpio_chip.label,
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+ ar5312_gpio_chip.ngpio);
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+ return ret;
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+}
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+
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@ -2182,7 +2126,7 @@
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+
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--- /dev/null
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+++ b/arch/mips/ar231x/ar2315.c
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@@ -0,0 +1,615 @@
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@@ -0,0 +1,557 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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@ -2242,8 +2186,8 @@
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+ ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
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+
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+ /* Enable interrupt with edge detection */
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+ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) !=
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+ AR2315_GPIO_CR_I(bit))
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+ if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(bit)) !=
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+ AR2315_GPIO_DIR_I(bit))
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+ return;
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+
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+ if (bit >= 0)
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@ -2310,8 +2254,8 @@
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+ unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE;
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+
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+ /* Enable interrupt with edge detection */
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+ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) !=
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+ AR2315_GPIO_CR_I(gpio))
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+ if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(gpio)) !=
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+ AR2315_GPIO_DIR_I(gpio))
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+ return;
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+
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+ gpiointmask |= (1 << gpio);
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@ -2390,7 +2334,7 @@
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+ irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
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+ handle_level_irq);
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+ }
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+ for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) {
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+ for (i = 0; i < AR2315_NUM_GPIO; i++) {
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+ int irq = AR531X_GPIO_IRQ_BASE + i;
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+ irq_set_chip_and_handler(irq, &ar2315_gpio_irq_chip,
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+ handle_level_irq);
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@ -2400,102 +2344,46 @@
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+ irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
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+}
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+
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+static u32
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+ar2315_gpio_set_output(u32 mask, u32 val)
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+{
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+ u32 reg;
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+
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+ reg = ar231x_read_reg(AR2315_GPIO_CR);
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+ reg &= ~mask;
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+ reg |= val;
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+ ar231x_write_reg(AR2315_GPIO_CR, reg);
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+ return reg;
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+}
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+
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+static u32
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+ar2315_gpio_get(u32 valid_mask)
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+{
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+ u32 reg;
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+ reg = ar231x_read_reg(AR2315_GPIO_DI);
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+ reg &= valid_mask;
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+ return reg;
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+}
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+
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+static u32
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+ar2315_gpio_set(u32 mask, u32 value)
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+{
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+ u32 reg;
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+ reg = ar231x_read_reg(AR2315_GPIO_DO);
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+ reg &= ~mask;
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+ reg |= value;
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+ ar231x_write_reg(AR2315_GPIO_DO, reg);
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+ return reg;
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+}
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+
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+/*
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+ * gpiolib implementation. Original legacy mask based methods
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+ * preserved for now.
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+ * gpiolib implementation
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+ */
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+static int
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+ar2315_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
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+{
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+ struct ar231x_gpio_chip *gpch =
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+ container_of(chip, struct ar231x_gpio_chip, chip);
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+ u32 mask = 1 << gpio;
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+ u32 rett;
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+ if (!(gpch->valid_mask & mask))
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+ return 0;
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+ rett = ar2315_gpio_get(gpch->valid_mask); /* legacy code */
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+ return !!(rett & mask);
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+ return (ar231x_read_reg(AR2315_GPIO_DI) >> gpio) & 1;
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+}
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+
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+static void
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+ar2315_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
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+{
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+ struct ar231x_gpio_chip *gpch =
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+ container_of(chip, struct ar231x_gpio_chip, chip);
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+ u32 mask = 1 << gpio;
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+ if (!(gpch->valid_mask & mask))
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+ return;
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+ ar2315_gpio_set(mask, (!!value) * mask); /* legacy */
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+ u32 reg = ar231x_read_reg(AR2315_GPIO_DO);
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+ reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
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+ ar231x_write_reg(AR2315_GPIO_DO, reg);
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+}
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+
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+static int
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+ar2315_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
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+{
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+ struct ar231x_gpio_chip *gpch =
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+ container_of(chip, struct ar231x_gpio_chip, chip);
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+ u32 mask = 1 << gpio;
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+ if (!(gpch->valid_mask & mask))
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+ return -ENXIO;
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+ ar2315_gpio_set_output(mask, 0); /* legacy */
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+ ar231x_mask_reg(AR2315_GPIO_DIR, 1 << gpio, 0);
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+ return 0;
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+}
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+
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+static int
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+ar2315_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
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+{
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+ struct ar231x_gpio_chip *gpch =
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+ container_of(chip, struct ar231x_gpio_chip, chip);
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+ u32 mask = 1 << gpio;
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+ if (!(gpch->valid_mask & mask))
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+ return -ENXIO;
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+ ar2315_gpio_set_output(mask, mask); /* both legacy */
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+ ar2315_gpio_set(mask, (!!value) * mask);
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+ ar231x_mask_reg(AR2315_GPIO_DIR, 0, 1 << gpio);
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+ ar2315_gpio_set_value(chip, gpio, value);
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+ return 0;
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+}
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+
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+static struct ar231x_gpio_chip ar2315_gpio_chip = {
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+ .valid_mask = (1 << 22) - 1,
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+ .chip = {
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+static struct gpio_chip ar2315_gpio_chip = {
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+ .label = "ar2315-gpio",
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+ .direction_input = ar2315_gpio_direction_input,
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+ .direction_output = ar2315_gpio_direction_output,
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+ .set = ar2315_gpio_set_value,
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+ .get = ar2315_gpio_get_value,
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+ .base = 0,
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+ .ngpio = AR531X_GPIO_IRQ_COUNT, /* 22 */
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+ }
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+ .ngpio = AR2315_NUM_GPIO, /* 22 */
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+};
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+
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+/* end of gpiolib */
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@ -2731,19 +2619,17 @@
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+ mips_hpt_frequency = ar2315_cpu_frequency() / 2;
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+}
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+
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+int __init
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+static int __init
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+ar2315_gpio_init(void)
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+{
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+ int ret;
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+ struct ar231x_gpio_chip *gpch;
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+ gpch = &ar2315_gpio_chip;
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+ ret = gpiochip_add(&gpch->chip);
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+ ret = gpiochip_add(&ar2315_gpio_chip);
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+ if (ret) {
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+ pr_err("%s: failed to add gpiochip\n", gpch->chip.label);
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+ pr_err("%s: failed to add gpiochip\n", ar2315_gpio_chip.label);
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+ return ret;
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+ }
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+ pr_info("%s: registered %d GPIOs\n", gpch->chip.label,
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+ gpch->chip.ngpio);
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+ pr_info("%s: registered %d GPIOs\n", ar2315_gpio_chip.label,
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+ ar2315_gpio_chip.ngpio);
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+ return ret;
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+}
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+
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@ -2881,7 +2767,7 @@
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+#endif
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
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@@ -0,0 +1,44 @@
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@@ -0,0 +1,43 @@
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+#ifndef __AR531X_H
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+#define __AR531X_H
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+
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@ -2895,10 +2781,9 @@
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+#define AR531X_IRQ_NONE (MIPS_CPU_IRQ_BASE+0)
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+#define AR531X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
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+
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+/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
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+/* GPIO Interrupts, share ARXXXX_MISC_IRQ_GPIO */
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+#define AR531X_GPIO_IRQ_NONE (AR531X_GPIO_IRQ_BASE+0)
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+#define AR531X_GPIO_IRQ(n) (AR531X_GPIO_IRQ_BASE+n)
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+#define AR531X_GPIO_IRQ_COUNT 22
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+
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+static inline u32
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+ar231x_read_reg(u32 reg)
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@ -2928,10 +2813,9 @@
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+#endif
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--- /dev/null
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+++ b/arch/mips/ar231x/devices.h
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@@ -0,0 +1,42 @@
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@@ -0,0 +1,37 @@
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+#ifndef __AR231X_DEVICES_H
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+#define __AR231X_DEVICES_H
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+#include <linux/gpio.h>
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+
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+enum {
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+ /* handled by ar5312.c */
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@ -2966,10 +2850,6 @@
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+ return !is_2315();
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+}
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+
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+struct ar231x_gpio_chip {
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+ u32 valid_mask;
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+ struct gpio_chip chip;
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+};
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+#endif
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--- /dev/null
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+++ b/arch/mips/ar231x/devices.c
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