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rename DDR registers

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SVN-Revision: 13363
This commit is contained in:
Gabor Juhos 2008-11-26 17:17:13 +00:00
parent 4fc7535fc7
commit 9f93bd51cf
3 changed files with 22 additions and 22 deletions
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4
target/linux/ar71xx/files/arch/mips/ar71xx/platform.c
View file

@ -198,7 +198,7 @@ static struct resource ar71xx_eth0_resources[] = {
struct ag71xx_platform_data ar71xx_eth0_data = { struct ag71xx_platform_data ar71xx_eth0_data = {
.reset_bit = RESET_MODULE_GE0_MAC, .reset_bit = RESET_MODULE_GE0_MAC,
.flush_reg = DDR_REG_FLUSH_GE0, .flush_reg = AR71XX_DDR_REG_FLUSH_GE0,
}; };
static struct platform_device ar71xx_eth0_device = { static struct platform_device ar71xx_eth0_device = {
@ -237,7 +237,7 @@ static struct resource ar71xx_eth1_resources[] = {
struct ag71xx_platform_data ar71xx_eth1_data = { struct ag71xx_platform_data ar71xx_eth1_data = {
.reset_bit = RESET_MODULE_GE1_MAC, .reset_bit = RESET_MODULE_GE1_MAC,
.flush_reg = DDR_REG_FLUSH_GE1, .flush_reg = AR71XX_DDR_REG_FLUSH_GE1,
}; };
static struct platform_device ar71xx_eth1_device = { static struct platform_device ar71xx_eth1_device = {

16
target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
View file

@ -316,14 +316,14 @@ static int __init __ar71xx_pci_bios_init(unsigned nr_irqs,
ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE, ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE,
AR71XX_PCI_CFG_SIZE); AR71XX_PCI_CFG_SIZE);
ar71xx_ddr_wr(DDR_REG_PCI_WIN0, PCI_WIN0_OFFS); ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN0, PCI_WIN0_OFFS);
ar71xx_ddr_wr(DDR_REG_PCI_WIN1, PCI_WIN1_OFFS); ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN1, PCI_WIN1_OFFS);
ar71xx_ddr_wr(DDR_REG_PCI_WIN2, PCI_WIN2_OFFS); ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN2, PCI_WIN2_OFFS);
ar71xx_ddr_wr(DDR_REG_PCI_WIN3, PCI_WIN3_OFFS); ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN3, PCI_WIN3_OFFS);
ar71xx_ddr_wr(DDR_REG_PCI_WIN4, PCI_WIN4_OFFS); ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN4, PCI_WIN4_OFFS);
ar71xx_ddr_wr(DDR_REG_PCI_WIN5, PCI_WIN5_OFFS); ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN5, PCI_WIN5_OFFS);
ar71xx_ddr_wr(DDR_REG_PCI_WIN6, PCI_WIN6_OFFS); ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN6, PCI_WIN6_OFFS);
ar71xx_ddr_wr(DDR_REG_PCI_WIN7, PCI_WIN7_OFFS); ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN7, PCI_WIN7_OFFS);
ar71xx_pci_delay(); ar71xx_pci_delay();

24
target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
View file

@ -207,18 +207,18 @@ extern void ar71xx_gpio_function_disable(u32 mask);
/* /*
* DDR_CTRL block * DDR_CTRL block
*/ */
#define DDR_REG_PCI_WIN0 0x7c #define AR71XX_DDR_REG_PCI_WIN0 0x7c
#define DDR_REG_PCI_WIN1 0x80 #define AR71XX_DDR_REG_PCI_WIN1 0x80
#define DDR_REG_PCI_WIN2 0x84 #define AR71XX_DDR_REG_PCI_WIN2 0x84
#define DDR_REG_PCI_WIN3 0x88 #define AR71XX_DDR_REG_PCI_WIN3 0x88
#define DDR_REG_PCI_WIN4 0x8c #define AR71XX_DDR_REG_PCI_WIN4 0x8c
#define DDR_REG_PCI_WIN5 0x90 #define AR71XX_DDR_REG_PCI_WIN5 0x90
#define DDR_REG_PCI_WIN6 0x94 #define AR71XX_DDR_REG_PCI_WIN6 0x94
#define DDR_REG_PCI_WIN7 0x98 #define AR71XX_DDR_REG_PCI_WIN7 0x98
#define DDR_REG_FLUSH_GE0 0x9c #define AR71XX_DDR_REG_FLUSH_GE0 0x9c
#define DDR_REG_FLUSH_GE1 0xa0 #define AR71XX_DDR_REG_FLUSH_GE1 0xa0
#define DDR_REG_FLUSH_USB 0xa4 #define AR71XX_DDR_REG_FLUSH_USB 0xa4
#define DDR_REG_FLUSH_PCI 0xa8 #define AR71XX_DDR_REG_FLUSH_PCI 0xa8
#define PCI_WIN0_OFFS 0x10000000 #define PCI_WIN0_OFFS 0x10000000
#define PCI_WIN1_OFFS 0x11000000 #define PCI_WIN1_OFFS 0x11000000