adds new lantiq kernel. once the codebase is fully tested and know to be working on all the devices previously supported by ifxmips, we will drop ifxmips support.

SVN-Revision: 24526
This commit is contained in:
John Crispin 2010-12-12 22:57:16 +00:00
parent f590b304ef
commit 9f47e80bb3
52 changed files with 40307 additions and 0 deletions

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#
# Copyright (C) 2009-2010 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
# ralph / blogic
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_BASE_NAME:=dsl_cpe_control_danube
PKG_VERSION:=3.24.4.4
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_BASE_NAME)-$(PKG_VERSION).tar.gz
PKG_BUILD_DIR:=$(BUILD_DIR)/dsl_cpe_control-$(PKG_VERSION)
PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources/
PKG_MD5SUM:=ee315306626b68794d3d3636dabfe161
include $(INCLUDE_DIR)/package.mk
define Package/lqdsl-app
SECTION:=net
CATEGORY:=Network
TITLE:=Lantiq DSL userland tool
URL:=http://www.lantiq.com/
MAINTAINER:=Lantiq
DEPENDS:=@TARGET_lantiq_xway +kmod-lqdsl +libpthread
endef
define Package/lqdsl-app/description
Infineon DSL CPE API for Amazon SE, Danube and Vinax.
endef
IFX_DSL_MAX_DEVICE=1
IFX_DSL_LINES_PER_DEVICE=1
IFX_DSL_CHANNELS_PER_LINE=1
#CONFIG_IFX_CLI=y
CONFIGURE_ARGS += \
--with-max-device="$(IFX_DSL_MAX_DEVICE)" \
--with-lines-per-device="$(IFX_DSL_LINES_PER_DEVICE)" \
--with-channels-per-line="$(IFX_DSL_CHANNELS_PER_LINE)" \
--enable-danube \
--enable-driver-include="-I$(STAGING_DIR)/usr/include" \
--enable-debug-prints \
--enable-add-appl-cflags="-DMAX_CLI_PIPES=2" \
--enable-cmv-scripts \
--enable-debug-tool-interface \
--enable-adsl-led \
--enable-dsl-ceoc \
--enable-script-notification \
--enable-dsl-pm \
--enable-dsl-pm-total \
--enable-dsl-pm-history \
--enable-dsl-pm-showtime \
--enable-dsl-pm-channel-counters \
--enable-dsl-pm-datapath-counters \
--enable-dsl-pm-line-counters \
--enable-dsl-pm-channel-thresholds \
--enable-dsl-pm-datapath-thresholds \
--enable-dsl-pm-line-thresholds \
--enable-dsl-pm-optional-parameters
ifeq ($(CONFIG_IFX_CLI),y)
CONFIGURE_ARGS += \
--enable-cli-support \
--enable-soap-support
endif
TARGET_CFLAGS += -I$(LINUX_DIR)/include
define Package/lqdsl-app/install
$(INSTALL_DIR) $(1)/etc/init.d
$(INSTALL_BIN) ./files/ifx_cpe_control_init.sh $(1)/etc/init.d/
$(INSTALL_DIR) $(1)/sbin
$(INSTALL_BIN) $(PKG_BUILD_DIR)/src/dsl_cpe_control $(1)/sbin
endef
$(eval $(call BuildPackage,lqdsl-app))

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#!/bin/sh /etc/rc.common
# Copyright (C) 2008 OpenWrt.org
START=99
start() {
# start CPE dsl daemon in the background
/sbin/dsl_cpe_control -i -f /lib/firmware/ModemHWE.bin &
# PS=`ps`
# echo $PS | grep -q dsl_cpe_control && {
# # workaround for nfs: allow write to pipes for non-root
# while [ ! -e /tmp/pipe/dsl_cpe1_ack ] ; do sleep 1; done
# chmod a+w /tmp/pipe/dsl_*
# }
echo $PS | grep -q dsl_cpe_control || {
echo "Start of dsl_cpe_control failed!!!"
false
}
}

25
package/lqdsl/Config.in Normal file
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@ -0,0 +1,25 @@
choice
prompt "Firmware"
default LANTIQ_ANNEX_B
depends on PACKAGE_kmod-lqdsl
help
This option controls which firmware is loaded
config LANTIQ_ANNEX_A
bool "Annex-A"
help
Annex-A
config LANTIQ_ANNEX_B
bool "Annex-B"
help
Annex-B
endchoice
config LANTIQ_DSL_DEBUG
bool "lqdsl debugging"
depends on PACKAGE_kmod-lqdsl
help
Say Y, if you need lantiq-dsl to display debug messages.

158
package/lqdsl/Makefile Normal file
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@ -0,0 +1,158 @@
#
# Copyright (C) 2009-2010 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
# ralph / blogic
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=lqdsl
PKG_BASE_NAME:=drv_dsl_cpe_api_danube
PKG_VERSION:=3.24.4.4
PKG_RELEASE:=2
PKG_SOURCE:=$(PKG_BASE_NAME)-$(PKG_VERSION).tar.gz
PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/drv_dsl_cpe_api-$(PKG_VERSION)
PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources/
PKG_MD5SUM:=c45bc531c1ed2ac80f68fb986b63bb87
ifeq ($(DUMP),)
STAMP_CONFIGURED:=$(strip $(STAMP_CONFIGURED))_$(shell grep '^CONFIG_LANTIQ_DSL_' $(TOPDIR)/.config | md5s)
endif
FW_BASE_NAME:=dsl_danube_firmware_adsl
FW_A_VER:=02.04.04.00.00.01
FW_B_VER:=02.04.01.07.00.02
FW_A_FILE_VER:=244001
FW_B_FILE_VER:=241702
FW_A_MD5:=f717db3067a0049a26e233ab11238710
FW_B_MD5:=349de7cd20368f4ac9b7e8322114a512
PATCH_DIR ?= ./patches$(if $(wildcard ./patches-$(KERNEL_PATCHVER)),-$(KERNEL_PATCHVER))
include $(INCLUDE_DIR)/package.mk
define KernelPackage/lqdsl
SECTION:=sys
CATEGORY:=Kernel modules
SUBMENU:=Network Devices
TITLE:=Lantiq dsl driver
URL:=http://www.lantiq.com/
MAINTAINER:=Lantiq
DEPENDS:=@TARGET_lantiq_xway +kmod-atm
FILES:=$(PKG_BUILD_DIR)/src/mei/lantiq_mei.ko \
$(PKG_BUILD_DIR)/src/drv_dsl_cpe_api.ko \
$(PKG_BUILD_DIR)/src/mei/lantiq_atm.ko
AUTOLOAD:=$(call AutoLoad,50,lantiq_mei drv_dsl_cpe_api lantiq_atm)
endef
define KernelPackage/lqdsl/description
Infineon DSL CPE API for Amazon SE, Danube and Vinax.
This package contains the DSL CPE API driver for Amazon SE & Danube.
Supported Devices:
- Amazon SE
- Danube
endef
define KernelPackage/lqdsl/config
source "$(SOURCE)/Config.in"
endef
define Download/annex-a
FILE:=$(FW_BASE_NAME)_a-$(FW_A_VER).tar.gz
URL:=http://mirror2.openwrt.org/sources/
MD5SUM:=$(FW_A_MD5)
endef
$(eval $(call Download,annex-a))
define Download/annex-b
FILE:=$(FW_BASE_NAME)_b-$(FW_B_VER).tar.gz
URL:=http://mirror2.openwrt.org/sources/
MD5SUM:=$(FW_B_MD5)
endef
$(eval $(call Download,annex-b))
IFX_DSL_MAX_DEVICE=1
IFX_DSL_LINES_PER_DEVICE=1
IFX_DSL_CHANNELS_PER_LINE=1
CONFIGURE_ARGS += --enable-kernel-include="$(LINUX_DIR)/include" \
--with-max-device="$(IFX_DSL_MAX_DEVICE)" \
--with-lines-per-device="$(IFX_DSL_LINES_PER_DEVICE)" \
--with-channels-per-line="$(IFX_DSL_CHANNELS_PER_LINE)" \
--enable-danube \
--enable-add-drv-cflags="-DMODULE" \
--disable-dsl-delt-static \
--disable-adsl-led \
--enable-dsl-ceoc \
--enable-dsl-pm \
--enable-dsl-pm-total \
--enable-dsl-pm-history \
--enable-dsl-pm-showtime \
--enable-dsl-pm-channel-counters \
--enable-dsl-pm-datapath-counters \
--enable-dsl-pm-line-counters \
--enable-dsl-pm-channel-thresholds \
--enable-dsl-pm-datapath-thresholds \
--enable-dsl-pm-line-thresholds \
--enable-dsl-pm-optional-parameters \
--enable-linux-26 \
--enable-kernelbuild="$(LINUX_DIR)" \
ARCH=$(LINUX_KARCH)
EXTRA_CFLAGS = -fno-pic -mno-abicalls -mlong-calls -G 0
ifeq ($(CONFIG_LANTIQ_DSL_DEBUG),y)
CONFIGURE_ARGS += \
--enable-debug=yes \
--enable-debug-prints=yes
EXTRA_CFLAGS += -DDEBUG
endif
define Build/Prepare
$(PKG_UNPACK)
$(INSTALL_DIR) $(PKG_BUILD_DIR)/src/mei/
$(CP) ./src/* $(PKG_BUILD_DIR)/src/mei/
$(Build/Patch)
ifeq ($(CONFIG_LANTIQ_DSL_FIRMWARE),)
$(TAR) -C $(PKG_BUILD_DIR) -xzf $(DL_DIR)/$(FW_BASE_NAME)_a-$(FW_A_VER).tar.gz
$(TAR) -C $(PKG_BUILD_DIR) -xzf $(DL_DIR)/$(FW_BASE_NAME)_b-$(FW_B_VER).tar.gz
endif
endef
define Build/Configure
(cd $(PKG_BUILD_DIR); aclocal && autoconf && automake)
$(call Build/Configure/Default)
endef
define Build/Compile
cd $(LINUX_DIR); \
ARCH=mips CROSS_COMPILE="$(KERNEL_CROSS)" \
$(MAKE) M=$(PKG_BUILD_DIR)/src/mei/ V=1 modules
$(call Build/Compile/Default)
endef
define Build/InstallDev
$(INSTALL_DIR) $(1)/usr/include
$(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api.h $(1)/usr/include
$(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_ioctl.h $(1)/usr/include
$(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_adslmib.h $(1)/usr/include
$(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_adslmib_ioctl.h $(1)/usr/include
$(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_g997.h $(1)/usr/include
$(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_types.h $(1)/usr/include
$(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_pm.h $(1)/usr/include
$(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_error.h $(1)/usr/include
$(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_danube_ctx.h $(1)/usr/include
$(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_cmv_danube.h $(1)/usr/include
endef
define KernelPackage/lqdsl/install
$(INSTALL_DIR) $(1)/lib/firmware/
$(CP) $(PKG_BUILD_DIR)/$(FW_BASE_NAME)_$(if $(CONFIG_LANTIQ_ANNEX_A),a_$(FW_A_FILE_VER),b_$(FW_B_FILE_VER)).bin $(1)/lib/firmware/ModemHWE.bin
endef
$(eval $(call KernelPackage,lqdsl))

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@ -0,0 +1,62 @@
--- a/src/include/drv_dsl_cpe_device_danube.h
+++ b/src/include/drv_dsl_cpe_device_danube.h
@@ -24,7 +24,7 @@
#include "drv_dsl_cpe_simulator_danube.h"
#else
/* Include for the low level driver interface header file */
-#include "asm/ifx/ifx_mei_bsp.h"
+#include "mei/ifxmips_mei_interface.h"
#endif /* defined(DSL_CPE_SIMULATOR_DRIVER) && defined(WIN32)*/
#define DSL_MAX_LINE_NUMBER 1
--- a/src/common/drv_dsl_cpe_os_linux.c
+++ b/src/common/drv_dsl_cpe_os_linux.c
@@ -11,6 +11,7 @@
#ifdef __LINUX__
#define DSL_INTERN
+#include <linux/device.h>
#include "drv_dsl_cpe_api.h"
#include "drv_dsl_cpe_api_ioctl.h"
@@ -1058,6 +1059,7 @@ static void DSL_DRV_DebugInit(void)
/* Entry point of driver */
int __init DSL_ModuleInit(void)
{
+ struct class *dsl_class;
DSL_int_t i;
printk(DSL_DRV_CRLF DSL_DRV_CRLF "Infineon CPE API Driver version: %s" DSL_DRV_CRLF,
@@ -1104,7 +1106,8 @@ int __init DSL_ModuleInit(void)
}
DSL_DRV_DevNodeInit();
-
+ dsl_class = class_create(THIS_MODULE, "dsl_cpe_api");
+ device_create(dsl_class, NULL, MKDEV(DRV_DSL_CPE_API_DEV_MAJOR, 0), NULL, "dsl_cpe_api");
return 0;
}
--- a/src/include/drv_dsl_cpe_os_linux.h
+++ b/src/include/drv_dsl_cpe_os_linux.h
@@ -17,17 +17,17 @@
#endif
#include <asm/ioctl.h>
-#include <linux/autoconf.h>
+#include <generated/autoconf.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/ctype.h>
#include <linux/version.h>
#include <linux/spinlock.h>
-
+#include <linux/sched.h>
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
- #include <linux/utsrelease.h>
+ #include <generated/utsrelease.h>
#endif
#include <linux/types.h>

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@ -0,0 +1,218 @@
Index: drv_dsl_cpe_api-3.24.4.4/configure.in
===================================================================
--- drv_dsl_cpe_api-3.24.4.4.orig/configure.in 2009-08-13 13:39:21.000000000 +0200
+++ drv_dsl_cpe_api-3.24.4.4/configure.in 2010-10-14 02:14:55.000000000 +0200
@@ -310,7 +310,7 @@
AC_ARG_ENABLE(kernelbuild,
AC_HELP_STRING(--enable-kernel-build=x,Set the target kernel build path),
[
- if test -e $enableval/include/linux/autoconf.h; then
+ if test -e $enableval/include/linux/autoconf.h -o -e $enableval/include/generated/autoconf.h; then
AC_SUBST([KERNEL_BUILD_PATH],[$enableval])
else
AC_MSG_ERROR([The kernel build directory is not valid or not configured!])
@@ -333,12 +333,12 @@
echo Set the lib_ifxos include path $enableval
AC_SUBST([IFXOS_INCLUDE_PATH],[$enableval])
else
- echo -e Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
+ echo Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
AC_SUBST([IFXOS_INCLUDE_PATH],[$DEFAULT_IFXOS_INCLUDE_PATH])
fi
],
[
- echo -e Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
+ echo Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
AC_SUBST([IFXOS_INCLUDE_PATH],[$DEFAULT_IFXOS_INCLUDE_PATH])
]
)
@@ -1702,73 +1702,73 @@
AC_SUBST([DISTCHECK_CONFIGURE_PARAMS],[$CONFIGURE_OPTIONS])
AC_CONFIG_COMMANDS_PRE([
-echo -e "------------------------------------------------------------------------"
-echo -e " Configuration for drv_dsl_cpe_api:"
-echo -e " Configure model type: $DSL_CONFIG_MODEL_TYPE"
-echo -e " Source code location: $srcdir"
-echo -e " Compiler: $CC"
-echo -e " Compiler c-flags: $CFLAGS"
-echo -e " Extra compiler c-flags: $EXTRA_DRV_CFLAGS"
-echo -e " Host System Type: $host"
-echo -e " Install path: $prefix"
-echo -e " Linux kernel include path: $KERNEL_INCL_PATH"
-echo -e " Linux kernel build path: $KERNEL_BUILD_PATH"
-echo -e " Linux kernel architecture: $KERNEL_ARCH"
-echo -e " Include IFXOS: $INCLUDE_DSL_CPE_API_IFXOS_SUPPORT"
-echo -e " IFXOS include path: $IFXOS_INCLUDE_PATH"
-echo -e " Driver Include Path $DSL_DRIVER_INCL_PATH"
-echo -e " DSL device: $DSL_DEVICE_NAME"
-echo -e " Max device number: $DSL_DRV_MAX_DEVICE_NUMBER"
-echo -e " Channels per line: $DSL_CHANNELS_PER_LINE"
-echo -e " Build lib (only for kernel 2.6) $DSL_CPE_API_LIBRARY_BUILD_2_6"
-echo -e " DSL data led flash frequency: $DSL_DATA_LED_FLASH_FREQUENCY Hz"
-echo -e " Disable debug prints: $DSL_DEBUG_DISABLE"
-echo -e " Preselection of max. debug level: $DSL_DBG_MAX_LEVEL_SET"
-echo -e " Preselected max. debug level: $DSL_DBG_MAX_LEVEL_PRE"
-echo -e " Include deprecated functions: $INCLUDE_DEPRECATED"
-echo -e " Include Device Exception Codes: $INCLUDE_DEVICE_EXCEPTION_CODES"
-echo -e " Include FW request support: $INCLUDE_FW_REQUEST_SUPPORT"
-echo -e " Include ADSL trace buffer: $INCLUDE_DSL_CPE_TRACE_BUFFER"
-echo -e " Include ADSL MIB: $INCLUDE_DSL_ADSL_MIB"
-echo -e " Include ADSL LED: $INCLUDE_ADSL_LED"
-echo -e " Include CEOC: $INCLUDE_DSL_CEOC"
-echo -e " Include config get support: $INCLUDE_DSL_CONFIG_GET"
-echo -e " Include System i/f configuration: $INCLUDE_DSL_SYSTEM_INTERFACE"
-echo -e " Include Resource Statistics: $INCLUDE_DSL_RESOURCE_STATISTICS"
-echo -e " Include Framing Parameters: $INCLUDE_DSL_FRAMING_PARAMETERS"
-echo -e " Include G997 Line Inventory: $INCLUDE_DSL_G997_LINE_INVENTORY"
-echo -e " Include G997 Framing Parameters: $INCLUDE_DSL_G997_FRAMING_PARAMETERS"
-echo -e " Include G997 per tone data: $INCLUDE_DSL_G997_PER_TONE"
-echo -e " Include G997 status: $INCLUDE_DSL_G997_STATUS"
-echo -e " Include G997 alarm: $INCLUDE_DSL_G997_ALARM"
-echo -e " Include DSL Bonding: $INCLUDE_DSL_BONDING"
-echo -e " Include Misc Line Status $INCLUDE_DSL_CPE_MISC_LINE_STATUS"
-echo -e " Include DELT: $INCLUDE_DSL_DELT"
-echo -e " Include DELT data static storage: $DSL_CPE_STATIC_DELT_DATA"
-echo -e " Include PM: $INCLUDE_DSL_PM"
-echo -e " Include PM config: $INCLUDE_DSL_CPE_PM_CONFIG"
-echo -e " Include PM total: $INCLUDE_DSL_CPE_PM_TOTAL_COUNTERS"
-echo -e " Include PM history: $INCLUDE_DSL_CPE_PM_HISTORY"
-echo -e " Include PM showtime: $INCLUDE_DSL_CPE_PM_SHOWTIME_COUNTERS"
-echo -e " Include PM optional: $INCLUDE_DSL_CPE_PM_OPTIONAL_PARAMETERS"
-echo -e " Include PM line: $INCLUDE_DSL_CPE_PM_LINE_COUNTERS"
-echo -e " Include PM line event showtime: $INCLUDE_DSL_CPE_PM_LINE_EVENT_SHOWTIME_COUNTERS"
-echo -e " Include PM channel: $INCLUDE_DSL_CPE_PM_CHANNEL_COUNTERS"
-echo -e " Include PM channel extended: $INCLUDE_DSL_CPE_PM_CHANNEL_EXT_COUNTERS"
-echo -e " Include PM data path: $INCLUDE_DSL_CPE_PM_DATA_PATH_COUNTERS"
-echo -e " Include PM data path failure: $INCLUDE_DSL_CPE_PM_DATA_PATH_FAILURE_COUNTERS"
-echo -e " Include PM ReTx: $INCLUDE_DSL_CPE_PM_RETX_COUNTERS"
-echo -e " Include PM line threshold: $INCLUDE_DSL_CPE_PM_LINE_THRESHOLDS"
-echo -e " Include PM channel threshold: $INCLUDE_DSL_CPE_PM_CHANNEL_THRESHOLDS"
-echo -e " Include PM data path threshold: $INCLUDE_DSL_CPE_PM_DATA_PATH_THRESHOLDS"
-echo -e " Include PM ReTx threshold: $INCLUDE_DSL_CPE_PM_RETX_THRESHOLDS"
-echo -e " Include FW memory free support: $INCLUDE_DSL_FIRMWARE_MEMORY_FREE"
-echo -e "----------------------- deprectated ! ----------------------------------"
-echo -e " Include PM line failure: $INCLUDE_DSL_CPE_PM_LINE_FAILURE_COUNTERS"
-echo -e ""
-echo -e " Settings:"
-echo -e " Configure options: $CONFIGURE_OPTIONS"
-echo -e "------------------------------------------------------------------------"
+echo "------------------------------------------------------------------------"
+echo " Configuration for drv_dsl_cpe_api:"
+echo " Configure model type: $DSL_CONFIG_MODEL_TYPE"
+echo " Source code location: $srcdir"
+echo " Compiler: $CC"
+echo " Compiler c-flags: $CFLAGS"
+echo " Extra compiler c-flags: $EXTRA_DRV_CFLAGS"
+echo " Host System Type: $host"
+echo " Install path: $prefix"
+echo " Linux kernel include path: $KERNEL_INCL_PATH"
+echo " Linux kernel build path: $KERNEL_BUILD_PATH"
+echo " Linux kernel architecture: $KERNEL_ARCH"
+echo " Include IFXOS: $INCLUDE_DSL_CPE_API_IFXOS_SUPPORT"
+echo " IFXOS include path: $IFXOS_INCLUDE_PATH"
+echo " Driver Include Path $DSL_DRIVER_INCL_PATH"
+echo " DSL device: $DSL_DEVICE_NAME"
+echo " Max device number: $DSL_DRV_MAX_DEVICE_NUMBER"
+echo " Channels per line: $DSL_CHANNELS_PER_LINE"
+echo " Build lib (only for kernel 2.6) $DSL_CPE_API_LIBRARY_BUILD_2_6"
+echo " DSL data led flash frequency: $DSL_DATA_LED_FLASH_FREQUENCY Hz"
+echo " Disable debug prints: $DSL_DEBUG_DISABLE"
+echo " Preselection of max. debug level: $DSL_DBG_MAX_LEVEL_SET"
+echo " Preselected max. debug level: $DSL_DBG_MAX_LEVEL_PRE"
+echo " Include deprecated functions: $INCLUDE_DEPRECATED"
+echo " Include Device Exception Codes: $INCLUDE_DEVICE_EXCEPTION_CODES"
+echo " Include FW request support: $INCLUDE_FW_REQUEST_SUPPORT"
+echo " Include ADSL trace buffer: $INCLUDE_DSL_CPE_TRACE_BUFFER"
+echo " Include ADSL MIB: $INCLUDE_DSL_ADSL_MIB"
+echo " Include ADSL LED: $INCLUDE_ADSL_LED"
+echo " Include CEOC: $INCLUDE_DSL_CEOC"
+echo " Include config get support: $INCLUDE_DSL_CONFIG_GET"
+echo " Include System i/f configuration: $INCLUDE_DSL_SYSTEM_INTERFACE"
+echo " Include Resource Statistics: $INCLUDE_DSL_RESOURCE_STATISTICS"
+echo " Include Framing Parameters: $INCLUDE_DSL_FRAMING_PARAMETERS"
+echo " Include G997 Line Inventory: $INCLUDE_DSL_G997_LINE_INVENTORY"
+echo " Include G997 Framing Parameters: $INCLUDE_DSL_G997_FRAMING_PARAMETERS"
+echo " Include G997 per tone data: $INCLUDE_DSL_G997_PER_TONE"
+echo " Include G997 status: $INCLUDE_DSL_G997_STATUS"
+echo " Include G997 alarm: $INCLUDE_DSL_G997_ALARM"
+echo " Include DSL Bonding: $INCLUDE_DSL_BONDING"
+echo " Include Misc Line Status $INCLUDE_DSL_CPE_MISC_LINE_STATUS"
+echo " Include DELT: $INCLUDE_DSL_DELT"
+echo " Include DELT data static storage: $DSL_CPE_STATIC_DELT_DATA"
+echo " Include PM: $INCLUDE_DSL_PM"
+echo " Include PM config: $INCLUDE_DSL_CPE_PM_CONFIG"
+echo " Include PM total: $INCLUDE_DSL_CPE_PM_TOTAL_COUNTERS"
+echo " Include PM history: $INCLUDE_DSL_CPE_PM_HISTORY"
+echo " Include PM showtime: $INCLUDE_DSL_CPE_PM_SHOWTIME_COUNTERS"
+echo " Include PM optional: $INCLUDE_DSL_CPE_PM_OPTIONAL_PARAMETERS"
+echo " Include PM line: $INCLUDE_DSL_CPE_PM_LINE_COUNTERS"
+echo " Include PM line event showtime: $INCLUDE_DSL_CPE_PM_LINE_EVENT_SHOWTIME_COUNTERS"
+echo " Include PM channel: $INCLUDE_DSL_CPE_PM_CHANNEL_COUNTERS"
+echo " Include PM channel extended: $INCLUDE_DSL_CPE_PM_CHANNEL_EXT_COUNTERS"
+echo " Include PM data path: $INCLUDE_DSL_CPE_PM_DATA_PATH_COUNTERS"
+echo " Include PM data path failure: $INCLUDE_DSL_CPE_PM_DATA_PATH_FAILURE_COUNTERS"
+echo " Include PM ReTx: $INCLUDE_DSL_CPE_PM_RETX_COUNTERS"
+echo " Include PM line threshold: $INCLUDE_DSL_CPE_PM_LINE_THRESHOLDS"
+echo " Include PM channel threshold: $INCLUDE_DSL_CPE_PM_CHANNEL_THRESHOLDS"
+echo " Include PM data path threshold: $INCLUDE_DSL_CPE_PM_DATA_PATH_THRESHOLDS"
+echo " Include PM ReTx threshold: $INCLUDE_DSL_CPE_PM_RETX_THRESHOLDS"
+echo " Include FW memory free support: $INCLUDE_DSL_FIRMWARE_MEMORY_FREE"
+echo "----------------------- deprectated ! ----------------------------------"
+echo " Include PM line failure: $INCLUDE_DSL_CPE_PM_LINE_FAILURE_COUNTERS"
+echo ""
+echo " Settings:"
+echo " Configure options: $CONFIGURE_OPTIONS"
+echo "------------------------------------------------------------------------"
])
AC_CONFIG_FILES([Makefile src/Makefile])
Index: drv_dsl_cpe_api-3.24.4.4/src/Makefile.am
===================================================================
--- drv_dsl_cpe_api-3.24.4.4.orig/src/Makefile.am 2009-07-03 14:06:34.000000000 +0200
+++ drv_dsl_cpe_api-3.24.4.4/src/Makefile.am 2010-10-14 02:14:55.000000000 +0200
@@ -303,7 +303,7 @@
drv_dsl_cpe_api_OBJS = "$(subst .c,.o,$(filter %.c,$(drv_dsl_cpe_api_SOURCES)))"
drv_dsl_cpe_api.ko: $(drv_dsl_cpe_api_SOURCES)
- @echo -e "drv_dsl_cpe_api: Making Linux 2.6.x kernel object"
+ @echo "drv_dsl_cpe_api: Making Linux 2.6.x kernel object"
if test ! -e common/drv_dsl_cpe_api.c ; then \
echo "copy source files (as links only!)"; \
for f in $(filter %.c,$(drv_dsl_cpe_api_SOURCES)); do \
@@ -311,10 +311,10 @@
cp -s $(addprefix @abs_srcdir@/,$$f) $(PWD)/`dirname $$f`/ ; \
done \
fi
- @echo -e "# drv_dsl_cpe_api: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild
- @echo -e "obj-m := $(subst .ko,.o,$@)" >> $(PWD)/Kbuild
- @echo -e "$(subst .ko,,$@)-y := $(drv_dsl_cpe_api_OBJS)" >> $(PWD)/Kbuild
- @echo -e "EXTRA_CFLAGS := $(CFLAGS) -DHAVE_CONFIG_H $(drv_dsl_cpe_api_CFLAGS) $(DSL_DRIVER_INCL_PATH) $(IFXOS_INCLUDE_PATH) -I@abs_srcdir@/include -I$(PWD)/include" >> $(PWD)/Kbuild
+ @echo "# drv_dsl_cpe_api: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild
+ @echo "obj-m := $(subst .ko,.o,$@)" >> $(PWD)/Kbuild
+ @echo "$(subst .ko,,$@)-y := $(drv_dsl_cpe_api_OBJS)" >> $(PWD)/Kbuild
+ @echo "EXTRA_CFLAGS := $(CFLAGS) -DHAVE_CONFIG_H $(drv_dsl_cpe_api_CFLAGS) $(DSL_DRIVER_INCL_PATH) $(IFXOS_INCLUDE_PATH) -I@abs_srcdir@/include -I$(PWD)/include" >> $(PWD)/Kbuild
$(MAKE) ARCH=@KERNEL_ARCH@ -C @KERNEL_BUILD_PATH@ O=@KERNEL_BUILD_PATH@ M=$(PWD) modules
clean-generic:
Index: drv_dsl_cpe_api-3.24.4.4/src/include/drv_dsl_cpe_os_linux.h
===================================================================
--- drv_dsl_cpe_api-3.24.4.4.orig/src/include/drv_dsl_cpe_os_linux.h 2010-10-14 02:14:55.000000000 +0200
+++ drv_dsl_cpe_api-3.24.4.4/src/include/drv_dsl_cpe_os_linux.h 2010-10-14 02:14:55.000000000 +0200
@@ -16,8 +16,6 @@
extern "C" {
#endif
-#include <asm/ioctl.h>
-#include <generated/autoconf.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
@@ -40,6 +38,7 @@
#include <linux/poll.h>
#include <asm/uaccess.h>
#include <linux/smp_lock.h>
+#include <asm/ioctl.h>
#ifdef INCLUDE_DSL_CPE_API_IFXOS_SUPPORT
/** IFXOS includes*/

View file

@ -0,0 +1,3 @@
obj-m = lantiq_mei.o lantiq_atm.o
lantiq_atm-objs := ifxmips_atm_core.o ifxmips_atm_danube.o

108
package/lqdsl/src/ifx_atm.h Normal file
View file

@ -0,0 +1,108 @@
/******************************************************************************
**
** FILE NAME : ifx_atm.h
** PROJECT : UEIP
** MODULES : ATM
**
** DATE : 17 Jun 2009
** AUTHOR : Xu Liang
** DESCRIPTION : Global ATM driver header file
** COPYRIGHT : Copyright (c) 2006
** Infineon Technologies AG
** Am Campeon 1-12, 85579 Neubiberg, Germany
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** HISTORY
** $Date $Author $Comment
** 07 JUL 2009 Xu Liang Init Version
*******************************************************************************/
#ifndef IFX_ATM_H
#define IFX_ATM_H
/*
* ATM MIB
*/
typedef struct {
__u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */
__u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */
__u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */
__u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */
__u32 ifInErrors; /*!< counter of error ingress cells */
__u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */
__u32 ifOutErrors; /*!< counter of error egress cells */
} atm_cell_ifEntry_t;
typedef struct {
__u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
__u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
__u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */
__u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */
__u32 ifInUcastPkts; /*!< counter of ingress packets */
__u32 ifOutUcastPkts; /*!< counter of egress packets */
__u32 ifInErrors; /*!< counter of error ingress packets */
__u32 ifInDiscards; /*!< counter of dropped ingress packets */
__u32 ifOutErros; /*!< counter of error egress packets */
__u32 ifOutDiscards; /*!< counter of dropped egress packets */
} atm_aal5_ifEntry_t;
typedef struct {
__u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */
__u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet
__u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */
} atm_aal5_vcc_t;
typedef struct {
int vpi; /*!< VPI of the VCC to get MIB counters */
int vci; /*!< VCI of the VCC to get MIB counters */
atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */
} atm_aal5_vcc_x_t;
/*!
\brief ATM IOCTL Magic Number
*/
#define PPE_ATM_IOC_MAGIC 'o'
/*!
\brief ATM IOCTL Command - Get Cell Level MIB Counters
This command is obsolete. User can get cell level MIB from DSL API.
This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
*/
#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t)
/*!
\brief ATM IOCTL Command - Get AAL5 Level MIB Counters
Get AAL5 packet counters.
This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
*/
#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t)
/*!
\brief ATM IOCTL Command - Get Per PVC MIB Counters
Get AAL5 packet counters for each PVC.
This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
*/
#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
/*!
\brief Total Number of ATM IOCTL Commands
*/
#define PPE_ATM_IOC_MAXNR 3
/*@}*/
#ifdef __KERNEL__
struct port_cell_info {
unsigned int port_num;
unsigned int tx_link_rate[2];
};
#endif
#endif

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@ -0,0 +1,172 @@
/******************************************************************************
**
** FILE NAME : ifx_atm.h
** PROJECT : UEIP
** MODULES : ATM
**
** DATE : 17 Jun 2009
** AUTHOR : Xu Liang
** DESCRIPTION : Global ATM driver header file
** COPYRIGHT : Copyright (c) 2006
** Infineon Technologies AG
** Am Campeon 1-12, 85579 Neubiberg, Germany
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** HISTORY
** $Date $Author $Comment
** 07 JUL 2009 Xu Liang Init Version
*******************************************************************************/
#ifndef IFX_ATM_H
#define IFX_ATM_H
/*!
\defgroup IFX_ATM UEIP Project - ATM driver module
\brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
*/
/*!
\defgroup IFX_ATM_IOCTL IOCTL Commands
\ingroup IFX_ATM
\brief IOCTL Commands used by user application.
*/
/*!
\defgroup IFX_ATM_STRUCT Structures
\ingroup IFX_ATM
\brief Structures used by user application.
*/
/*!
\file ifx_atm.h
\ingroup IFX_ATM
\brief ATM driver header file
*/
/*
* ####################################
* Definition
* ####################################
*/
/*!
\addtogroup IFX_ATM_STRUCT
*/
/*@{*/
/*
* ATM MIB
*/
typedef struct {
__u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */
__u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */
__u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */
__u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */
__u32 ifInErrors; /*!< counter of error ingress cells */
__u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */
__u32 ifOutErrors; /*!< counter of error egress cells */
} atm_cell_ifEntry_t;
typedef struct {
__u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
__u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
__u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */
__u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */
__u32 ifInUcastPkts; /*!< counter of ingress packets */
__u32 ifOutUcastPkts; /*!< counter of egress packets */
__u32 ifInErrors; /*!< counter of error ingress packets */
__u32 ifInDiscards; /*!< counter of dropped ingress packets */
__u32 ifOutErros; /*!< counter of error egress packets */
__u32 ifOutDiscards; /*!< counter of dropped egress packets */
} atm_aal5_ifEntry_t;
typedef struct {
__u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */
__u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet
__u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */
} atm_aal5_vcc_t;
typedef struct {
int vpi; /*!< VPI of the VCC to get MIB counters */
int vci; /*!< VCI of the VCC to get MIB counters */
atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */
} atm_aal5_vcc_x_t;
/*@}*/
/*
* ####################################
* IOCTL
* ####################################
*/
/*!
\addtogroup IFX_ATM_IOCTL
*/
/*@{*/
/*
* ioctl Command
*/
/*!
\brief ATM IOCTL Magic Number
*/
#define PPE_ATM_IOC_MAGIC 'o'
/*!
\brief ATM IOCTL Command - Get Cell Level MIB Counters
This command is obsolete. User can get cell level MIB from DSL API.
This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
*/
#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t)
/*!
\brief ATM IOCTL Command - Get AAL5 Level MIB Counters
Get AAL5 packet counters.
This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
*/
#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t)
/*!
\brief ATM IOCTL Command - Get Per PVC MIB Counters
Get AAL5 packet counters for each PVC.
This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
*/
#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
/*!
\brief Total Number of ATM IOCTL Commands
*/
#define PPE_ATM_IOC_MAXNR 3
/*@}*/
/*
* ####################################
* API
* ####################################
*/
#ifdef __KERNEL__
struct port_cell_info {
unsigned int port_num;
unsigned int tx_link_rate[2];
};
#endif
#endif // IFX_ATM_H

File diff suppressed because it is too large Load diff

View file

@ -0,0 +1,249 @@
/******************************************************************************
**
** FILE NAME : ifxmips_atm_core.h
** PROJECT : UEIP
** MODULES : ATM
**
** DATE : 7 Jul 2009
** AUTHOR : Xu Liang
** DESCRIPTION : ATM driver header file (core functions)
** COPYRIGHT : Copyright (c) 2006
** Infineon Technologies AG
** Am Campeon 1-12, 85579 Neubiberg, Germany
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** HISTORY
** $Date $Author $Comment
** 17 JUN 2009 Xu Liang Init Version
*******************************************************************************/
#ifndef IFXMIPS_ATM_CORE_H
#define IFXMIPS_ATM_CORE_H
#include "ifxmips_compat.h"
#include "ifx_atm.h"
#include "ifxmips_atm_ppe_common.h"
#include "ifxmips_atm_fw_regs_common.h"
/*
* ####################################
* Definition
* ####################################
*/
/*
* Compile Options
*/
#define ENABLE_DEBUG 1
#define ENABLE_ASSERT 1
#define INLINE
#define DEBUG_DUMP_SKB 1
#define DEBUG_QOS 1
#define ENABLE_DBG_PROC 1
#define ENABLE_FW_PROC 1
#ifdef CONFIG_IFX_ATM_TASKLET
#define ENABLE_TASKLET 1
#endif
/*
* Debug/Assert/Error Message
*/
#define DBG_ENABLE_MASK_ERR (1 << 0)
#define DBG_ENABLE_MASK_DEBUG_PRINT (1 << 1)
#define DBG_ENABLE_MASK_ASSERT (1 << 2)
#define DBG_ENABLE_MASK_DUMP_SKB_RX (1 << 8)
#define DBG_ENABLE_MASK_DUMP_SKB_TX (1 << 9)
#define DBG_ENABLE_MASK_DUMP_QOS (1 << 10)
#define DBG_ENABLE_MASK_DUMP_INIT (1 << 11)
#define DBG_ENABLE_MASK_ALL (DBG_ENABLE_MASK_ERR | DBG_ENABLE_MASK_DEBUG_PRINT | DBG_ENABLE_MASK_ASSERT | DBG_ENABLE_MASK_DUMP_SKB_RX | DBG_ENABLE_MASK_DUMP_SKB_TX | DBG_ENABLE_MASK_DUMP_QOS | DBG_ENABLE_MASK_DUMP_INIT)
#define err(format, arg...) do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ERR) ) printk(KERN_ERR __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
#if defined(ENABLE_DEBUG) && ENABLE_DEBUG
#undef dbg
#define dbg(format, arg...) do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DEBUG_PRINT) ) printk(KERN_WARNING __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
#else
#if !defined(dbg)
#define dbg(format, arg...)
#endif
#endif
#if defined(ENABLE_ASSERT) && ENABLE_ASSERT
#define ASSERT(cond, format, arg...) do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ASSERT) && !(cond) ) printk(KERN_ERR __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
#else
#define ASSERT(cond, format, arg...)
#endif
/*
* Constants
*/
#define DEFAULT_TX_LINK_RATE 3200 // in cells
/*
* ATM Port, QSB Queue, DMA RX/TX Channel Parameters
*/
#define ATM_PORT_NUMBER 2
#define MAX_QUEUE_NUMBER 16
#define OAM_RX_QUEUE 15
#define QSB_RESERVE_TX_QUEUE 0
#define FIRST_QSB_QID 1
#define MAX_PVC_NUMBER (MAX_QUEUE_NUMBER - FIRST_QSB_QID)
#define MAX_RX_DMA_CHANNEL_NUMBER 8
#define MAX_TX_DMA_CHANNEL_NUMBER 16
#define DATA_BUFFER_ALIGNMENT EMA_ALIGNMENT
#define DESC_ALIGNMENT 8
#define DEFAULT_RX_HUNT_BITTH 4
/*
* RX DMA Channel Allocation
*/
#define RX_DMA_CH_OAM 0
#define RX_DMA_CH_AAL 1
#define RX_DMA_CH_TOTAL 2
#define RX_DMA_CH_OAM_DESC_LEN 32
#define RX_DMA_CH_OAM_BUF_SIZE (CELL_SIZE & ~15)
#define RX_DMA_CH_AAL_BUF_SIZE (2048 - 48)
/*
* OAM Constants
*/
#define OAM_HTU_ENTRY_NUMBER 3
#define OAM_F4_SEG_HTU_ENTRY 0
#define OAM_F4_TOT_HTU_ENTRY 1
#define OAM_F5_HTU_ENTRY 2
#define OAM_F4_CELL_ID 0
#define OAM_F5_CELL_ID 15
//#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
// #undef OAM_HTU_ENTRY_NUMBER
// #define OAM_HTU_ENTRY_NUMBER 4
// #define OAM_ARQ_HTU_ENTRY 3
//#endif
/*
* RX Frame Definitions
*/
#define MAX_RX_PACKET_ALIGN_BYTES 3
#define MAX_RX_PACKET_PADDING_BYTES 3
#define RX_INBAND_TRAILER_LENGTH 8
#define MAX_RX_FRAME_EXTRA_BYTES (RX_INBAND_TRAILER_LENGTH + MAX_RX_PACKET_ALIGN_BYTES + MAX_RX_PACKET_PADDING_BYTES)
/*
* TX Frame Definitions
*/
#define MAX_TX_HEADER_ALIGN_BYTES 12
#define MAX_TX_PACKET_ALIGN_BYTES 3
#define MAX_TX_PACKET_PADDING_BYTES 3
#define TX_INBAND_HEADER_LENGTH 8
#define MAX_TX_FRAME_EXTRA_BYTES (TX_INBAND_HEADER_LENGTH + MAX_TX_HEADER_ALIGN_BYTES + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES)
/*
* Cell Constant
*/
#define CELL_SIZE ATM_AAL0_SDU
/*
* ####################################
* Data Type
* ####################################
*/
typedef struct {
unsigned int h;
unsigned int l;
} ppe_u64_t;
struct port {
unsigned int tx_max_cell_rate;
unsigned int tx_current_cell_rate;
struct atm_dev *dev;
};
struct connection {
struct atm_vcc *vcc;
volatile struct tx_descriptor
*tx_desc;
unsigned int tx_desc_pos;
struct sk_buff **tx_skb;
unsigned int aal5_vcc_crc_err; /* number of packets with CRC error */
unsigned int aal5_vcc_oversize_sdu; /* number of packets with oversize error */
unsigned int port;
};
struct atm_priv_data {
unsigned long conn_table;
struct connection conn[MAX_PVC_NUMBER];
volatile struct rx_descriptor
*aal_desc;
unsigned int aal_desc_pos;
volatile struct rx_descriptor
*oam_desc;
unsigned char *oam_buf;
unsigned int oam_desc_pos;
struct port port[ATM_PORT_NUMBER];
unsigned int wrx_pdu; /* successfully received AAL5 packet */
unsigned int wrx_drop_pdu; /* AAL5 packet dropped by driver on RX */
unsigned int wtx_pdu; /* successfully tranmitted AAL5 packet */
unsigned int wtx_err_pdu; /* error AAL5 packet */
unsigned int wtx_drop_pdu; /* AAL5 packet dropped by driver on TX */
ppe_u64_t wrx_total_byte;
ppe_u64_t wtx_total_byte;
unsigned int prev_wrx_total_byte;
unsigned int prev_wtx_total_byte;
void *aal_desc_base;
void *oam_desc_base;
void *oam_buf_base;
void *tx_desc_base;
void *tx_skb_base;
};
/*
* ####################################
* Declaration
* ####################################
*/
extern unsigned int ifx_atm_dbg_enable;
extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor);
extern void ifx_atm_init_chip(void);
extern void ifx_atm_uninit_chip(void);
extern int ifx_pp32_start(int pp32);
extern void ifx_pp32_stop(int pp32);
#endif // IFXMIPS_ATM_CORE_H

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@ -0,0 +1,271 @@
/******************************************************************************
**
** FILE NAME : ifxmips_atm_danube.c
** PROJECT : UEIP
** MODULES : ATM
**
** DATE : 7 Jul 2009
** AUTHOR : Xu Liang
** DESCRIPTION : ATM driver common source file (core functions)
** COPYRIGHT : Copyright (c) 2006
** Infineon Technologies AG
** Am Campeon 1-12, 85579 Neubiberg, Germany
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** HISTORY
** $Date $Author $Comment
** 07 JUL 2009 Xu Liang Init Version
*******************************************************************************/
/*
* ####################################
* Head File
* ####################################
*/
/*
* Common Head File
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/version.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/proc_fs.h>
#include <linux/init.h>
#include <linux/ioctl.h>
#include <asm/delay.h>
/*
* Chip Specific Head File
*/
#include <lantiq.h>
#include <lantiq_regs.h>
#include "ifxmips_compat.h"
#include "ifxmips_atm_core.h"
#include "ifxmips_atm_fw_danube.h"
/*
* ####################################
* Definition
* ####################################
*/
/*
* EMA Settings
*/
#define EMA_CMD_BUF_LEN 0x0040
#define EMA_CMD_BASE_ADDR (0x00001580 << 2)
#define EMA_DATA_BUF_LEN 0x0100
#define EMA_DATA_BASE_ADDR (0x00001900 << 2)
#define EMA_WRITE_BURST 0x2
#define EMA_READ_BURST 0x2
/*
* ####################################
* Declaration
* ####################################
*/
/*
* Hardware Init/Uninit Functions
*/
static inline void init_pmu(void);
static inline void uninit_pmu(void);
static inline void init_ema(void);
static inline void init_mailbox(void);
static inline void init_atm_tc(void);
static inline void clear_share_buffer(void);
/*
* ####################################
* Local Variable
* ####################################
*/
/*
* ####################################
* Local Function
* ####################################
*/
static inline void init_pmu(void)
{
//*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);
}
static inline void uninit_pmu(void)
{
PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);
}
static inline void init_ema(void)
{
IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
IFX_REG_W32(0x000000FF, EMA_IER);
IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
}
static inline void init_mailbox(void)
{
IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
}
static inline void init_atm_tc(void)
{
// for ReTX expansion in future
//*FFSM_CFG0 = SET_BITS(*FFSM_CFG0, 5, 0, 6); // pnum = 6
//*FFSM_CFG1 = SET_BITS(*FFSM_CFG1, 5, 0, 6); // pnum = 6
}
static inline void clear_share_buffer(void)
{
volatile u32 *p = SB_RAM0_ADDR(0);
unsigned int i;
for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
IFX_REG_W32(0, p++);
}
/*
* Description:
* Download PPE firmware binary code.
* Input:
* src --- u32 *, binary code buffer
* dword_len --- unsigned int, binary code length in DWORD (32-bit)
* Output:
* int --- IFX_SUCCESS: Success
* else: Error Code
*/
static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
{
volatile u32 *dest;
if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
|| data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
return IFX_ERROR;
if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
IFX_REG_W32(0x00, CDM_CFG);
else
IFX_REG_W32(0x02, CDM_CFG);
/* copy code */
dest = CDM_CODE_MEMORY(0, 0);
while ( code_dword_len-- > 0 )
IFX_REG_W32(*code_src++, dest++);
/* copy data */
dest = CDM_DATA_MEMORY(0, 0);
while ( data_dword_len-- > 0 )
IFX_REG_W32(*data_src++, dest++);
return IFX_SUCCESS;
}
/*
* ####################################
* Global Function
* ####################################
*/
extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor)
{
ASSERT(major != NULL, "pointer is NULL");
ASSERT(minor != NULL, "pointer is NULL");
*major = ATM_FW_VER_MAJOR;
*minor = ATM_FW_VER_MINOR;
}
void ifx_atm_init_chip(void)
{
init_pmu();
init_ema();
init_mailbox();
init_atm_tc();
clear_share_buffer();
}
void ifx_atm_uninit_chip(void)
{
uninit_pmu();
}
/*
* Description:
* Initialize and start up PP32.
* Input:
* none
* Output:
* int --- IFX_SUCCESS: Success
* else: Error Code
*/
int ifx_pp32_start(int pp32)
{
int ret;
/* download firmware */
ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
if ( ret != IFX_SUCCESS )
return ret;
/* run PP32 */
IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL);
/* idle for a while to let PP32 init itself */
udelay(10);
return IFX_SUCCESS;
}
/*
* Description:
* Halt PP32.
* Input:
* none
* Output:
* none
*/
void ifx_pp32_stop(int pp32)
{
/* halt PP32 */
IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL);
}

View file

@ -0,0 +1,429 @@
#ifndef IFXMIPS_ATM_FW_DANUBE_H
#define IFXMIPS_ATM_FW_DANUBE_H
/******************************************************************************
**
** FILE NAME : ifxmips_atm_fw_danube.h
** PROJECT : Danube
** MODULES : ATM (ADSL)
**
** DATE : 1 AUG 2005
** AUTHOR : Xu Liang
** DESCRIPTION : ATM Driver (PP32 Firmware)
** COPYRIGHT : Copyright (c) 2006
** Infineon Technologies AG
** Am Campeon 1-12, 85579 Neubiberg, Germany
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** HISTORY
** $Date $Author $Comment
** 4 AUG 2005 Xu Liang Initiate Version
** 23 OCT 2006 Xu Liang Add GPL header.
*******************************************************************************/
#define ATM_FW_VER_MAJOR 0
#define ATM_FW_VER_MINOR 1
static unsigned int firmware_binary_code[] = {
0x800004A0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000FFC8, 0x00000000, 0x00000000, 0x00000000,
0xC1000002, 0xD90C0000, 0xC2000002, 0xDA080001, 0x80004710, 0xC2000000, 0xDA080001, 0x80003D98,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x80003D50, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x80004F18, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x80003C50, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xC0400000, 0xC0004840, 0xC8840000, 0x800043D0, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xC0400002, 0xC0004840, 0xC8840000, 0x80004350, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xC3C00004, 0xDBC80001, 0xC10C0002, 0xD90C0000, 0x8000FEC8, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xC10E0002, 0xD90C0000, 0xC0004808, 0xC8400000, 0x80004380, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xC3E1FFFE, 0x597DFFFE, 0x593DFE14, 0x900004D9, 0x00000000, 0x00000000, 0x00000000, 0x90CC0481,
0x00000000, 0x00000000, 0x00000000, 0xC3C00000, 0xDBC80001, 0xC1400008, 0xC1900000, 0x71948000,
0x15000100, 0xC140000A, 0xC1900002, 0x71948000, 0x15000100, 0xC140000C, 0xC1900004, 0x71948000,
0x15000100, 0xC1400004, 0xC1900006, 0x71948000, 0x15000100, 0xC1400006, 0xC1900008, 0x71948000,
0x15000100, 0xC140000E, 0xC190000A, 0x71948000, 0x15000100, 0xC1400000, 0xC190000C, 0x71948000,
0x15000100, 0xC1400002, 0xC190000E, 0x71948000, 0x15000100, 0xC0400000, 0xC11C0000, 0xC000082C,
0xCD040E08, 0xC11C0002, 0xC000082C, 0xCD040E08, 0xC0400002, 0xC11C0000, 0xC000082C, 0xCD040E08,
0xC11C0002, 0xC000082C, 0xCD040E08, 0xC0000824, 0x00000000, 0xCBC00001, 0xCB800001, 0xCB400001,
0xCB000000, 0xC0004878, 0x5BFC4000, 0xCFC00001, 0x5BB84000, 0xCF800001, 0x5B744000, 0xCF400001,
0x5B304000, 0xCF000000, 0xC0000A10, 0x00000000, 0xCBC00001, 0xCB800000, 0xC0004874, 0x5BFC4000,
0xCFC00001, 0x5BB84000, 0xCF800000, 0xC30001FE, 0xC000140A, 0xCF000000, 0xC3000000, 0x7F018000,
0xC000042E, 0xCF000000, 0xC000040E, 0xCF000000, 0xC3C1FFFE, 0xC000490E, 0xCFC00080, 0xC000492C,
0xCFC00080, 0xC0004924, 0xCFC00040, 0xC0004912, 0xCFC00040, 0xC0004966, 0xCFC00040, 0xC0004968,
0xCFC00080, 0xC000496A, 0xCFC00080, 0xC3C00000, 0xC2800020, 0xC3000000, 0x7F018000, 0x6FF88000,
0x6FD44000, 0x4395C000, 0x5BB84A00, 0x5838000A, 0xCF000000, 0x5BFC0002, 0xB7E8FFA8, 0x00000000,
0xC3C00000, 0xC2800010, 0x6FF86000, 0x47F9C000, 0x5BB84C80, 0xC3400000, 0x58380004, 0xCB420080,
0x00000000, 0x58380008, 0xCF400080, 0x5BFC0002, 0xB7E8FF90, 0x00000000, 0xC3C00000, 0xC2800020,
0xC348001E, 0xC3000000, 0x7F018000, 0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20,
0x58380008, 0xCF400420, 0x5838000A, 0xCF000000, 0x5BFC0002, 0xB7E8FF90, 0x00000000, 0x00000000,
0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0x80000518, 0x00000000, 0x80002118, 0x00000000,
0x8000FFC8, 0xC0004958, 0xC8400000, 0x00000000, 0xC3C00002, 0x7BC42000, 0xCC400000, 0xC0004848,
0xCB840000, 0xC000495C, 0xCAC40000, 0xC0004844, 0xC8840000, 0x46F90000, 0x8400FF6A, 0xC000487C,
0xC8040000, 0x00000000, 0x00000000, 0x40080000, 0xCA000000, 0xC0001624, 0xCB040000, 0xA63C005A,
0x00000000, 0x00000000, 0xA71EFF02, 0x00000000, 0xC0000824, 0xCA840000, 0x6CA08000, 0x6CA42000,
0x46610000, 0x42290000, 0xC35E0002, 0xC6340068, 0xC0001624, 0xCF440080, 0xC2000000, 0xC161FFFE,
0x5955FFFE, 0x15400000, 0x00000000, 0xC0004844, 0xC8840000, 0xC000082C, 0xCA040040, 0x00000000,
0x00000000, 0x58880002, 0xB608FFF8, 0x00000000, 0xC0800000, 0xC0004844, 0xCC840040, 0x5AEC0002,
0xC000495C, 0xCEC40000, 0x5E6C0006, 0x84000048, 0xC0004848, 0xCB840000, 0xC0000838, 0xC2500002,
0xCE440808, 0x5FB80002, 0xC0004848, 0xCF840000, 0x5EEC0002, 0xC000495C, 0xCEC40000, 0x00000000,
0xC121FFFE, 0x5911FE14, 0x15000000, 0x8000FD80, 0xC000495A, 0xC8400000, 0x00000000, 0xC3C00002,
0x7BC42000, 0xCC400000, 0xC0004960, 0xCAC40000, 0x00000000, 0x00000000, 0x5EEC0000, 0x840000F2,
0x00000000, 0xB6FC0030, 0xC0001600, 0xCA040000, 0x00000000, 0x00000000, 0xA61E00B2, 0x6FE90000,
0xC0000A28, 0xCE840808, 0xC2C00000, 0xC2800004, 0xB6E80080, 0xC0001604, 0xCA840000, 0xC0004960,
0xCEC40000, 0xA69EFCA2, 0x00000000, 0x6FE90000, 0xC0000A28, 0xCE840808, 0xC2C00002, 0xC0001600,
0xCA040000, 0x00000000, 0x00000000, 0xA61E000A, 0x6FE90000, 0xC0000A28, 0xCE840808, 0xC2C00000,
0xC0001604, 0xCA840000, 0xC0004960, 0xCEC40000, 0xA69EFC0A, 0xC2400000, 0xC0000A14, 0xCA440030,
0x00000000, 0x00000000, 0x46E52000, 0xA4400000, 0xC2800000, 0xDFEB0031, 0x8000FFF8, 0xDFEA0031,
0xB668FB82, 0x00000000, 0xC00048A0, 0xCB040000, 0xC0000A10, 0xCA840000, 0x6F208000, 0x6F242000,
0x46610000, 0x42A10000, 0xC2400000, 0xC0000A14, 0xCA440030, 0xC35E0002, 0xC6340068, 0xC0001604,
0xCF440080, 0x5B300002, 0xB670FFF8, 0x5AEC0002, 0xC3000000, 0xC00048A0, 0xCF040000, 0xC0004960,
0xCEC40000, 0x8000FAC0, 0xC0004918, 0xD2800000, 0xC2000000, 0xDF600040, 0x5E600080, 0x8400025A,
0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000480A, 0xCA000000, 0xC0004912,
0xCA400000, 0xC0004924, 0xCA800000, 0xC0004966, 0xCAC00000, 0x00000000, 0xC121FFFE, 0x5911FE14,
0x15000000, 0x76610000, 0x76A10000, 0x76E10000, 0x840001B2, 0xC0004918, 0xCA400000, 0xC28001FE,
0x76A10000, 0x5A640002, 0x6A254010, 0x5EE80000, 0x84000002, 0x6AA54000, 0x8000FFF8, 0xC6280000,
0x62818008, 0xC0004918, 0xCF000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC0004966,
0xCA400000, 0xC2000002, 0x6A310000, 0x7E010000, 0x76252000, 0xCE400000, 0x00000000, 0xC121FFFE,
0x5911FE14, 0x15000000, 0x6F346000, 0x4735A000, 0x5B744C80, 0xC2800000, 0x58340006, 0xCA800080,
0xC2C00000, 0x58340000, 0xCAC000E0, 0xC2400000, 0x5834000A, 0xCA420080, 0x6EA82000, 0x42E9E000,
0x6F2CA000, 0x42E56000, 0x5AEC1400, 0xC3990040, 0xC7381C20, 0xC6F80068, 0x99005930, 0xDB980000,
0xDBD80001, 0x00000000, 0xDEA00000, 0x47210000, 0x8400FD68, 0xC0004958, 0xC8400000, 0x00000000,
0xC3C00002, 0x7BC42000, 0xCC400000, 0xC0004848, 0xCB840000, 0xC0004844, 0xC8840000, 0x5FB80000,
0x8400F7DA, 0xC0001A1C, 0xCA000000, 0xC2400002, 0x6A452000, 0x76610000, 0x8400F7AA, 0xC000487C,
0xC8040000, 0x00000000, 0x00000000, 0x40080000, 0xCA000000, 0xC4240000, 0x00000000, 0xA63C17BA,
0x00000000, 0xC0004878, 0xC8040000, 0x6C908000, 0x44908000, 0x44908000, 0x40100000, 0xCA000000,
0xC4240000, 0x00000000, 0xC0004934, 0xCE000000, 0xC2800002, 0xC4681C10, 0xC62821D8, 0xC2600010,
0x5A650040, 0xC0004800, 0xCB400000, 0xC2200400, 0x5A200000, 0xC7601048, 0xC0001220, 0xCE800000,
0xC0001200, 0xCE400000, 0xC0001202, 0xCE000000, 0xC0001240, 0xCB400000, 0x00000000, 0x00000000,
0xA754FFC0, 0xC2000000, 0xC7600048, 0xA7520022, 0x00000000, 0x00000000, 0x990060A8, 0xC0004822,
0xC9400000, 0xC1800002, 0x80001668, 0x58204080, 0xC2000000, 0xCA000020, 0xC2400000, 0xCA414008,
0xC2800000, 0xCA812008, 0xC2C00000, 0xCAC20020, 0xC0004938, 0xCE000000, 0xC0004920, 0xCE400000,
0xC0004916, 0xCE800000, 0xC0004922, 0xCEC00000, 0xA6400520, 0x00000000, 0xC0004938, 0xCBC00000,
0x00000000, 0xC3800000, 0x6FF48000, 0x6FD44000, 0x4355A000, 0x5B744A00, 0x58340000, 0xCB802018,
0x00000000, 0xC2000000, 0x6FB46000, 0x47B5A000, 0x5B744C80, 0x5834000C, 0xCA000028, 0xC000491A,
0xCF800000, 0x5E200000, 0x84000452, 0xC2000000, 0xDF610050, 0x5E6001E8, 0x8800FFD0, 0xC2000002,
0xC2400466, 0xC2A00000, 0x5AA80000, 0xC0001006, 0xCE000000, 0xC0001008, 0xCE400000, 0xC000100A,
0xCE800000, 0x99005370, 0xC1A0FFFE, 0xC0000824, 0xC9840068, 0xC0004934, 0xCA400000, 0xC2000000,
0xC2800002, 0x990053B0, 0xDA980000, 0xC6140000, 0xC6580000, 0xC161FFFE, 0x5955FFFE, 0x15400000,
0x00000000, 0x99005498, 0xC000491A, 0xC9400000, 0x00000000, 0x00000000, 0xC121FFFE, 0x5911FE14,
0x15000000, 0xC0004922, 0xCA001120, 0xC3C00000, 0xC3800000, 0xC0004930, 0xCE001120, 0xC0004932,
0xCBC000E0, 0xC2800000, 0xC000491E, 0xCFC00000, 0xC0004862, 0xCA800068, 0xC3A0001A, 0x5BB94000,
0xC6B80068, 0xC000491C, 0xCF800000, 0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0x00000000,
0x00000000, 0x00000000, 0xA8E2FFC8, 0xC2000000, 0xC1220002, 0xD90C0000, 0xDF600040, 0x5E600080,
0x8400FFDA, 0xC000491C, 0xCA000000, 0xC000491E, 0xCA400000, 0x00000000, 0x00000000, 0x99005930,
0xDA180000, 0xDA580001, 0x00000000, 0xC2000000, 0xDF610050, 0x5E6001FE, 0x8800FFD0, 0xC0004916,
0xCA800000, 0xC2C00000, 0xDFEC0050, 0xC2400000, 0x46E52000, 0x84000032, 0x5EA80000, 0x84000022,
0xC2600002, 0x990060A8, 0xC000482E, 0xC9400000, 0xC1800002, 0x80000018, 0xC2600000, 0x990060A8,
0xC000482C, 0xC9400000, 0xC1800002, 0xC2000068, 0xC6240080, 0xC0004930, 0xCE400088, 0xC000491A,
0xC9800000, 0xC0004862, 0xC9400000, 0x6D9C6000, 0x459CE000, 0x59DC4C80, 0x99005790, 0xD9580000,
0xD9980001, 0xD9D40000, 0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0xC2000000, 0xDF600040,
0x5E600080, 0x8400FFD2, 0x00000000, 0xC000491C, 0xCA000000, 0xC000491E, 0xCA400000, 0x00000000,
0x00000000, 0x99005930, 0xDA180000, 0xDA580001, 0x00000000, 0x800010D0, 0x00000000, 0x990060A8,
0xC000482A, 0xC9400000, 0xC1800002, 0x800010A0, 0xC0004938, 0xCBC00000, 0x00000000, 0x00000000,
0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB84A00, 0x58380008, 0xCA000000, 0x00000000, 0x00000000,
0xA6000362, 0x00000000, 0xC0004938, 0xCBC00000, 0xC3000000, 0x00000000, 0x6FF88000, 0x6FD44000,
0x4395C000, 0x5BB84A00, 0x58380000, 0xCB002018, 0xC2000000, 0x58380008, 0xCA020080, 0x5838000C,
0xCAC00000, 0x5838000E, 0xCA400000, 0xC000491A, 0xCF000000, 0xC0004930, 0xCEC00000, 0xC000493C,
0xCE000000, 0xC0004932, 0xCE400000, 0x5E200000, 0x84000108, 0xC2800000, 0xA6FE009A, 0x6F206000,
0x47210000, 0x5A204C80, 0x5820000C, 0xCA800028, 0x00000000, 0x00000000, 0x5EA80000, 0x840001DA,
0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0x99005498, 0xC000491A, 0xC9400000,
0x00000000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0xC0004930, 0xCAC00000, 0xC0004932,
0xCA400000, 0xC7EC1120, 0xC0004930, 0xCEC00000, 0x5838000C, 0xCEC00000, 0x58000002, 0xCE400000,
0xC0004934, 0xCA000000, 0xC2400002, 0x6E642000, 0x6E642000, 0x76252000, 0x84000012, 0xC2400002,
0x6E684000, 0x58380008, 0xCE800208, 0xA6000000, 0x6E682000, 0x58380008, 0xCE800108, 0xC2400002,
0x6E642000, 0x76252000, 0x840000D2, 0x58380008, 0xCA000000, 0xC2800000, 0xC2400000, 0xA60200A0,
0xDBA80000, 0x6F386000, 0x4739C000, 0x5BB84C80, 0x58380004, 0xCA400080, 0x58380002, 0xCA800080,
0x00000000, 0xDEB80000, 0x46694000, 0x88000048, 0x00000000, 0xC0004824, 0xCA000000, 0xC2400002,
0x6E640000, 0x5A200002, 0xCE000000, 0x58380008, 0xCE400008, 0x80000000, 0x00000000, 0x80000030,
0xC0004934, 0xCA000000, 0x00000000, 0x00000000, 0xA6020C4A, 0x00000000, 0x00000000, 0x80000C80,
0xC2800000, 0xC2000200, 0xC240001A, 0xDF690050, 0x46A14000, 0x46694000, 0x8800FFBA, 0xC2000006,
0xC2600982, 0x5A643B6E, 0x5838000A, 0xCA800000, 0xC0001006, 0xCE000000, 0xC0001008, 0xCE400000,
0xC000100A, 0xCE800000, 0x99005370, 0xC1A0FFFE, 0xC0000824, 0xC9840068, 0xC2000000, 0xC0004930,
0xCA02E010, 0x58380026, 0xCA400000, 0x00000000, 0xC2800000, 0x990053B0, 0xDA980000, 0xC6140000,
0xC6580000, 0xC0004934, 0xCA000000, 0x00000000, 0x00000000, 0xA6020002, 0x00000000, 0x00000000,
0x80000300, 0xC0004938, 0xCBC00000, 0xC0004878, 0xC8040000, 0x6C908000, 0x44908000, 0x44908000,
0x40100000, 0xCA000000, 0xC4240000, 0x00000000, 0x58240018, 0xCA000000, 0x6FF88000, 0x6FD44000,
0x4395C000, 0x5BB84A00, 0xC3000000, 0xC3400002, 0xC2C00000, 0xC62C0080, 0xC6270040, 0xC0004940,
0xCE400040, 0xC6260040, 0xC0004942, 0xCE400040, 0xC000493C, 0xCA000000, 0x5EEC0000, 0x84000172,
0x5A6C0010, 0x46614000, 0x88000178, 0x5A600052, 0x466D4000, 0x88000160, 0x58380006, 0xCA800000,
0xC0004940, 0xCA000000, 0xC2400000, 0xC6A70040, 0x7E412000, 0x76252000, 0xC2000000, 0xC6A10040,
0x46610000, 0x84000120, 0xC0004942, 0xCA000000, 0xC2400000, 0xC6A60040, 0x7E412000, 0x76252000,
0xC2000000, 0xC6A00040, 0x58380002, 0xCA800000, 0x46610000, 0x840000D0, 0xC2400000, 0xC6A60080,
0x46E50000, 0x880000C2, 0xC2400000, 0xC6A40080, 0x58380008, 0xCA800000, 0x466D0000, 0x880000A2,
0x00000000, 0xA682FFF8, 0x00000000, 0xC7700B08, 0xA6840078, 0x00000000, 0xC7700A08, 0x80000068,
0xC7700208, 0xC000493C, 0xCAC00000, 0x80000048, 0xC7700308, 0xC000493C, 0xCAC00000, 0x80000028,
0xC7700908, 0x80000018, 0xC7700808, 0x80000008, 0xC7700708, 0x8000FFF8, 0xC7700508, 0xC0004944,
0xCF000000, 0xC000493E, 0xCEC00000, 0xC0004938, 0xCA400000, 0xC000493C, 0xCB800000, 0xC000493E,
0xCB400000, 0xC3000000, 0x6E608000, 0x6E544000, 0x42150000, 0x5A204A00, 0x5AA00008, 0x58200004,
0xCB000080, 0xC0004934, 0xCA000000, 0xC2400000, 0xC0004930, 0xCA42E010, 0xC3C00018, 0xA6020078,
0x00000000, 0x43656000, 0x46F90000, 0x88000038, 0x47AD6000, 0x6EE04010, 0x5BE00004, 0xC2000000,
0xC6E00010, 0x5E200000, 0x8400002A, 0x5BFC0002, 0x80000018, 0xC3C00004, 0x5A2C0008, 0x46390000,
0x8800FFFA, 0x5FB80008, 0x6FE04000, 0x42390000, 0x46312000, 0x88000050, 0xC2400000, 0xC0004930,
0xCA42E010, 0xC2060002, 0xC6800000, 0xCE000308, 0x6FE04000, 0x4631C000, 0x5F700010, 0x4675A000,
0xC2000000, 0xC6340010, 0xC25A000A, 0xC000491A, 0xCA401C20, 0xC2800000, 0xC0004932, 0xCA8000E0,
0xC0004862, 0xCA400068, 0x6FA04010, 0x42290000, 0xC000491E, 0xCE000000, 0xC7E41050, 0xC000491C,
0xCE400000, 0x6FE04000, 0x43A1C000, 0xC000493C, 0xCF800000, 0xC000493E, 0xCF400000, 0xC000493A,
0xCFC00000, 0x8000FFF0, 0x00000000, 0x00000000, 0x00000000, 0xC2000000, 0xDCE00000, 0xA622FFB8,
0xC1220002, 0xD90C0000, 0xC0004938, 0xCBC00000, 0xC0004944, 0xCB400000, 0xC0004862, 0xCB000000,
0xC0004934, 0xCA000000, 0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB84A00, 0xA6020248, 0xC2400000,
0x58380008, 0xCA406008, 0xDFE80000, 0xC2218E08, 0x5A21BAF6, 0x46294000, 0x8400000A, 0xC2080002,
0x7235A000, 0x80000040, 0x5E640000, 0x8400000A, 0xC20C0002, 0x7235A000, 0x80000018, 0xC2000000,
0xC760E718, 0xC7604220, 0x5E200000, 0x8400025A, 0xC2200002, 0xC0004930, 0xCE001008, 0x990060A8,
0xC0004828, 0xC9400000, 0xC1800002, 0x58380000, 0xCA000000, 0x00000000, 0x00000000, 0xA6000112,
0xC0004940, 0xCA800000, 0xC0004942, 0xCA400000, 0xC7600080, 0xC6A01840, 0xC6601040, 0xC000493A,
0xCA400000, 0xC0004934, 0xCA800000, 0xC0007200, 0x40300000, 0x40240000, 0x5C000004, 0x5EC07400,
0x8800FFFA, 0x5C000200, 0xCE000000, 0x58000002, 0x5EC07400, 0x8800FFFA, 0x5C000200, 0xCE800000,
0xC000493E, 0xCA000000, 0xC2400000, 0x5838000C, 0xCE400000, 0x990060A8, 0xC0004830, 0xC9400000,
0xC6180000, 0xC0004930, 0xC6100080, 0xCD000080, 0x80000090, 0xC2400002, 0x58380008, 0xCE400008,
0xC0004944, 0xCF400000, 0x80000260, 0xC000493C, 0xCA400000, 0xDFE80000, 0x5A300018, 0xC0007200,
0x40200000, 0xCA000000, 0x58380008, 0xC6501080, 0xCD001080, 0x5838000A, 0xCE800000, 0x58380026,
0xCE000000, 0xC0004944, 0xCF400000, 0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0x80000020,
0x00000000, 0x990060A8, 0xC0004826, 0xC9400000, 0xC1800002, 0x8000FDC0, 0xC2000000, 0xC2400200,
0xDF600040, 0xB624FFCA, 0xC000491C, 0xCA400000, 0xC000491E, 0xCA800000, 0x99005930, 0xDA580000,
0xDA980001, 0x00000000, 0xC0004934, 0xCA000000, 0x00000000, 0xC2800000, 0xA6020140, 0xC2400004,
0xC2000200, 0xDF690050, 0x46A14000, 0x46694000, 0x8800FFC2, 0x00000000, 0xC000491A, 0xC9800000,
0xC0004862, 0xC9400000, 0x6D9C6000, 0x459CE000, 0x59DC4C80, 0x99005790, 0xD9580000, 0xD9980001,
0xD9D40000, 0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0xC2000000, 0xC2400200, 0xDF600040,
0xB624FFCA, 0xC000491C, 0xCA400000, 0xC000491E, 0xCA800000, 0x99005930, 0xDA580000, 0xDA980001,
0x00000000, 0x58380008, 0xCA400000, 0xC2000000, 0xCE000020, 0xC2A1FFFE, 0x5AA9FFFE, 0xCE001080,
0x5838000A, 0xCE800000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC0000838, 0xC2500002,
0xCE440808, 0xC0004848, 0xCB840000, 0xC2000000, 0xC000082C, 0xCA040030, 0x5FB80002, 0xC0004848,
0xCF840000, 0x58880002, 0xB608FFF8, 0x00000000, 0xC0800000, 0xC0004844, 0xCC840000, 0x00000000,
0xC121FFFE, 0x5911FE14, 0x15000000, 0x8000DEC0, 0xC2000000, 0xDF600040, 0x5E200080, 0x84000252,
0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000480C, 0xCA000000, 0xC0004910,
0xCA400000, 0xC000492C, 0xCA800000, 0xC0004968, 0xCAC00000, 0x00000000, 0xC121FFFE, 0x5911FE14,
0x15000000, 0x76610000, 0x76A10000, 0x762D6000, 0x840001AA, 0xC0004926, 0xCA400000, 0xC201FFFE,
0x762D6000, 0x5A640002, 0x6AE50010, 0x5F200000, 0x84000002, 0x6A250000, 0x8000FFF8, 0xC6E00000,
0x62014008, 0xC0004926, 0xCE800000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC0004968,
0xCA400000, 0xC2000002, 0x6A290000, 0x7E010000, 0x76252000, 0xCE400000, 0x00000000, 0xC121FFFE,
0x5911FE14, 0x15000000, 0x6EB4A000, 0x6E944000, 0x4575A000, 0x46B5A000, 0x5B744E20, 0x58340002,
0xC2000000, 0xCA0000E0, 0x5834002E, 0xC2400000, 0xCA400080, 0x6EB0A000, 0x6EBC4000, 0x47F18000,
0x46B18000, 0x5B300E4E, 0x5B300004, 0x6E642000, 0x4225E000, 0xC39A8024, 0xC7380068, 0xC6B81C20,
0x99005930, 0xDB980000, 0xDBD80001, 0x00000000, 0xC2000000, 0xDF600040, 0x5E200080, 0x8400028A,
0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000490E, 0xCA000000, 0xC000492A,
0xCA400000, 0xC000496A, 0xCB000000, 0xC0004956, 0xCAC00000, 0x00000000, 0xC121FFFE, 0x5911FE14,
0x15000000, 0x76318000, 0x76718000, 0x840001EA, 0xC201FFFE, 0x76318000, 0x5AEC0002, 0x6B2D0010,
0x5EA00000, 0x84000002, 0x6A2D0000, 0x8000FFF8, 0xC7200000, 0x62016008, 0xC0004956, 0xCEC00000,
0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000496A, 0xCA400000, 0xC2000002, 0x6A2D0000,
0x7E010000, 0x76252000, 0xCE400000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0x6EF4A000,
0x6ED44000, 0x4575A000, 0x46F5A000, 0x5B744E20, 0x5834000E, 0xC2000000, 0xCA0000E0, 0x58340008,
0xC2400000, 0xCA420080, 0x5834000C, 0xC2800000, 0xCA832018, 0x6E644010, 0x42250000, 0x4229E000,
0xC39A8008, 0x58340008, 0xCB809020, 0x58340008, 0xC2800000, 0xCA810018, 0x6EE0A000, 0x6EE44000,
0x46610000, 0x46E10000, 0x5A200008, 0x5A200E28, 0x42290000, 0xC6380068, 0xC6F81C20, 0x99005930,
0xDB980000, 0xDBD80001, 0x00000000, 0xC000495A, 0xC8400000, 0x00000000, 0xC3C00002, 0x7BC42000,
0xCC400000, 0xC0001A1C, 0xCA000000, 0xC2400008, 0x6A452000, 0x76610000, 0x8400D91A, 0xC0000A28,
0xC3800000, 0xCB840030, 0xC0000A14, 0xC3400000, 0xCB440030, 0xC0004880, 0xCB040000, 0xB7B4D8CA,
0x58041802, 0xCAC00000, 0xA7000018, 0x00000000, 0x00000000, 0xA6C8D898, 0xC2800000, 0xC6E80020,
0x80000030, 0xC2800000, 0xC7282020, 0xC000490E, 0xCA400000, 0x6BE9E000, 0x00000000, 0x77E52000,
0x8400D848, 0x6EA0A000, 0x6E944000, 0x45610000, 0x46A10000, 0x5A204E20, 0x5820000C, 0xCA000000,
0xC0004946, 0xCE800000, 0xA6220348, 0x00000000, 0xC2200060, 0xC0004948, 0xCE000010, 0xCE001040,
0xC240000A, 0xC000494A, 0xCE400000, 0xC2B60002, 0xC0004964, 0xCE801B08, 0x99005C00, 0xC00048A0,
0xC8840000, 0x00000000, 0xC0004946, 0xCBC00000, 0x00000000, 0x00000000, 0x6FF8A000, 0x6FD44000,
0x4579C000, 0x47F9C000, 0x5BB84E20, 0x990059C0, 0xDBD80000, 0xDB980001, 0x00000000, 0x99005708,
0xC000491C, 0xC1400000, 0xC9420050, 0xC000491C, 0x99005BB8, 0xC9400001, 0xC9800000, 0x00000000,
0x99005930, 0xD9580000, 0xD9980001, 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000,
0x990055F8, 0xDBD80000, 0xDB980001, 0xC7D80000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000,
0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20, 0x58380010, 0xCA000000, 0xC0004874,
0xC8040000, 0x6C908000, 0x44908000, 0x44908000, 0x40100000, 0xCA400000, 0xC4340000, 0x00000000,
0xC7400000, 0xCE000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000490E, 0xCA400000,
0xC2800002, 0x6ABD4000, 0x72A52000, 0xCE400000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000,
0x990060A8, 0xC0004836, 0xC9400000, 0xC1800002, 0x00000000, 0x00000000, 0x00000000, 0xA8E2FFC8,
0x00000000, 0xC1220002, 0xD90C0000, 0xC2000000, 0xC0000A14, 0xCA040030, 0xC0000A28, 0xC2500002,
0xCE440808, 0x58880002, 0xB608FFF8, 0xC00048A0, 0xC0800000, 0xCC840000, 0x8000D498, 0xC0004946,
0xCBC00000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000490E, 0xCA400000, 0xC2800002,
0x6ABD4000, 0x72A52000, 0xCE400000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0x6FF8A000,
0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20, 0x58380008, 0xCA000000, 0x5838000C, 0xCA400000,
0xC3400000, 0xC6340008, 0xC000494E, 0xCF400000, 0xC2800000, 0xC62A0080, 0xC3000000, 0xC6308020,
0x6F304000, 0x43298000, 0xC000493C, 0xCF000000, 0xC2C00000, 0xC66C0080, 0xC0004950, 0xCEC00000,
0xC2800000, 0xC66AE028, 0xC0004954, 0xCE800000, 0x5F740000, 0x84000188, 0x5E300028, 0x462D2000,
0x84000152, 0x462D2000, 0x8800011A, 0x5E300018, 0x462D2000, 0x88000012, 0x462D2000, 0x8400002A,
0x00000000, 0x800000A8, 0x00000000, 0x99005D40, 0xDBD80000, 0xDB980001, 0xC7800000, 0xC3400002,
0xC000494E, 0xCF400000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000490E, 0xCA400000,
0xC2800002, 0x6ABD4000, 0x7E814000, 0x76A52000, 0xCE400000, 0x00000000, 0xC121FFFE, 0x5911FE14,
0x15000000, 0xC2200060, 0xC0004948, 0xCE001040, 0xC2000000, 0xC000494C, 0xCE000000, 0x80000068,
0x00000000, 0x99005D40, 0xDBD80000, 0xDB980001, 0xC7800000, 0x99005F40, 0xDBD80000, 0xDB980001,
0xC7800000, 0xC2200058, 0xC0004948, 0xCE001040, 0xC2000002, 0xC000494C, 0xCE000000, 0xC2000006,
0xC0001006, 0xCE000000, 0x5838000A, 0xCA400000, 0xC2200982, 0x5A203B6E, 0xC0001008, 0xCE000000,
0xC000100A, 0xCE400000, 0xC0004954, 0xCA800000, 0xC200000C, 0xC000494A, 0xCE000000, 0xC0004948,
0xCE800010, 0xC2B60000, 0xC0004964, 0xCE800000, 0x99005C00, 0xC00048A0, 0xC8840000, 0x00000000,
0xC0004946, 0xCBC00000, 0xC000494C, 0xCA000000, 0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000,
0x5BB84E20, 0x5E200000, 0x840000E2, 0x00000000, 0x990059C0, 0xDBD80000, 0xDB980001, 0x00000000,
0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0xC000491C, 0x99005BB8, 0xC9400001, 0xC9800000,
0x00000000, 0x99005930, 0xD9580000, 0xD9980001, 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000,
0x00000000, 0x990055F8, 0xDBD80000, 0xDB980001, 0xC7D80000, 0x00000000, 0xC121FFFE, 0x5911FE14,
0x15000000, 0xC000493C, 0xCA800000, 0xC000494E, 0xCAC00000, 0xC3000018, 0xC3400006, 0x5E200000,
0x84000012, 0xC2800000, 0xC2C00000, 0xC300001E, 0xC3400000, 0xC6AC1080, 0xC72C0420, 0xC76C0818,
0x58380010, 0xCA800000, 0x58380008, 0xCEC00000, 0xC6280108, 0xC0004874, 0xC8040000, 0x6C908000,
0x44908000, 0x44908000, 0x40100000, 0xCB000000, 0xC4340000, 0x00000000, 0xC7400000, 0xCE800000,
0xC0004952, 0xCE800000, 0x00000000, 0x00000000, 0x00000000, 0xA8E2FFC8, 0x00000000, 0xC000494C,
0xCA000000, 0xC0004950, 0xCAC00000, 0x5E200000, 0x84000052, 0xDFE80000, 0x7E814000, 0x5834001A,
0xCE800000, 0x990060A8, 0xC0004834, 0xC9400000, 0xC1800002, 0x990060A8, 0xC0004838, 0xC9400000,
0xC6D80000, 0xC1220002, 0xD90C0000, 0x5E200000, 0x84000028, 0x5838002C, 0xCB000000, 0xDFE80000,
0x00000000, 0x58380014, 0xCF000000, 0x80000000, 0xC2A1FFFE, 0x5AA9FFFE, 0x5838000A, 0xCE800000,
0xC3000000, 0xC0000A14, 0xCB040030, 0xC2D00002, 0xC0000A28, 0xCEC40808, 0xC000494E, 0xCA800000,
0x58880002, 0xB4B0FFF8, 0xC00048A0, 0xC0800000, 0xCC840000, 0x5EA80000, 0x8400013A, 0x5E200000,
0x84000128, 0xC000493C, 0xCA800000, 0x00000000, 0x00000000, 0x5AA80060, 0xCE800000, 0x99005D40,
0xDBD80000, 0xDB980001, 0xC7800000, 0x99005F40, 0xDBD80000, 0xDB980001, 0xC7800000, 0xC0004952,
0xCAC00000, 0x58380000, 0xCA800000, 0xC30C0002, 0xC7F00020, 0xA6800078, 0x00000000, 0x00000000,
0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC0001800, 0xCA000000, 0x00000000, 0x00000000,
0xA60CFFCA, 0xC6F00508, 0xC6B0C408, 0xCF000000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000,
0x8000CB48, 0xDCBC0001, 0x5FFC0000, 0x8400003A, 0xC3800002, 0xDB880001, 0x5FFC0004, 0x8400C4B2,
0xC3800000, 0xDB880001, 0xC3CE0002, 0xC0000800, 0xCFC00708, 0xC3E1FFFE, 0x597DFFFE, 0x593DFE14,
0x94000001, 0x00000000, 0x00000000, 0x00000000, 0xC000487C, 0xC8040000, 0x00000000, 0x00000000,
0x40080000, 0xCBC00000, 0xC4380000, 0x00000000, 0xC000480E, 0xCA000000, 0xC0004858, 0xCB440000,
0x00000000, 0x00000000, 0x46350000, 0x88000098, 0x00000000, 0xA7C00028, 0xC0004854, 0xC1000002,
0xCD040000, 0xC11C0000, 0xC000082C, 0xCD040E08, 0x800000C0, 0x00000000, 0xA7D20118, 0x00000000,
0xC7E14048, 0xC2400000, 0xC6246030, 0xC200006A, 0x46610000, 0xC6240038, 0xC0000810, 0xCE440038,
0x8000FF58, 0xC2000000, 0xC0000808, 0xCA040018, 0xC11C0000, 0xC000082C, 0xCD040E08, 0x5A200002,
0x5E600010, 0x8400FFF8, 0xC2000000, 0xC0000808, 0xCE040018, 0xC3400000, 0x80000010, 0xC1200002,
0xC0000818, 0xCD041008, 0x5B740002, 0xC0004858, 0xCF440000, 0x99005348, 0xC0004848, 0xC9440000,
0xC1800000, 0xC11C0002, 0xC000082C, 0xCD040E08, 0x800005C8, 0x5B740002, 0xC0004858, 0xCF440000,
0xC7800000, 0xC13C0002, 0xCD001E08, 0xC0004848, 0xC9440000, 0xC1800000, 0xC000082C, 0xC9840030,
0x59540002, 0xC0004848, 0xCD440000, 0x58880002, 0xB4980540, 0x00000000, 0xC0800000, 0x80000530,
0xC000487C, 0xC8040000, 0x00000000, 0x00000000, 0x40080000, 0xCBC00000, 0xC4280000, 0x00000000,
0xA7C00110, 0xC000484C, 0xCA040000, 0xC2400000, 0xC0001AEC, 0xCA440020, 0x5A200002, 0xC000484C,
0xCE040000, 0xB624006A, 0xC6800000, 0xC13C0002, 0xCD001E08, 0xC0004848, 0xC9440000, 0xC1800000,
0xC000082C, 0xC9840030, 0x59540002, 0xC0004848, 0xCD440000, 0x58880002, 0xB4980430, 0x00000000,
0xC0800000, 0x80000420, 0xC0004854, 0xC1000004, 0xCD040000, 0xC0000820, 0xC2000002, 0xCE040000,
0xC2000000, 0xC000484C, 0xCE040000, 0xC0004858, 0xCE040000, 0x8000FF10, 0xC0004854, 0xC1000000,
0xCD040000, 0xC11C0000, 0xC000082C, 0xCD040E08, 0x99005348, 0xC0004848, 0xC9440000, 0xC1800000,
0xC1200000, 0xC0000818, 0xCD041008, 0xC11C0002, 0xC000082C, 0xCD040E08, 0xC2000000, 0xC000484C,
0xCE040000, 0x80000320, 0xC0001AC0, 0xCB840000, 0xC000487C, 0xC8040000, 0x00000000, 0x00000000,
0x40080000, 0xCBC00000, 0xC4280000, 0x00000000, 0xA780022A, 0x00000000, 0x00000000, 0xA7C001EA,
0x00000000, 0xC0001B00, 0xC2060006, 0xCE040310, 0xA7E801A2, 0x00000000, 0xC0004850, 0xCA040000,
0xC2400000, 0xC0001AEC, 0xCA448020, 0x5A200002, 0xC0004850, 0xCE040000, 0xB624008A, 0x00000000,
0xC6800000, 0xC13C0002, 0xCD001E08, 0xC0001ACC, 0xC2000002, 0xCE040008, 0xC0004848, 0xC9440000,
0xC1800000, 0xC000082C, 0xC9840030, 0x59540002, 0xC0004848, 0xCD440000, 0x58880002, 0xB49801A8,
0x00000000, 0xC0800000, 0x80000198, 0xC0004854, 0xC1000000, 0xCD040000, 0xC11C0000, 0xC000082C,
0xCD040E08, 0x99005348, 0xC0004848, 0xC9440000, 0xC1800000, 0xC2000000, 0xC0000820, 0xCE040000,
0xC1200000, 0xC0000818, 0xCD041008, 0xC11C0002, 0xC000082C, 0xCD040E08, 0xC0004850, 0xCE040000,
0xC2000002, 0xC0001ACC, 0xCE040010, 0x800000D0, 0xC2000002, 0xC0004850, 0xCE040000, 0x8000FE70,
0xC2000000, 0xC0004850, 0xCE040000, 0xA7E60012, 0x00000000, 0xC2000002, 0xC0001B00, 0xCE040008,
0x8000FE58, 0x00000000, 0xA7860032, 0x00000000, 0xC6800000, 0xC13C0002, 0xCD001E08, 0xC2020002,
0xC7E2A548, 0xC0001B00, 0xCE040000, 0x8000FE00, 0xC2040002, 0xC0001B00, 0xCE040208, 0x8000FDE0,
0xC2C80002, 0x6AC56000, 0xDACC0000, 0xC0004854, 0xCB440000, 0xC0004848, 0xCB840000, 0xC0000838,
0xC3C00000, 0xCBC40030, 0x5EF40004, 0x8400000A, 0xC3000000, 0xC0001ACC, 0xCF040108, 0x47BD8000,
0x84000012, 0x47BD8000, 0x88000018, 0xC1006E8C, 0x8000B908, 0xC0004840, 0xCC840000, 0x8000F6B8,
0xC0001AC0, 0xCAC40000, 0xC0004854, 0xCB440000, 0xA6C0FBD2, 0x00000000, 0x5EF40000, 0x8400F712,
0x5EF40002, 0x8400F9A2, 0x5EF40004, 0x8400FBA2, 0xC1006CE8, 0x8000B880, 0x00000000, 0xC0800000,
0xDF4B0040, 0xC0004900, 0xCB800000, 0xC2000000, 0xC000490A, 0xA78000B0, 0xCBC00000, 0xC1000000,
0xD9000001, 0xC1000002, 0xD90C0000, 0x6FF46000, 0x47F5A000, 0x5B744C80, 0xC2400000, 0x58340004,
0xCA400080, 0xC0004900, 0xCE000008, 0x5A640002, 0x58340004, 0xC6500080, 0xCD000080, 0xC0004914,
0xCA400000, 0xC2000002, 0x6A3D0000, 0x72252000, 0xCE400000, 0xC0000408, 0xCE000000, 0xA78200B8,
0xC0004908, 0xCBC00000, 0xC1000000, 0xD9000001, 0xC1000002, 0xD90C0000, 0x6FF4A000, 0x6FD44000,
0x4575A000, 0x47F5A000, 0x5B744E20, 0xC2800000, 0x58340006, 0xCA800080, 0xC2000000, 0xC0004900,
0xCE000108, 0x5EA80002, 0x58340006, 0xC6900080, 0xCD000080, 0x5A7C0020, 0xC2000002, 0x6A250000,
0xC0000408, 0xCE000000, 0xDCA80001, 0x5EA80000, 0x8400B6F0, 0x00000000, 0xA4800210, 0x00000000,
0xC3C00000, 0xC000140E, 0xCBC00020, 0xC3400000, 0xC2400000, 0x6FF86000, 0x47F9C000, 0x5BB84C80,
0x58380008, 0xCB400080, 0x58380006, 0xCA400080, 0x5F740002, 0x58380008, 0xC7500080, 0xCD000080,
0xC2000000, 0x58380004, 0xCA020080, 0xC3000000, 0x5838000C, 0xCB000028, 0x5A640002, 0x46250000,
0x8400FFF8, 0xC2400000, 0x58380006, 0xC6500080, 0xCD000080, 0xC2000000, 0x5838000A, 0xCA020080,
0x5B300002, 0x5838000C, 0xC7100028, 0xCD000028, 0xC2420020, 0x5A200004, 0x46612000, 0x8400FFF8,
0xC2000000, 0x5838000A, 0xC6101080, 0xCD001080, 0xC0004966, 0xCA400000, 0xC2000002, 0x6A3D0000,
0x72252000, 0xCE400000, 0x5F740000, 0x84000028, 0xC0004912, 0xCA000000, 0xC2C00002, 0x6AFD6000,
0x7EC16000, 0x76E10000, 0xCE000000, 0x5F300020, 0x84000028, 0xC0004924, 0xCA000000, 0xC2C00002,
0x6AFD6000, 0x7EC16000, 0x76E10000, 0xCE000000, 0xA4820050, 0xC2400000, 0xC000140E, 0xCA408020,
0xC2000002, 0xC0004900, 0xCE000008, 0xC000490A, 0xCE400000, 0xC1000000, 0xD9000001, 0xD8400080,
0xC1000004, 0xD9000001, 0xA4840288, 0x00000000, 0xC3C00000, 0xC000140E, 0xCBC10020, 0xC2800000,
0xC2000000, 0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20, 0x5838002E, 0xCA800080,
0x58380006, 0xCA020080, 0xC3400000, 0x5838002E, 0xCB420080, 0x5AA80002, 0x46290000, 0x8400FFF8,
0xC2800000, 0x5838002E, 0xC6900080, 0xCD000080, 0x5F740002, 0x5838002E, 0xC7501080, 0xCD001080,
0xC0004968, 0xCA400000, 0xC2000002, 0x6A3D0000, 0x72252000, 0xCE400000, 0xC000492A, 0xCA800000,
0x5E740000, 0x84000028, 0xC0004910, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x76E10000,
0xCE000000, 0x6ABD4010, 0xA68000D2, 0x00000000, 0xC0004910, 0xCA000000, 0xC2C00002, 0x6AFD6000,
0x7EC16000, 0x76E10000, 0xCE000000, 0x58380032, 0xCA000000, 0x58000002, 0xCA400000, 0x5838000C,
0x00000000, 0xCE000001, 0xCE400000, 0xC000492A, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x72E10000,
0xCE000000, 0xC000492C, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x72E10000, 0xCE000000, 0x80000028,
0xC000492C, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x76E10000, 0xCE000000, 0xA4880100,
0xC2C00000, 0xC000140E, 0xCAC20020, 0xC000490E, 0xCA400000, 0xC2000002, 0x6A2D0000, 0x7E010000,
0x76252000, 0xCE400000, 0xC000496A, 0xCA400000, 0xC2000002, 0x6A2D0000, 0x72252000, 0xCE400000,
0x6EF0A000, 0x6ED44000, 0x45718000, 0x46F18000, 0x5B304E20, 0x58300000, 0xCA000000, 0x00000000,
0xC2400002, 0x76252000, 0x84000032, 0xC24C0002, 0xC6E40020, 0xC624C408, 0x58300010, 0xCA400508,
0x00000000, 0xC0001800, 0xCE400000, 0xA4860050, 0xC2400000, 0xC000140E, 0xCA418020, 0xC2020002,
0xC0004900, 0xCE000108, 0xC0004908, 0xCE400000, 0xC1000000, 0xD9000001, 0xD8400080, 0xC1000004,
0xD9000001, 0xC0001408, 0xCC800000, 0xC10E0002, 0xD90C0000, 0x8000EDA8, 0xDFBC0001, 0xC000496E,
0x99006050, 0xC9400000, 0xC7D80000, 0x00000000, 0xC5700000, 0x5EF00020, 0x88000130, 0x6F346000,
0x4735A000, 0x5B744C80, 0x58340008, 0xC2400000, 0xCA400080, 0x00000000, 0xC2000000, 0x5A640002,
0xCE400080, 0x58340004, 0xCA000080, 0x00000000, 0x00000000, 0x5E200002, 0xCE000080, 0xC0004912,
0xCA800000, 0xC2400002, 0x6A712000, 0x72694000, 0xCE800000, 0x5E200000, 0x8400003A, 0xC000480A,
0xCA000000, 0xC0000408, 0xCA800000, 0x76610000, 0x00000000, 0x72294000, 0xCE800000, 0x80000020,
0xC0004914, 0xCA000000, 0x7E412000, 0x00000000, 0x76610000, 0xCE000000, 0x800000B8, 0x6EF4A000,
0x6ED44000, 0x4575A000, 0x46F5A000, 0x5B744E20, 0x5834002E, 0xC2400000, 0xCA420080, 0x00000000,
0xC2000000, 0x5A640002, 0xC6501080, 0xCD001080, 0x58340006, 0xCA000080, 0x00000000, 0x00000000,
0x5A200002, 0xCE000080, 0xC0004910, 0xCA400000, 0xC2000002, 0x6A2D0000, 0x72252000, 0xCE400000,
0xC2000002, 0x6A310000, 0xC000042A, 0xCE000000, 0xC1040002, 0xD90C0000, 0x00000000, 0x8000EB18,
0x00000000, 0xC4980930, 0x9D000000, 0xC5580030, 0xC0000838, 0xCD840000, 0xC1440200, 0xC1C03200,
0xC55C1078, 0xC000100E, 0x9D000000, 0xCD800000, 0xC000100C, 0xCDC00000, 0xC0004862, 0xC9C00000,
0x00000000, 0x00000000, 0xD9D80001, 0xC0007200, 0x401C0000, 0x5DC07400, 0x8800FFFA, 0x5C000200,
0xCD800000, 0xC1F0000A, 0x71D4A000, 0xDD980000, 0xDD9C0001, 0x41D8E000, 0xC5D40268, 0xC0001010,
0xCD400000, 0x6C9C8000, 0x449CE000, 0x449CE000, 0x59DC0004, 0xC1601260, 0xC5D40268, 0x9D000000,
0xC0001012, 0xCD400000, 0x00000000, 0x00000000, 0xD9580000, 0x6D586000, 0x4558C000, 0x59984C80,
0xD9980001, 0x5818000A, 0xC1800000, 0xC9800080, 0xC0005400, 0x6D5CA000, 0x401C0000, 0x40180000,
0xC9400000, 0x58000002, 0x00000000, 0xC9C00000, 0xC0004930, 0xCD400000, 0xC0004932, 0xCDC00000,
0x59980004, 0xC1C20020, 0xB59CFFF8, 0x00000000, 0xC1800000, 0xDD9C0001, 0x581C000A, 0xCD800080,
0x581C000C, 0xC1800000, 0xC9800028, 0xC1C00002, 0xDD940000, 0x69D4E000, 0x5D980002, 0xCD800028,
0xC0004924, 0xC9800000, 0x00000000, 0x9D000000, 0x00000000, 0x71D8C000, 0xCD800000, 0xC000492A,
0xC9400000, 0xC1C00002, 0x69D8E000, 0x7DC0C000, 0x7594A000, 0xCD400000, 0xC000492C, 0xC9400000,
0xDD800001, 0x58000032, 0x75D4A000, 0x84000078, 0xC9400001, 0xC9800000, 0xDD800001, 0x5800000C,
0x00000000, 0xCD400001, 0xCD800000, 0xC000492C, 0xC9400000, 0xC000492A, 0xC9800000, 0x71D4A000,
0xC000492C, 0xCD400000, 0x71D8C000, 0xC000492A, 0xCD800000, 0x9D000000, 0x00000000, 0x00000000,
0x00000000, 0xC0004862, 0xC9800000, 0x00000000, 0xC1C00200, 0x4194C000, 0x45D8E000, 0x8800FFFA,
0xC5D80000, 0xC0004862, 0xCD800000, 0xC0001406, 0xC9800000, 0xC1C00002, 0x9D000000, 0xC5D80A08,
0xC5581050, 0xCD800000, 0xC0004930, 0xC9800000, 0xC0004932, 0xC9C00000, 0xC140000E, 0xC5581C20,
0xDD940000, 0xC0007200, 0x40140000, 0x5D407400, 0x8800FFFA, 0x5C000200, 0xCD800000, 0x58000002,
0x5D407400, 0x8800FFFA, 0x5C000200, 0xCDC00000, 0xDD540000, 0xC1C00000, 0x58140006, 0xC9C20080,
0xC1800000, 0x58140000, 0xC98000E0, 0x6DDC2000, 0xC000491E, 0x41D8E000, 0xCDC00000, 0xDD980000,
0xC1C00022, 0xC5D80D78, 0xDD940001, 0xC5581C20, 0xC000491C, 0xCD800000, 0xDD540000, 0xC1C00000,
0x58140006, 0xC9C20080, 0xC1800000, 0x58140004, 0xC9820080, 0x00000000, 0x59DC0002, 0x459CC000,
0x8400FFF8, 0xC1C00000, 0x9D000000, 0x58140006, 0xC5D81080, 0xCD801080, 0xC0004860, 0xC9400000,
0xC1800100, 0xC1D00002, 0x58146B00, 0xD5800000, 0x58000002, 0xD5800001, 0x59540004, 0xB558FFF8,
0xC0004860, 0xC1400000, 0xCD400000, 0xDD980001, 0x9D000000, 0xDD940000, 0xC0001404, 0xCDC00808,
0xC1C00000, 0xC1800200, 0x5D980004, 0xDF5D0050, 0x45D8A000, 0x8800FFDA, 0xDD800001, 0x5800000C,
0x00000000, 0xC9400001, 0xC9800000, 0xC1C00002, 0xC5D43F08, 0xC5D81E08, 0xC0004862, 0xC9C00000,
0x00000000, 0x00000000, 0x581C7200, 0x5DC07400, 0x8800FFFA, 0x5C000200, 0xCD400000, 0x58000002,
0x5DC07400, 0x8800FFFA, 0x5C000200, 0xCD800000, 0xC0004862, 0xC9C00000, 0x00000000, 0xC15004C0,
0xC5D40068, 0xDD9C0000, 0xC5D41C20, 0xC1C00000, 0xDD800001, 0x58000030, 0xC9C00080, 0xDD800001,
0x58000002, 0xC9800000, 0x6DDC2000, 0xC000491C, 0x41D8E000, 0xCD400001, 0xCDC00000, 0xDD940001,
0xC1C00000, 0x58140030, 0xC9C00080, 0xC1800000, 0x58140006, 0xC9820080, 0x00000000, 0x59DC0002,
0x459CC000, 0x8400FFF8, 0xC1C00000, 0x9D000000, 0x58140030, 0xC5D80080, 0xCD800080, 0xC1C00000,
0xDF5C0040, 0x5DDC0080, 0x8400FFD2, 0x00000000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000,
0xC160FFFE, 0xC0000A10, 0xC9440068, 0xC1A0FFFE, 0x59980E28, 0xC000100C, 0xCD400000, 0xC000100E,
0xCD800000, 0xC0004964, 0xC9800000, 0x00000000, 0xC170000A, 0x7194A000, 0x6C988000, 0x4498C000,
0x4498C000, 0x59980004, 0xC5940278, 0xC0001010, 0xCD400000, 0xC0004946, 0xC9400000, 0x00000000,
0x00000000, 0x6D58A000, 0x6D5C4000, 0x45D8C000, 0x4558C000, 0xC000494A, 0xC9400000, 0xC0004948,
0xC9C00000, 0x4194C000, 0xC1400012, 0xC55C1820, 0x9D000000, 0xC59C0270, 0xC0001012, 0xCDC00000,
0xC1400000, 0x58000012, 0xC9410040, 0xC0004950, 0xC9C00000, 0xC5580000, 0xC5940840, 0xC5581080,
0xD9940000, 0xC000493C, 0xC9400000, 0xC0004954, 0xC9800000, 0x59DC00A8, 0x455CE000, 0x41D8E000,
0x5D5C0030, 0x8800FFF8, 0xC1C00030, 0xC1800000, 0xC5D84030, 0xC1400000, 0xC5D40010, 0x5DD40002,
0x8400005A, 0x5DD40004, 0x84000082, 0x5DD40006, 0x840000AA, 0x5DD80026, 0x840000D2, 0xDD540000,
0xDD800001, 0x58000008, 0x40180000, 0xCD400000, 0x59980002, 0x8000FFA8, 0xDD540000, 0xDD800001,
0x58000008, 0x40180000, 0xCD4000C0, 0x59980002, 0x8000FF70, 0xDD540000, 0xDD800001, 0x58000008,
0x40180000, 0xCD400080, 0x59980002, 0x8000FF38, 0xDD540000, 0xDD800001, 0x58000008, 0x40180000,
0xCD400040, 0x59980002, 0x8000FF00, 0x00000000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000,
0x58000012, 0xC9400000, 0xC0004954, 0xC9C00000, 0xC0004950, 0xC9400080, 0xDD800001, 0x58000028,
0x5D9C0000, 0x8400003A, 0x5D9C0002, 0x8400003A, 0x5D9C0004, 0x84000052, 0xC55B0040, 0xC55C08C0,
0xCD800041, 0xCDC008C0, 0x80000048, 0xCD400000, 0x80000038, 0xC55900C0, 0xC55C1840, 0xCD8000C1,
0xCDC01840, 0x80000010, 0xC55A0080, 0xC55C1080, 0xCD800081, 0xCDC01080, 0x9D000000, 0x00000000,
0x00000000, 0x00000000, 0x59540002, 0x6994E018, 0x61C0C008, 0x4194A000, 0x5D940040, 0x8800FFFA,
0xC5940000, 0x9D000000, 0xCD400000, 0x00000000, 0x00000000, 0x9D000000, 0x4158A000, 0xCD400000,
0x00000000,
};
static unsigned int firmware_binary_data[] = {
};
#endif // IFXMIPS_ATM_FW_DANUBE_H

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#ifndef IFXMIPS_ATM_FW_REGS_COMMON_H
#define IFXMIPS_ATM_FW_REGS_COMMON_H
#if defined(CONFIG_DANUBE)
#include "ifxmips_atm_fw_regs_danube.h"
#elif defined(CONFIG_AMAZON_SE)
#include "ifxmips_atm_fw_regs_amazon_se.h"
#elif defined(CONFIG_AR9)
#include "ifxmips_atm_fw_regs_ar9.h"
#elif defined(CONFIG_VR9)
#include "ifxmips_atm_fw_regs_vr9.h"
#else
#error Platform is not specified!
#endif
/*
* PPE ATM Cell Header
*/
#if defined(__BIG_ENDIAN)
struct uni_cell_header {
unsigned int gfc :4;
unsigned int vpi :8;
unsigned int vci :16;
unsigned int pti :3;
unsigned int clp :1;
};
#else
struct uni_cell_header {
unsigned int clp :1;
unsigned int pti :3;
unsigned int vci :16;
unsigned int vpi :8;
unsigned int gfc :4;
};
#endif // defined(__BIG_ENDIAN)
/*
* Inband Header and Trailer
*/
#if defined(__BIG_ENDIAN)
struct rx_inband_trailer {
/* 0 - 3h */
unsigned int uu :8;
unsigned int cpi :8;
unsigned int stw_res1:4;
unsigned int stw_clp :1;
unsigned int stw_ec :1;
unsigned int stw_uu :1;
unsigned int stw_cpi :1;
unsigned int stw_ovz :1;
unsigned int stw_mfl :1;
unsigned int stw_usz :1;
unsigned int stw_crc :1;
unsigned int stw_il :1;
unsigned int stw_ra :1;
unsigned int stw_res2:2;
/* 4 - 7h */
unsigned int gfc :4;
unsigned int vpi :8;
unsigned int vci :16;
unsigned int pti :3;
unsigned int clp :1;
};
struct tx_inband_header {
/* 0 - 3h */
unsigned int gfc :4;
unsigned int vpi :8;
unsigned int vci :16;
unsigned int pti :3;
unsigned int clp :1;
/* 4 - 7h */
unsigned int uu :8;
unsigned int cpi :8;
unsigned int pad :8;
unsigned int res1 :8;
};
#else
struct rx_inband_trailer {
/* 0 - 3h */
unsigned int stw_res2:2;
unsigned int stw_ra :1;
unsigned int stw_il :1;
unsigned int stw_crc :1;
unsigned int stw_usz :1;
unsigned int stw_mfl :1;
unsigned int stw_ovz :1;
unsigned int stw_cpi :1;
unsigned int stw_uu :1;
unsigned int stw_ec :1;
unsigned int stw_clp :1;
unsigned int stw_res1:4;
unsigned int cpi :8;
unsigned int uu :8;
/* 4 - 7h */
unsigned int clp :1;
unsigned int pti :3;
unsigned int vci :16;
unsigned int vpi :8;
unsigned int gfc :4;
};
struct tx_inband_header {
/* 0 - 3h */
unsigned int clp :1;
unsigned int pti :3;
unsigned int vci :16;
unsigned int vpi :8;
unsigned int gfc :4;
/* 4 - 7h */
unsigned int res1 :8;
unsigned int pad :8;
unsigned int cpi :8;
unsigned int uu :8;
};
#endif // defined(__BIG_ENDIAN)
/*
* MIB Table Maintained by Firmware
*/
struct wan_mib_table {
u32 res1;
u32 wrx_drophtu_cell;
u32 wrx_dropdes_pdu;
u32 wrx_correct_pdu;
u32 wrx_err_pdu;
u32 wrx_dropdes_cell;
u32 wrx_correct_cell;
u32 wrx_err_cell;
u32 wrx_total_byte;
u32 res2;
u32 wtx_total_pdu;
u32 wtx_total_cell;
u32 wtx_total_byte;
};
/*
* Host-PPE Communication Data Structure
*/
#if defined(__BIG_ENDIAN)
struct wrx_queue_config {
/* 0h */
unsigned int res2 :27;
unsigned int dmach :4;
unsigned int errdp :1;
/* 1h */
unsigned int oversize :16;
unsigned int undersize :16;
/* 2h */
unsigned int res1 :16;
unsigned int mfs :16;
/* 3h */
unsigned int uumask :8;
unsigned int cpimask :8;
unsigned int uuexp :8;
unsigned int cpiexp :8;
};
struct wtx_port_config {
unsigned int res1 :27;
unsigned int qid :4;
unsigned int qsben :1;
};
struct wtx_queue_config {
unsigned int res1 :25;
unsigned int sbid :1;
unsigned int res2 :3;
unsigned int type :2;
unsigned int qsben :1;
};
struct wrx_dma_channel_config {
/* 0h */
unsigned int res1 :1;
unsigned int mode :2;
unsigned int rlcfg :1;
unsigned int desba :28;
/* 1h */
unsigned int chrl :16;
unsigned int clp1th :16;
/* 2h */
unsigned int deslen :16;
unsigned int vlddes :16;
};
struct wtx_dma_channel_config {
/* 0h */
unsigned int res2 :1;
unsigned int mode :2;
unsigned int res3 :1;
unsigned int desba :28;
/* 1h */
unsigned int res1 :32;
/* 2h */
unsigned int deslen :16;
unsigned int vlddes :16;
};
struct htu_entry {
unsigned int res1 :1;
unsigned int clp :1;
unsigned int pid :2;
unsigned int vpi :8;
unsigned int vci :16;
unsigned int pti :3;
unsigned int vld :1;
};
struct htu_mask {
unsigned int set :1;
unsigned int clp :1;
unsigned int pid_mask :2;
unsigned int vpi_mask :8;
unsigned int vci_mask :16;
unsigned int pti_mask :3;
unsigned int clear :1;
};
struct htu_result {
unsigned int res1 :12;
unsigned int cellid :4;
unsigned int res2 :5;
unsigned int type :1;
unsigned int ven :1;
unsigned int res3 :5;
unsigned int qid :4;
};
struct rx_descriptor {
/* 0 - 3h */
unsigned int own :1;
unsigned int c :1;
unsigned int sop :1;
unsigned int eop :1;
unsigned int res1 :3;
unsigned int byteoff :2;
unsigned int res2 :2;
unsigned int id :4;
unsigned int err :1;
unsigned int datalen :16;
/* 4 - 7h */
unsigned int res3 :4;
unsigned int dataptr :28;
};
struct tx_descriptor {
/* 0 - 3h */
unsigned int own :1;
unsigned int c :1;
unsigned int sop :1;
unsigned int eop :1;
unsigned int byteoff :5;
unsigned int res1 :5;
unsigned int iscell :1;
unsigned int clp :1;
unsigned int datalen :16;
/* 4 - 7h */
unsigned int res2 :4;
unsigned int dataptr :28;
};
#else
struct wrx_queue_config {
/* 0h */
unsigned int errdp :1;
unsigned int dmach :4;
unsigned int res2 :27;
/* 1h */
unsigned int undersize :16;
unsigned int oversize :16;
/* 2h */
unsigned int mfs :16;
unsigned int res1 :16;
/* 3h */
unsigned int cpiexp :8;
unsigned int uuexp :8;
unsigned int cpimask :8;
unsigned int uumask :8;
};
struct wtx_port_config {
unsigned int qsben :1;
unsigned int qid :4;
unsigned int res1 :27;
};
struct wtx_queue_config {
unsigned int qsben :1;
unsigned int type :2;
unsigned int res2 :3;
unsigned int sbid :1;
unsigned int res1 :25;
};
struct wrx_dma_channel_config
{
/* 0h */
unsigned int desba :28;
unsigned int rlcfg :1;
unsigned int mode :2;
unsigned int res1 :1;
/* 1h */
unsigned int clp1th :16;
unsigned int chrl :16;
/* 2h */
unsigned int vlddes :16;
unsigned int deslen :16;
};
struct wtx_dma_channel_config {
/* 0h */
unsigned int desba :28;
unsigned int res3 :1;
unsigned int mode :2;
unsigned int res2 :1;
/* 1h */
unsigned int res1 :32;
/* 2h */
unsigned int vlddes :16;
unsigned int deslen :16;
};
struct rx_descriptor {
/* 4 - 7h */
unsigned int dataptr :28;
unsigned int res3 :4;
/* 0 - 3h */
unsigned int datalen :16;
unsigned int err :1;
unsigned int id :4;
unsigned int res2 :2;
unsigned int byteoff :2;
unsigned int res1 :3;
unsigned int eop :1;
unsigned int sop :1;
unsigned int c :1;
unsigned int own :1;
};
struct tx_descriptor {
/* 4 - 7h */
unsigned int dataptr :28;
unsigned int res2 :4;
/* 0 - 3h */
unsigned int datalen :16;
unsigned int clp :1;
unsigned int iscell :1;
unsigned int res1 :5;
unsigned int byteoff :5;
unsigned int eop :1;
unsigned int sop :1;
unsigned int c :1;
unsigned int own :1;
};
#endif // defined(__BIG_ENDIAN)
#endif // IFXMIPS_ATM_FW_REGS_COMMON_H

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#ifndef IFXMIPS_ATM_FW_REGS_DANUBE_H
#define IFXMIPS_ATM_FW_REGS_DANUBE_H
/*
* Host-PPE Communication Data Address Mapping
*/
#define FW_VER_ID SB_BUFFER(0x2001)
#define CFG_WRX_HTUTS SB_BUFFER(0x2400) /* WAN RX HTU Table Size, must be configured before enable PPE firmware. */
#define CFG_WRX_QNUM SB_BUFFER(0x2401) /* WAN RX Queue Number */
#define CFG_WRX_DCHNUM SB_BUFFER(0x2402) /* WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware. */
#define CFG_WTX_DCHNUM SB_BUFFER(0x2403) /* WAN TX DMA Channel Number, no more than 16, must be configured before enable PPE firmware. */
#define CFG_WRDES_DELAY SB_BUFFER(0x2404) /* WAN Descriptor Write Delay, must be configured before enable PPE firmware. */
#define WRX_DMACH_ON SB_BUFFER(0x2405) /* WAN RX DMA Channel Enable, must be configured before enable PPE firmware. */
#define WTX_DMACH_ON SB_BUFFER(0x2406) /* WAN TX DMA Channel Enable, must be configured before enable PPE firmware. */
#define WRX_HUNT_BITTH SB_BUFFER(0x2407) /* WAN RX HUNT Threshold, must be between 2 to 8. */
#define WRX_QUEUE_CONFIG(i) ((struct wrx_queue_config*) SB_BUFFER(0x2500 + (i) * 20))
#define WRX_DMA_CHANNEL_CONFIG(i) ((struct wrx_dma_channel_config*) SB_BUFFER(0x2640 + (i) * 7))
#define WTX_PORT_CONFIG(i) ((struct wtx_port_config*) SB_BUFFER(0x2440 + (i)))
#define WTX_QUEUE_CONFIG(i) ((struct wtx_queue_config*) SB_BUFFER(0x2710 + (i) * 27))
#define WTX_DMA_CHANNEL_CONFIG(i) ((struct wtx_dma_channel_config*) SB_BUFFER(0x2711 + (i) * 27))
#define WAN_MIB_TABLE ((struct wan_mib_table*) SB_BUFFER(0x2410))
#define HTU_ENTRY(i) ((struct htu_entry*) SB_BUFFER(0x2000 + (i)))
#define HTU_MASK(i) ((struct htu_mask*) SB_BUFFER(0x2020 + (i)))
#define HTU_RESULT(i) ((struct htu_result*) SB_BUFFER(0x2040 + (i)))
#endif // IFXMIPS_ATM_FW_REGS_DANUBE_H

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#ifndef IFXMIPS_ATM_PPE_COMMON_H
#define IFXMIPS_ATM_PPE_COMMON_H
#if defined(CONFIG_LANTIQ)
#include "ifxmips_atm_ppe_danube.h"
#define CONFIG_DANUBE
#elif defined(CONFIG_DANUBE)
#include "ifxmips_atm_ppe_danube.h"
#elif defined(CONFIG_AMAZON_SE)
#include "ifxmips_atm_ppe_amazon_se.h"
#elif defined(CONFIG_AR9)
#include "ifxmips_atm_ppe_ar9.h"
#elif defined(CONFIG_VR9)
#include "ifxmips_atm_ppe_vr9.h"
#else
#error Platform is not specified!
#endif
/*
* Code/Data Memory (CDM) Interface Configuration Register
*/
#define CDM_CFG PPE_REG_ADDR(0x0100)
#define CDM_CFG_RAM1 GET_BITS(*CDM_CFG, 3, 2)
#define CDM_CFG_RAM0 (*CDM_CFG & (1 << 1))
#define CDM_CFG_RAM1_SET(value) SET_BITS(0, 3, 2, value)
#define CDM_CFG_RAM0_SET(value) ((value) ? (1 << 1) : 0)
/*
* QSB Internal Cell Delay Variation Register
*/
#define QSB_ICDV QSB_CONF_REG_ADDR(0x0007)
#define QSB_ICDV_TAU GET_BITS(*QSB_ICDV, 5, 0)
#define QSB_ICDV_TAU_SET(value) SET_BITS(0, 5, 0, value)
/*
* QSB Scheduler Burst Limit Register
*/
#define QSB_SBL QSB_CONF_REG_ADDR(0x0009)
#define QSB_SBL_SBL GET_BITS(*QSB_SBL, 3, 0)
#define QSB_SBL_SBL_SET(value) SET_BITS(0, 3, 0, value)
/*
* QSB Configuration Register
*/
#define QSB_CFG QSB_CONF_REG_ADDR(0x000A)
#define QSB_CFG_TSTEPC GET_BITS(*QSB_CFG, 1, 0)
#define QSB_CFG_TSTEPC_SET(value) SET_BITS(0, 1, 0, value)
/*
* QSB RAM Transfer Table Register
*/
#define QSB_RTM QSB_CONF_REG_ADDR(0x000B)
#define QSB_RTM_DM (*QSB_RTM)
#define QSB_RTM_DM_SET(value) ((value) & 0xFFFFFFFF)
/*
* QSB RAM Transfer Data Register
*/
#define QSB_RTD QSB_CONF_REG_ADDR(0x000C)
#define QSB_RTD_TTV (*QSB_RTD)
#define QSB_RTD_TTV_SET(value) ((value) & 0xFFFFFFFF)
/*
* QSB RAM Access Register
*/
#define QSB_RAMAC QSB_CONF_REG_ADDR(0x000D)
#define QSB_RAMAC_RW (*QSB_RAMAC & (1 << 31))
#define QSB_RAMAC_TSEL GET_BITS(*QSB_RAMAC, 27, 24)
#define QSB_RAMAC_LH (*QSB_RAMAC & (1 << 16))
#define QSB_RAMAC_TESEL GET_BITS(*QSB_RAMAC, 9, 0)
#define QSB_RAMAC_RW_SET(value) ((value) ? (1 << 31) : 0)
#define QSB_RAMAC_TSEL_SET(value) SET_BITS(0, 27, 24, value)
#define QSB_RAMAC_LH_SET(value) ((value) ? (1 << 16) : 0)
#define QSB_RAMAC_TESEL_SET(value) SET_BITS(0, 9, 0, value)
/*
* QSB Queue Scheduling and Shaping Definitions
*/
#define QSB_WFQ_NONUBR_MAX 0x3f00
#define QSB_WFQ_UBR_BYPASS 0x3fff
#define QSB_TP_TS_MAX 65472
#define QSB_TAUS_MAX 64512
#define QSB_GCR_MIN 18
/*
* QSB Constant
*/
#define QSB_RAMAC_RW_READ 0
#define QSB_RAMAC_RW_WRITE 1
#define QSB_RAMAC_TSEL_QPT 0x01
#define QSB_RAMAC_TSEL_SCT 0x02
#define QSB_RAMAC_TSEL_SPT 0x03
#define QSB_RAMAC_TSEL_VBR 0x08
#define QSB_RAMAC_LH_LOW 0
#define QSB_RAMAC_LH_HIGH 1
#define QSB_QPT_SET_MASK 0x0
#define QSB_QVPT_SET_MASK 0x0
#define QSB_SET_SCT_MASK 0x0
#define QSB_SET_SPT_MASK 0x0
#define QSB_SET_SPT_SBVALID_MASK 0x7FFFFFFF
#define QSB_SPT_SBV_VALID (1 << 31)
#define QSB_SPT_PN_SET(value) (((value) & 0x01) ? (1 << 16) : 0)
#define QSB_SPT_INTRATE_SET(value) SET_BITS(0, 13, 0, value)
/*
* QSB Queue Parameter Table Entry and Queue VBR Parameter Table Entry
*/
#if defined(__BIG_ENDIAN)
union qsb_queue_parameter_table {
struct {
unsigned int res1 :1;
unsigned int vbr :1;
unsigned int wfqf :14;
unsigned int tp :16;
} bit;
u32 dword;
};
union qsb_queue_vbr_parameter_table {
struct {
unsigned int taus :16;
unsigned int ts :16;
} bit;
u32 dword;
};
#else
union qsb_queue_parameter_table {
struct {
unsigned int tp :16;
unsigned int wfqf :14;
unsigned int vbr :1;
unsigned int res1 :1;
} bit;
u32 dword;
};
union qsb_queue_vbr_parameter_table {
struct {
unsigned int ts :16;
unsigned int taus :16;
} bit;
u32 dword;
};
#endif // defined(__BIG_ENDIAN)
/*
* Mailbox IGU0 Registers
*/
#define MBOX_IGU0_ISRS PPE_REG_ADDR(0x0200)
#define MBOX_IGU0_ISRC PPE_REG_ADDR(0x0201)
#define MBOX_IGU0_ISR PPE_REG_ADDR(0x0202)
#define MBOX_IGU0_IER PPE_REG_ADDR(0x0203)
#define MBOX_IGU0_ISRS_SET(n) (1 << (n))
#define MBOX_IGU0_ISRC_CLEAR(n) (1 << (n))
#define MBOX_IGU0_ISR_ISR(n) (*MBOX_IGU0_ISR & (1 << (n)))
#define MBOX_IGU0_IER_EN(n) (*MBOX_IGU0_IER & (1 << (n)))
#define MBOX_IGU0_IER_EN_SET(n) (1 << (n))
/*
* Mailbox IGU1 Registers
*/
#define MBOX_IGU1_ISRS PPE_REG_ADDR(0x0204)
#define MBOX_IGU1_ISRC PPE_REG_ADDR(0x0205)
#define MBOX_IGU1_ISR PPE_REG_ADDR(0x0206)
#define MBOX_IGU1_IER PPE_REG_ADDR(0x0207)
#define MBOX_IGU1_ISRS_SET(n) (1 << (n))
#define MBOX_IGU1_ISRC_CLEAR(n) (1 << (n))
#define MBOX_IGU1_ISR_ISR(n) (*MBOX_IGU1_ISR & (1 << (n)))
#define MBOX_IGU1_IER_EN(n) (*MBOX_IGU1_IER & (1 << (n)))
#define MBOX_IGU1_IER_EN_SET(n) (1 << (n))
/*
* Mailbox IGU3 Registers
*/
#define MBOX_IGU3_ISRS PPE_REG_ADDR(0x0214)
#define MBOX_IGU3_ISRC PPE_REG_ADDR(0x0215)
#define MBOX_IGU3_ISR PPE_REG_ADDR(0x0216)
#define MBOX_IGU3_IER PPE_REG_ADDR(0x0217)
#define MBOX_IGU3_ISRS_SET(n) (1 << (n))
#define MBOX_IGU3_ISRC_CLEAR(n) (1 << (n))
#define MBOX_IGU3_ISR_ISR(n) (*MBOX_IGU3_ISR & (1 << (n)))
#define MBOX_IGU3_IER_EN(n) (*MBOX_IGU3_IER & (1 << (n)))
#define MBOX_IGU3_IER_EN_SET(n) (1 << (n))
/*
* RTHA/TTHA Registers
*/
#define SFSM_STATE0 PPE_REG_ADDR(0x0410)
#define SFSM_STATE1 PPE_REG_ADDR(0x0411)
#define SFSM_DBA0 PPE_REG_ADDR(0x0412)
#define SFSM_DBA1 PPE_REG_ADDR(0x0413)
#define SFSM_CBA0 PPE_REG_ADDR(0x0414)
#define SFSM_CBA1 PPE_REG_ADDR(0x0415)
#define SFSM_CFG0 PPE_REG_ADDR(0x0416)
#define SFSM_CFG1 PPE_REG_ADDR(0x0417)
#define SFSM_PGCNT0 PPE_REG_ADDR(0x041C)
#define SFSM_PGCNT1 PPE_REG_ADDR(0x041D)
#define FFSM_DBA0 PPE_REG_ADDR(0x0508)
#define FFSM_DBA1 PPE_REG_ADDR(0x0509)
#define FFSM_CFG0 PPE_REG_ADDR(0x050A)
#define FFSM_CFG1 PPE_REG_ADDR(0x050B)
#define FFSM_IDLE_HEAD_BC0 PPE_REG_ADDR(0x050E)
#define FFSM_IDLE_HEAD_BC1 PPE_REG_ADDR(0x050F)
#define FFSM_PGCNT0 PPE_REG_ADDR(0x0514)
#define FFSM_PGCNT1 PPE_REG_ADDR(0x0515)
#endif // IFXMIPS_ATM_PPE_COMMON_H

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#ifndef IFXMIPS_ATM_PPE_DANUBE_H
#define IFXMIPS_ATM_PPE_DANUBE_H
#include <lantiq.h>
/*
* FPI Configuration Bus Register and Memory Address Mapping
*/
#define IFX_PPE (KSEG1 | 0x1E180000)
#define PP32_DEBUG_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0000) << 2)))
#define PPM_INT_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0030) << 2)))
#define PP32_INTERNAL_RES_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0040) << 2)))
#define CDM_CODE_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x1000) << 2)))
#define PPE_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x4000) << 2)))
#define CDM_DATA_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x5000) << 2)))
#define PPM_INT_UNIT_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6000) << 2)))
#define PPM_TIMER0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6100) << 2)))
#define PPM_TASK_IND_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6200) << 2)))
#define PPS_BRK_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6300) << 2)))
#define PPM_TIMER1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6400) << 2)))
#define SB_RAM0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8000) << 2)))
#define SB_RAM1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8400) << 2)))
#define SB_RAM2_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8C00) << 2)))
#define SB_RAM3_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x9600) << 2)))
#define QSB_CONF_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0xC000) << 2)))
/*
* DWORD-Length of Memory Blocks
*/
#define PP32_DEBUG_REG_DWLEN 0x0030
#define PPM_INT_REG_DWLEN 0x0010
#define PP32_INTERNAL_RES_DWLEN 0x00C0
#define CDM_CODE_MEMORYn_DWLEN(n) ((n) == 0 ? 0x1000 : 0x0800)
#define PPE_REG_DWLEN 0x1000
#define CDM_DATA_MEMORY_DWLEN CDM_CODE_MEMORYn_DWLEN(1)
#define PPM_INT_UNIT_DWLEN 0x0100
#define PPM_TIMER0_DWLEN 0x0100
#define PPM_TASK_IND_REG_DWLEN 0x0100
#define PPS_BRK_DWLEN 0x0100
#define PPM_TIMER1_DWLEN 0x0100
#define SB_RAM0_DWLEN 0x0400
#define SB_RAM1_DWLEN 0x0800
#define SB_RAM2_DWLEN 0x0A00
#define SB_RAM3_DWLEN 0x0400
#define QSB_CONF_REG_DWLEN 0x0100
/*
* PP32 to FPI Address Mapping
*/
#define SB_BUFFER(__sb_addr) ((volatile unsigned int *)((((__sb_addr) >= 0x2000) && ((__sb_addr) <= 0x23FF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2000) : \
(((__sb_addr) >= 0x2400) && ((__sb_addr) <= 0x2BFF)) ? SB_RAM1_ADDR((__sb_addr) - 0x2400) : \
(((__sb_addr) >= 0x2C00) && ((__sb_addr) <= 0x35FF)) ? SB_RAM2_ADDR((__sb_addr) - 0x2C00) : \
(((__sb_addr) >= 0x3600) && ((__sb_addr) <= 0x39FF)) ? SB_RAM3_ADDR((__sb_addr) - 0x3600) : \
0))
/*
* PP32 Debug Control Register
*/
#define PP32_DBG_CTRL PP32_DEBUG_REG_ADDR(0, 0x0000)
#define DBG_CTRL_START_SET(value) ((value) ? (1 << 0) : 0)
#define DBG_CTRL_STOP_SET(value) ((value) ? (1 << 1) : 0)
#define DBG_CTRL_STEP_SET(value) ((value) ? (1 << 2) : 0)
#define PP32_HALT_STAT PP32_DEBUG_REG_ADDR(0, 0x0001)
#define PP32_BRK_SRC PP32_DEBUG_REG_ADDR(0, 0x0002)
#define PP32_DBG_PC_MIN(i) PP32_DEBUG_REG_ADDR(0, 0x0010 + (i))
#define PP32_DBG_PC_MAX(i) PP32_DEBUG_REG_ADDR(0, 0x0014 + (i))
#define PP32_DBG_DATA_MIN(i) PP32_DEBUG_REG_ADDR(0, 0x0018 + (i))
#define PP32_DBG_DATA_MAX(i) PP32_DEBUG_REG_ADDR(0, 0x001A + (i))
#define PP32_DBG_DATA_VAL(i) PP32_DEBUG_REG_ADDR(0, 0x001C + (i))
#define PP32_DBG_CUR_PC PP32_DEBUG_REG_ADDR(0, 0x0080)
#define PP32_DBG_TASK_NO PP32_DEBUG_REG_ADDR(0, 0x0081)
/*
* EMA Registers
*/
#define EMA_CMDCFG PPE_REG_ADDR(0x0A00)
#define EMA_DATACFG PPE_REG_ADDR(0x0A01)
#define EMA_CMDCNT PPE_REG_ADDR(0x0A02)
#define EMA_DATACNT PPE_REG_ADDR(0x0A03)
#define EMA_ISR PPE_REG_ADDR(0x0A04)
#define EMA_IER PPE_REG_ADDR(0x0A05)
#define EMA_CFG PPE_REG_ADDR(0x0A06)
#define EMA_SUBID PPE_REG_ADDR(0x0A07)
#define EMA_ALIGNMENT 4
/*
* Mailbox IGU1 Interrupt
*/
#define PPE_MAILBOX_IGU1_INT LQ_PPE_MBOX_INT
#endif // IFXMIPS_ATM_PPE_DANUBE_H

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#ifndef _IFXMIPS_COMPAT_H__
#define _IFXMIPS_COMPAT_H__
#define IFX_SUCCESS 0
#define IFX_ERROR (-1)
#define ATM_VBR_NRT ATM_VBR
#define ATM_VBR_RT 6
#define ATM_UBR_PLUS 7
#define ATM_GFR 8
#define NUM_ENTITY(x) (sizeof(x) / sizeof(*(x)))
#define SET_BITS(x, msb, lsb, value) \
(((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
#define IFX_PMU_ENABLE 1
#define IFX_PMU_DISABLE 0
#define IFX_PMU_MODULE_DSL_DFE (1 << 9)
#define IFX_PMU_MODULE_AHBS (1 << 13)
#define IFX_PMU_MODULE_PPE_QSB (1 << 18)
#define IFX_PMU_MODULE_PPE_SLL01 (1 << 19)
#define IFX_PMU_MODULE_PPE_TC (1 << 21)
#define IFX_PMU_MODULE_PPE_EMA (1 << 22)
#define IFX_PMU_MODULE_PPE_TOP (1 << 29)
#define ifx_pmu_set(a,b) {if(a == IFX_PMU_ENABLE) lq_pmu_enable(b); else lq_pmu_disable(b);}
#define PPE_TOP_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_TOP, (__x))
#define PPE_SLL01_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_SLL01, (__x))
#define PPE_TC_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_TC, (__x))
#define PPE_EMA_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_EMA, (__x))
#define PPE_QSB_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_QSB, (__x))
#define PPE_TPE_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_AHBS, (__x))
#define DSL_DFE_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_DSL_DFE, (__x))
#define IFX_REG_W32(_v, _r) __raw_writel((_v), (_r))
#define CONFIG_IFXMIPS_DSL_CPE_MEI y
#endif

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/******************************************************************************
Copyright (c) 2009
Infineon Technologies AG
Am Campeon 1-12; 81726 Munich, Germany
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
#ifndef IFXMIPS_MEI_H
#define IFXMIPS_MEI_H
#define CONFIG_DANUBE 1
#if !defined(CONFIG_DANUBE) && !defined(CONFIG_AMAZON_SE) && !defined(CONFIG_AR9) && !defined(CONFIG_VR9)
#error Platform undefined!!!
#endif
#ifdef IFX_MEI_BSP
/** This is the character datatype. */
typedef char DSL_char_t;
/** This is the unsigned 8-bit datatype. */
typedef unsigned char DSL_uint8_t;
/** This is the signed 8-bit datatype. */
typedef signed char DSL_int8_t;
/** This is the unsigned 16-bit datatype. */
typedef unsigned short DSL_uint16_t;
/** This is the signed 16-bit datatype. */
typedef signed short DSL_int16_t;
/** This is the unsigned 32-bit datatype. */
typedef unsigned long DSL_uint32_t;
/** This is the signed 32-bit datatype. */
typedef signed long DSL_int32_t;
/** This is the float datatype. */
typedef float DSL_float_t;
/** This is the void datatype. */
typedef void DSL_void_t;
/** integer type, width is depending on processor arch */
typedef int DSL_int_t;
/** unsigned integer type, width is depending on processor arch */
typedef unsigned int DSL_uint_t;
typedef struct file DSL_DRV_file_t;
typedef struct inode DSL_DRV_inode_t;
/**
* Defines all possible CMV groups
* */
typedef enum {
DSL_CMV_GROUP_CNTL = 1,
DSL_CMV_GROUP_STAT = 2,
DSL_CMV_GROUP_INFO = 3,
DSL_CMV_GROUP_TEST = 4,
DSL_CMV_GROUP_OPTN = 5,
DSL_CMV_GROUP_RATE = 6,
DSL_CMV_GROUP_PLAM = 7,
DSL_CMV_GROUP_CNFG = 8
} DSL_CmvGroup_t;
/**
* Defines all opcode types
* */
typedef enum {
H2D_CMV_READ = 0x00,
H2D_CMV_WRITE = 0x04,
H2D_CMV_INDICATE_REPLY = 0x10,
H2D_ERROR_OPCODE_UNKNOWN =0x20,
H2D_ERROR_CMV_UNKNOWN =0x30,
D2H_CMV_READ_REPLY =0x01,
D2H_CMV_WRITE_REPLY = 0x05,
D2H_CMV_INDICATE = 0x11,
D2H_ERROR_OPCODE_UNKNOWN = 0x21,
D2H_ERROR_CMV_UNKNOWN = 0x31,
D2H_ERROR_CMV_READ_NOT_AVAILABLE = 0x41,
D2H_ERROR_CMV_WRITE_ONLY = 0x51,
D2H_ERROR_CMV_READ_ONLY = 0x61,
H2D_DEBUG_READ_DM = 0x02,
H2D_DEBUG_READ_PM = 0x06,
H2D_DEBUG_WRITE_DM = 0x0a,
H2D_DEBUG_WRITE_PM = 0x0e,
D2H_DEBUG_READ_DM_REPLY = 0x03,
D2H_DEBUG_READ_FM_REPLY = 0x07,
D2H_DEBUG_WRITE_DM_REPLY = 0x0b,
D2H_DEBUG_WRITE_FM_REPLY = 0x0f,
D2H_ERROR_ADDR_UNKNOWN = 0x33,
D2H_AUTONOMOUS_MODEM_READY_MSG = 0xf1
} DSL_CmvOpcode_t;
/* mutex macros */
#define MEI_MUTEX_INIT(id,flag) \
sema_init(&id,flag)
#define MEI_MUTEX_LOCK(id) \
down_interruptible(&id)
#define MEI_MUTEX_UNLOCK(id) \
up(&id)
#define MEI_WAIT(ms) \
{\
set_current_state(TASK_INTERRUPTIBLE);\
schedule_timeout(ms);\
}
#define MEI_INIT_WAKELIST(name,queue) \
init_waitqueue_head(&queue)
/* wait for an event, timeout is measured in ms */
#define MEI_WAIT_EVENT_TIMEOUT(ev,timeout)\
interruptible_sleep_on_timeout(&ev,timeout * HZ / 1000)
#define MEI_WAKEUP_EVENT(ev)\
wake_up_interruptible(&ev)
#endif /* IFX_MEI_BSP */
/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/
#define ME_DX_DATA (0x0000)
#define ME_VERSION (0x0004)
#define ME_ARC_GP_STAT (0x0008)
#define ME_DX_STAT (0x000C)
#define ME_DX_AD (0x0010)
#define ME_DX_MWS (0x0014)
#define ME_ME2ARC_INT (0x0018)
#define ME_ARC2ME_STAT (0x001C)
#define ME_ARC2ME_MASK (0x0020)
#define ME_DBG_WR_AD (0x0024)
#define ME_DBG_RD_AD (0x0028)
#define ME_DBG_DATA (0x002C)
#define ME_DBG_DECODE (0x0030)
#define ME_CONFIG (0x0034)
#define ME_RST_CTRL (0x0038)
#define ME_DBG_MASTER (0x003C)
#define ME_CLK_CTRL (0x0040)
#define ME_BIST_CTRL (0x0044)
#define ME_BIST_STAT (0x0048)
#define ME_XDATA_BASE_SH (0x004c)
#define ME_XDATA_BASE (0x0050)
#define ME_XMEM_BAR_BASE (0x0054)
#define ME_XMEM_BAR0 (0x0054)
#define ME_XMEM_BAR1 (0x0058)
#define ME_XMEM_BAR2 (0x005C)
#define ME_XMEM_BAR3 (0x0060)
#define ME_XMEM_BAR4 (0x0064)
#define ME_XMEM_BAR5 (0x0068)
#define ME_XMEM_BAR6 (0x006C)
#define ME_XMEM_BAR7 (0x0070)
#define ME_XMEM_BAR8 (0x0074)
#define ME_XMEM_BAR9 (0x0078)
#define ME_XMEM_BAR10 (0x007C)
#define ME_XMEM_BAR11 (0x0080)
#define ME_XMEM_BAR12 (0x0084)
#define ME_XMEM_BAR13 (0x0088)
#define ME_XMEM_BAR14 (0x008C)
#define ME_XMEM_BAR15 (0x0090)
#define ME_XMEM_BAR16 (0x0094)
#define WHILE_DELAY 20000
/*
** Define where in ME Processor's memory map the Stratify chip lives
*/
#define MAXSWAPSIZE (8 * 1024) //8k *(32bits)
// Mailboxes
#define MSG_LENGTH 16 // x16 bits
#define YES_REPLY 1
#define NO_REPLY 0
#define CMV_TIMEOUT 1000 //jiffies
// Block size per BAR
#define SDRAM_SEGMENT_SIZE (64*1024)
// Number of Bar registers
#define MAX_BAR_REGISTERS (17)
#define XDATA_REGISTER (15)
// ARC register addresss
#define ARC_STATUS 0x0
#define ARC_LP_START 0x2
#define ARC_LP_END 0x3
#define ARC_DEBUG 0x5
#define ARC_INT_MASK 0x10A
#define IRAM0_BASE (0x00000)
#define IRAM1_BASE (0x04000)
#if defined(CONFIG_DANUBE)
#define BRAM_BASE (0x0A000)
#elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9)
#define BRAM_BASE (0x08000)
#endif
#define XRAM_BASE (0x18000)
#define YRAM_BASE (0x1A000)
#define EXT_MEM_BASE (0x80000)
#define ARC_GPIO_CTRL (0xC030)
#define ARC_GPIO_DATA (0xC034)
#define IRAM0_SIZE (16*1024)
#define IRAM1_SIZE (16*1024)
#define BRAM_SIZE (12*1024)
#define XRAM_SIZE (8*1024)
#define YRAM_SIZE (8*1024)
#define EXT_MEM_SIZE (1536*1024)
#define ADSL_BASE (0x20000)
#define CRI_BASE (ADSL_BASE + 0x11F00)
#define CRI_CCR0 (CRI_BASE + 0x00)
#define CRI_RST (CRI_BASE + 0x04*4)
#define ADSL_DILV_BASE (ADSL_BASE+0x20000)
//
#define IRAM0_ADDR_BIT_MASK 0xFFF
#define IRAM1_ADDR_BIT_MASK 0xFFF
#define BRAM_ADDR_BIT_MASK 0xFFF
#define RX_DILV_ADDR_BIT_MASK 0x1FFF
/*** Bit definitions ***/
#define ARC_AUX_HALT (1 << 25)
#define ARC_DEBUG_HALT (1 << 1)
#define FALSE 0
#define TRUE 1
#define BIT0 (1<<0)
#define BIT1 (1<<1)
#define BIT2 (1<<2)
#define BIT3 (1<<3)
#define BIT4 (1<<4)
#define BIT5 (1<<5)
#define BIT6 (1<<6)
#define BIT7 (1<<7)
#define BIT8 (1<<8)
#define BIT9 (1<<9)
#define BIT10 (1<<10)
#define BIT11 (1<<11)
#define BIT12 (1<<12)
#define BIT13 (1<<13)
#define BIT14 (1<<14)
#define BIT15 (1<<15)
#define BIT16 (1<<16)
#define BIT17 (1<<17)
#define BIT18 (1<<18)
#define BIT19 (1<<19)
#define BIT20 (1<<20)
#define BIT21 (1<<21)
#define BIT22 (1<<22)
#define BIT23 (1<<23)
#define BIT24 (1<<24)
#define BIT25 (1<<25)
#define BIT26 (1<<26)
#define BIT27 (1<<27)
#define BIT28 (1<<28)
#define BIT29 (1<<29)
#define BIT30 (1<<30)
#define BIT31 (1<<31)
// CRI_CCR0 Register definitions
#define CLK_2M_MODE_ENABLE BIT6
#define ACL_CLK_MODE_ENABLE BIT4
#define FDF_CLK_MODE_ENABLE BIT2
#define STM_CLK_MODE_ENABLE BIT0
// CRI_RST Register definitions
#define FDF_SRST BIT3
#define MTE_SRST BIT2
#define FCI_SRST BIT1
#define AAI_SRST BIT0
// MEI_TO_ARC_INTERRUPT Register definitions
#define MEI_TO_ARC_INT1 BIT3
#define MEI_TO_ARC_INT0 BIT2
#define MEI_TO_ARC_CS_DONE BIT1 //need to check
#define MEI_TO_ARC_MSGAV BIT0
// ARC_TO_MEI_INTERRUPT Register definitions
#define ARC_TO_MEI_INT1 BIT8
#define ARC_TO_MEI_INT0 BIT7
#define ARC_TO_MEI_CS_REQ BIT6
#define ARC_TO_MEI_DBG_DONE BIT5
#define ARC_TO_MEI_MSGACK BIT4
#define ARC_TO_MEI_NO_ACCESS BIT3
#define ARC_TO_MEI_CHECK_AAITX BIT2
#define ARC_TO_MEI_CHECK_AAIRX BIT1
#define ARC_TO_MEI_MSGAV BIT0
// ARC_TO_MEI_INTERRUPT_MASK Register definitions
#define GP_INT1_EN BIT8
#define GP_INT0_EN BIT7
#define CS_REQ_EN BIT6
#define DBG_DONE_EN BIT5
#define MSGACK_EN BIT4
#define NO_ACC_EN BIT3
#define AAITX_EN BIT2
#define AAIRX_EN BIT1
#define MSGAV_EN BIT0
#define MEI_SOFT_RESET BIT0
#define HOST_MSTR BIT0
#define JTAG_MASTER_MODE 0x0
#define MEI_MASTER_MODE HOST_MSTR
// MEI_DEBUG_DECODE Register definitions
#define MEI_DEBUG_DEC_MASK (0x3)
#define MEI_DEBUG_DEC_AUX_MASK (0x0)
#define ME_DBG_DECODE_DMP1_MASK (0x1)
#define MEI_DEBUG_DEC_DMP2_MASK (0x2)
#define MEI_DEBUG_DEC_CORE_MASK (0x3)
#define AUX_STATUS (0x0)
#define AUX_ARC_GPIO_CTRL (0x10C)
#define AUX_ARC_GPIO_DATA (0x10D)
// ARC_TO_MEI_MAILBOX[11] is a special location used to indicate
// page swap requests.
#if defined(CONFIG_DANUBE)
#define OMBOX_BASE 0xDF80
#define ARC_TO_MEI_MAILBOX 0xDFA0
#define IMBOX_BASE 0xDFC0
#define MEI_TO_ARC_MAILBOX 0xDFD0
#elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9)
#define OMBOX_BASE 0xAF80
#define ARC_TO_MEI_MAILBOX 0xAFA0
#define IMBOX_BASE 0xAFC0
#define MEI_TO_ARC_MAILBOX 0xAFD0
#endif
#define MEI_TO_ARC_MAILBOXR (MEI_TO_ARC_MAILBOX + 0x2C)
#define ARC_MEI_MAILBOXR (ARC_TO_MEI_MAILBOX + 0x2C)
#define OMBOX1 (OMBOX_BASE+0x4)
// Codeswap request messages are indicated by setting BIT31
#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK (0x80000000)
// Clear Eoc messages received are indicated by setting BIT17
#define OMB_CLEAREOC_INTERRUPT_CODE (0x00020000)
#define OMB_REBOOT_INTERRUPT_CODE (1 << 18)
/*
** Swap page header
*/
// Page must be loaded at boot time if size field has BIT31 set
#define BOOT_FLAG (BIT31)
#define BOOT_FLAG_MASK ~BOOT_FLAG
#define FREE_RELOAD 1
#define FREE_SHOWTIME 2
#define FREE_ALL 3
// marcos
#define IFX_MEI_WRITE_REGISTER_L(data,addr) *((volatile u32*)(addr)) = (u32)(data)
#define IFX_MEI_READ_REGISTER_L(addr) (*((volatile u32*)(addr)))
#define SET_BIT(reg, mask) reg |= (mask)
#define CLEAR_BIT(reg, mask) reg &= (~mask)
#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
//#define SET_BITS(reg, mask) SET_BIT(reg, mask)
#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
#define ALIGN_SIZE ( 1L<<10 ) //1K size align
#define MEM_ALIGN(addr) (((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) )
// swap marco
#define MEI_HALF_WORD_SWAP(data) {data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);}
#define MEI_BYTE_SWAP(data) {data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);}
#ifdef CONFIG_PROC_FS
typedef struct reg_entry
{
int *flag;
char name[30]; /* big enough to hold names */
char description[100]; /* big enough to hold description */
unsigned short low_ino;
} reg_entry_t;
#endif
// Swap page header describes size in 32-bit words, load location, and image offset
// for program and/or data segments
typedef struct _arc_swp_page_hdr {
u32 p_offset; //Offset bytes of progseg from beginning of image
u32 p_dest; //Destination addr of progseg on processor
u32 p_size; //Size in 32-bitwords of program segment
u32 d_offset; //Offset bytes of dataseg from beginning of image
u32 d_dest; //Destination addr of dataseg on processor
u32 d_size; //Size in 32-bitwords of data segment
} ARC_SWP_PAGE_HDR;
/*
** Swap image header
*/
#define GET_PROG 0 // Flag used for program mem segment
#define GET_DATA 1 // Flag used for data mem segment
// Image header contains size of image, checksum for image, and count of
// page headers. Following that are 'count' page headers followed by
// the code and/or data segments to be loaded
typedef struct _arc_img_hdr {
u32 size; // Size of binary image in bytes
u32 checksum; // Checksum for image
u32 count; // Count of swp pages in image
ARC_SWP_PAGE_HDR page[1]; // Should be "count" pages - '1' to make compiler happy
} ARC_IMG_HDR;
typedef struct smmu_mem_info {
int type;
int boot;
unsigned long nCopy;
unsigned long size;
unsigned char *address;
unsigned char *org_address;
} smmu_mem_info_t;
#ifdef __KERNEL__
typedef struct ifx_mei_device_private {
int modem_ready;
int arcmsgav;
int cmv_reply;
int cmv_waiting;
// Mei to ARC CMV count, reply count, ARC Indicator count
int modem_ready_cnt;
int cmv_count;
int reply_count;
unsigned long image_size;
int nBar;
u16 Recent_indicator[MSG_LENGTH];
u16 CMV_RxMsg[MSG_LENGTH] __attribute__ ((aligned (4)));
smmu_mem_info_t adsl_mem_info[MAX_BAR_REGISTERS];
ARC_IMG_HDR *img_hdr;
// to wait for arc cmv reply, sleep on wait_queue_arcmsgav;
wait_queue_head_t wait_queue_arcmsgav;
wait_queue_head_t wait_queue_modemready;
struct semaphore mei_cmv_sema;
} ifx_mei_device_private_t;
#endif
typedef struct winhost_message {
union {
u16 RxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));
u16 TxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));
} msg;
} DSL_DEV_WinHost_Message_t;
/********************************************************************************************************
* DSL CPE API Driver Stack Interface Definitions
* *****************************************************************************************************/
/** IOCTL codes for bsp driver */
#define DSL_IOC_MEI_BSP_MAGIC 's'
#define DSL_FIO_BSP_DSL_START _IO (DSL_IOC_MEI_BSP_MAGIC, 0)
#define DSL_FIO_BSP_RUN _IO (DSL_IOC_MEI_BSP_MAGIC, 1)
#define DSL_FIO_BSP_FREE_RESOURCE _IO (DSL_IOC_MEI_BSP_MAGIC, 2)
#define DSL_FIO_BSP_RESET _IO (DSL_IOC_MEI_BSP_MAGIC, 3)
#define DSL_FIO_BSP_REBOOT _IO (DSL_IOC_MEI_BSP_MAGIC, 4)
#define DSL_FIO_BSP_HALT _IO (DSL_IOC_MEI_BSP_MAGIC, 5)
#define DSL_FIO_BSP_BOOTDOWNLOAD _IO (DSL_IOC_MEI_BSP_MAGIC, 6)
#define DSL_FIO_BSP_JTAG_ENABLE _IO (DSL_IOC_MEI_BSP_MAGIC, 7)
#define DSL_FIO_FREE_RESOURCE _IO (DSL_IOC_MEI_BSP_MAGIC, 8)
#define DSL_FIO_ARC_MUX_TEST _IO (DSL_IOC_MEI_BSP_MAGIC, 9)
#define DSL_FIO_BSP_REMOTE _IOW (DSL_IOC_MEI_BSP_MAGIC, 10, u32)
#define DSL_FIO_BSP_GET_BASE_ADDRESS _IOR (DSL_IOC_MEI_BSP_MAGIC, 11, u32)
#define DSL_FIO_BSP_IS_MODEM_READY _IOR (DSL_IOC_MEI_BSP_MAGIC, 12, u32)
#define DSL_FIO_BSP_GET_VERSION _IOR (DSL_IOC_MEI_BSP_MAGIC, 13, DSL_DEV_Version_t)
#define DSL_FIO_BSP_CMV_WINHOST _IOWR(DSL_IOC_MEI_BSP_MAGIC, 14, DSL_DEV_WinHost_Message_t)
#define DSL_FIO_BSP_CMV_READ _IOWR(DSL_IOC_MEI_BSP_MAGIC, 15, DSL_DEV_MeiReg_t)
#define DSL_FIO_BSP_CMV_WRITE _IOW (DSL_IOC_MEI_BSP_MAGIC, 16, DSL_DEV_MeiReg_t)
#define DSL_FIO_BSP_DEBUG_READ _IOWR(DSL_IOC_MEI_BSP_MAGIC, 17, DSL_DEV_MeiDebug_t)
#define DSL_FIO_BSP_DEBUG_WRITE _IOWR(DSL_IOC_MEI_BSP_MAGIC, 18, DSL_DEV_MeiDebug_t)
#define DSL_FIO_BSP_GET_CHIP_INFO _IOR (DSL_IOC_MEI_BSP_MAGIC, 19, DSL_DEV_HwVersion_t)
#define DSL_DEV_MEIDEBUG_BUFFER_SIZES 512
typedef struct DSL_DEV_MeiDebug
{
DSL_uint32_t iAddress;
DSL_uint32_t iCount;
DSL_uint32_t buffer[DSL_DEV_MEIDEBUG_BUFFER_SIZES];
} DSL_DEV_MeiDebug_t; /* meidebug */
/**
* Structure is used for debug access only.
* Refer to configure option INCLUDE_ADSL_WINHOST_DEBUG */
typedef struct struct_meireg
{
/*
* Specifies that address for debug access */
unsigned long iAddress;
/*
* Specifies the pointer to the data that has to be written or returns a
* pointer to the data that has been read out*/
unsigned long iData;
} DSL_DEV_MeiReg_t; /* meireg */
typedef struct DSL_DEV_Device
{
DSL_int_t nInUse; /* modem state, update by bsp driver, */
DSL_void_t *pPriv;
DSL_uint32_t base_address; /* mei base address */
DSL_int_t nIrq[2]; /* irq number */
#define IFX_DFEIR 0
#define IFX_DYING_GASP 1
DSL_DEV_MeiDebug_t lop_debugwr; /* dying gasp */
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0))
struct module *owner;
#endif
} DSL_DEV_Device_t; /* ifx_adsl_device_t */
#define DSL_DEV_PRIVATE(dev) ((ifx_mei_device_private_t*)(dev->pPriv))
typedef struct DSL_DEV_Version /* ifx_adsl_bsp_version */
{
unsigned long major;
unsigned long minor;
unsigned long revision;
} DSL_DEV_Version_t; /* ifx_adsl_bsp_version_t */
typedef struct DSL_DEV_ChipInfo
{
unsigned long major;
unsigned long minor;
} DSL_DEV_HwVersion_t;
typedef struct
{
DSL_uint8_t dummy;
} DSL_DEV_DeviceConfig_t;
/** error code definitions */
typedef enum DSL_DEV_MeiError
{
DSL_DEV_MEI_ERR_SUCCESS = 0,
DSL_DEV_MEI_ERR_FAILURE = -1,
DSL_DEV_MEI_ERR_MAILBOX_FULL = -2,
DSL_DEV_MEI_ERR_MAILBOX_EMPTY = -3,
DSL_DEV_MEI_ERR_MAILBOX_TIMEOUT = -4
} DSL_DEV_MeiError_t; /* MEI_ERROR */
typedef enum {
DSL_BSP_MEMORY_READ=0,
DSL_BSP_MEMORY_WRITE,
} DSL_BSP_MemoryAccessType_t; /* ifx_adsl_memory_access_type_t */
typedef enum
{
DSL_LED_LINK_ID=0,
DSL_LED_DATA_ID
} DSL_DEV_LedId_t; /* ifx_adsl_led_id_t */
typedef enum
{
DSL_LED_LINK_TYPE=0,
DSL_LED_DATA_TYPE
} DSL_DEV_LedType_t; /* ifx_adsl_led_type_t */
typedef enum
{
DSL_LED_HD_CPU=0,
DSL_LED_HD_FW
} DSL_DEV_LedHandler_t; /* ifx_adsl_led_handler_t */
typedef enum {
DSL_LED_ON=0,
DSL_LED_OFF,
DSL_LED_FLASH,
} DSL_DEV_LedMode_t; /* ifx_adsl_led_mode_t */
typedef enum {
DSL_CPU_HALT=0,
DSL_CPU_RUN,
DSL_CPU_RESET,
} DSL_DEV_CpuMode_t; /* ifx_adsl_cpu_mode_t */
#if 0
typedef enum {
DSL_BSP_EVENT_DYING_GASP = 0,
DSL_BSP_EVENT_CEOC_IRQ,
} DSL_BSP_Event_id_t; /* ifx_adsl_event_id_t */
typedef union DSL_BSP_CB_Param
{
DSL_uint32_t nIrqMessage;
} DSL_BSP_CB_Param_t; /* ifx_adsl_cbparam_t */
typedef struct DSL_BSP_CB_Event
{
DSL_BSP_Event_id_t nID;
DSL_DEV_Device_t *pDev;
DSL_BSP_CB_Param_t *pParam;
} DSL_BSP_CB_Event_t; /* ifx_adsl_cb_event_t */
#endif
/* external functions (from the BSP Driver) */
extern DSL_DEV_Device_t* DSL_BSP_DriverHandleGet(int, int);
extern DSL_int_t DSL_BSP_DriverHandleDelete(DSL_DEV_Device_t *);
extern DSL_DEV_MeiError_t DSL_BSP_FWDownload(DSL_DEV_Device_t *, const DSL_char_t *, DSL_uint32_t, DSL_int32_t *, DSL_int32_t *);
extern int DSL_BSP_KernelIoctls(DSL_DEV_Device_t *, unsigned int, unsigned long);
extern DSL_DEV_MeiError_t DSL_BSP_SendCMV(DSL_DEV_Device_t *, DSL_uint16_t *, DSL_int_t, DSL_uint16_t *);
extern DSL_DEV_MeiError_t DSL_BSP_AdslLedInit(DSL_DEV_Device_t *, DSL_DEV_LedId_t, DSL_DEV_LedType_t, DSL_DEV_LedHandler_t);
extern DSL_DEV_MeiError_t DSL_BSP_Showtime(DSL_DEV_Device_t *, DSL_uint32_t, DSL_uint32_t);
extern int DSL_BSP_ATMLedCBRegister( int (*ifx_adsl_ledcallback)(void));
extern DSL_DEV_MeiError_t DSL_BSP_MemoryDebugAccess(DSL_DEV_Device_t *, DSL_BSP_MemoryAccessType_t, DSL_uint32_t, DSL_uint32_t *, DSL_uint32_t);
extern volatile DSL_DEV_Device_t *adsl_dev;
/**
* Dummy structure by now to show mechanism of extended data that will be
* provided within event callback itself.
* */
typedef struct
{
/**
* Dummy value */
DSL_uint32_t nDummy1;
} DSL_BSP_CB_Event1DataDummy_t;
/**
* Dummy structure by now to show mechanism of extended data that will be
* provided within event callback itself.
* */
typedef struct
{
/**
* Dummy value */
DSL_uint32_t nDummy2;
} DSL_BSP_CB_Event2DataDummy_t;
/**
* encapsulate all data structures that are necessary for status event
* callbacks.
* */
typedef union
{
DSL_BSP_CB_Event1DataDummy_t dataEvent1;
DSL_BSP_CB_Event2DataDummy_t dataEvent2;
} DSL_BSP_CB_DATA_Union_t;
typedef enum
{
/**
* Informs the upper layer driver (DSL CPE API) about a reboot request from the
* firmware.
* \note This event does NOT include any additional data.
* More detailed information upon reboot reason has to be requested from
* upper layer software via CMV (INFO 109) if necessary. */
DSL_BSP_CB_FIRST = 0,
DSL_BSP_CB_DYING_GASP,
DSL_BSP_CB_CEOC_IRQ,
DSL_BSP_CB_FIRMWARE_REBOOT,
/**
* Delimiter only */
DSL_BSP_CB_LAST
} DSL_BSP_CB_Type_t;
/**
* Specifies the common event type that has to be used for registering and
* signalling of interrupts/autonomous status events from MEI BSP Driver.
*
* \param pDev
* Context pointer from MEI BSP Driver.
*
* \param IFX_ADSL_BSP_CallbackType_t
* Specifies the event callback type (reason of callback). Regrading to the
* setting of this value the data which is included in the following union
* might have different meanings.
* Please refer to the description of the union to get information about the
* meaning of the included data.
*
* \param pData
* Data according to \ref DSL_BSP_CB_DATA_Union_t.
* If this pointer is NULL there is no additional data available.
*
* \return depending on event
*/
typedef int (*DSL_BSP_EventCallback_t)
(
DSL_DEV_Device_t *pDev,
DSL_BSP_CB_Type_t nCallbackType,
DSL_BSP_CB_DATA_Union_t *pData
);
typedef struct {
DSL_BSP_EventCallback_t function;
DSL_BSP_CB_Type_t event;
DSL_BSP_CB_DATA_Union_t *pData;
} DSL_BSP_EventCallBack_t;
extern int DSL_BSP_EventCBRegister(DSL_BSP_EventCallBack_t *);
extern int DSL_BSP_EventCBUnregister(DSL_BSP_EventCallBack_t *);
/** Modem states */
#define DSL_DEV_STAT_InitState 0x0000
#define DSL_DEV_STAT_ReadyState 0x0001
#define DSL_DEV_STAT_FailState 0x0002
#define DSL_DEV_STAT_IdleState 0x0003
#define DSL_DEV_STAT_QuietState 0x0004
#define DSL_DEV_STAT_GhsState 0x0005
#define DSL_DEV_STAT_FullInitState 0x0006
#define DSL_DEV_STAT_ShowTimeState 0x0007
#define DSL_DEV_STAT_FastRetrainState 0x0008
#define DSL_DEV_STAT_LoopDiagMode 0x0009
#define DSL_DEV_STAT_ShortInit 0x000A /* Bis short initialization */
#define DSL_DEV_STAT_CODESWAP_COMPLETE 0x0002
#endif //IFXMIPS_MEI_H

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@ -0,0 +1,25 @@
#
# Copyright (C) 2007-2010 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
ARCH:=mips
BOARD:=lantiq
BOARDNAME:=Lantiq GPON/XWAY
FEATURES:=squashfs jffs2 atm
SUBTARGETS:=xway
LINUX_VERSION:=2.6.35.9
CFLAGS=-Os -pipe -mips32r2 -mtune=mips32r2 -funit-at-a-time
include $(INCLUDE_DIR)/target.mk
define Target/Description
Build firmware images for Lantiq SoC
endef
$(eval $(call BuildTarget))

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@ -0,0 +1,26 @@
config interface loopback
option ifname lo
option proto static
option ipaddr 127.0.0.1
option netmask 255.0.0.0
config interface lan
option ifname eth0
option type bridge
option proto static
option ipaddr 192.168.1.1
option netmask 255.255.255.0
config atm-bridge
option unit 0
option encaps llc
option vpi 1
option vci 32
option payload bridged # some ISPs need this set to 'routed'
config interface wan
option ifname nas0
option proto pppoe
option username ""
option password ""
option unit 0

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@ -0,0 +1,4 @@
::sysinit:/etc/init.d/rcS S boot
::shutdown:/etc/init.d/rcS K stop
ttyS0::askfirst:/bin/ash --login
ttyS1::askfirst:/bin/ash --login

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PART_NAME=linux
platform_check_image() {
[ "$ARGC" -gt 1 ] && return 1
case "$(get_magic_word "$1")" in
# .trx files
2705) return 0;;
*)
echo "Invalid image type"
return 1
;;
esac
}
# use default for platform_do_upgrade()
disable_watchdog() {
killall watchdog
( ps | grep -v 'grep' | grep '/dev/watchdog' ) && {
echo 'Could not disable watchdog'
return 1
}
}
append sysupgrade_pre_upgrade disable_watchdog

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# CONFIG_TC35815 is not set
# CONFIG_TINY_RCU is not set
# CONFIG_TREE_PREEMPT_RCU is not set
# CONFIG_HAVE_IDE is not set
# CONFIG_64BIT is not set
# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
# CONFIG_AR7 is not set
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_BCM47XX is not set
# CONFIG_BCM63XX is not set
# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
# CONFIG_CPU_CAVIUM_OCTEON is not set
# CONFIG_CPU_LITTLE_ENDIAN is not set
# CONFIG_CPU_LOONGSON2E is not set
# CONFIG_CPU_LOONGSON2F is not set
# CONFIG_CPU_MIPS32_R1 is not set
# CONFIG_CPU_MIPS64_R1 is not set
# CONFIG_CPU_MIPS64_R2 is not set
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R5500 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_RM9000 is not set
# CONFIG_CPU_SB1 is not set
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_DM9000 is not set
# CONFIG_FSNOTIFY is not set
# CONFIG_HZ_100 is not set
# CONFIG_LOONGSON_UART_BASE is not set
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
# CONFIG_MACH_LOONGSON is not set
# CONFIG_MACH_TX39XX is not set
# CONFIG_MACH_TX49XX is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_MIKROTIK_RB532 is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MIPS_MALTA is not set
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MIPS_VPE_LOADER is not set
# CONFIG_NO_IOPORT is not set
# CONFIG_NXP_STB220 is not set
# CONFIG_NXP_STB225 is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
# CONFIG_POWERTV is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SERIAL_8250 is not set
# CONFIG_SERIAL_8250_EXTENDED is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP28 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_SWARM is not set
CONFIG_32BIT=y
CONFIG_ADM6996_PHY=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_ARCH_SUPPORTS_OPROFILE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_BITREVERSE=y
CONFIG_CEVT_R4K=y
CONFIG_CEVT_R4K_LIB=y
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_CPU_MIPS32=y
CONFIG_CPU_MIPS32_R2=y
CONFIG_CPU_MIPSR2=y
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_BLKCIPHER2=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_CSRC_R4K=y
CONFIG_CSRC_R4K_LIB=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DEVPORT=y
CONFIG_DMA_NEED_PCI_MAP_STATE=y
CONFIG_DMA_NONCOHERENT=y
CONFIG_EARLY_PRINTK=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_FIND_LAST_BIT=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HW_RANDOM=y
CONFIG_HZ=250
CONFIG_HZ_250=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IRQ_CPU=y
CONFIG_LANTIQ=y
CONFIG_MIPS=y
CONFIG_MIPS_L1_CACHE_SHIFT=5
CONFIG_MIPS_MACHINE=y
CONFIG_MIPS_MT_DISABLED=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_LANTIQ=y
CONFIG_NLS=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PHYLIB=y
CONFIG_SCHED_OMIT_FRAME_POINTER=y
CONFIG_SERIAL_LANTIQ=y
CONFIG_SWAP_IO_SPACE=y
CONFIG_SWCONFIG=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_SYS_HAS_CPU_MIPS32_R2=y
CONFIG_SYS_HAS_EARLY_PRINTK=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
CONFIG_SYS_SUPPORTS_MULTITHREADING=y
CONFIG_TRAD_SIGNALS=y
CONFIG_TREE_RCU=y
CONFIG_ZONE_DMA_FLAG=0
CONFIG_IFX_UDP_REDIRECT=y

View file

@ -0,0 +1,89 @@
#
# Copyright (C) 2010 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/image.mk
JFFS2_BLOCKSIZE = 64k 128k 256k
xway_cmdline=-console=ttyS1,115200 rootfstype=squashfs,jffs2
falcon_cmdline=-console=ttyS0,115200 rootfstype=squashfs,jffs2
define CompressLzma
$(STAGING_DIR_HOST)/bin/lzma e $(1) $(2)
endef
define PatchKernelLzma
cp $(KDIR)/vmlinux $(KDIR)/vmlinux-$(1)
$(STAGING_DIR_HOST)/bin/patch-cmdline $(KDIR)/vmlinux-$(1) '$(strip $(2))'
$(call CompressLzma,$(KDIR)/vmlinux-$(1),$(KDIR)/vmlinux-$(1).lzma)
endef
define MkImageLzma
mkimage -A mips -O linux -T kernel -a 0x80002000 -C lzma \
-e 0x80002000 -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \
-d $(KDIR)/vmlinux-$(1).lzma $(KDIR)/uImage-$(1)
endef
define Image/Build/squashfs
cat $(KDIR)/uImage-$(2) $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).image
$(call prepare_generic_squashfs,$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).image)
endef
define Image/Build/jffs2-64k
dd if=$(KDIR)/uImage-$(2) of=$(KDIR)/uImage-$(2)-$(1) bs=64k conv=sync
cat $(KDIR)/uImage-$(2)-$(1) $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).image
endef
define Image/Build/jffs2-128k
dd if=$(KDIR)/uImage-$(2) of=$(KDIR)/uImage-$(2)-$(1) bs=128k conv=sync
cat $(KDIR)/uImage-$(2)-$(1) $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).image
endef
define Image/Build/jffs2-256k
dd if=$(KDIR)/uImage-$(2) of=$(KDIR)/uImage-$(2)-$(1) bs=256k conv=sync
cat $(KDIR)/uImage-$(2)-$(1) $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).image
endef
define Image/BuildKernel/Template
$(call PatchKernelLzma,$(1),$(if $(2),$(2) machtype=$(1),))
$(call MkImageLzma,$(1))
$(CP) $(KDIR)/uImage-$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(1)-uImage
endef
ifeq ($(CONFIG_SOC_LANTIQ_XWAY),y)
define Image/BuildKernel
$(call Image/BuildKernel/Template,EASY4010,$(xway_cmdline))
$(call Image/BuildKernel/Template,EASY50712,$(xway_cmdline))
$(call Image/BuildKernel/Template,EASY50812,$(xway_cmdline))
$(call Image/BuildKernel/Template,ARV452,$(xway_cmdline))
$(call Image/BuildKernel/Template,NONE)
endef
define Image/Build
$(call Image/Build/$(1),$(1),EASY4010)
$(call Image/Build/$(1),$(1),EASY50712)
$(call Image/Build/$(1),$(1),EASY50812)
$(call Image/Build/$(1),$(1),ARV452)
$(call Image/Build/$(1),$(1),NONE)
$(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(1).rootfs
endef
endif
ifeq ($(CONFIG_SOC_LANTIQ_FALCON),y)
define Image/BuildKernel
$(call Image/BuildKernel/Template,EASY98000,$(falcon_cmdline))
$(call Image/BuildKernel/Template,NONE)
endef
define Image/Build
$(call Image/Build/$(1),$(1),EASY98000)
$(call Image/Build/$(1),$(1),NONE)
$(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(1).rootfs
endef
endif
$(eval $(call BuildImage))

View file

@ -0,0 +1,47 @@
#
# Copyright (C) 2010 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
define KernelPackage/lantiq-deu
TITLE:=Lantiq data encryption unit
SUBMENU:=$(CRYPTO_MENU)
DEPENDS:=@TARGET_lantiq
KCONFIG:=CONFIG_CRYPTO_DEV_LANTIQ \
CONFIG_CRYPTO_HW=y \
CONFIG_CRYPTO_DEV_LANTIQ_AES=y \
CONFIG_CRYPTO_DEV_LANTIQ_DES=y \
CONFIG_CRYPTO_DEV_LANTIQ_MD5=y \
CONFIG_CRYPTO_DEV_LANTIQ_SHA1=y
$(call AddDepends/crypto)
endef
define KernelPackage/lantiq-deu/description
Kernel support for the Lantiq crypto HW
endef
$(eval $(call KernelPackage,lantiq-deu))
USB_MENU:=USB Support
define KernelPackage/usb-dwc-otg
TITLE:=Synopsis DWC_OTG support
SUBMENU:=$(USB_MENU)
DEPENDS+=@TARGET_lantiq_xway +kmod-usb-core
KCONFIG:=CONFIG_DWC_OTG \
CONFIG_DWC_OTG_DEBUG=n \
CONFIG_DWC_OTG_LANTIQ=y \
CONFIG_DWC_OTG_HOST_ONLY=y
FILES:=$(LINUX_DIR)/drivers/usb/dwc_otg/dwc_otg.ko
AUTOLOAD:=$(call AutoLoad,50,dwc_otg)
endef
define KernelPackage/usb-dwc-otg/description
Kernel support for Synopsis USB on XWAY
endef
$(eval $(call KernelPackage,usb-dwc-otg))

View file

@ -0,0 +1,35 @@
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1496,7 +1496,18 @@ void __cpuinit per_cpu_trap_init(void)
if (cpu_has_mips_r2) {
cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
+
+ if (!cp0_compare_irq)
+ cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
+
cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
+
+ if (!cp0_perfcount_irq)
+ cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
+
+ if (arch_fixup_c0_irqs)
+ arch_fixup_c0_irqs();
+
if (cp0_perfcount_irq == cp0_compare_irq)
cp0_perfcount_irq = -1;
} else {
--- a/arch/mips/include/asm/irq.h
+++ b/arch/mips/include/asm/irq.h
@@ -133,9 +133,11 @@ extern void free_irqno(unsigned int irq)
* IE7. Since R2 their number has to be read from the c0_intctl register.
*/
#define CP0_LEGACY_COMPARE_IRQ 7
+#define CP0_LEGACY_PERFCNT_IRQ 7
extern int cp0_compare_irq;
extern int cp0_compare_irq_shift;
extern int cp0_perfcount_irq;
+extern void __weak arch_fixup_c0_irqs(void);
#endif /* _ASM_IRQ_H */

View file

@ -0,0 +1,33 @@
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -22,6 +22,22 @@
#ifndef CONFIG_MIPS_MT_SMTC
+/*
+ * Compare interrupt can be routed and latched outside the core,
+ * so a single execution hazard barrier may not be enough to give
+ * it time to clear as seen in the Cause register. 4 time the
+ * pipeline depth seems reasonably conservative, and empirically
+ * works better in configurations with high CPU/bus clock ratios.
+ */
+
+#define compare_change_hazard() \
+ do { \
+ irq_disable_hazard(); \
+ irq_disable_hazard(); \
+ irq_disable_hazard(); \
+ irq_disable_hazard(); \
+ } while (0)
+
static int mips_next_event(unsigned long delta,
struct clock_event_device *evt)
{
@@ -31,6 +47,7 @@ static int mips_next_event(unsigned long
cnt = read_c0_count();
cnt += delta;
write_c0_compare(cnt);
+ compare_change_hazard();
res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
return res;
}

View file

@ -0,0 +1,12 @@
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -650,6 +650,9 @@ handle_percpu_irq(unsigned int irq, stru
kstat_incr_irqs_this_cpu(irq, desc);
+ if (unlikely(!desc->action || (desc->status & IRQ_DISABLED)))
+ return;
+
if (desc->chip->ack)
desc->chip->ack(irq);

View file

@ -0,0 +1,641 @@
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -139,6 +139,9 @@ config MACH_DECSTATION
otherwise choose R3000.
+config LANTIQ
+ bool "Lantiq MIPS"
+
config MACH_JAZZ
bool "Jazz family of machines"
select ARC
@@ -693,6 +696,7 @@ source "arch/mips/txx9/Kconfig"
source "arch/mips/vr41xx/Kconfig"
source "arch/mips/cavium-octeon/Kconfig"
source "arch/mips/loongson/Kconfig"
+source "arch/mips/lantiq/Kconfig"
endmenu
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -317,6 +317,17 @@ cflags-$(CONFIG_MIPS_COBALT) += -I$(srct
load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000
#
+# Lantiq
+#
+load-$(CONFIG_LANTIQ) += 0xffffffff80002000
+core-$(CONFIG_LANTIQ) += arch/mips/lantiq/
+cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq
+core-$(CONFIG_SOC_LANTIQ_FALCON) += arch/mips/lantiq/falcon/
+cflags-$(CONFIG_SOC_LANTIQ_FALCON) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon
+core-$(CONFIG_SOC_LANTIQ_XWAY) += arch/mips/lantiq/xway/
+cflags-$(CONFIG_SOC_LANTIQ_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway
+
+#
# DECstation family
#
core-$(CONFIG_MACH_DECSTATION) += arch/mips/dec/
--- /dev/null
+++ b/arch/mips/lantiq/Kconfig
@@ -0,0 +1,36 @@
+if LANTIQ
+
+config SOC_LANTIQ
+ bool
+ select DMA_NONCOHERENT
+ select IRQ_CPU
+ select CEVT_R4K
+ select CSRC_R4K
+ select SYS_HAS_CPU_MIPS32_R1
+ select SYS_HAS_CPU_MIPS32_R2
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_MULTITHREADING
+ select SYS_HAS_EARLY_PRINTK
+ select HW_HAS_PCI
+ select ARCH_REQUIRE_GPIOLIB
+ select SWAP_IO_SPACE
+ select MIPS_MACHINE
+
+choice
+ prompt "SoC Type"
+ default SOC_LANTIQ_XWAY
+
+#config SOC_LANTIQ_FALCON
+# bool "FALCON"
+# select SOC_LANTIQ
+
+config SOC_LANTIQ_XWAY
+ bool "XWAY"
+ select SOC_LANTIQ
+endchoice
+
+#source "arch/mips/lantiq/falcon/Kconfig"
+source "arch/mips/lantiq/xway/Kconfig"
+
+endif
--- /dev/null
+++ b/arch/mips/lantiq/Makefile
@@ -0,0 +1,2 @@
+obj-y := irq.o setup.o clk.o prom.o
+obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
--- /dev/null
+++ b/arch/mips/lantiq/irq.c
@@ -0,0 +1,212 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/module.h>
+#include <linux/interrupt.h>
+
+#include <asm/bootinfo.h>
+#include <asm/irq_cpu.h>
+
+#include <lantiq.h>
+#include <irq.h>
+
+#define LQ_ICU_BASE_ADDR (KSEG1 | 0x1F880200)
+
+#define LQ_ICU_IM0_ISR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0000))
+#define LQ_ICU_IM0_IER ((u32 *)(LQ_ICU_BASE_ADDR + 0x0008))
+#define LQ_ICU_IM0_IOSR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0010))
+#define LQ_ICU_IM0_IRSR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0018))
+#define LQ_ICU_IM0_IMR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0020))
+
+#define LQ_ICU_IM1_ISR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0028))
+#define LQ_ICU_IM2_ISR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0050))
+#define LQ_ICU_IM3_ISR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0078))
+#define LQ_ICU_IM4_ISR ((u32 *)(LQ_ICU_BASE_ADDR + 0x00A0))
+
+#define LQ_ICU_OFFSET (LQ_ICU_IM1_ISR - LQ_ICU_IM0_ISR)
+
+void
+lq_disable_irq(unsigned int irq_nr)
+{
+ u32 *ier = LQ_ICU_IM0_IER;
+ irq_nr -= INT_NUM_IRQ0;
+ ier += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
+ irq_nr %= INT_NUM_IM_OFFSET;
+ lq_w32(lq_r32(ier) & ~(1 << irq_nr), ier);
+}
+EXPORT_SYMBOL(lq_disable_irq);
+
+void
+lq_mask_and_ack_irq(unsigned int irq_nr)
+{
+ u32 *ier = LQ_ICU_IM0_IER;
+ u32 *isr = LQ_ICU_IM0_ISR;
+ irq_nr -= INT_NUM_IRQ0;
+ ier += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
+ isr += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
+ irq_nr %= INT_NUM_IM_OFFSET;
+ lq_w32(lq_r32(ier) & ~(1 << irq_nr), ier);
+ lq_w32((1 << irq_nr), isr);
+}
+EXPORT_SYMBOL(lq_mask_and_ack_irq);
+
+static void
+lq_ack_irq(unsigned int irq_nr)
+{
+ u32 *isr = LQ_ICU_IM0_ISR;
+ irq_nr -= INT_NUM_IRQ0;
+ isr += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
+ irq_nr %= INT_NUM_IM_OFFSET;
+ lq_w32((1 << irq_nr), isr);
+}
+
+void
+lq_enable_irq(unsigned int irq_nr)
+{
+ u32 *ier = LQ_ICU_IM0_IER;
+ irq_nr -= INT_NUM_IRQ0;
+ ier += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
+ irq_nr %= INT_NUM_IM_OFFSET;
+ lq_w32(lq_r32(ier) | (1 << irq_nr), ier);
+}
+EXPORT_SYMBOL(lq_enable_irq);
+
+static unsigned int
+lq_startup_irq(unsigned int irq)
+{
+ lq_enable_irq(irq);
+ return 0;
+}
+
+static void
+lq_end_irq(unsigned int irq)
+{
+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+ lq_enable_irq(irq);
+}
+
+static struct irq_chip
+lq_irq_type = {
+ "lq_irq",
+ .startup = lq_startup_irq,
+ .enable = lq_enable_irq,
+ .disable = lq_disable_irq,
+ .unmask = lq_enable_irq,
+ .ack = lq_ack_irq,
+ .mask = lq_disable_irq,
+ .mask_ack = lq_mask_and_ack_irq,
+ .end = lq_end_irq,
+};
+
+static void
+lq_hw_irqdispatch(int module)
+{
+ u32 irq;
+
+ irq = lq_r32(LQ_ICU_IM0_IOSR + (module * LQ_ICU_OFFSET));
+ if (irq == 0)
+ return;
+
+ /* silicon bug causes only the msb set to 1 to be valid. all
+ other bits might be bogus */
+ irq = __fls(irq);
+ do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
+}
+
+#define DEFINE_HWx_IRQDISPATCH(x) \
+static void lq_hw ## x ## _irqdispatch(void)\
+{\
+ lq_hw_irqdispatch(x); \
+}
+static void lq_hw5_irqdispatch(void)
+{
+ do_IRQ(MIPS_CPU_TIMER_IRQ);
+}
+DEFINE_HWx_IRQDISPATCH(0)
+DEFINE_HWx_IRQDISPATCH(1)
+DEFINE_HWx_IRQDISPATCH(2)
+DEFINE_HWx_IRQDISPATCH(3)
+DEFINE_HWx_IRQDISPATCH(4)
+/*DEFINE_HWx_IRQDISPATCH(5)*/
+
+asmlinkage void
+plat_irq_dispatch(void)
+{
+ unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
+ unsigned int i;
+
+ if (pending & CAUSEF_IP7)
+ {
+ do_IRQ(MIPS_CPU_TIMER_IRQ);
+ goto out;
+ } else {
+ for (i = 0; i < 5; i++)
+ {
+ if (pending & (CAUSEF_IP2 << i))
+ {
+ lq_hw_irqdispatch(i);
+ goto out;
+ }
+ }
+ }
+ printk(KERN_ALERT "Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
+
+out:
+ return;
+}
+
+static struct irqaction
+cascade = {
+ .handler = no_action,
+ .flags = IRQF_DISABLED,
+ .name = "cascade",
+};
+
+void __init
+arch_init_irq(void)
+{
+ int i;
+
+ for (i = 0; i < 5; i++)
+ lq_w32(0, LQ_ICU_IM0_IER + (i * LQ_ICU_OFFSET));
+
+ mips_cpu_irq_init();
+
+ for (i = 2; i <= 6; i++)
+ setup_irq(i, &cascade);
+
+ if (cpu_has_vint) {
+ printk(KERN_INFO "Setting up vectored interrupts\n");
+ set_vi_handler(2, lq_hw0_irqdispatch);
+ set_vi_handler(3, lq_hw1_irqdispatch);
+ set_vi_handler(4, lq_hw2_irqdispatch);
+ set_vi_handler(5, lq_hw3_irqdispatch);
+ set_vi_handler(6, lq_hw4_irqdispatch);
+ set_vi_handler(7, lq_hw5_irqdispatch);
+ }
+
+ for (i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
+ set_irq_chip_and_handler(i, &lq_irq_type,
+ handle_level_irq);
+
+ #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
+ set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
+ IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
+ #else
+ set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
+ IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
+ #endif
+}
+
+void __cpuinit
+arch_fixup_c0_irqs(void)
+{
+ /* FIXME: check for CPUID and only do fix for specific chips/versions */
+ cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
+ cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
+}
--- /dev/null
+++ b/arch/mips/lantiq/setup.c
@@ -0,0 +1,47 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+
+#include <lantiq.h>
+#include <lantiq_regs.h>
+
+void __init
+plat_mem_setup(void)
+{
+ /* assume 16M as default */
+ int memsize = 16;
+ char **envp = (char **) KSEG1ADDR(fw_arg2);
+ u32 status;
+
+ /* make sure to have no "reverse endian" for user mode! */
+ status = read_c0_status();
+ status &= (~(1<<25));
+ write_c0_status(status);
+
+ ioport_resource.start = IOPORT_RESOURCE_START;
+ ioport_resource.end = IOPORT_RESOURCE_END;
+ iomem_resource.start = IOMEM_RESOURCE_START;
+ iomem_resource.end = IOMEM_RESOURCE_END;
+
+ while (*envp)
+ {
+ char *e = (char *)KSEG1ADDR(*envp);
+ if (!strncmp(e, "memsize=", 8))
+ {
+ e += 8;
+ memsize = simple_strtoul(e, NULL, 10);
+ }
+ envp++;
+ }
+ memsize *= 1024 * 1024;
+ add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
+}
--- /dev/null
+++ b/arch/mips/lantiq/clk.c
@@ -0,0 +1,141 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 Thomas Langer, Lantiq Deutschland
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/list.h>
+
+#include <asm/time.h>
+#include <asm/irq.h>
+#include <asm/div64.h>
+
+#include <lantiq.h>
+#ifdef CONFIG_SOC_LANTIQ_XWAY
+#include <xway.h>
+#endif
+
+extern unsigned long lq_get_cpu_hz(void);
+extern unsigned long lq_get_fpi_hz(void);
+extern unsigned long lq_get_io_region_clock(void);
+
+struct clk {
+ const char *name;
+ unsigned long rate;
+ unsigned long (*get_rate) (void);
+};
+
+static struct clk *cpu_clk = 0;
+static int cpu_clk_cnt = 0;
+
+static unsigned int r4k_offset;
+static unsigned int r4k_cur;
+
+static struct clk cpu_clk_generic[] = {
+ {
+ .name = "cpu",
+ .get_rate = lq_get_cpu_hz,
+ }, {
+ .name = "fpi",
+ .get_rate = lq_get_fpi_hz,
+ }, {
+ .name = "io",
+ .get_rate = lq_get_io_region_clock,
+ },
+};
+
+void
+clk_init(void)
+{
+ int i;
+ cpu_clk = cpu_clk_generic;
+ cpu_clk_cnt = ARRAY_SIZE(cpu_clk_generic);
+ for(i = 0; i < cpu_clk_cnt; i++)
+ printk("%s: %ld\n", cpu_clk[i].name, clk_get_rate(&cpu_clk[i]));
+}
+
+static inline int
+clk_good(struct clk *clk)
+{
+ return clk && !IS_ERR(clk);
+}
+
+unsigned long
+clk_get_rate(struct clk *clk)
+{
+ if (unlikely(!clk_good(clk)))
+ return 0;
+
+ if (clk->rate != 0)
+ return clk->rate;
+
+ if (clk->get_rate != NULL)
+ return clk->get_rate();
+
+ return 0;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+struct clk*
+clk_get(struct device *dev, const char *id)
+{
+ int i;
+ for(i = 0; i < cpu_clk_cnt; i++)
+ if (!strcmp(id, cpu_clk[i].name))
+ return &cpu_clk[i];
+ BUG();
+ return ERR_PTR(-ENOENT);
+}
+EXPORT_SYMBOL(clk_get);
+
+void
+clk_put(struct clk *clk)
+{
+ /* not used */
+}
+EXPORT_SYMBOL(clk_put);
+
+static inline u32
+lq_get_counter_resolution(void)
+{
+ u32 res;
+ __asm__ __volatile__(
+ ".set push\n"
+ ".set mips32r2\n"
+ ".set noreorder\n"
+ "rdhwr %0, $3\n"
+ "ehb\n"
+ ".set pop\n"
+ : "=&r" (res)
+ : /* no input */
+ : "memory");
+ instruction_hazard();
+ return res;
+}
+
+void __init
+plat_time_init(void)
+{
+ struct clk *clk = clk_get(0, "cpu");
+ mips_hpt_frequency = clk_get_rate(clk) / lq_get_counter_resolution();
+ r4k_cur = (read_c0_count() + r4k_offset);
+ write_c0_compare(r4k_cur);
+
+#ifdef CONFIG_SOC_LANTIQ_XWAY
+#define LQ_GPTU_GPT_CLC ((u32 *)(LQ_GPTU_BASE_ADDR + 0x0000))
+ lq_pmu_enable(PMU_GPT);
+ lq_pmu_enable(PMU_FPI);
+
+ lq_w32(0x100, LQ_GPTU_GPT_CLC);
+#endif
+}
--- /dev/null
+++ b/arch/mips/lantiq/prom.c
@@ -0,0 +1,118 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <asm/bootinfo.h>
+#include <asm/time.h>
+
+#include <lantiq.h>
+
+#include "prom.h"
+
+static struct lq_soc_info soc_info;
+
+/* for Multithreading (APRP) on MIPS34K */
+unsigned long physical_memsize;
+
+/* all access to the ebu must be locked */
+DEFINE_SPINLOCK(ebu_lock);
+EXPORT_SYMBOL_GPL(ebu_lock);
+
+extern void clk_init(void);
+
+unsigned int
+lq_get_cpu_ver(void)
+{
+ return soc_info.rev;
+}
+EXPORT_SYMBOL(lq_get_cpu_ver);
+
+unsigned int
+lq_get_soc_type(void)
+{
+ return soc_info.type;
+}
+EXPORT_SYMBOL(lq_get_soc_type);
+
+const char*
+get_system_type(void)
+{
+ return soc_info.sys_type;
+}
+
+void
+prom_free_prom_memory(void)
+{
+}
+
+#ifdef CONFIG_IMAGE_CMDLINE_HACK
+extern char __image_cmdline[];
+
+static void __init
+prom_init_image_cmdline(void)
+{
+ char *p = __image_cmdline;
+ int replace = 0;
+
+ if (*p == '-') {
+ replace = 1;
+ p++;
+ }
+
+ if (*p == '\0')
+ return;
+
+ if (replace) {
+ strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline));
+ } else {
+ strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
+ strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
+ }
+}
+#else
+static void __init prom_init_image_cmdline(void) { return; }
+#endif
+
+static void __init
+prom_init_cmdline(void)
+{
+ int argc = fw_arg0;
+ char **argv = (char**)KSEG1ADDR(fw_arg1);
+ int i;
+
+ arcs_cmdline[0] = '\0';
+ if(argc)
+ for (i = 1; i < argc; i++)
+ {
+ strlcat(arcs_cmdline, (char*)KSEG1ADDR(argv[i]), COMMAND_LINE_SIZE);
+ if(i + 1 != argc)
+ strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
+ }
+
+ if (!*arcs_cmdline)
+ strcpy(&(arcs_cmdline[0]),
+ "console=ttyS1,115200 rootfstype=squashfs,jffs2");
+ prom_init_image_cmdline();
+}
+
+void __init
+prom_init(void)
+{
+ struct clk *clk;
+ lq_soc_detect(&soc_info);
+
+ clk_init();
+ clk = clk_get(0, "cpu");
+ snprintf(soc_info.sys_type, LQ_SYS_TYPE_LEN - 1, "%s rev1.%d %ldMhz",
+ soc_info.name, soc_info.rev, clk_get_rate(clk) / 1000000);
+ soc_info.sys_type[LQ_SYS_TYPE_LEN - 1] = '\0';
+ printk("SoC: %s\n", soc_info.sys_type);
+
+ prom_init_cmdline();
+}
--- /dev/null
+++ b/arch/mips/lantiq/prom.h
@@ -0,0 +1,24 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef _LQ_PROM_H__
+#define _LQ_PROM_H__
+
+#define LQ_SYS_TYPE_LEN 0x100
+
+struct lq_soc_info {
+ unsigned char *name;
+ unsigned int rev;
+ unsigned int partnum;
+ unsigned int type;
+ unsigned char sys_type[LQ_SYS_TYPE_LEN];
+};
+
+void lq_soc_detect(struct lq_soc_info *i);
+
+#endif

View file

@ -0,0 +1,136 @@
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/war.h
@@ -0,0 +1,24 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#ifndef __ASM_MIPS_MACH_LANTIQ_WAR_H
+#define __ASM_MIPS_MACH_LANTIQ_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR 0
+#define R4600_V1_HIT_CACHEOP_WAR 0
+#define R4600_V2_HIT_CACHEOP_WAR 0
+#define R5432_CP0_INTERRUPT_WAR 0
+#define BCM1250_M3_WAR 0
+#define SIBYTE_1956_WAR 0
+#define MIPS4K_ICACHE_REFILL_WAR 0
+#define MIPS_CACHE_SYNC_WAR 0
+#define TX49XX_ICACHE_INDEX_INV_WAR 0
+#define RM9000_CDEX_SMP_WAR 0
+#define ICACHE_REFILLS_WORKAROUND_WAR 0
+#define R10000_LLSC_WAR 0
+#define MIPS34K_MISSED_ITLB_WAR 0
+
+#endif
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -0,0 +1,47 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef _LANTIQ_H__
+#define _LANTIQ_H__
+
+/* generic reg access functions */
+#define lq_r32(reg) __raw_readl(reg)
+#define lq_w32(val, reg) __raw_writel(val, reg)
+#define lq_w32_mask(clear, set, reg) lq_w32((lq_r32(reg) & ~clear) | set, reg)
+
+extern unsigned int lq_get_cpu_ver(void);
+extern unsigned int lq_get_soc_type(void);
+
+/* clock speeds */
+#define CLOCK_60M 60000000
+#define CLOCK_83M 83333333
+#define CLOCK_111M 111111111
+#define CLOCK_111M 111111111
+#define CLOCK_133M 133333333
+#define CLOCK_167M 166666667
+#define CLOCK_200M 200000000
+#define CLOCK_333M 333333333
+#define CLOCK_400M 400000000
+
+/* spinlock all ebu i/o */
+extern spinlock_t ebu_lock;
+
+/* some irq helpers */
+extern void lq_disable_irq(unsigned int irq_nr);
+extern void lq_mask_and_ack_irq(unsigned int irq_nr);
+extern void lq_enable_irq(unsigned int irq_nr);
+
+#define IOPORT_RESOURCE_START 0x10000000
+#define IOPORT_RESOURCE_END 0xffffffff
+#define IOMEM_RESOURCE_START 0x10000000
+#define IOMEM_RESOURCE_END 0xffffffff
+
+#define LQ_FLASH_START 0x10000000
+#define LQ_FLASH_MAX 0x04000000
+
+#endif
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/lantiq_regs.h
@@ -0,0 +1,17 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef _LANTIQ_REGS_H__
+#define _LANTIQ_REGS_H__
+
+#ifdef CONFIG_SOC_LANTIQ_XWAY
+#include <xway.h>
+#include <xway_irq.h>
+#endif
+
+#endif
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
@@ -0,0 +1,36 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef _LANTIQ_PLATFORM_H__
+#define _LANTIQ_PLATFORM_H__
+
+#include <linux/mtd/partitions.h>
+
+/* struct used to pass info to network drivers */
+enum {
+ MII_MODE,
+ REV_MII_MODE,
+};
+
+struct lq_eth_data {
+ unsigned char *mac;
+ int mii_mode;
+};
+
+/* struct used to pass info to the pci core */
+enum {
+ PCI_CLOCK_INT = 0,
+ PCI_CLOCK_EXT
+};
+
+struct lq_pci_data {
+ int clock;
+ int req_mask;
+};
+
+#endif

File diff suppressed because it is too large Load diff

View file

@ -0,0 +1,565 @@
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/irq.h
@@ -0,0 +1,18 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef __LANTIQ_IRQ_H
+#define __LANTIQ_IRQ_H
+
+#include <xway_irq.h>
+
+#define NR_IRQS 256
+
+#include_next <irq.h>
+
+#endif
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
@@ -0,0 +1,155 @@
+#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
+#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
+
+
+/******************************************************************************
+ Copyright (c) 2002, Infineon Technologies. All rights reserved.
+
+ No Warranty
+ Because the program is licensed free of charge, there is no warranty for
+ the program, to the extent permitted by applicable law. Except when
+ otherwise stated in writing the copyright holders and/or other parties
+ provide the program "as is" without warranty of any kind, either
+ expressed or implied, including, but not limited to, the implied
+ warranties of merchantability and fitness for a particular purpose. The
+ entire risk as to the quality and performance of the program is with
+ you. should the program prove defective, you assume the cost of all
+ necessary servicing, repair or correction.
+
+ In no event unless required by applicable law or agreed to in writing
+ will any copyright holder, or any other party who may modify and/or
+ redistribute the program as permitted above, be liable to you for
+ damages, including any general, special, incidental or consequential
+ damages arising out of the use or inability to use the program
+ (including but not limited to loss of data or data being rendered
+ inaccurate or losses sustained by you or third parties or a failure of
+ the program to operate with any other programs), even if such holder or
+ other party has been advised of the possibility of such damages.
+******************************************************************************/
+
+
+/*
+ * ####################################
+ * Definition
+ * ####################################
+ */
+
+/*
+ * Available Timer/Counter Index
+ */
+#define TIMER(n, X) (n * 2 + (X ? 1 : 0))
+#define TIMER_ANY 0x00
+#define TIMER1A TIMER(1, 0)
+#define TIMER1B TIMER(1, 1)
+#define TIMER2A TIMER(2, 0)
+#define TIMER2B TIMER(2, 1)
+#define TIMER3A TIMER(3, 0)
+#define TIMER3B TIMER(3, 1)
+
+/*
+ * Flag of Timer/Counter
+ * These flags specify the way in which timer is configured.
+ */
+/* Bit size of timer/counter. */
+#define TIMER_FLAG_16BIT 0x0000
+#define TIMER_FLAG_32BIT 0x0001
+/* Switch between timer and counter. */
+#define TIMER_FLAG_TIMER 0x0000
+#define TIMER_FLAG_COUNTER 0x0002
+/* Stop or continue when overflowing/underflowing. */
+#define TIMER_FLAG_ONCE 0x0000
+#define TIMER_FLAG_CYCLIC 0x0004
+/* Count up or counter down. */
+#define TIMER_FLAG_UP 0x0000
+#define TIMER_FLAG_DOWN 0x0008
+/* Count on specific level or edge. */
+#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
+#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040
+#define TIMER_FLAG_RISE_EDGE 0x0010
+#define TIMER_FLAG_FALL_EDGE 0x0020
+#define TIMER_FLAG_ANY_EDGE 0x0030
+/* Signal is syncronous to module clock or not. */
+#define TIMER_FLAG_UNSYNC 0x0000
+#define TIMER_FLAG_SYNC 0x0080
+/* Different interrupt handle type. */
+#define TIMER_FLAG_NO_HANDLE 0x0000
+#if defined(__KERNEL__)
+ #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100
+#endif // defined(__KERNEL__)
+#define TIMER_FLAG_SIGNAL 0x0300
+/* Internal clock source or external clock source */
+#define TIMER_FLAG_INT_SRC 0x0000
+#define TIMER_FLAG_EXT_SRC 0x1000
+
+
+/*
+ * ioctl Command
+ */
+#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */
+#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */
+#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */
+#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */
+#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */
+#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/
+#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */
+#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */
+
+/*
+ * Data Type Used to Call ioctl
+ */
+struct gptu_ioctl_param {
+ unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
+ * GPTU_SET_COUNTER, this field is ID of expected *
+ * timer/counter. If it's zero, a timer/counter would *
+ * be dynamically allocated and ID would be stored in *
+ * this field. *
+ * In command GPTU_GET_COUNT_VALUE, this field is *
+ * ignored. *
+ * In other command, this field is ID of timer/counter *
+ * allocated. */
+ unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
+ * GPTU_SET_COUNTER, this field contains flags to *
+ * specify how to configure timer/counter. *
+ * In command GPTU_START_TIMER, zero indicate start *
+ * and non-zero indicate resume timer/counter. *
+ * In other command, this field is ignored. */
+ unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains *
+ * init/reload value. *
+ * In command GPTU_SET_TIMER, this field contains *
+ * frequency (0.001Hz) of timer. *
+ * In command GPTU_GET_COUNT_VALUE, current count *
+ * value would be stored in this field. *
+ * In command GPTU_CALCULATE_DIVIDER, this field *
+ * contains frequency wanted, and after calculation, *
+ * divider would be stored in this field to overwrite *
+ * the frequency. *
+ * In other command, this field is ignored. */
+ int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
+ * if signal is required, this field contains process *
+ * ID to which signal would be sent. *
+ * In other command, this field is ignored. */
+ int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
+ * if signal is required, this field contains signal *
+ * number which would be sent. *
+ * In other command, this field is ignored. */
+};
+
+/*
+ * ####################################
+ * Data Type
+ * ####################################
+ */
+typedef void (*timer_callback)(unsigned long arg);
+
+extern int ifxmips_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
+extern int ifxmips_free_timer(unsigned int);
+extern int ifxmips_start_timer(unsigned int, int);
+extern int ifxmips_stop_timer(unsigned int);
+extern int ifxmips_reset_counter_flags(u32 timer, u32 flags);
+extern int ifxmips_get_count_value(unsigned int, unsigned long *);
+extern u32 ifxmips_cal_divider(unsigned long);
+extern int ifxmips_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
+extern int ifxmips_set_counter(unsigned int timer, unsigned int flag,
+ u32 reload, unsigned long arg1, unsigned long arg2);
+
+#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/xway.h
@@ -0,0 +1,121 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2005 infineon
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#ifdef CONFIG_SOC_LANTIQ_XWAY
+
+#ifndef _LQ_XWAY_H__
+#define _LQ_XWAY_H__
+
+#include <lantiq.h>
+
+/* request a non-gpio and set the PIO config */
+extern int lq_gpio_request(unsigned int pin, unsigned int alt0,
+ unsigned int alt1, unsigned int dir, const char *name);
+extern int lq_gpio_setconfig(unsigned int pin, unsigned int reg, unsigned int val);
+
+extern void lq_pmu_enable(unsigned int module);
+extern void lq_pmu_disable(unsigned int module);
+
+extern unsigned int lq_get_fpi_bus_clock(int bus);
+
+#define BOARD_SYSTEM_TYPE "LANTIQ"
+
+/*------------ Chip IDs */
+#define SOC_ID_DANUBE1 0x129
+#define SOC_ID_DANUBE2 0x12B
+#define SOC_ID_TWINPASS 0x12D
+#define SOC_ID_ARX188 0x16C
+#define SOC_ID_ARX168 0x16D
+#define SOC_ID_ARX182 0x16F
+
+/*------------ SoC Types */
+#define SOC_TYPE_DANUBE 0x01
+#define SOC_TYPE_TWINPASS 0x02
+#define SOC_TYPE_AR9 0x03
+
+/*------------ ASC0/1 */
+#define LQ_ASC0_BASE 0x1E100400
+#define LQ_ASC1_BASE 0x1E100C00
+#define LQ_ASC_SIZE 0x400
+
+/*------------ RCU */
+#define LQ_RCU_BASE_ADDR 0xBF203000
+
+/*------------ GPTU */
+#define LQ_GPTU_BASE_ADDR 0xB8000300
+
+/*------------ EBU */
+#define LQ_EBU_GPIO_START 0x14000000
+#define LQ_EBU_GPIO_SIZE 0x1000
+
+#define LQ_EBU_BASE_ADDR 0xBE105300
+
+#define LQ_EBU_BUSCON0 ((u32 *)(LQ_EBU_BASE_ADDR + 0x0060))
+#define LQ_EBU_PCC_CON ((u32 *)(LQ_EBU_BASE_ADDR + 0x0090))
+#define LQ_EBU_PCC_IEN ((u32 *)(LQ_EBU_BASE_ADDR + 0x00A4))
+#define LQ_EBU_PCC_ISTAT ((u32 *)(LQ_EBU_BASE_ADDR + 0x00A0))
+#define LQ_EBU_BUSCON1 ((u32 *)(LQ_EBU_BASE_ADDR + 0x0064))
+#define LQ_EBU_ADDRSEL1 ((u32 *)(LQ_EBU_BASE_ADDR + 0x0024))
+
+#define EBU_WRDIS 0x80000000
+
+/*------------ CGU */
+#define LQ_CGU_BASE_ADDR (KSEG1 + 0x1F103000)
+
+/*------------ PMU */
+#define LQ_PMU_BASE_ADDR (KSEG1 + 0x1F102000)
+
+#define PMU_DMA 0x0020
+#define PMU_USB 0x8041
+#define PMU_LED 0x0800
+#define PMU_GPT 0x1000
+#define PMU_PPE 0x2000
+#define PMU_FPI 0x4000
+#define PMU_SWITCH 0x10000000
+
+/*------------ ETOP */
+#define LQ_PPE32_BASE_ADDR 0xBE180000
+#define LQ_PPE32_SIZE 0x40000
+
+/*------------ DMA */
+#define LQ_DMA_BASE_ADDR 0xBE104100
+
+/*------------ PCI */
+#define PCI_CR_PR_BASE_ADDR (KSEG1 + 0x1E105400)
+#define PCI_CS_PR_BASE_ADDR (KSEG1 + 0x17000000)
+
+/*------------ WDT */
+#define LQ_WDT_BASE 0x1F880000
+#define LQ_WDT_SIZE 0x400
+
+/*------------ Serial To Parallel conversion */
+#define LQ_STP_BASE 0x1E100BB0
+#define LQ_STP_SIZE 0x40
+
+/*------------ GPIO */
+#define LQ_GPIO0_BASE_ADDR 0x1E100B10
+#define LQ_GPIO1_BASE_ADDR 0x1E100B40
+#define LQ_GPIO_SIZE 0x30
+
+/*------------ SSC */
+#define LQ_SSC_BASE_ADDR (KSEG1 + 0x1e100800)
+
+/*------------ MEI */
+#define LQ_MEI_BASE_ADDR (KSEG1 + 0x1E116000)
+
+/*------------ DEU */
+#define LQ_DEU_BASE (KSEG1 + 0x1E103100)
+
+/*------------ MPS */
+#define LQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
+#define LQ_MPS_CHIPID ((u32 *)(LQ_MPS_BASE_ADDR + 0x0344))
+
+#endif
+
+#endif
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
@@ -0,0 +1,144 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) 2005 infineon
+ * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ *
+ */
+#ifndef _LQ_DMA_H__
+#define _LQ_DMA_H__
+
+#define RCV_INT 1
+#define TX_BUF_FULL_INT 2
+#define TRANSMIT_CPT_INT 4
+#define LQ_DMA_CH_ON 1
+#define LQ_DMA_CH_OFF 0
+#define LQ_DMA_CH_DEFAULT_WEIGHT 100
+
+enum attr_t{
+ TX = 0,
+ RX = 1,
+ RESERVED = 2,
+ DEFAULT = 3,
+};
+
+#define DMA_OWN 1
+#define CPU_OWN 0
+#define DMA_MAJOR 250
+
+#define DMA_DESC_OWN_CPU 0x0
+#define DMA_DESC_OWN_DMA 0x80000000
+#define DMA_DESC_CPT_SET 0x40000000
+#define DMA_DESC_SOP_SET 0x20000000
+#define DMA_DESC_EOP_SET 0x10000000
+
+#define MISCFG_MASK 0x40
+#define RDERR_MASK 0x20
+#define CHOFF_MASK 0x10
+#define DESCPT_MASK 0x8
+#define DUR_MASK 0x4
+#define EOP_MASK 0x2
+
+#define DMA_DROP_MASK (1<<31)
+
+#define LQ_DMA_RX -1
+#define LQ_DMA_TX 1
+
+struct dma_chan_map {
+ const char *dev_name;
+ enum attr_t dir;
+ int pri;
+ int irq;
+ int rel_chan_no;
+};
+
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+struct rx_desc {
+ u32 data_length:16;
+ volatile u32 reserved:7;
+ volatile u32 byte_offset:2;
+ volatile u32 Burst_length_offset:3;
+ volatile u32 EoP:1;
+ volatile u32 Res:1;
+ volatile u32 C:1;
+ volatile u32 OWN:1;
+ volatile u32 Data_Pointer; /* fixme: should be 28 bits here */
+};
+
+struct tx_desc {
+ volatile u32 data_length:16;
+ volatile u32 reserved1:7;
+ volatile u32 byte_offset:5;
+ volatile u32 EoP:1;
+ volatile u32 SoP:1;
+ volatile u32 C:1;
+ volatile u32 OWN:1;
+ volatile u32 Data_Pointer; /* fixme: should be 28 bits here */
+};
+#else /* BIG */
+struct rx_desc {
+ union {
+ struct {
+ volatile u32 OWN:1;
+ volatile u32 C:1;
+ volatile u32 SoP:1;
+ volatile u32 EoP:1;
+ volatile u32 Burst_length_offset:3;
+ volatile u32 byte_offset:2;
+ volatile u32 reserve:7;
+ volatile u32 data_length:16;
+ } field;
+ volatile u32 word;
+ } status;
+ volatile u32 Data_Pointer;
+};
+
+struct tx_desc {
+ union {
+ struct {
+ volatile u32 OWN:1;
+ volatile u32 C:1;
+ volatile u32 SoP:1;
+ volatile u32 EoP:1;
+ volatile u32 byte_offset:5;
+ volatile u32 reserved:7;
+ volatile u32 data_length:16;
+ } field;
+ volatile u32 word;
+ } status;
+ volatile u32 Data_Pointer;
+};
+#endif /* ENDIAN */
+
+struct dma_channel_info {
+ /* relative channel number */
+ int rel_chan_no;
+ /* class for this channel for QoS */
+ int pri;
+ /* specify byte_offset */
+ int byte_offset;
+ /* direction */
+ int dir;
+ /* irq number */
+ int irq;
+ /* descriptor parameter */
+ int desc_base;
+ int desc_len;
+ int curr_desc;
+ int prev_desc; /* only used if it is a tx channel*/
+ /* weight setting for WFQ algorithm*/
+ int weight;
+ int default_weight;
+ int packet_size;
+ int burst_len;
+ /* on or off of this channel */
+ int control;
+ /* optional information for the upper layer devices */
+#if defined(CONFIG_LQ_ETHERNET_D2) || defined(CONFIG_LQ_PPA)
+ void *opt[64];
+#else
+ void *opt[25];
+#endif
+ /* Pointer to the peripheral device who is using this channel */
+ void *dma_dev;
+ /* channel operations */
+ void (*open)(struct dma_channel_info *pCh);
+ void (*close)(struct dma_channel_info *pCh);
+ void (*reset)(struct dma_channel_info *pCh);
+ void (*enable_irq)(struct dma_channel_info *pCh);
+ void (*disable_irq)(struct dma_channel_info *pCh);
+};
+
+struct dma_device_info {
+ /* device name of this peripheral */
+ char device_name[15];
+ int reserved;
+ int tx_burst_len;
+ int rx_burst_len;
+ int default_weight;
+ int current_tx_chan;
+ int current_rx_chan;
+ int num_tx_chan;
+ int num_rx_chan;
+ int max_rx_chan_num;
+ int max_tx_chan_num;
+ struct dma_channel_info *tx_chan[20];
+ struct dma_channel_info *rx_chan[20];
+ /*functions, optional*/
+ u8 *(*buffer_alloc)(int len, int *offset, void **opt);
+ void (*buffer_free)(u8 *dataptr, void *opt);
+ int (*intr_handler)(struct dma_device_info *info, int status);
+ void *priv; /* used by peripheral driver only */
+};
+
+struct dma_device_info *dma_device_reserve(char *dev_name);
+void dma_device_release(struct dma_device_info *dev);
+void dma_device_register(struct dma_device_info *info);
+void dma_device_unregister(struct dma_device_info *info);
+int dma_device_read(struct dma_device_info *info, u8 **dataptr, void **opt);
+int dma_device_write(struct dma_device_info *info, u8 *dataptr, int len,
+ void *opt);
+
+#endif
+
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/xway_irq.h
@@ -0,0 +1,62 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef _LANTIQ_XWAY_IRQ_H__
+#define _LANTIQ_XWAY_IRQ_H__
+
+#define INT_NUM_IRQ0 8
+#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
+#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32)
+#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64)
+#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96)
+#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
+#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
+
+#define LQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 7))
+#define LQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 7) + 2)
+#define LQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 7) + 3)
+
+#define LQ_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
+#define LQ_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
+#define LQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
+
+#define LQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21)
+#define LQ_MEI_INT (INT_NUM_IM1_IRL0 + 23)
+
+#define LQ_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
+#define LQ_USB_INT (INT_NUM_IM1_IRL0 + 22)
+#define LQ_USB_OC_INT (INT_NUM_IM4_IRL0 + 23)
+
+#define MIPS_CPU_TIMER_IRQ 7
+
+#define LQ_DMA_CH0_INT (INT_NUM_IM2_IRL0)
+#define LQ_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
+#define LQ_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
+#define LQ_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
+#define LQ_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
+#define LQ_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
+#define LQ_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
+#define LQ_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
+#define LQ_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
+#define LQ_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
+#define LQ_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
+#define LQ_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
+#define LQ_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
+#define LQ_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
+#define LQ_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
+#define LQ_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
+#define LQ_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
+#define LQ_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
+#define LQ_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
+#define LQ_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
+
+#define LQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24)
+
+#define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14)
+
+#endif

View file

@ -0,0 +1,93 @@
--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
@@ -33,4 +33,19 @@ endchoice
source "arch/mips/lantiq/falcon/Kconfig"
source "arch/mips/lantiq/xway/Kconfig"
+if EARLY_PRINTK
+choice
+ prompt "Early printk port"
+ default LANTIQ_PROM_ASC1
+ help
+ Choose which serial port is used, until the console driver is loaded
+
+config LANTIQ_PROM_ASC0
+ bool "ASC0"
+
+config LANTIQ_PROM_ASC1
+ bool "ASC1"
+endchoice
+endif
+
endif
--- /dev/null
+++ b/arch/mips/lantiq/early_printk.c
@@ -0,0 +1,68 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/init.h>
+#include <linux/cpu.h>
+
+#include <lantiq.h>
+
+#ifdef CONFIG_SOC_LANTIQ_XWAY
+#include <xway.h>
+#ifdef CONFIG_LANTIQ_PROM_ASC0
+#define LQ_ASC_BASE KSEG1ADDR(LQ_ASC0_BASE)
+#else
+#define LQ_ASC_BASE KSEG1ADDR(LQ_ASC1_BASE)
+#endif
+
+#elif CONFIG_SOC_LANTIQ_FALCON
+#include <falcon/gpon_reg_base.h>
+#ifdef CONFIG_LANTIQ_PROM_ASC0
+#define LQ_ASC_BASE GPON_ASC0_BASE
+#else
+#define LQ_ASC_BASE GPON_ASC1_BASE
+#endif
+
+#endif
+
+#define ASC_BUF 1024
+#define LQ_ASC_FSTAT 0x0048
+#define LQ_ASC_TBUF 0x0020
+#define TXMASK 0x3F00
+#define TXOFFSET 8
+
+static char buf[ASC_BUF];
+
+void
+prom_putchar(char c)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ while ((lq_r32((u32 *)(LQ_ASC_BASE + LQ_ASC_FSTAT)) & TXMASK) >> TXOFFSET);
+
+ if (c == '\n')
+ lq_w32('\r', (u32 *)(LQ_ASC_BASE + LQ_ASC_TBUF));
+ lq_w32(c, (u32 *)(LQ_ASC_BASE + LQ_ASC_TBUF));
+ local_irq_restore(flags);
+}
+
+void
+early_printf(const char *fmt, ...)
+{
+ va_list args;
+ int l;
+ char *p, *buf_end;
+
+ va_start(args, fmt);
+ l = vsnprintf(buf, ASC_BUF, fmt, args);
+ va_end(args);
+ buf_end = buf + l;
+
+ for (p = buf; p < buf_end; p++)
+ prom_putchar(*p);
+}

View file

@ -0,0 +1,55 @@
--- a/arch/mips/lantiq/setup.c
+++ b/arch/mips/lantiq/setup.c
@@ -13,7 +13,8 @@
#include <linux/ioport.h>
#include <lantiq.h>
-#include <lantiq_regs.h>
+
+#include <machine.h>
void __init
plat_mem_setup(void)
@@ -46,3 +47,25 @@ plat_mem_setup(void)
memsize *= 1024 * 1024;
add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
}
+
+static int __init
+lq_machine_setup(void)
+{
+ mips_machine_setup();
+ return 0;
+}
+
+static void __init
+mach_generic_init(void)
+{
+}
+
+MIPS_MACHINE(LANTIQ_MACH_GENERIC,
+ "Generic",
+ "Generic",
+ mach_generic_init);
+
+arch_initcall(lq_machine_setup);
+
+/* for backward compatibility, define "board=" as alias for "machtype=" */
+__setup("board=", mips_machtype_setup);
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/machine.h
@@ -0,0 +1,14 @@
+#include <asm/mips_machine.h>
+
+enum lantiq_mach_type {
+ LANTIQ_MACH_GENERIC,
+
+ /* FALCON */
+ LANTIQ_MACH_EASY98000, /* Falcon Eval Board, NOR Flash */
+ LANTIQ_MACH_EASY98020, /* Falcon Reference Board */
+
+ /* XWAY */
+ LANTIQ_MACH_EASY4010, /* Twinpass evalkit */
+ LANTIQ_MACH_EASY50712, /* Danube evalkit */
+ LANTIQ_MACH_EASY50812, /* AR9 eval board */
+};

View file

@ -0,0 +1,799 @@
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -1397,6 +1397,14 @@
help
Support for Console on the NWP serial ports.
+config SERIAL_LANTIQ
+ bool "Lantiq serial driver"
+ depends on LANTIQ
+ select SERIAL_CORE
+ select SERIAL_CORE_CONSOLE
+ help
+ Driver for the Lantiq SoC ASC hardware
+
config SERIAL_QE
tristate "Freescale QUICC Engine serial port support"
depends on QUICC_ENGINE
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -84,3 +84,4 @@
obj-$(CONFIG_SERIAL_GRLIB_GAISLER_APBUART) += apbuart.o
obj-$(CONFIG_SERIAL_ALTERA_JTAGUART) += altera_jtaguart.o
obj-$(CONFIG_SERIAL_ALTERA_UART) += altera_uart.o
+obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o
--- /dev/null
+++ b/drivers/serial/lantiq.c
@@ -0,0 +1,772 @@
+/*
+ * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Copyright (C) 2004 Infineon IFAP DC COM CPE
+ * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2010 Thomas Langer, Lantiq Deutschland
+ */
+
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/sysrq.h>
+#include <linux/device.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+
+#define lq_r32(reg) __raw_readl(reg)
+#define lq_r8(reg) __raw_readb(reg)
+#define lq_w32(val, reg) __raw_writel(val, reg)
+#define lq_w8(val, reg) __raw_writeb(val, reg)
+#define lq_w32_mask(clear, set, reg) lq_w32((lq_r32(reg) & ~(clear)) | (set), reg)
+
+#define PORT_IFXMIPSASC 111
+#define MAXPORTS 2
+
+#define UART_DUMMY_UER_RX 1
+
+#define DRVNAME "lq_asc"
+
+#ifdef __BIG_ENDIAN
+#define IFXMIPS_ASC_TBUF (0x0020 + 3)
+#define IFXMIPS_ASC_RBUF (0x0024 + 3)
+#else
+#define IFXMIPS_ASC_TBUF 0x0020
+#define IFXMIPS_ASC_RBUF 0x0024
+#endif
+
+#define IFXMIPS_ASC_FSTAT 0x0048
+#define IFXMIPS_ASC_WHBSTATE 0x0018
+#define IFXMIPS_ASC_STATE 0x0014
+#define IFXMIPS_ASC_IRNCR 0x00F8
+#define IFXMIPS_ASC_CLC 0x0000
+#define IFXMIPS_ASC_ID 0x0008
+#define IFXMIPS_ASC_PISEL 0x0004
+#define IFXMIPS_ASC_TXFCON 0x0044
+#define IFXMIPS_ASC_RXFCON 0x0040
+#define IFXMIPS_ASC_CON 0x0010
+#define IFXMIPS_ASC_BG 0x0050
+#define IFXMIPS_ASC_IRNREN 0x00F4
+
+#define ASC_IRNREN_TX 0x1
+#define ASC_IRNREN_RX 0x2
+#define ASC_IRNREN_ERR 0x4
+#define ASC_IRNREN_TX_BUF 0x8
+#define ASC_IRNCR_TIR 0x1
+#define ASC_IRNCR_RIR 0x2
+#define ASC_IRNCR_EIR 0x4
+
+#define ASCOPT_CSIZE 0x3
+#define ASCOPT_CS7 0x1
+#define ASCOPT_CS8 0x2
+#define ASCOPT_PARENB 0x4
+#define ASCOPT_STOPB 0x8
+#define ASCOPT_PARODD 0x0
+#define ASCOPT_CREAD 0x20
+#define TXFIFO_FL 1
+#define RXFIFO_FL 1
+#define ASCCLC_DISS 0x2
+#define ASCCLC_RMCMASK 0x0000FF00
+#define ASCCLC_RMCOFFSET 8
+#define ASCCON_M_8ASYNC 0x0
+#define ASCCON_M_7ASYNC 0x2
+#define ASCCON_ODD 0x00000020
+#define ASCCON_STP 0x00000080
+#define ASCCON_BRS 0x00000100
+#define ASCCON_FDE 0x00000200
+#define ASCCON_R 0x00008000
+#define ASCCON_FEN 0x00020000
+#define ASCCON_ROEN 0x00080000
+#define ASCCON_TOEN 0x00100000
+#define ASCSTATE_PE 0x00010000
+#define ASCSTATE_FE 0x00020000
+#define ASCSTATE_ROE 0x00080000
+#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
+#define ASCWHBSTATE_CLRREN 0x00000001
+#define ASCWHBSTATE_SETREN 0x00000002
+#define ASCWHBSTATE_CLRPE 0x00000004
+#define ASCWHBSTATE_CLRFE 0x00000008
+#define ASCWHBSTATE_CLRROE 0x00000020
+#define ASCTXFCON_TXFEN 0x0001
+#define ASCTXFCON_TXFFLU 0x0002
+#define ASCTXFCON_TXFITLMASK 0x3F00
+#define ASCTXFCON_TXFITLOFF 8
+#define ASCRXFCON_RXFEN 0x0001
+#define ASCRXFCON_RXFFLU 0x0002
+#define ASCRXFCON_RXFITLMASK 0x3F00
+#define ASCRXFCON_RXFITLOFF 8
+#define ASCFSTAT_RXFFLMASK 0x003F
+#define ASCFSTAT_TXFFLMASK 0x3F00
+#define ASCFSTAT_TXFFLOFF 8
+#define ASCFSTAT_RXFREEMASK 0x003F0000
+#define ASCFSTAT_RXFREEOFF 16
+#define ASCFSTAT_TXFREEMASK 0x3F000000
+#define ASCFSTAT_TXFREEOFF 24
+
+static void lqasc_tx_chars(struct uart_port *port);
+extern void prom_printf(const char *fmt, ...);
+static struct lq_uart_port *lqasc_port[2];
+static struct uart_driver lqasc_reg;
+
+struct lq_uart_port {
+ struct uart_port port;
+ struct clk *clk;
+ unsigned int tx_irq;
+ unsigned int rx_irq;
+ unsigned int err_irq;
+};
+
+static inline struct
+lq_uart_port *to_lq_uart_port(struct uart_port *port)
+{
+ return container_of(port, struct lq_uart_port, port);
+}
+
+static void
+lqasc_stop_tx(struct uart_port *port)
+{
+ return;
+}
+
+static void
+lqasc_start_tx(struct uart_port *port)
+{
+ unsigned long flags;
+ local_irq_save(flags);
+ lqasc_tx_chars(port);
+ local_irq_restore(flags);
+ return;
+}
+
+static void
+lqasc_stop_rx(struct uart_port *port)
+{
+ lq_w32(ASCWHBSTATE_CLRREN, port->membase + IFXMIPS_ASC_WHBSTATE);
+}
+
+static void
+lqasc_enable_ms(struct uart_port *port)
+{
+}
+
+static void
+lqasc_rx_chars(struct uart_port *port)
+{
+ struct tty_struct *tty = port->state->port.tty;
+ unsigned int ch = 0, rsr = 0, fifocnt;
+
+ fifocnt = lq_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_RXFFLMASK;
+ while (fifocnt--) {
+ u8 flag = TTY_NORMAL;
+ ch = lq_r8(port->membase + IFXMIPS_ASC_RBUF);
+ rsr = (lq_r32(port->membase + IFXMIPS_ASC_STATE)
+ & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
+ tty_flip_buffer_push(tty);
+ port->icount.rx++;
+
+ /*
+ * Note that the error handling code is
+ * out of the main execution path
+ */
+ if (rsr & ASCSTATE_ANY) {
+ if (rsr & ASCSTATE_PE) {
+ port->icount.parity++;
+ lq_w32_mask(0, ASCWHBSTATE_CLRPE,
+ port->membase + IFXMIPS_ASC_WHBSTATE);
+ } else if (rsr & ASCSTATE_FE) {
+ port->icount.frame++;
+ lq_w32_mask(0, ASCWHBSTATE_CLRFE,
+ port->membase + IFXMIPS_ASC_WHBSTATE);
+ }
+ if (rsr & ASCSTATE_ROE) {
+ port->icount.overrun++;
+ lq_w32_mask(0, ASCWHBSTATE_CLRROE,
+ port->membase + IFXMIPS_ASC_WHBSTATE);
+ }
+
+ rsr &= port->read_status_mask;
+
+ if (rsr & ASCSTATE_PE)
+ flag = TTY_PARITY;
+ else if (rsr & ASCSTATE_FE)
+ flag = TTY_FRAME;
+ }
+
+ if ((rsr & port->ignore_status_mask) == 0)
+ tty_insert_flip_char(tty, ch, flag);
+
+ if (rsr & ASCSTATE_ROE)
+ /*
+ * Overrun is special, since it's reported
+ * immediately, and doesn't affect the current
+ * character
+ */
+ tty_insert_flip_char(tty, 0, TTY_OVERRUN);
+ }
+ if (ch != 0)
+ tty_flip_buffer_push(tty);
+ return;
+}
+
+static void
+lqasc_tx_chars(struct uart_port *port)
+{
+ struct circ_buf *xmit = &port->state->xmit;
+ if (uart_tx_stopped(port)) {
+ lqasc_stop_tx(port);
+ return;
+ }
+
+ while (((lq_r32(port->membase + IFXMIPS_ASC_FSTAT) &
+ ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) {
+ if (port->x_char) {
+ lq_w8(port->x_char, port->membase + IFXMIPS_ASC_TBUF);
+ port->icount.tx++;
+ port->x_char = 0;
+ continue;
+ }
+
+ if (uart_circ_empty(xmit))
+ break;
+
+ lq_w8(port->state->xmit.buf[port->state->xmit.tail],
+ port->membase + IFXMIPS_ASC_TBUF);
+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+ port->icount.tx++;
+ }
+
+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+ uart_write_wakeup(port);
+}
+
+static irqreturn_t
+lqasc_tx_int(int irq, void *_port)
+{
+ struct uart_port *port = (struct uart_port *)_port;
+ lq_w32(ASC_IRNCR_TIR, port->membase + IFXMIPS_ASC_IRNCR);
+ lqasc_start_tx(port);
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t
+lqasc_err_int(int irq, void *_port)
+{
+ struct uart_port *port = (struct uart_port *)_port;
+ /* clear any pending interrupts */
+ lq_w32_mask(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE,
+ port->membase + IFXMIPS_ASC_WHBSTATE);
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t
+lqasc_rx_int(int irq, void *_port)
+{
+ struct uart_port *port = (struct uart_port *)_port;
+ lq_w32(ASC_IRNCR_RIR, port->membase + IFXMIPS_ASC_IRNCR);
+ lqasc_rx_chars(port);
+ return IRQ_HANDLED;
+}
+
+static unsigned int
+lqasc_tx_empty(struct uart_port *port)
+{
+ int status;
+ status = lq_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK;
+ return status ? 0 : TIOCSER_TEMT;
+}
+
+static unsigned int
+lqasc_get_mctrl(struct uart_port *port)
+{
+ return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
+}
+
+static void
+lqasc_set_mctrl(struct uart_port *port, u_int mctrl)
+{
+}
+
+static void
+lqasc_break_ctl(struct uart_port *port, int break_state)
+{
+}
+
+static int
+lqasc_startup(struct uart_port *port)
+{
+ struct lq_uart_port *ifx_port = to_lq_uart_port(port);
+ int retval;
+
+ port->uartclk = clk_get_rate(ifx_port->clk);
+
+ lq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET),
+ port->membase + IFXMIPS_ASC_CLC);
+
+ lq_w32(0, port->membase + IFXMIPS_ASC_PISEL);
+ lq_w32(
+ ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) |
+ ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU,
+ port->membase + IFXMIPS_ASC_TXFCON);
+ lq_w32(
+ ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK)
+ | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU,
+ port->membase + IFXMIPS_ASC_RXFCON);
+ /* make sure other settings are written to hardware before setting enable bits */
+ wmb();
+ lq_w32_mask(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN |
+ ASCCON_ROEN, port->membase + IFXMIPS_ASC_CON);
+
+ retval = request_irq(ifx_port->tx_irq, lqasc_tx_int,
+ IRQF_DISABLED, "asc_tx", port);
+ if (retval) {
+ pr_err("failed to request lqasc_tx_int\n");
+ return retval;
+ }
+
+ retval = request_irq(ifx_port->rx_irq, lqasc_rx_int,
+ IRQF_DISABLED, "asc_rx", port);
+ if (retval) {
+ pr_err("failed to request lqasc_rx_int\n");
+ goto err1;
+ }
+
+ retval = request_irq(ifx_port->err_irq, lqasc_err_int,
+ IRQF_DISABLED, "asc_err", port);
+ if (retval) {
+ pr_err("failed to request lqasc_err_int\n");
+ goto err2;
+ }
+
+ lq_w32(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX,
+ port->membase + IFXMIPS_ASC_IRNREN);
+ return 0;
+
+err2:
+ free_irq(ifx_port->rx_irq, port);
+err1:
+ free_irq(ifx_port->tx_irq, port);
+ return retval;
+}
+
+static void
+lqasc_shutdown(struct uart_port *port)
+{
+ struct lq_uart_port *ifx_port = to_lq_uart_port(port);
+ free_irq(ifx_port->tx_irq, port);
+ free_irq(ifx_port->rx_irq, port);
+ free_irq(ifx_port->err_irq, port);
+
+ lq_w32(0, port->membase + IFXMIPS_ASC_CON);
+ lq_w32_mask(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU,
+ port->membase + IFXMIPS_ASC_RXFCON);
+ lq_w32_mask(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU,
+ port->membase + IFXMIPS_ASC_TXFCON);
+}
+
+static void
+lqasc_set_termios(struct uart_port *port,
+ struct ktermios *new, struct ktermios *old)
+{
+ unsigned int cflag;
+ unsigned int iflag;
+ unsigned int quot;
+ unsigned int baud;
+ unsigned int con = 0;
+ unsigned long flags;
+
+ cflag = new->c_cflag;
+ iflag = new->c_iflag;
+
+ switch (cflag & CSIZE) {
+ case CS7:
+ con = ASCCON_M_7ASYNC;
+ break;
+
+ case CS5:
+ case CS6:
+ default:
+ con = ASCCON_M_8ASYNC;
+ break;
+ }
+
+ if (cflag & CSTOPB)
+ con |= ASCCON_STP;
+
+ if (cflag & PARENB) {
+ if (!(cflag & PARODD))
+ con &= ~ASCCON_ODD;
+ else
+ con |= ASCCON_ODD;
+ }
+
+ port->read_status_mask = ASCSTATE_ROE;
+ if (iflag & INPCK)
+ port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
+
+ port->ignore_status_mask = 0;
+ if (iflag & IGNPAR)
+ port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
+
+ if (iflag & IGNBRK) {
+ /*
+ * If we're ignoring parity and break indicators,
+ * ignore overruns too (for real raw support).
+ */
+ if (iflag & IGNPAR)
+ port->ignore_status_mask |= ASCSTATE_ROE;
+ }
+
+ if ((cflag & CREAD) == 0)
+ port->ignore_status_mask |= UART_DUMMY_UER_RX;
+
+ /* set error signals - framing, parity and overrun, enable receiver */
+ con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
+
+ local_irq_save(flags);
+
+ /* set up CON */
+ lq_w32_mask(0, con, port->membase + IFXMIPS_ASC_CON);
+
+ /* Set baud rate - take a divider of 2 into account */
+ baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
+ quot = uart_get_divisor(port, baud);
+ quot = quot / 2 - 1;
+
+ /* disable the baudrate generator */
+ lq_w32_mask(ASCCON_R, 0, port->membase + IFXMIPS_ASC_CON);
+
+ /* make sure the fractional divider is off */
+ lq_w32_mask(ASCCON_FDE, 0, port->membase + IFXMIPS_ASC_CON);
+
+ /* set up to use divisor of 2 */
+ lq_w32_mask(ASCCON_BRS, 0, port->membase + IFXMIPS_ASC_CON);
+
+ /* now we can write the new baudrate into the register */
+ lq_w32(quot, port->membase + IFXMIPS_ASC_BG);
+
+ /* turn the baudrate generator back on */
+ lq_w32_mask(0, ASCCON_R, port->membase + IFXMIPS_ASC_CON);
+
+ /* enable rx */
+ lq_w32(ASCWHBSTATE_SETREN, port->membase + IFXMIPS_ASC_WHBSTATE);
+
+ local_irq_restore(flags);
+}
+
+static const char*
+lqasc_type(struct uart_port *port)
+{
+ if (port->type == PORT_IFXMIPSASC)
+ return DRVNAME;
+ else
+ return NULL;
+}
+
+static void
+lqasc_release_port(struct uart_port *port)
+{
+ if (port->flags & UPF_IOREMAP) {
+ iounmap(port->membase);
+ port->membase = NULL;
+ }
+}
+
+static int
+lqasc_request_port(struct uart_port *port)
+{
+ struct platform_device *pdev = to_platform_device(port->dev);
+ struct resource *mmres;
+ int size;
+
+ mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!mmres)
+ return -ENODEV;
+ size = resource_size(mmres);
+
+ if (port->flags & UPF_IOREMAP) {
+ port->membase = ioremap_nocache(port->mapbase, size);
+ if (port->membase == NULL)
+ return -ENOMEM;
+ }
+ return 0;
+}
+
+static void
+lqasc_config_port(struct uart_port *port, int flags)
+{
+ if (flags & UART_CONFIG_TYPE) {
+ port->type = PORT_IFXMIPSASC;
+ lqasc_request_port(port);
+ }
+}
+
+static int
+lqasc_verify_port(struct uart_port *port,
+ struct serial_struct *ser)
+{
+ int ret = 0;
+ if (ser->type != PORT_UNKNOWN && ser->type != PORT_IFXMIPSASC)
+ ret = -EINVAL;
+ if (ser->irq < 0 || ser->irq >= NR_IRQS)
+ ret = -EINVAL;
+ if (ser->baud_base < 9600)
+ ret = -EINVAL;
+ return ret;
+}
+
+static struct uart_ops lqasc_pops = {
+ .tx_empty = lqasc_tx_empty,
+ .set_mctrl = lqasc_set_mctrl,
+ .get_mctrl = lqasc_get_mctrl,
+ .stop_tx = lqasc_stop_tx,
+ .start_tx = lqasc_start_tx,
+ .stop_rx = lqasc_stop_rx,
+ .enable_ms = lqasc_enable_ms,
+ .break_ctl = lqasc_break_ctl,
+ .startup = lqasc_startup,
+ .shutdown = lqasc_shutdown,
+ .set_termios = lqasc_set_termios,
+ .type = lqasc_type,
+ .release_port = lqasc_release_port,
+ .request_port = lqasc_request_port,
+ .config_port = lqasc_config_port,
+ .verify_port = lqasc_verify_port,
+};
+
+static void
+lqasc_console_putchar(struct uart_port *port, int ch)
+{
+ int fifofree;
+
+ if (!port->membase)
+ return;
+
+ do {
+ fifofree = (lq_r32(port->membase + IFXMIPS_ASC_FSTAT)
+ & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF;
+ } while (fifofree == 0);
+ lq_w8(ch, port->membase + IFXMIPS_ASC_TBUF);
+}
+
+
+static void
+lqasc_console_write(struct console *co, const char *s, u_int count)
+{
+ struct lq_uart_port *ifx_port;
+ struct uart_port *port;
+ unsigned long flags;
+
+ if (co->index >= MAXPORTS)
+ return;
+
+ ifx_port = lqasc_port[co->index];
+ if (!ifx_port)
+ return;
+
+ port = &ifx_port->port;
+
+ local_irq_save(flags);
+ uart_console_write(port, s, count, lqasc_console_putchar);
+ local_irq_restore(flags);
+}
+
+static int __init
+lqasc_console_setup(struct console *co, char *options)
+{
+ struct lq_uart_port *ifx_port;
+ struct uart_port *port;
+ int baud = 115200;
+ int bits = 8;
+ int parity = 'n';
+ int flow = 'n';
+
+ if (co->index >= MAXPORTS)
+ return -ENODEV;
+
+ ifx_port = lqasc_port[co->index];
+ if (!ifx_port)
+ return -ENODEV;
+
+ port = &ifx_port->port;
+
+ port->uartclk = clk_get_rate(ifx_port->clk);
+
+ if (options)
+ uart_parse_options(options, &baud, &parity, &bits, &flow);
+ return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+static struct console lqasc_console = {
+ .name = "ttyS",
+ .write = lqasc_console_write,
+ .device = uart_console_device,
+ .setup = lqasc_console_setup,
+ .flags = CON_PRINTBUFFER,
+ .index = -1,
+ .data = &lqasc_reg,
+};
+
+static int __init
+lqasc_console_init(void)
+{
+ register_console(&lqasc_console);
+ return 0;
+}
+console_initcall(lqasc_console_init);
+
+static struct uart_driver lqasc_reg = {
+ .owner = THIS_MODULE,
+ .driver_name = DRVNAME,
+ .dev_name = "ttyS",
+ .major = TTY_MAJOR,
+ .minor = 64,
+ .nr = MAXPORTS,
+ .cons = &lqasc_console,
+};
+
+static int __devinit
+lqasc_probe(struct platform_device *pdev)
+{
+ struct lq_uart_port *ifx_port;
+ struct uart_port *port;
+ struct resource *mmres, *irqres;
+ int tx_irq, rx_irq, err_irq;
+ struct clk *clk;
+ int ret;
+
+ mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (!mmres || !irqres)
+ return -ENODEV;
+
+ if (pdev->id >= MAXPORTS)
+ return -EBUSY;
+
+ if (lqasc_port[pdev->id] != NULL)
+ return -EBUSY;
+
+ clk = clk_get(&pdev->dev, "fpi");
+ if (IS_ERR(clk)) {
+ pr_err("failed to get fpi clk\n");
+ return -ENOENT;
+ }
+
+ tx_irq = platform_get_irq_byname(pdev, "tx");
+ if (tx_irq < 0) {
+ /* without named resources: assume standard irq scheme */
+ tx_irq = irqres->start;
+ rx_irq = irqres->start+2;
+ err_irq = irqres->start+3;
+ } else {
+ /* other irqs must be named also! */
+ rx_irq = platform_get_irq_byname(pdev, "rx");
+ err_irq = platform_get_irq_byname(pdev, "err");
+ if ((rx_irq < 0) | (err_irq < 0))
+ return -ENODEV;
+ }
+
+ ifx_port = kzalloc(sizeof(struct lq_uart_port), GFP_KERNEL);
+ if (!ifx_port)
+ return -ENOMEM;
+
+ port = &ifx_port->port;
+
+ port->iotype = SERIAL_IO_MEM;
+ port->flags = ASYNC_BOOT_AUTOCONF | UPF_IOREMAP;
+ port->ops = &lqasc_pops;
+ port->fifosize = 16;
+ port->type = PORT_IFXMIPSASC,
+ port->line = pdev->id;
+ port->dev = &pdev->dev;
+
+ port->irq = tx_irq; /* unused, just to be backward-compatibe */
+ port->mapbase = mmres->start;
+
+ ifx_port->clk = clk;
+
+ ifx_port->tx_irq = tx_irq;
+ ifx_port->rx_irq = rx_irq;
+ ifx_port->err_irq = err_irq;
+
+ lqasc_port[pdev->id] = ifx_port;
+ platform_set_drvdata(pdev, ifx_port);
+
+ ret = uart_add_one_port(&lqasc_reg, port);
+
+ return ret;
+}
+
+static int __devexit
+lqasc_remove(struct platform_device *pdev)
+{
+ struct lq_uart_port *ifx_port = platform_get_drvdata(pdev);
+ int ret;
+
+ clk_put(ifx_port->clk);
+ platform_set_drvdata(pdev, NULL);
+ lqasc_port[pdev->id] = NULL;
+ ret = uart_remove_one_port(&lqasc_reg, &ifx_port->port);
+ kfree(ifx_port);
+
+ return 0;
+}
+
+static struct platform_driver lqasc_driver = {
+ .probe = lqasc_probe,
+ .remove = __devexit_p(lqasc_remove),
+
+ .driver = {
+ .name = DRVNAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+int __init
+init_lqasc(void)
+{
+ int ret;
+
+ ret = uart_register_driver(&lqasc_reg);
+ if (ret != 0)
+ return ret;
+
+ ret = platform_driver_register(&lqasc_driver);
+ if (ret != 0)
+ uart_unregister_driver(&lqasc_reg);
+
+ return ret;
+}
+
+void __exit
+exit_lqasc(void)
+{
+ platform_driver_unregister(&lqasc_driver);
+ uart_unregister_driver(&lqasc_reg);
+}
+
+module_init(init_lqasc);
+module_exit(exit_lqasc);
+
+MODULE_DESCRIPTION("Lantiq serial port driver");
+MODULE_LICENSE("GPL");

View file

@ -0,0 +1,245 @@
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -251,6 +251,12 @@
help
Support for flash chips on NETtel/SecureEdge/SnapGear boards.
+config MTD_LANTIQ
+ bool "Lantiq SoC NOR support"
+ depends on LANTIQ && MTD_PARTITIONS
+ help
+ Support for NOR flsh chips on Lantiq SoC
+
config MTD_DILNETPC
tristate "CFI Flash device mapped on DIL/Net PC"
depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -59,3 +59,4 @@
obj-$(CONFIG_MTD_RBTX4939) += rbtx4939-flash.o
obj-$(CONFIG_MTD_VMU) += vmu-flash.o
obj-$(CONFIG_MTD_GPIO_ADDR) += gpio-addr-flash.o
+obj-$(CONFIG_MTD_LANTIQ) += lantiq.o
--- /dev/null
+++ b/drivers/mtd/maps/lantiq.c
@@ -0,0 +1,169 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2004 Liu Peng Infineon IFAP DC COM CPE
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/cfi.h>
+#include <linux/magic.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+
+#include <lantiq.h>
+#include <lantiq_platform.h>
+
+static map_word
+lq_read16(struct map_info *map, unsigned long adr)
+{
+ unsigned long flags;
+ map_word temp;
+ spin_lock_irqsave(&ebu_lock, flags);
+ adr ^= 2;
+ temp.x[0] = *((__u16 *)(map->virt + adr));
+ spin_unlock_irqrestore(&ebu_lock, flags);
+ return temp;
+}
+
+static void
+lq_write16(struct map_info *map, map_word d, unsigned long adr)
+{
+ unsigned long flags;
+ spin_lock_irqsave(&ebu_lock, flags);
+ adr ^= 2;
+ *((__u16 *)(map->virt + adr)) = d.x[0];
+ spin_unlock_irqrestore(&ebu_lock, flags);
+}
+
+void
+lq_copy_from(struct map_info *map, void *to,
+ unsigned long from, ssize_t len)
+{
+ unsigned char *p;
+ unsigned char *to_8;
+ unsigned long flags;
+ spin_lock_irqsave(&ebu_lock, flags);
+ from = (unsigned long)(from + map->virt);
+ p = (unsigned char *) from;
+ to_8 = (unsigned char *) to;
+ while (len--)
+ *to_8++ = *p++;
+ spin_unlock_irqrestore(&ebu_lock, flags);
+}
+
+void
+lq_copy_to(struct map_info *map, unsigned long to,
+ const void *from, ssize_t len)
+{
+ unsigned char *p = (unsigned char *)from;
+ unsigned char *to_8;
+ unsigned long flags;
+ spin_lock_irqsave(&ebu_lock, flags);
+ to += (unsigned long) map->virt;
+ to_8 = (unsigned char *)to;
+ while (len--)
+ *p++ = *to_8++;
+ spin_unlock_irqrestore(&ebu_lock, flags);
+}
+
+static const char *part_probe_types[] = { "cmdlinepart", NULL };
+
+static struct map_info lq_map = {
+ .name = "lq_nor",
+ .bankwidth = 2,
+ .read = lq_read16,
+ .write = lq_write16,
+ .copy_from = lq_copy_from,
+ .copy_to = lq_copy_to,
+};
+
+static int
+lq_mtd_probe(struct platform_device *pdev)
+{
+ struct physmap_flash_data *lq_mtd_data =
+ (struct physmap_flash_data*) dev_get_platdata(&pdev->dev);
+ struct mtd_info *lq_mtd = NULL;
+ struct mtd_partition *parts = NULL;
+ struct resource *res = 0;
+ int nr_parts = 0;
+
+#ifdef CONFIG_SOC_LANTIQ_XWAY
+ lq_w32(lq_r32(LQ_EBU_BUSCON0) & ~EBU_WRDIS, LQ_EBU_BUSCON0);
+#endif
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if(!res)
+ {
+ dev_err(&pdev->dev, "failed to get memory resource");
+ return -ENOENT;
+ }
+ res = request_mem_region(res->start, resource_size(res),
+ dev_name(&pdev->dev));
+ if(!res)
+ {
+ dev_err(&pdev->dev, "failed to request mem resource");
+ return -EBUSY;
+ }
+
+ lq_map.phys = res->start;
+ lq_map.size = resource_size(res);
+ lq_map.virt = ioremap_nocache(lq_map.phys, lq_map.size);
+
+ if (!lq_map.virt ) {
+ dev_err(&pdev->dev, "failed to ioremap!\n");
+ return -EIO;
+ }
+
+ lq_mtd = (struct mtd_info *) do_map_probe("cfi_probe", &lq_map);
+ if (!lq_mtd) {
+ iounmap(lq_map.virt);
+ dev_err(&pdev->dev, "probing failed\n");
+ return -ENXIO;
+ }
+
+ lq_mtd->owner = THIS_MODULE;
+
+ nr_parts = parse_mtd_partitions(lq_mtd, part_probe_types, &parts, 0);
+ if (nr_parts > 0) {
+ dev_info(&pdev->dev, "using %d partitions from cmdline", nr_parts);
+ } else {
+ nr_parts = lq_mtd_data->nr_parts;
+ parts = lq_mtd_data->parts;
+ }
+
+ add_mtd_partitions(lq_mtd, parts, nr_parts);
+ return 0;
+}
+
+static struct platform_driver lq_mtd_driver = {
+ .probe = lq_mtd_probe,
+ .driver = {
+ .name = "lq_nor",
+ .owner = THIS_MODULE,
+ },
+};
+
+int __init
+init_lq_mtd(void)
+{
+ int ret = platform_driver_register(&lq_mtd_driver);
+ if (ret)
+ printk(KERN_INFO "lq_nor: error registering platfom driver");
+ return ret;
+}
+
+module_init(init_lq_mtd);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+MODULE_DESCRIPTION("Lantiq SoC NOR");
--- a/drivers/mtd/chips/cfi_cmdset_0001.c
+++ b/drivers/mtd/chips/cfi_cmdset_0001.c
@@ -41,7 +41,11 @@
/* #define CMDSET0001_DISABLE_WRITE_SUSPEND */
// debugging, turns off buffer write mode if set to 1
-#define FORCE_WORD_WRITE 0
+#ifdef CONFIG_LANTIQ
+# define FORCE_WORD_WRITE 1
+#else
+# define FORCE_WORD_WRITE 0
+#endif
/* Intel chips */
#define I82802AB 0x00ad
@@ -1491,6 +1495,9 @@
int ret=0;
adr += chip->start;
+#ifdef CONFIG_LANTIQ
+ adr ^= 2;
+#endif
switch (mode) {
case FL_WRITING:
--- a/drivers/mtd/chips/cfi_cmdset_0002.c
+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
@@ -40,7 +40,11 @@
#include <linux/mtd/xip.h>
#define AMD_BOOTLOC_BUG
-#define FORCE_WORD_WRITE 0
+#ifdef CONFIG_LANTIQ
+# define FORCE_WORD_WRITE 1
+#else
+# define FORCE_WORD_WRITE 0
+#endif
#define MAX_WORD_RETRIES 3
@@ -1156,6 +1160,10 @@
adr += chip->start;
+#ifdef CONFIG_LANTIQ
+ adr ^= 2;
+#endif
+
mutex_lock(&chip->mutex);
ret = get_chip(map, chip, adr, FL_WRITING);
if (ret) {

View file

@ -0,0 +1,99 @@
--- a/drivers/mtd/maps/lantiq.c
+++ b/drivers/mtd/maps/lantiq.c
@@ -24,6 +24,10 @@
#include <lantiq.h>
#include <lantiq_platform.h>
+#ifdef CONFIG_SOC_LANTIQ_XWAY
+#include <xway.h>
+#endif
+
static map_word
lq_read16(struct map_info *map, unsigned long adr)
{
@@ -77,6 +81,75 @@ lq_copy_to(struct map_info *map, unsigne
spin_unlock_irqrestore(&ebu_lock, flags);
}
+static unsigned long
+find_uImage_size(struct map_info *map, unsigned long offset)
+{
+#define UBOOT_MAGIC 0x56190527
+ unsigned long magic;
+ unsigned long temp;
+ map->copy_from(map, &magic, offset, 4);
+ if (le32_to_cpu(magic) != UBOOT_MAGIC)
+ return 0;
+ map->copy_from(map, &temp, offset + 12, 4);
+ return temp + 0x40;
+}
+
+static int
+detect_squashfs_partition(struct map_info *map, unsigned long offset)
+{
+ unsigned long temp;
+ map->copy_from(map, &temp, offset, 4);
+ return le32_to_cpu(temp) == SQUASHFS_MAGIC;
+}
+
+static struct mtd_partition split_partitions[] = {
+ {
+ .name = "kernel",
+ .offset = 0x0,
+ .size = 0x0,
+ }, {
+ .name = "rootfs",
+ .offset = 0x0,
+ .size = 0x0,
+ },
+};
+
+static int
+mtd_split_linux(struct map_info *map, struct mtd_info *mtd,
+ struct mtd_partition *parts, int nr_parts)
+{
+ int base_part = 0;
+ int i;
+ for (i = 0; i < nr_parts && !base_part; i++) {
+ if(!strcmp("linux", parts[i].name))
+ base_part = i;
+ }
+ if (!base_part)
+ return 0;
+ split_partitions[0].size = find_uImage_size(map, parts[base_part].offset);
+ if (!split_partitions[0].size) {
+ printk(KERN_INFO "lq_nor: no uImage found in linux partition");
+ return -1;
+ }
+ if (!detect_squashfs_partition(map,
+ parts[base_part].offset + split_partitions[0].size)) {
+ split_partitions[0].size &= ~(mtd->erasesize - 1);
+ split_partitions[0].size += mtd->erasesize;
+ }
+ split_partitions[0].offset = parts[base_part].offset;
+ split_partitions[1].offset =
+ parts[base_part].offset + split_partitions[0].size;
+ split_partitions[1].size =
+ parts[base_part].size - split_partitions[0].size;
+
+ base_part++;
+ add_mtd_partitions(mtd, parts, base_part);
+ add_mtd_partitions(mtd, split_partitions, 2);
+ if(nr_parts != base_part)
+ add_mtd_partitions(mtd, &parts[base_part], nr_parts - base_part);
+ return nr_parts + 2;
+}
+
static const char *part_probe_types[] = { "cmdlinepart", NULL };
static struct map_info lq_map = {
@@ -142,7 +215,8 @@ lq_mtd_probe(struct platform_device *pde
parts = lq_mtd_data->parts;
}
- add_mtd_partitions(lq_mtd, parts, nr_parts);
+ if (!mtd_split_linux(&lq_map, lq_mtd, parts, nr_parts))
+ add_mtd_partitions(lq_mtd, parts, nr_parts);
return 0;
}

View file

@ -0,0 +1,580 @@
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -343,6 +343,12 @@ config MACB
source "drivers/net/arm/Kconfig"
+config LANTIQ_ETOP
+ tristate "Lantiq SoC ETOP driver"
+ depends on SOC_LANTIQ_XWAY
+ help
+ Support for the MII0 inside the Lantiq SoC
+
config AX88796
tristate "ASIX AX88796 NE2000 clone support"
depends on ARM || MIPS || SUPERH
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -204,6 +204,7 @@ obj-$(CONFIG_SNI_82596) += sni_82596.o
obj-$(CONFIG_MVME16x_NET) += 82596.o
obj-$(CONFIG_BVME6000_NET) += 82596.o
obj-$(CONFIG_SC92031) += sc92031.o
+obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o
# This is also a 82596 and should probably be merged
obj-$(CONFIG_LP486E) += lp486e.o
--- /dev/null
+++ b/drivers/net/lantiq_etop.c
@@ -0,0 +1,552 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) 2005 Wu Qi Ming <Qi-Ming.Wu@infineon.com>
+ * Copyright (C) 2008 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/uaccess.h>
+#include <linux/in.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/phy.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/skbuff.h>
+#include <linux/mm.h>
+#include <linux/platform_device.h>
+#include <linux/ethtool.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+
+#include <asm/checksum.h>
+
+#include <xway.h>
+#include <xway_dma.h>
+#include <lantiq_platform.h>
+
+#define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600
+#define LQ_PPE32_MEM_MAP ((u32 *)(LQ_PPE32_BASE_ADDR + 0x10000))
+#define LQ_PPE32_SRST ((u32 *)(LQ_PPE32_BASE_ADDR + 0x10080))
+
+/* mdio access */
+#define LQ_PPE32_MDIO_CFG ((u32 *)(LQ_PPE32_BASE_ADDR + 0x11800))
+#define LQ_PPE32_MDIO_ACC ((u32 *)(LQ_PPE32_BASE_ADDR + 0x11804))
+
+#define MDIO_ACC_REQUEST 0x80000000
+#define MDIO_ACC_READ 0x40000000
+#define MDIO_ACC_ADDR_MASK 0x1f
+#define MDIO_ACC_ADDR_OFFSET 0x15
+#define MDIO_ACC_REG_MASK 0x1f
+#define MDIO_ACC_REG_OFFSET 0x10
+#define MDIO_ACC_VAL_MASK 0xffff
+
+/* configuration */
+#define LQ_PPE32_CFG ((u32 *)(LQ_PPE32_MEM_MAP + 0x1808))
+
+#define PPE32_MII_MASK 0xfffffffc
+#define PPE32_MII_NORMAL 0x8
+#define PPE32_MII_REVERSE 0xe
+
+/* packet length */
+#define LQ_PPE32_IG_PLEN_CTRL ((u32 *)(LQ_PPE32_MEM_MAP + 0x1820))
+
+#define PPE32_PLEN_OVER 0x5ee
+#define PPE32_PLEN_UNDER 0x400000
+
+/* enet */
+#define LQ_PPE32_ENET_MAC_CFG ((u32 *)(LQ_PPE32_MEM_MAP + 0x1840))
+
+#define PPE32_CGEN 0x800
+
+struct lq_mii_priv {
+ struct net_device_stats stats;
+ struct dma_device_info *dma_device;
+ struct sk_buff *skb;
+
+ struct mii_bus *mii_bus;
+ struct phy_device *phydev;
+ int oldlink, oldspeed, oldduplex;
+};
+
+static struct net_device *lq_etop_dev;
+static unsigned char mac_addr[MAX_ADDR_LEN];
+
+static int lq_mdiobus_write(struct mii_bus *bus, int phy_addr,
+ int phy_reg, u16 phy_data)
+{
+ u32 val = MDIO_ACC_REQUEST |
+ ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
+ ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET) |
+ phy_data;
+
+ while (lq_r32(LQ_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST)
+ ;
+ lq_w32(val, LQ_PPE32_MDIO_ACC);
+
+ return 0;
+}
+
+static int lq_mdiobus_read(struct mii_bus *bus, int phy_addr, int phy_reg)
+{
+ u32 val = MDIO_ACC_REQUEST | MDIO_ACC_READ |
+ ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
+ ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET);
+
+ while (lq_r32(LQ_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST)
+ ;
+ lq_w32(val, LQ_PPE32_MDIO_ACC);
+ while (lq_r32(LQ_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST)
+ ;
+ val = lq_r32(LQ_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
+ return val;
+}
+
+int lq_mii_open(struct net_device *dev)
+{
+ struct lq_mii_priv *priv = (struct lq_mii_priv *)netdev_priv(dev);
+ struct dma_device_info *dma_dev = priv->dma_device;
+ int i;
+
+ for (i = 0; i < dma_dev->max_rx_chan_num; i++) {
+ if ((dma_dev->rx_chan[i])->control == LQ_DMA_CH_ON)
+ (dma_dev->rx_chan[i])->open(dma_dev->rx_chan[i]);
+ }
+ netif_start_queue(dev);
+ return 0;
+}
+
+int lq_mii_release(struct net_device *dev)
+{
+ struct lq_mii_priv *priv = (struct lq_mii_priv *)netdev_priv(dev);
+ struct dma_device_info *dma_dev = priv->dma_device;
+ int i;
+
+ for (i = 0; i < dma_dev->max_rx_chan_num; i++)
+ dma_dev->rx_chan[i]->close(dma_dev->rx_chan[i]);
+ netif_stop_queue(dev);
+ return 0;
+}
+
+int lq_mii_hw_receive(struct net_device *dev, struct dma_device_info *dma_dev)
+{
+ struct lq_mii_priv *priv = (struct lq_mii_priv *)netdev_priv(dev);
+ unsigned char *buf = NULL;
+ struct sk_buff *skb = NULL;
+ int len = 0;
+
+ len = dma_device_read(dma_dev, &buf, (void **)&skb);
+
+ if (len >= ETHERNET_PACKET_DMA_BUFFER_SIZE) {
+ printk(KERN_INFO "lq_etop: packet too large %d\n", len);
+ goto lq_mii_hw_receive_err_exit;
+ }
+
+ /* remove CRC */
+ len -= 4;
+ if (skb == NULL) {
+ printk(KERN_INFO "lq_etop: cannot restore pointer\n");
+ goto lq_mii_hw_receive_err_exit;
+ }
+
+ if (len > (skb->end - skb->tail)) {
+ printk(KERN_INFO "lq_etop: BUG, len:%d end:%p tail:%p\n",
+ (len+4), skb->end, skb->tail);
+ goto lq_mii_hw_receive_err_exit;
+ }
+
+ skb_put(skb, len);
+ skb->dev = dev;
+ skb->protocol = eth_type_trans(skb, dev);
+ netif_rx(skb);
+
+ priv->stats.rx_packets++;
+ priv->stats.rx_bytes += len;
+ return 0;
+
+lq_mii_hw_receive_err_exit:
+ if (len == 0) {
+ if (skb)
+ dev_kfree_skb_any(skb);
+ priv->stats.rx_errors++;
+ priv->stats.rx_dropped++;
+ return -EIO;
+ } else {
+ return len;
+ }
+}
+
+int lq_mii_hw_tx(char *buf, int len, struct net_device *dev)
+{
+ int ret = 0;
+ struct lq_mii_priv *priv = netdev_priv(dev);
+ struct dma_device_info *dma_dev = priv->dma_device;
+ ret = dma_device_write(dma_dev, buf, len, priv->skb);
+ return ret;
+}
+
+int lq_mii_tx(struct sk_buff *skb, struct net_device *dev)
+{
+ int len;
+ char *data;
+ struct lq_mii_priv *priv = netdev_priv(dev);
+ struct dma_device_info *dma_dev = priv->dma_device;
+
+ len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
+ data = skb->data;
+ priv->skb = skb;
+ dev->trans_start = jiffies;
+ /* TODO: we got more than 1 dma channel,
+ so we should do something intelligent here to select one */
+ dma_dev->current_tx_chan = 0;
+
+ wmb();
+
+ if (lq_mii_hw_tx(data, len, dev) != len) {
+ dev_kfree_skb_any(skb);
+ priv->stats.tx_errors++;
+ priv->stats.tx_dropped++;
+ } else {
+ priv->stats.tx_packets++;
+ priv->stats.tx_bytes += len;
+ }
+
+ return 0;
+}
+
+void lq_mii_tx_timeout(struct net_device *dev)
+{
+ int i;
+ struct lq_mii_priv *priv = (struct lq_mii_priv *)netdev_priv(dev);
+
+ priv->stats.tx_errors++;
+ for (i = 0; i < priv->dma_device->max_tx_chan_num; i++)
+ priv->dma_device->tx_chan[i]->disable_irq(priv->dma_device->tx_chan[i]);
+ netif_wake_queue(dev);
+ return;
+}
+
+int dma_intr_handler(struct dma_device_info *dma_dev, int status)
+{
+ int i;
+
+ switch (status) {
+ case RCV_INT:
+ lq_mii_hw_receive(lq_etop_dev, dma_dev);
+ break;
+
+ case TX_BUF_FULL_INT:
+ printk(KERN_INFO "lq_etop: tx buffer full\n");
+ netif_stop_queue(lq_etop_dev);
+ for (i = 0; i < dma_dev->max_tx_chan_num; i++) {
+ if ((dma_dev->tx_chan[i])->control == LQ_DMA_CH_ON)
+ dma_dev->tx_chan[i]->enable_irq(dma_dev->tx_chan[i]);
+ }
+ break;
+
+ case TRANSMIT_CPT_INT:
+ for (i = 0; i < dma_dev->max_tx_chan_num; i++)
+ dma_dev->tx_chan[i]->disable_irq(dma_dev->tx_chan[i]);
+
+ netif_wake_queue(lq_etop_dev);
+ break;
+ }
+
+ return 0;
+}
+
+unsigned char *lq_etop_dma_buffer_alloc(int len, int *byte_offset, void **opt)
+{
+ unsigned char *buffer = NULL;
+ struct sk_buff *skb = NULL;
+
+ skb = dev_alloc_skb(ETHERNET_PACKET_DMA_BUFFER_SIZE);
+ if (skb == NULL)
+ return NULL;
+
+ buffer = (unsigned char *)(skb->data);
+ skb_reserve(skb, 2);
+ *(int *)opt = (int)skb;
+ *byte_offset = 2;
+
+ return buffer;
+}
+
+void lq_etop_dma_buffer_free(unsigned char *dataptr, void *opt)
+{
+ struct sk_buff *skb = NULL;
+
+ if (opt == NULL) {
+ kfree(dataptr);
+ } else {
+ skb = (struct sk_buff *)opt;
+ dev_kfree_skb_any(skb);
+ }
+}
+
+static void
+lq_adjust_link(struct net_device *dev)
+{
+ struct lq_mii_priv *priv = netdev_priv(dev);
+ struct phy_device *phydev = priv->phydev;
+ int new_state = 0;
+
+ /* Did anything change? */
+ if (priv->oldlink != phydev->link ||
+ priv->oldduplex != phydev->duplex ||
+ priv->oldspeed != phydev->speed) {
+ /* Yes, so update status and mark as changed */
+ new_state = 1;
+ priv->oldduplex = phydev->duplex;
+ priv->oldspeed = phydev->speed;
+ priv->oldlink = phydev->link;
+ }
+
+ /* If link status changed, show new status */
+ if (new_state)
+ phy_print_status(phydev);
+}
+
+static int mii_probe(struct net_device *dev)
+{
+ struct lq_mii_priv *priv = netdev_priv(dev);
+ struct phy_device *phydev = NULL;
+ int phy_addr;
+
+ priv->oldlink = 0;
+ priv->oldspeed = 0;
+ priv->oldduplex = -1;
+
+ /* find the first (lowest address) PHY on the current MAC's MII bus */
+ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
+ if (priv->mii_bus->phy_map[phy_addr]) {
+ phydev = priv->mii_bus->phy_map[phy_addr];
+ break; /* break out with first one found */
+ }
+ }
+
+ if (!phydev) {
+ printk (KERN_ERR "%s: no PHY found\n", dev->name);
+ return -ENODEV;
+ }
+
+ /* now we are supposed to have a proper phydev, to attach to... */
+ BUG_ON(!phydev);
+ BUG_ON(phydev->attached_dev);
+
+ phydev = phy_connect(dev, dev_name(&phydev->dev), &lq_adjust_link,
+ 0, PHY_INTERFACE_MODE_MII);
+
+ if (IS_ERR(phydev)) {
+ printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
+ return PTR_ERR(phydev);
+ }
+
+ /* mask with MAC supported features */
+ phydev->supported &= (SUPPORTED_10baseT_Half
+ | SUPPORTED_10baseT_Full
+ | SUPPORTED_100baseT_Half
+ | SUPPORTED_100baseT_Full
+ | SUPPORTED_Autoneg
+ /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
+ | SUPPORTED_MII
+ | SUPPORTED_TP);
+
+ phydev->advertising = phydev->supported;
+
+ priv->phydev = phydev;
+
+ printk(KERN_INFO "%s: attached PHY driver [%s] "
+ "(mii_bus:phy_addr=%s, irq=%d)\n",
+ dev->name, phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
+
+ return 0;
+}
+
+
+static int lq_mii_dev_init(struct net_device *dev)
+{
+ int i;
+ struct lq_mii_priv *priv = (struct lq_mii_priv *)netdev_priv(dev);
+ ether_setup(dev);
+ dev->watchdog_timeo = 10 * HZ;
+ dev->mtu = 1500;
+ memset(priv, 0, sizeof(struct lq_mii_priv));
+ priv->dma_device = dma_device_reserve("PPE");
+ if (!priv->dma_device) {
+ BUG();
+ return -ENODEV;
+ }
+ priv->dma_device->buffer_alloc = &lq_etop_dma_buffer_alloc;
+ priv->dma_device->buffer_free = &lq_etop_dma_buffer_free;
+ priv->dma_device->intr_handler = &dma_intr_handler;
+ priv->dma_device->max_rx_chan_num = 4;
+
+ for (i = 0; i < priv->dma_device->max_rx_chan_num; i++) {
+ priv->dma_device->rx_chan[i]->packet_size = ETHERNET_PACKET_DMA_BUFFER_SIZE;
+ priv->dma_device->rx_chan[i]->control = LQ_DMA_CH_ON;
+ }
+
+ for (i = 0; i < priv->dma_device->max_tx_chan_num; i++)
+ if (i == 0)
+ priv->dma_device->tx_chan[i]->control = LQ_DMA_CH_ON;
+ else
+ priv->dma_device->tx_chan[i]->control = LQ_DMA_CH_OFF;
+
+ dma_device_register(priv->dma_device);
+
+ printk(KERN_INFO "%s: using mac=", dev->name);
+ for (i = 0; i < 6; i++) {
+ dev->dev_addr[i] = mac_addr[i];
+ printk("%02X%c", dev->dev_addr[i], (i == 5) ? ('\n') : (':'));
+ }
+
+ priv->mii_bus = mdiobus_alloc();
+ if (priv->mii_bus == NULL)
+ return -ENOMEM;
+
+ priv->mii_bus->priv = dev;
+ priv->mii_bus->read = lq_mdiobus_read;
+ priv->mii_bus->write = lq_mdiobus_write;
+ priv->mii_bus->name = "lq_mii";
+ snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
+ priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
+ for(i = 0; i < PHY_MAX_ADDR; ++i)
+ priv->mii_bus->irq[i] = PHY_POLL;
+
+ mdiobus_register(priv->mii_bus);
+
+ return mii_probe(dev);
+}
+
+static void lq_mii_chip_init(int mode)
+{
+ lq_pmu_enable(PMU_DMA);
+ lq_pmu_enable(PMU_PPE);
+
+ if (mode == REV_MII_MODE)
+ lq_w32_mask(PPE32_MII_MASK, PPE32_MII_REVERSE, LQ_PPE32_CFG);
+ else if (mode == MII_MODE)
+ lq_w32_mask(PPE32_MII_MASK, PPE32_MII_NORMAL, LQ_PPE32_CFG);
+ lq_w32(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, LQ_PPE32_IG_PLEN_CTRL);
+ lq_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
+ wmb();
+}
+
+static int lq_mii_eth_mac_addr(struct net_device *dev, void *p)
+{
+ int retcode;
+
+ retcode = eth_mac_addr(dev, p);
+
+ if (retcode)
+ return retcode;
+
+ // set rx_addr for unicast filter
+ lq_w32(((dev->dev_addr[0]<<24)|(dev->dev_addr[1]<<16)|(dev->dev_addr[2]<< 8)|dev->dev_addr[3]), (u32*)(LQ_PPE32_BASE_ADDR|(0x461b<<2)));
+ lq_w32(((dev->dev_addr[4]<<24)|(dev->dev_addr[5]<<16)), (u32*)(LQ_PPE32_BASE_ADDR|(0x461c<<2)));
+
+ return 0;
+}
+
+static void lq_mii_set_rx_mode (struct net_device *dev)
+{
+ // rx_mode promisc: unset unicast filter
+ if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI))
+ lq_w32(lq_r32((u32*)(LQ_PPE32_BASE_ADDR|(0x4614<<2))) & ~(1<<28), (u32*)(LQ_PPE32_BASE_ADDR|(0x4614<<2)));
+ // enable unicast filter
+ else
+ lq_w32(lq_r32((u32*)(LQ_PPE32_BASE_ADDR|(0x4614<<2))) | (1<<28), (u32*)(LQ_PPE32_BASE_ADDR|(0x4614<<2)));
+}
+
+static const struct net_device_ops lq_eth_netdev_ops = {
+ .ndo_init = lq_mii_dev_init,
+ .ndo_open = lq_mii_open,
+ .ndo_stop = lq_mii_release,
+ .ndo_start_xmit = lq_mii_tx,
+ .ndo_tx_timeout = lq_mii_tx_timeout,
+ .ndo_change_mtu = eth_change_mtu,
+ .ndo_set_mac_address = lq_mii_eth_mac_addr,
+ .ndo_validate_addr = eth_validate_addr,
+ .ndo_set_multicast_list = lq_mii_set_rx_mode,
+};
+
+static int
+lq_mii_probe(struct platform_device *dev)
+{
+ int result = 0;
+ struct lq_eth_data *eth = (struct lq_eth_data*)dev->dev.platform_data;
+ lq_etop_dev = alloc_etherdev(sizeof(struct lq_mii_priv));
+ lq_etop_dev->netdev_ops = &lq_eth_netdev_ops;
+ memcpy(mac_addr, eth->mac, 6);
+ strcpy(lq_etop_dev->name, "eth%d");
+ lq_mii_chip_init(eth->mii_mode);
+ result = register_netdev(lq_etop_dev);
+ if (result) {
+ printk(KERN_INFO "lq_etop: error %i registering device \"%s\"\n", result, lq_etop_dev->name);
+ goto out;
+ }
+
+ printk(KERN_INFO "lq_etop: driver loaded!\n");
+
+out:
+ return result;
+}
+
+static int lq_mii_remove(struct platform_device *dev)
+{
+ struct lq_mii_priv *priv = (struct lq_mii_priv *)netdev_priv(lq_etop_dev);
+
+ printk(KERN_INFO "lq_etop: lq_etop cleanup\n");
+
+ dma_device_unregister(priv->dma_device);
+ dma_device_release(priv->dma_device);
+ kfree(priv->dma_device);
+ unregister_netdev(lq_etop_dev);
+ return 0;
+}
+
+static struct platform_driver lq_mii_driver = {
+ .probe = lq_mii_probe,
+ .remove = lq_mii_remove,
+ .driver = {
+ .name = "lq_etop",
+ .owner = THIS_MODULE,
+ },
+};
+
+int __init lq_mii_init(void)
+{
+ int ret = platform_driver_register(&lq_mii_driver);
+ if (ret)
+ printk(KERN_INFO "lq_etop: Error registering platfom driver!");
+ return ret;
+}
+
+static void __exit lq_mii_cleanup(void)
+{
+ platform_driver_unregister(&lq_mii_driver);
+}
+
+module_init(lq_mii_init);
+module_exit(lq_mii_cleanup);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+MODULE_DESCRIPTION("ethernet driver for IFXMIPS boards");

View file

@ -0,0 +1,246 @@
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -840,6 +840,12 @@ config TXX9_WDT
help
Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs.
+config LANTIQ_WDT
+ bool "Lantiq SoC watchdog"
+ depends on LANTIQ
+ help
+ Hardware driver for the Lantiq SoC Watchdog Timer.
+
# PARISC Architecture
# POWERPC Architecture
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -112,6 +112,7 @@ obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt
obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
+obj-$(CONFIG_LANTIQ_WDT) += lantiq_wdt.o
# PARISC Architecture
--- /dev/null
+++ b/drivers/watchdog/lantiq_wdt.c
@@ -0,0 +1,218 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ * Based on EP93xx wdt driver
+ */
+
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/miscdevice.h>
+#include <linux/watchdog.h>
+#include <linux/platform_device.h>
+#include <linux/uaccess.h>
+#include <linux/clk.h>
+
+#include <lantiq.h>
+
+#define LQ_WDT_PW1 0x00BE0000
+#define LQ_WDT_PW2 0x00DC0000
+
+#define LQ_BIU_WDT_CR 0x3F0
+#define LQ_BIU_WDT_SR 0x3F8
+
+#ifndef CONFIG_WATCHDOG_NOWAYOUT
+static int wdt_ok_to_close;
+#endif
+
+static int wdt_timeout = 30;
+static __iomem void *wdt_membase = NULL;
+static unsigned long io_region_clk = 0;
+
+static int
+lq_wdt_enable(unsigned int timeout)
+{
+/* printk("%s:%s[%d] %08X\n",
+ __FILE__, __func__, __LINE__,
+ lq_r32(wdt_membase + LQ_BIU_WDT_SR));
+ if(!lq_r32(wdt_membase + LQ_BIU_WDT_SR))
+ {
+*/ lq_w32(LQ_WDT_PW1, wdt_membase + LQ_BIU_WDT_CR);
+ lq_w32(LQ_WDT_PW2 |
+ (0x3 << 26) | /* PWL */
+ (0x3 << 24) | /* CLKDIV */
+ (0x1 << 31) | /* enable */
+ ((timeout * (io_region_clk / 0x40000)) + 0x1000), /* reload */
+ wdt_membase + LQ_BIU_WDT_CR);
+// }
+ return 0;
+}
+
+static void
+lq_wdt_disable(void)
+{
+#ifndef CONFIG_WATCHDOG_NOWAYOUT
+ wdt_ok_to_close = 0;
+#endif
+ lq_w32(LQ_WDT_PW1, wdt_membase + LQ_BIU_WDT_CR);
+ lq_w32(LQ_WDT_PW2, wdt_membase+ LQ_BIU_WDT_CR);
+}
+
+static ssize_t
+lq_wdt_write(struct file *file, const char __user *data,
+ size_t len, loff_t *ppos)
+{
+ size_t i;
+
+ if (!len)
+ return 0;
+
+#ifndef CONFIG_WATCHDOG_NOWAYOUT
+ for (i = 0; i != len; i++) {
+ char c;
+ if (get_user(c, data + i))
+ return -EFAULT;
+ if (c == 'V')
+ wdt_ok_to_close = 1;
+ }
+#endif
+ lq_wdt_enable(wdt_timeout);
+ return len;
+}
+
+static struct watchdog_info ident = {
+ .options = WDIOF_MAGICCLOSE,
+ .identity = "lq_wdt",
+};
+
+static int
+lq_wdt_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ int ret = -ENOTTY;
+
+ switch (cmd) {
+ case WDIOC_GETSUPPORT:
+ ret = copy_to_user((struct watchdog_info __user *)arg, &ident,
+ sizeof(ident)) ? -EFAULT : 0;
+ break;
+
+ case WDIOC_GETTIMEOUT:
+ ret = put_user(wdt_timeout, (int __user *)arg);
+ break;
+
+ case WDIOC_SETTIMEOUT:
+ ret = get_user(wdt_timeout, (int __user *)arg);
+ break;
+
+ case WDIOC_KEEPALIVE:
+ lq_wdt_enable(wdt_timeout);
+ ret = 0;
+ break;
+ }
+ return ret;
+}
+
+static int
+lq_wdt_open(struct inode *inode, struct file *file)
+{
+ lq_wdt_enable(wdt_timeout);
+ return nonseekable_open(inode, file);
+}
+
+static int
+lq_wdt_release(struct inode *inode, struct file *file)
+{
+#ifndef CONFIG_WATCHDOG_NOWAYOUT
+ if (wdt_ok_to_close)
+ lq_wdt_disable();
+ else
+#endif
+ printk(KERN_ERR "lq_wdt: watchdog closed without warning,"
+ " rebooting system\n");
+ return 0;
+}
+
+static const struct file_operations lq_wdt_fops = {
+ .owner = THIS_MODULE,
+ .write = lq_wdt_write,
+ .ioctl = lq_wdt_ioctl,
+ .open = lq_wdt_open,
+ .release = lq_wdt_release,
+};
+
+static struct miscdevice lq_wdt_miscdev = {
+ .minor = WATCHDOG_MINOR,
+ .name = "watchdog",
+ .fops = &lq_wdt_fops,
+};
+
+static int
+lq_wdt_probe(struct platform_device *pdev)
+{
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ struct clk *clk;
+ int ret = 0;
+ if(!res)
+ return -ENOENT;
+ res = request_mem_region(res->start, resource_size(res),
+ dev_name(&pdev->dev));
+ if(!res)
+ return -EBUSY;
+ wdt_membase = ioremap_nocache(res->start, resource_size(res));
+ if(!wdt_membase)
+ {
+ ret = -ENOMEM;
+ goto err_release_mem_region;
+ }
+ clk = clk_get(&pdev->dev, "io");
+ io_region_clk = clk_get_rate(clk);;
+ ret = misc_register(&lq_wdt_miscdev);
+ if(!ret)
+ return 0;
+
+ iounmap(wdt_membase);
+err_release_mem_region:
+ release_mem_region(res->start, resource_size(res));
+ return ret;
+}
+
+static int
+lq_wdt_remove(struct platform_device *dev)
+{
+ lq_wdt_disable();
+ misc_deregister(&lq_wdt_miscdev);
+ return 0;
+}
+
+static struct platform_driver lq_wdt_driver = {
+ .probe = lq_wdt_probe,
+ .remove = lq_wdt_remove,
+ .driver = {
+ .name = "lq_wdt",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init
+init_lq_wdt(void)
+{
+ return platform_driver_register(&lq_wdt_driver);
+}
+
+static void __exit
+exit_lq_wdt(void)
+{
+ platform_driver_unregister(&lq_wdt_driver);
+}
+
+module_init(init_lq_wdt);
+module_exit(exit_lq_wdt);
+
+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+MODULE_DESCRIPTION("ifxmips Watchdog");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);

View file

@ -0,0 +1,436 @@
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capc
obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
+obj-$(CONFIG_LANTIQ) += pci-lantiq.o ops-lantiq.o
ifdef CONFIG_PCI_MSI
obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
--- /dev/null
+++ b/arch/mips/pci/ops-lantiq.c
@@ -0,0 +1,127 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/mm.h>
+#include <asm/addrspace.h>
+#include <linux/vmalloc.h>
+
+#include <xway.h>
+
+#define LQ_PCI_CFG_BUSNUM_SHF 16
+#define LQ_PCI_CFG_DEVNUM_SHF 11
+#define LQ_PCI_CFG_FUNNUM_SHF 8
+
+#define PCI_ACCESS_READ 0
+#define PCI_ACCESS_WRITE 1
+
+extern u32 lq_pci_mapped_cfg;
+
+static int
+lq_pci_config_access(unsigned char access_type,
+ struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data)
+{
+ unsigned long cfg_base;
+ unsigned long flags;
+
+ u32 temp;
+
+ /* we support slot from 0 to 15 */
+ /* dev_fn 0&0x68 (AD29) is ifxmips itself */
+ if ((bus->number != 0) || ((devfn & 0xf8) > 0x78)
+ || ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68))
+ return 1;
+
+ spin_lock_irqsave(&ebu_lock, flags);
+
+ cfg_base = lq_pci_mapped_cfg;
+ cfg_base |= (bus->number << LQ_PCI_CFG_BUSNUM_SHF) | (devfn <<
+ LQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
+
+ /* Perform access */
+ if (access_type == PCI_ACCESS_WRITE)
+ {
+#ifdef CONFIG_SWAP_IO_SPACE
+ lq_w32(swab32(*data), ((u32*)cfg_base));
+#else
+ lq_w32(*data, ((u32*)cfg_base));
+#endif
+ } else {
+ *data = lq_r32(((u32*)(cfg_base)));
+#ifdef CONFIG_SWAP_IO_SPACE
+ *data = swab32(*data);
+#endif
+ }
+ wmb();
+
+ /* clean possible Master abort */
+ cfg_base = (lq_pci_mapped_cfg | (0x0 << LQ_PCI_CFG_FUNNUM_SHF)) + 4;
+ temp = lq_r32(((u32*)(cfg_base)));
+#ifdef CONFIG_SWAP_IO_SPACE
+ temp = swab32 (temp);
+#endif
+ cfg_base = (lq_pci_mapped_cfg | (0x68 << LQ_PCI_CFG_FUNNUM_SHF)) + 4;
+ lq_w32(temp, ((u32*)cfg_base));
+
+ spin_unlock_irqrestore(&ebu_lock, flags);
+
+ if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
+ return 1;
+
+ return 0;
+}
+
+int
+lq_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 * val)
+{
+ u32 data = 0;
+
+ if (lq_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ if (size == 1)
+ *val = (data >> ((where & 3) << 3)) & 0xff;
+ else if (size == 2)
+ *val = (data >> ((where & 3) << 3)) & 0xffff;
+ else
+ *val = data;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+int
+lq_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 val)
+{
+ u32 data = 0;
+
+ if (size == 4)
+ {
+ data = val;
+ } else {
+ if (lq_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ if (size == 1)
+ data = (data & ~(0xff << ((where & 3) << 3))) |
+ (val << ((where & 3) << 3));
+ else if (size == 2)
+ data = (data & ~(0xffff << ((where & 3) << 3))) |
+ (val << ((where & 3) << 3));
+ }
+
+ if (lq_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ return PCIBIOS_SUCCESSFUL;
+}
--- /dev/null
+++ b/arch/mips/pci/pci-lantiq.c
@@ -0,0 +1,293 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/mm.h>
+#include <linux/vmalloc.h>
+#include <linux/platform_device.h>
+
+#include <asm/gpio.h>
+#include <asm/addrspace.h>
+
+#include <xway.h>
+#include <xway_irq.h>
+#include <lantiq_platform.h>
+
+#define LQ_PCI_CFG_BASE 0x17000000
+#define LQ_PCI_CFG_SIZE 0x00008000
+#define LQ_PCI_MEM_BASE 0x18000000
+#define LQ_PCI_MEM_SIZE 0x02000000
+#define LQ_PCI_IO_BASE 0x1AE00000
+#define LQ_PCI_IO_SIZE 0x00200000
+
+#define PCI_CR_FCI_ADDR_MAP0 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C0))
+#define PCI_CR_FCI_ADDR_MAP1 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C4))
+#define PCI_CR_FCI_ADDR_MAP2 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C8))
+#define PCI_CR_FCI_ADDR_MAP3 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00CC))
+#define PCI_CR_FCI_ADDR_MAP4 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D0))
+#define PCI_CR_FCI_ADDR_MAP5 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D4))
+#define PCI_CR_FCI_ADDR_MAP6 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D8))
+#define PCI_CR_FCI_ADDR_MAP7 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00DC))
+#define PCI_CR_CLK_CTRL ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0000))
+#define PCI_CR_PCI_MOD ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0030))
+#define PCI_CR_PC_ARB ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0080))
+#define PCI_CR_FCI_ADDR_MAP11hg ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E4))
+#define PCI_CR_BAR11MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0044))
+#define PCI_CR_BAR12MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0048))
+#define PCI_CR_BAR13MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x004C))
+#define PCI_CS_BASE_ADDR1 ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0010))
+#define PCI_CR_PCI_ADDR_MAP11 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0064))
+#define PCI_CR_FCI_BURST_LENGTH ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E8))
+#define PCI_CR_PCI_EOI ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x002C))
+
+
+#define PCI_CS_STS_CMD ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0004))
+
+#define PCI_MASTER0_REQ_MASK_2BITS 8
+#define PCI_MASTER1_REQ_MASK_2BITS 10
+#define PCI_MASTER2_REQ_MASK_2BITS 12
+#define INTERNAL_ARB_ENABLE_BIT 0
+
+#define LQ_CGU_IFCCR ((u32 *)(LQ_CGU_BASE_ADDR + 0x0018))
+#define LQ_CGU_PCICR ((u32 *)(LQ_CGU_BASE_ADDR + 0x0034))
+
+extern int lq_pci_read_config_dword(struct pci_bus *bus,
+ unsigned int devfn, int where, int size, u32 *val);
+extern int lq_pci_write_config_dword(struct pci_bus *bus,
+ unsigned int devfn, int where, int size, u32 val);
+
+u32 lq_pci_mapped_cfg;
+
+/* Since the PCI REQ pins can be reused for other functionality, make it possible
+ to exclude those from interpretation by the PCI controller */
+static int lq_pci_req_mask = 0xf;
+
+struct pci_ops lq_pci_ops =
+{
+ .read = lq_pci_read_config_dword,
+ .write = lq_pci_write_config_dword
+};
+
+static struct resource pci_io_resource =
+{
+ .name = "pci io space",
+ .start = LQ_PCI_IO_BASE,
+ .end = LQ_PCI_IO_BASE + LQ_PCI_IO_SIZE - 1,
+ .flags = IORESOURCE_IO
+};
+
+static struct resource pci_mem_resource =
+{
+ .name = "pci memory space",
+ .start = LQ_PCI_MEM_BASE,
+ .end = LQ_PCI_MEM_BASE + LQ_PCI_MEM_SIZE - 1,
+ .flags = IORESOURCE_MEM
+};
+
+static struct pci_controller lq_pci_controller =
+{
+ .pci_ops = &lq_pci_ops,
+ .mem_resource = &pci_mem_resource,
+ .mem_offset = 0x00000000UL,
+ .io_resource = &pci_io_resource,
+ .io_offset = 0x00000000UL,
+};
+
+int
+pcibios_plat_dev_init(struct pci_dev *dev)
+{
+ u8 pin;
+
+ pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
+ switch(pin)
+ {
+ case 0:
+ break;
+ case 1:
+ //falling edge level triggered:0x4, low level:0xc, rising edge:0x2
+ lq_w32(lq_r32(LQ_EBU_PCC_CON) | 0xc, LQ_EBU_PCC_CON);
+ lq_w32(lq_r32(LQ_EBU_PCC_IEN) | 0x10, LQ_EBU_PCC_IEN);
+ break;
+ case 2:
+ case 3:
+ case 4:
+ printk ("WARNING: interrupt pin %d not supported yet!\n", pin);
+ default:
+ printk ("WARNING: invalid interrupt pin %d\n", pin);
+ return 1;
+ }
+ return 0;
+}
+
+static u32
+lq_calc_bar11mask(void)
+{
+ u32 mem, bar11mask;
+
+ /* BAR11MASK value depends on available memory on system. */
+ mem = num_physpages * PAGE_SIZE;
+ bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) -1)) -1)) | 8;
+
+ return bar11mask;
+}
+
+static void
+lq_pci_setup_clk(int external_clock)
+{
+ /* set clock to 33Mhz */
+ lq_w32(lq_r32(LQ_CGU_IFCCR) & ~0xf00000, LQ_CGU_IFCCR);
+ lq_w32(lq_r32(LQ_CGU_IFCCR) | 0x800000, LQ_CGU_IFCCR);
+ if (external_clock)
+ {
+ lq_w32(lq_r32(LQ_CGU_IFCCR) & ~(1 << 16), LQ_CGU_IFCCR);
+ lq_w32((1 << 30), LQ_CGU_PCICR);
+ } else {
+ lq_w32(lq_r32(LQ_CGU_IFCCR) | (1 << 16), LQ_CGU_IFCCR);
+ lq_w32((1 << 31) | (1 << 30), LQ_CGU_PCICR);
+ }
+}
+
+static void
+lq_pci_setup_gpio(void)
+{
+ /* PCI reset line is gpio driven */
+ lq_gpio_request(21, 0, 0, 1, "pci-reset");
+
+ /* PCI_REQ line */
+ lq_gpio_request(29, 1, 0, 0, "pci-req");
+
+ /* PCI_GNT line */
+ lq_gpio_request(30, 1, 0, 1, "pci-gnt");
+}
+
+static int __init
+lq_pci_startup(void)
+{
+ u32 temp_buffer;
+
+ /* setup pci clock and gpis used by pci */
+ lq_pci_setup_gpio();
+
+ /* enable auto-switching between PCI and EBU */
+ lq_w32(0xa, PCI_CR_CLK_CTRL);
+
+ /* busy, i.e. configuration is not done, PCI access has to be retried */
+ lq_w32(lq_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
+ wmb ();
+ /* BUS Master/IO/MEM access */
+ lq_w32(lq_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
+
+ /* enable external 2 PCI masters */
+ temp_buffer = lq_r32(PCI_CR_PC_ARB);
+ temp_buffer &= (~(lq_pci_req_mask << 16));
+ /* enable internal arbiter */
+ temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
+ /* enable internal PCI master reqest */
+ temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
+
+ /* enable EBU request */
+ temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
+
+ /* enable all external masters request */
+ temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
+ lq_w32(temp_buffer, PCI_CR_PC_ARB);
+ wmb ();
+
+ /* setup BAR memory regions */
+ lq_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
+ lq_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
+ lq_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
+ lq_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
+ lq_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
+ lq_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
+ lq_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
+ lq_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
+ lq_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
+ lq_w32(lq_calc_bar11mask(), PCI_CR_BAR11MASK);
+ lq_w32(0, PCI_CR_PCI_ADDR_MAP11);
+ lq_w32(0, PCI_CS_BASE_ADDR1);
+#ifdef CONFIG_SWAP_IO_SPACE
+ /* both TX and RX endian swap are enabled */
+ lq_w32(lq_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
+ wmb ();
+#endif
+ /*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
+ lq_w32(lq_r32(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK);
+ lq_w32(lq_r32(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK);
+ /*use 8 dw burst length */
+ lq_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
+ lq_w32(lq_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
+ wmb();
+
+ /* toggle reset pin */
+ __gpio_set_value(21, 0);
+ wmb();
+ mdelay(1);
+ __gpio_set_value(21, 1);
+ return 0;
+}
+
+int __init
+pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
+ switch(slot)
+ {
+ case 13:
+ /* IDSEL = AD29 --> USB Host Controller */
+ return (INT_NUM_IM1_IRL0 + 17);
+ case 14:
+ /* IDSEL = AD30 --> mini PCI connector */
+ return (INT_NUM_IM0_IRL0 + 22);
+ default:
+ printk("lq_pci: no IRQ found for slot %d, pin %d\n", slot, pin);
+ return 0;
+ }
+}
+
+static int
+lq_pci_probe(struct platform_device *pdev)
+{
+ struct lq_pci_data *lq_pci_data = (struct lq_pci_data*) pdev->dev.platform_data;
+ extern int pci_probe_only;
+
+ pci_probe_only = 0;
+ lq_pci_req_mask = lq_pci_data->req_mask;
+ lq_pci_setup_clk(lq_pci_data->clock);
+
+ lq_pci_startup();
+ lq_pci_mapped_cfg =
+ (u32)ioremap_nocache(LQ_PCI_CFG_BASE, LQ_PCI_CFG_BASE);
+ lq_pci_controller.io_map_base =
+ (unsigned long)ioremap(LQ_PCI_IO_BASE, LQ_PCI_IO_SIZE - 1);
+
+ register_pci_controller(&lq_pci_controller);
+ return 0;
+}
+
+static struct platform_driver
+lq_pci_driver = {
+ .probe = lq_pci_probe,
+ .driver = {
+ .name = "lq_pci",
+ .owner = THIS_MODULE,
+ },
+};
+
+int __init
+pcibios_init(void)
+{
+ int ret = platform_driver_register(&lq_pci_driver);
+ if(ret)
+ printk(KERN_INFO "lq_pci: Error registering platfom driver!");
+ return ret;
+}
+
+arch_initcall(pcibios_init);

File diff suppressed because it is too large Load diff

View file

@ -0,0 +1,346 @@
--- /dev/null
+++ b/include/linux/udp_redirect.h
@@ -0,0 +1,57 @@
+#ifndef _UDP_REDIRECT_H
+#define _UDP_REDIRECT_H
+
+/******************************************************************************
+
+ Copyright (c) 2006
+ Infineon Technologies AG
+ Am Campeon 1-12; 81726 Munich, Germany
+
+ THE DELIVERY OF THIS SOFTWARE AS WELL AS THE HEREBY GRANTED NON-EXCLUSIVE,
+ WORLDWIDE LICENSE TO USE, COPY, MODIFY, DISTRIBUTE AND SUBLICENSE THIS
+ SOFTWARE IS FREE OF CHARGE.
+
+ THE LICENSED SOFTWARE IS PROVIDED "AS IS" AND INFINEON EXPRESSLY DISCLAIMS
+ ALL REPRESENTATIONS AND WARRANTIES, WHETHER EXPRESS OR IMPLIED, INCLUDING
+ WITHOUT LIMITATION, WARRANTIES OR REPRESENTATIONS OF WORKMANSHIP,
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, DURABILITY, THAT THE
+ OPERATING OF THE LICENSED SOFTWARE WILL BE ERROR FREE OR FREE OF ANY THIRD
+ PARTY CLAIMS, INCLUDING WITHOUT LIMITATION CLAIMS OF THIRD PARTY INTELLECTUAL
+ PROPERTY INFRINGEMENT.
+
+ EXCEPT FOR ANY LIABILITY DUE TO WILFUL ACTS OR GROSS NEGLIGENCE AND EXCEPT
+ FOR ANY PERSONAL INJURY INFINEON SHALL IN NO EVENT BE LIABLE FOR ANY CLAIM
+ OR DAMAGES OF ANY KIND, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+
+******************************************************************************/
+
+/* ============================= */
+/* Includes */
+/* ============================= */
+#ifndef _LINUX_TYPES_H
+#include <linux/types.h>
+#endif
+
+
+/* ============================= */
+/* Definitions */
+/* ============================= */
+#define UDP_REDIRECT_MAGIC (void*)0x55445052L
+
+
+/* ============================= */
+/* Global variable declaration */
+/* ============================= */
+extern int (*udp_do_redirect_fn)(struct sock *sk, struct sk_buff *skb);
+extern int (*udpredirect_getfrag_fn)(void *p, char * to,
+ int offset, int fraglen, int odd,
+ struct sk_buff *skb);
+/* ============================= */
+/* Global function declaration */
+/* ============================= */
+
+extern int udpredirect_getfrag(void *p, char * to, int offset,
+ int fraglen, int odd, struct sk_buff *skb);
+#endif
--- /dev/null
+++ b/net/ipv4/udp_redirect_symb.c
@@ -0,0 +1,186 @@
+/******************************************************************************
+
+ Copyright (c) 2006
+ Infineon Technologies AG
+ Am Campeon 1-12; 81726 Munich, Germany
+
+ THE DELIVERY OF THIS SOFTWARE AS WELL AS THE HEREBY GRANTED NON-EXCLUSIVE,
+ WORLDWIDE LICENSE TO USE, COPY, MODIFY, DISTRIBUTE AND SUBLICENSE THIS
+ SOFTWARE IS FREE OF CHARGE.
+
+ THE LICENSED SOFTWARE IS PROVIDED "AS IS" AND INFINEON EXPRESSLY DISCLAIMS
+ ALL REPRESENTATIONS AND WARRANTIES, WHETHER EXPRESS OR IMPLIED, INCLUDING
+ WITHOUT LIMITATION, WARRANTIES OR REPRESENTATIONS OF WORKMANSHIP,
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, DURABILITY, THAT THE
+ OPERATING OF THE LICENSED SOFTWARE WILL BE ERROR FREE OR FREE OF ANY THIRD
+ PARTY CLAIMS, INCLUDING WITHOUT LIMITATION CLAIMS OF THIRD PARTY INTELLECTUAL
+ PROPERTY INFRINGEMENT.
+
+ EXCEPT FOR ANY LIABILITY DUE TO WILFUL ACTS OR GROSS NEGLIGENCE AND EXCEPT
+ FOR ANY PERSONAL INJURY INFINEON SHALL IN NO EVENT BE LIABLE FOR ANY CLAIM
+ OR DAMAGES OF ANY KIND, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+
+******************************************************************************/
+#if defined(CONFIG_IFX_UDP_REDIRECT) || defined(CONFIG_IFX_UDP_REDIRECT_MODULE)
+/* ============================= */
+/* Includes */
+/* ============================= */
+#include <net/checksum.h>
+#include <net/udp.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/udp_redirect.h>
+
+/* ============================= */
+/* Global variable definition */
+/* ============================= */
+int (*udpredirect_getfrag_fn) (void *p, char * to, int offset,
+ int fraglen, int odd, struct sk_buff *skb) = NULL;
+int (*udp_do_redirect_fn)(struct sock *sk, struct sk_buff *skb) = NULL;
+
+/* ============================= */
+/* Local type definitions */
+/* ============================= */
+struct udpfakehdr
+{
+ struct udphdr uh;
+ u32 saddr;
+ u32 daddr;
+ struct iovec *iov;
+ u32 wcheck;
+};
+
+/* ============================= */
+/* Local function declaration */
+/* ============================= */
+static int udpredirect_csum_partial_copy_fromiovecend(unsigned char *kdata,
+ struct iovec *iov, int offset, unsigned int len, __wsum *csump);
+
+static int udpredirect_memcpy_fromiovecend(unsigned char *kdata, struct iovec *iov, int offset,
+ int len);
+
+/* ============================= */
+/* Global function definition */
+/* ============================= */
+
+/*
+ Copy of udp_getfrag() from udp.c
+ This function exists because no copy_from_user() is needed for udpredirect.
+*/
+
+int
+udpredirect_getfrag(void *from, char *to, int offset, int len, int odd, struct sk_buff *skb)
+{
+ struct iovec *iov = from;
+
+ if (skb->ip_summed == CHECKSUM_PARTIAL) {
+ if (udpredirect_memcpy_fromiovecend(to, iov, offset, len) < 0)
+ return -EFAULT;
+ } else {
+ __wsum csum = 0;
+ if (udpredirect_csum_partial_copy_fromiovecend(to, iov, offset, len, &csum) < 0)
+ return -EFAULT;
+ skb->csum = csum_block_add(skb->csum, csum, odd);
+ }
+ return 0;
+}
+
+static int udpredirect_memcpy_fromiovecend(unsigned char *kdata, struct iovec *iov, int offset,
+ int len)
+{
+ /* Skip over the finished iovecs */
+ while (offset >= iov->iov_len) {
+ offset -= iov->iov_len;
+ iov++;
+ }
+
+ while (len > 0) {
+ u8 __user *base = iov->iov_base + offset;
+ int copy = min_t(unsigned int, len, iov->iov_len - offset);
+
+ offset = 0;
+ memcpy(kdata, base, copy);
+ len -= copy;
+ kdata += copy;
+ iov++;
+ }
+
+ return 0;
+}
+
+/*
+ Copy of csum_partial_copy_fromiovecend() from iovec.c
+ This function exists because no copy_from_user() is needed for udpredirect.
+*/
+
+int udpredirect_csum_partial_copy_fromiovecend(unsigned char *kdata, struct iovec *iov,
+ int offset, unsigned int len, __wsum *csump)
+{
+ __wsum csum = *csump;
+ int partial_cnt = 0, err = 0;
+
+ /* Skip over the finished iovecs */
+ while (offset >= iov->iov_len) {
+ offset -= iov->iov_len;
+ iov++;
+ }
+
+ while (len > 0) {
+ u8 __user *base = iov->iov_base + offset;
+ int copy = min_t(unsigned int, len, iov->iov_len - offset);
+
+ offset = 0;
+
+ /* There is a remnant from previous iov. */
+ if (partial_cnt) {
+ int par_len = 4 - partial_cnt;
+
+ /* iov component is too short ... */
+ if (par_len > copy) {
+ memcpy(kdata, base, copy);
+ kdata += copy;
+ base += copy;
+ partial_cnt += copy;
+ len -= copy;
+ iov++;
+ if (len)
+ continue;
+ *csump = csum_partial(kdata - partial_cnt,
+ partial_cnt, csum);
+ goto out;
+ }
+ memcpy(kdata, base, par_len);
+ csum = csum_partial(kdata - partial_cnt, 4, csum);
+ kdata += par_len;
+ base += par_len;
+ copy -= par_len;
+ len -= par_len;
+ partial_cnt = 0;
+ }
+
+ if (len > copy) {
+ partial_cnt = copy % 4;
+ if (partial_cnt) {
+ copy -= partial_cnt;
+ memcpy(kdata + copy, base + copy, partial_cnt);
+ }
+ }
+
+ if (copy) {
+ csum = csum_partial_copy_nocheck(base, kdata, copy, csum);
+ }
+ len -= copy + partial_cnt;
+ kdata += copy + partial_cnt;
+ iov++;
+ }
+ *csump = csum;
+out:
+ return err;
+}
+
+EXPORT_SYMBOL(udpredirect_getfrag);
+EXPORT_SYMBOL(udp_do_redirect_fn);
+EXPORT_SYMBOL(udpredirect_getfrag_fn);
+#endif /* CONFIG_IFX_UDP_REDIRECT* */
--- a/net/ipv4/Makefile
+++ b/net/ipv4/Makefile
@@ -14,6 +14,9 @@ obj-y := route.o inetpeer.o protocol
inet_fragment.o
obj-$(CONFIG_SYSCTL) += sysctl_net_ipv4.o
+ifneq ($(CONFIG_IFX_UDP_REDIRECT),)
+obj-$(CONFIG_IFX_UDP_REDIRECT) += udp_redirect_symb.o
+endif
obj-$(CONFIG_IP_FIB_HASH) += fib_hash.o
obj-$(CONFIG_IP_FIB_TRIE) += fib_trie.o
obj-$(CONFIG_PROC_FS) += proc.o
--- a/net/ipv4/udp.c
+++ b/net/ipv4/udp.c
@@ -106,6 +106,10 @@
#include <net/xfrm.h>
#include "udp_impl.h"
+#if defined(CONFIG_IFX_UDP_REDIRECT) || defined(CONFIG_IFX_UDP_REDIRECT_MODULE)
+#include <linux/udp_redirect.h>
+#endif
+
struct udp_table udp_table __read_mostly;
EXPORT_SYMBOL(udp_table);
@@ -782,7 +786,7 @@ int udp_sendmsg(struct kiocb *iocb, stru
u8 tos;
int err, is_udplite = IS_UDPLITE(sk);
int corkreq = up->corkflag || msg->msg_flags&MSG_MORE;
- int (*getfrag)(void *, char *, int, int, int, struct sk_buff *);
+ int (*getfrag)(void *, char *, int, int, int, struct sk_buff *) = NULL;
if (len > 0xFFFF)
return -EMSGSIZE;
@@ -944,6 +948,12 @@ back_from_confirm:
do_append_data:
up->len += ulen;
+ /* UDPREDIRECT */
+#if defined(CONFIG_IFX_UDP_REDIRECT) || defined(CONFIG_IFX_UDP_REDIRECT_MODULE)
+ if(udpredirect_getfrag_fn && sk->sk_user_data == UDP_REDIRECT_MAGIC)
+ getfrag = udpredirect_getfrag_fn;
+ else
+#endif /* IFX_UDP_REDIRECT */
getfrag = is_udplite ? udplite_getfrag : ip_generic_getfrag;
err = ip_append_data(sk, getfrag, msg->msg_iov, ulen,
sizeof(struct udphdr), &ipc, &rt,
@@ -1518,6 +1528,7 @@ int __udp4_lib_rcv(struct sk_buff *skb,
struct rtable *rt = skb_rtable(skb);
__be32 saddr, daddr;
struct net *net = dev_net(skb->dev);
+ int ret = 0;
/*
* Validate the packet.
@@ -1550,7 +1561,16 @@ int __udp4_lib_rcv(struct sk_buff *skb,
sk = __udp4_lib_lookup_skb(skb, uh->source, uh->dest, udptable);
if (sk != NULL) {
- int ret = udp_queue_rcv_skb(sk, skb);
+ /* UDPREDIRECT */
+#if defined(CONFIG_IFX_UDP_REDIRECT) || defined(CONFIG_IFX_UDP_REDIRECT_MODULE)
+ if(udp_do_redirect_fn && sk->sk_user_data == UDP_REDIRECT_MAGIC)
+ {
+ udp_do_redirect_fn(sk,skb);
+ kfree_skb(skb);
+ return(0);
+ }
+#endif
+ ret = udp_queue_rcv_skb(sk, skb);
sock_put(sk);
/* a return value > 0 means to resubmit the input, but
@@ -1845,7 +1865,7 @@ struct proto udp_prot = {
#endif
};
EXPORT_SYMBOL(udp_prot);
-
+EXPORT_SYMBOL(udp_rcv);
/* ------------------------------------------------------------------------ */
#ifdef CONFIG_PROC_FS
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -72,6 +72,12 @@ config INET
Short answer: say Y.
+config IFX_UDP_REDIRECT
+ bool "IFX Kernel Packet Interface for UDP redirection"
+ help
+ You can say Y here if you want to use hooks from kernel for
+ UDP redirection.
+
if INET
source "net/ipv4/Kconfig"
source "net/ipv6/Kconfig"

View file

@ -0,0 +1,42 @@
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -52,6 +52,8 @@
void (*_dma_cache_inv)(unsigned long start, unsigned long size);
EXPORT_SYMBOL(_dma_cache_wback_inv);
+EXPORT_SYMBOL(_dma_cache_wback);
+EXPORT_SYMBOL(_dma_cache_inv);
#endif /* CONFIG_DMA_NONCOHERENT */
--- a/net/atm/proc.c
+++ b/net/atm/proc.c
@@ -153,7 +153,7 @@
static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
{
static const char *const class_name[] = {
- "off", "UBR", "CBR", "VBR", "ABR"};
+ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"};
static const char *const aal_name[] = {
"---", "1", "2", "3/4", /* 0- 3 */
"???", "5", "???", "???", /* 4- 7 */
--- a/net/atm/common.c
+++ b/net/atm/common.c
@@ -60,11 +60,17 @@
write_unlock_irq(&vcc_sklist_lock);
}
+struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL;
+EXPORT_SYMBOL(ifx_atm_alloc_tx);
+
static struct sk_buff *alloc_tx(struct atm_vcc *vcc, unsigned int size)
{
struct sk_buff *skb;
struct sock *sk = sk_atm(vcc);
+ if (ifx_atm_alloc_tx != NULL)
+ return ifx_atm_alloc_tx(vcc, size);
+
if (sk_wmem_alloc_get(sk) && !atm_may_send(vcc, size)) {
pr_debug("Sorry: wmem_alloc = %d, size = %d, sndbuf = %d\n",
sk_wmem_alloc_get(sk), size, sk->sk_sndbuf);

View file

@ -0,0 +1,211 @@
--- a/arch/mips/include/asm/mach-lantiq/machine.h
+++ b/arch/mips/include/asm/mach-lantiq/machine.h
@@ -11,4 +11,7 @@
LANTIQ_MACH_EASY4010, /* Twinpass evalkit */
LANTIQ_MACH_EASY50712, /* Danube evalkit */
LANTIQ_MACH_EASY50812, /* AR9 eval board */
+ LANTIQ_MACH_ARV4518, /* Airties WAV-221, SMC-7908A-ISP */
+ LANTIQ_MACH_ARV452, /* Airties WAV-281, Arcor EasyboxA800 */
+ LANTIQ_MACH_ARV4525, /* Speedport W502V */
};
--- a/arch/mips/lantiq/xway/Kconfig
+++ b/arch/mips/lantiq/xway/Kconfig
@@ -14,6 +14,10 @@
bool "Easy4010"
default y
+config LANTIQ_MACH_ARV45XX
+ bool "ARV45XX"
+ default y
+
endmenu
endif
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -3,3 +3,4 @@
obj-$(CONFIG_LANTIQ_MACH_EASY50812) += mach-easy50812.o
obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
obj-$(CONFIG_LANTIQ_MACH_EASY4010) += mach-easy4010.o
+obj-$(CONFIG_LANTIQ_MACH_ARV45XX) += mach-arv45xx.o
--- /dev/null
+++ b/arch/mips/lantiq/xway/mach-arv45xx.c
@@ -0,0 +1,178 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/gpio_buttons.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/input.h>
+#include <linux/etherdevice.h>
+
+#include <machine.h>
+
+#include <xway.h>
+#include <lantiq_platform.h>
+
+#include "devices.h"
+
+#define ARV452_LATCH_SWITCH (1 << 10)
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition arv45xx_partitions[] =
+{
+ {
+ .name = "uboot",
+ .offset = 0x0,
+ .size = 0x20000,
+ },
+ {
+ .name = "uboot_env",
+ .offset = 0x20000,
+ .size = 0x10000,
+ },
+ {
+ .name = "linux",
+ .offset = 0x30000,
+ .size = 0x3c0000,
+ },
+ {
+ .name = "board_config",
+ .offset = 0x3f0000,
+ .size = 0x10000,
+ },
+};
+#endif
+
+static struct physmap_flash_data arv45xx_flash_data = {
+#ifdef CONFIG_MTD_PARTITIONS
+ .nr_parts = ARRAY_SIZE(arv45xx_partitions),
+ .parts = arv45xx_partitions,
+#endif
+};
+
+static struct lq_pci_data lq_pci_data = {
+ .clock = PCI_CLOCK_EXT,
+ .req_mask = 0xf,
+};
+
+static struct lq_eth_data lq_eth_data = {
+ .mii_mode = REV_MII_MODE,
+ .mac = "\xff\xff\xff\xff\xff\xff",
+};
+
+static struct gpio_led
+arv4518_leds_gpio[] __initdata = {
+ { .name = "soc:blue:power", .gpio = 3, .active_low = 1, },
+ { .name = "soc:blue:adsl", .gpio = 4, .active_low = 1, },
+ { .name = "soc:blue:internet", .gpio = 5, .active_low = 1, },
+ { .name = "soc:red:power", .gpio = 6, .active_low = 1, },
+ { .name = "soc:yello:wps", .gpio = 7, .active_low = 1, },
+ { .name = "soc:red:wps", .gpio = 9, .active_low = 1, },
+ { .name = "soc:blue:voip", .gpio = 32, .active_low = 1, },
+ { .name = "soc:blue:fxs1", .gpio = 33, .active_low = 1, },
+ { .name = "soc:blue:fxs2", .gpio = 34, .active_low = 1, },
+ { .name = "soc:blue:fxo", .gpio = 35, .active_low = 1, },
+ { .name = "soc:blue:voice", .gpio = 36, .active_low = 1, },
+ { .name = "soc:blue:usb", .gpio = 37, .active_low = 1, },
+ { .name = "soc:blue:wlan", .gpio = 38, .active_low = 1, },
+};
+
+static struct gpio_led
+arv452_leds_gpio[] __initdata = {
+ { .name = "soc:blue:power", .gpio = 3, .active_low = 1, },
+ { .name = "soc:blue:adsl", .gpio = 4, .active_low = 1, },
+ { .name = "soc:blue:internet", .gpio = 5, .active_low = 1, },
+ { .name = "soc:red:power", .gpio = 6, .active_low = 1, },
+ { .name = "soc:yello:wps", .gpio = 7, .active_low = 1, },
+ { .name = "soc:red:wps", .gpio = 9, .active_low = 1, },
+ { .name = "soc:blue:voip", .gpio = 32, .active_low = 1, },
+ { .name = "soc:blue:fxs1", .gpio = 33, .active_low = 1, },
+ { .name = "soc:blue:fxs2", .gpio = 34, .active_low = 1, },
+ { .name = "soc:blue:fxo", .gpio = 35, .active_low = 1, },
+ { .name = "soc:blue:voice", .gpio = 36, .active_low = 1, },
+ { .name = "soc:blue:usb", .gpio = 37, .active_low = 1, },
+ { .name = "soc:blue:wlan", .gpio = 38, .active_low = 1, },
+};
+
+static struct gpio_led arv4525_leds_gpio[] __initdata = {
+ { .name = "soc:green:festnetz", .gpio = 4, .active_low = 1, },
+ { .name = "soc:green:internet", .gpio = 5, .active_low = 1, },
+ { .name = "soc:green:dsl", .gpio = 6, .active_low = 1, },
+ { .name = "soc:green:wlan", .gpio = 8, .active_low = 1, },
+ { .name = "soc:green:online", .gpio = 9, .active_low = 1, },
+};
+
+static void
+arv45xx_register_ethernet(void)
+{
+#define ARV45XX_BRN_MAC 0x3f0016
+ memcpy_fromio(lq_eth_data.mac,
+ (void *)KSEG1ADDR(LQ_FLASH_START + ARV45XX_BRN_MAC), 6);
+ lq_register_ethernet(&lq_eth_data);
+}
+
+static void __init
+arv4518_init(void)
+{
+ lq_register_gpio();
+ lq_register_gpio_ebu(0);
+ lq_register_gpio_leds(arv4518_leds_gpio, ARRAY_SIZE(arv4518_leds_gpio));
+ lq_register_asc(0);
+ lq_register_asc(1);
+ lq_register_nor(&arv45xx_flash_data);
+ lq_register_pci(&lq_pci_data);
+ lq_register_wdt();
+ arv45xx_register_ethernet();
+}
+
+MIPS_MACHINE(LANTIQ_MACH_ARV4518,
+ "ARV4518",
+ "ARV4518 - SMC7908A-ISP",
+ arv4518_init);
+
+static void __init
+arv452_init(void)
+{
+ lq_register_gpio();
+ lq_register_gpio_ebu(ARV452_LATCH_SWITCH);
+ lq_register_gpio_leds(arv452_leds_gpio, ARRAY_SIZE(arv452_leds_gpio));
+ lq_register_asc(0);
+ lq_register_asc(1);
+ lq_register_nor(&arv45xx_flash_data);
+ lq_register_pci(&lq_pci_data);
+ lq_register_wdt();
+ arv45xx_register_ethernet();
+}
+
+MIPS_MACHINE(LANTIQ_MACH_ARV452,
+ "ARV452",
+ "ARV452 - Airties WAV-281, Arcor A800",
+ arv452_init);
+
+static void __init
+arv4525_init(void)
+{
+ lq_register_gpio();
+ lq_register_gpio_leds(arv4525_leds_gpio, ARRAY_SIZE(arv4525_leds_gpio));
+ lq_register_asc(0);
+ lq_register_asc(1);
+ lq_register_nor(&arv45xx_flash_data);
+ lq_register_pci(&lq_pci_data);
+ lq_register_wdt();
+ lq_eth_data.mii_mode = MII_MODE;
+ arv45xx_register_ethernet();
+}
+
+MIPS_MACHINE(LANTIQ_MACH_ARV4525,
+ "ARV4525",
+ "ARV4525 - Speedport W502V",
+ arv4525_init);

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File diff suppressed because it is too large Load diff

View file

@ -0,0 +1,301 @@
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1706,6 +1706,28 @@
help
IFX included extensions in APRP
+config IFX_VPE_CACHE_SPLIT
+ bool "IFX Cache Split Ways"
+ depends on IFX_VPE_EXT
+ help
+ IFX extension for reserving (splitting) cache ways among VPEs. You must
+ give kernel command line arguments vpe_icache_shared=0 or
+ vpe_dcache_shared=0 to enable splitting of icache or dcache
+ respectively. Then you can specify which cache ways should be
+ assigned to which VPE. There are total 8 cache ways, 4 each
+ for dcache and icache: dcache_way0, dcache_way1,dcache_way2,
+ dcache_way3 and icache_way0,icache_way1, icache_way2,icache_way3.
+
+ For example, if you specify vpe_icache_shared=0 and icache_way2=1,
+ then the 3rd icache way will be assigned to VPE0 and denied in VPE1.
+
+ For icache, software is required to make at least one cache way available
+ for a VPE at all times i.e., one can't assign all the icache ways to one
+ VPE.
+
+ By default, vpe_dcache_shared and vpe_icache_shared are set to 1
+ (i.e., both icache and dcache are shared among VPEs)
+
config PERFCTRS
bool "34K Performance counters"
depends on MIPS_MT && PROC_FS
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -128,6 +128,13 @@
EXPORT_SYMBOL(vpe1_wdog_timeout);
#endif
+
+#ifdef CONFIG_IFX_VPE_CACHE_SPLIT /* Code for splitting the cache ways among VPEs. */
+extern int vpe_icache_shared,vpe_dcache_shared;
+extern int icache_way0,icache_way1,icache_way2,icache_way3;
+extern int dcache_way0,dcache_way1,dcache_way2,dcache_way3;
+#endif
+
/* grab the likely amount of memory we will need. */
#ifdef CONFIG_MIPS_VPE_LOADER_TOM
#define P_SIZE (2 * 1024 * 1024)
@@ -866,6 +873,65 @@
/* enable this VPE */
write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
+#ifdef CONFIG_IFX_VPE_CACHE_SPLIT
+ if ( (!vpe_icache_shared) || (!vpe_dcache_shared) ) {
+
+ /* PCP bit must be 1 to split the cache */
+ if(read_c0_mvpconf0() & MVPCONF0_PCP) {
+
+ if ( !vpe_icache_shared ){
+ write_vpe_c0_vpeconf0((read_vpe_c0_vpeconf0()) & ~VPECONF0_ICS);
+
+ /*
+ * If any cache way is 1, then that way is denied
+ * in VPE1. Otherwise assign that way to VPE1.
+ */
+ if (!icache_way0)
+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_IWX0 );
+ else
+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_IWX0 );
+ if (!icache_way1)
+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_IWX1 );
+ else
+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_IWX1 );
+ if (!icache_way2)
+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_IWX2 );
+ else
+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_IWX2 );
+ if (!icache_way3)
+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_IWX3 );
+ else
+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_IWX3 );
+ }
+
+ if ( !vpe_dcache_shared ) {
+ write_vpe_c0_vpeconf0((read_vpe_c0_vpeconf0()) & ~VPECONF0_DCS);
+
+ /*
+ * If any cache way is 1, then that way is denied
+ * in VPE1. Otherwise assign that way to VPE1.
+ */
+ if (!dcache_way0)
+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_DWX0 );
+ else
+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_DWX0 );
+ if (!dcache_way1)
+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_DWX1 );
+ else
+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_DWX1 );
+ if (!dcache_way2)
+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_DWX2 );
+ else
+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_DWX2 );
+ if (!dcache_way3)
+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_DWX3 );
+ else
+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_DWX3 );
+ }
+ }
+ }
+#endif /* endif CONFIG_IFX_VPE_CACHE_SPLIT */
+
/* clear out any left overs from a previous program */
write_vpe_c0_status(0);
write_vpe_c0_cause(0);
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1348,6 +1348,106 @@
__setup("coherentio", setcoherentio);
#endif
+#ifdef CONFIG_IFX_VPE_CACHE_SPLIT /* Code for splitting the cache ways among VPEs. */
+
+#include <asm/mipsmtregs.h>
+
+/*
+ * By default, vpe_icache_shared and vpe_dcache_shared
+ * values are 1 i.e., both icache and dcache are shared
+ * among the VPEs.
+ */
+
+int vpe_icache_shared = 1;
+static int __init vpe_icache_shared_val(char *str)
+{
+ get_option(&str, &vpe_icache_shared);
+ return 1;
+}
+__setup("vpe_icache_shared=", vpe_icache_shared_val);
+EXPORT_SYMBOL(vpe_icache_shared);
+
+int vpe_dcache_shared = 1;
+static int __init vpe_dcache_shared_val(char *str)
+{
+ get_option(&str, &vpe_dcache_shared);
+ return 1;
+}
+__setup("vpe_dcache_shared=", vpe_dcache_shared_val);
+EXPORT_SYMBOL(vpe_dcache_shared);
+
+/*
+ * Software is required to make atleast one icache
+ * way available for a VPE at all times i.e., one
+ * can't assign all the icache ways to one VPE.
+ */
+
+int icache_way0 = 0;
+static int __init icache_way0_val(char *str)
+{
+ get_option(&str, &icache_way0);
+ return 1;
+}
+__setup("icache_way0=", icache_way0_val);
+
+int icache_way1 = 0;
+static int __init icache_way1_val(char *str)
+{
+ get_option(&str, &icache_way1);
+ return 1;
+}
+__setup("icache_way1=", icache_way1_val);
+
+int icache_way2 = 0;
+static int __init icache_way2_val(char *str)
+{
+ get_option(&str, &icache_way2);
+ return 1;
+}
+__setup("icache_way2=", icache_way2_val);
+
+int icache_way3 = 0;
+static int __init icache_way3_val(char *str)
+{
+ get_option(&str, &icache_way3);
+ return 1;
+}
+__setup("icache_way3=", icache_way3_val);
+
+int dcache_way0 = 0;
+static int __init dcache_way0_val(char *str)
+{
+ get_option(&str, &dcache_way0);
+ return 1;
+}
+__setup("dcache_way0=", dcache_way0_val);
+
+int dcache_way1 = 0;
+static int __init dcache_way1_val(char *str)
+{
+ get_option(&str, &dcache_way1);
+ return 1;
+}
+__setup("dcache_way1=", dcache_way1_val);
+
+int dcache_way2 = 0;
+static int __init dcache_way2_val(char *str)
+{
+ get_option(&str, &dcache_way2);
+ return 1;
+}
+__setup("dcache_way2=", dcache_way2_val);
+
+int dcache_way3 = 0;
+static int __init dcache_way3_val(char *str)
+{
+ get_option(&str, &dcache_way3);
+ return 1;
+}
+__setup("dcache_way3=", dcache_way3_val);
+
+#endif /* endif CONFIG_IFX_VPE_CACHE_SPLIT */
+
void __cpuinit r4k_cache_init(void)
{
extern void build_clear_page(void);
@@ -1367,6 +1467,78 @@
break;
}
+#ifdef CONFIG_IFX_VPE_CACHE_SPLIT
+ /*
+ * We split the cache ways appropriately among the VPEs
+ * based on cache ways values we received as command line
+ * arguments
+ */
+ if ( (!vpe_icache_shared) || (!vpe_dcache_shared) ){
+
+ /* PCP bit must be 1 to split the cache */
+ if(read_c0_mvpconf0() & MVPCONF0_PCP) {
+
+ /* Set CPA bit which enables us to modify VPEOpt register */
+ write_c0_mvpcontrol((read_c0_mvpcontrol()) | MVPCONTROL_CPA);
+
+ if ( !vpe_icache_shared ){
+ write_c0_vpeconf0((read_c0_vpeconf0()) & ~VPECONF0_ICS);
+ /*
+ * If any cache way is 1, then that way is denied
+ * in VPE0. Otherwise assign that way to VPE0.
+ */
+ printk(KERN_DEBUG "icache is split\n");
+ printk(KERN_DEBUG "icache_way0=%d icache_way1=%d icache_way2=%d icache_way3=%d\n",
+ icache_way0, icache_way1,icache_way2, icache_way3);
+ if (icache_way0)
+ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_IWX0 );
+ else
+ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_IWX0 );
+ if (icache_way1)
+ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_IWX1 );
+ else
+ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_IWX1 );
+ if (icache_way2)
+ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_IWX2 );
+ else
+ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_IWX2 );
+ if (icache_way3)
+ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_IWX3 );
+ else
+ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_IWX3 );
+ }
+
+ if ( !vpe_dcache_shared ) {
+ /*
+ * If any cache way is 1, then that way is denied
+ * in VPE0. Otherwise assign that way to VPE0.
+ */
+ printk(KERN_DEBUG "dcache is split\n");
+ printk(KERN_DEBUG "dcache_way0=%d dcache_way1=%d dcache_way2=%d dcache_way3=%d\n",
+ dcache_way0, dcache_way1, dcache_way2, dcache_way3);
+ write_c0_vpeconf0((read_c0_vpeconf0()) & ~VPECONF0_DCS);
+ if (dcache_way0)
+ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_DWX0 );
+ else
+ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_DWX0 );
+ if (dcache_way1)
+ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_DWX1 );
+ else
+ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_DWX1 );
+ if (dcache_way2)
+ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_DWX2 );
+ else
+ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_DWX2 );
+ if (dcache_way3)
+ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_DWX3 );
+ else
+ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_DWX3 );
+ }
+ }
+ }
+
+#endif /* endif CONFIG_IFX_VPE_CACHE_SPLIT */
+
probe_pcache();
setup_scache();

View file

@ -0,0 +1,40 @@
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/pci.h
@@ -0,0 +1,14 @@
+/*
+ * lantiq SoCs specific PCI definitions
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_LANTIQ_PCI_H
+#define __ASM_MACH_LANTIQ_PCI_H
+
+extern int (*ifxmips_pci_plat_dev_init)(struct pci_dev *dev);
+
+#endif
--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -68,6 +68,8 @@
u32 lq_pci_mapped_cfg;
+int (*lqpci_plat_dev_init)(struct pci_dev *dev) = NULL;
+
/* Since the PCI REQ pins can be reused for other functionality, make it possible
to exclude those from interpretation by the PCI controller */
static int lq_pci_req_mask = 0xf;
@@ -126,6 +128,10 @@
printk ("WARNING: invalid interrupt pin %d\n", pin);
return 1;
}
+
+ if (lqpci_plat_dev_init)
+ return lqpci_plat_dev_init(dev);
+
return 0;
}

View file

@ -0,0 +1,21 @@
# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
# CONFIG_CRYPTO_HW is not set
CONFIG_HAVE_IDE=y
CONFIG_HW_HAS_PCI=y
CONFIG_IMAGE_CMDLINE_HACK=y
CONFIG_LANTIQ_ETOP=y
CONFIG_LANTIQ_MACH_ARV45XX=y
CONFIG_LANTIQ_MACH_EASY4010=y
CONFIG_LANTIQ_MACH_EASY50712=y
CONFIG_LANTIQ_MACH_EASY50812=y
# CONFIG_LANTIQ_PROM_ASC0 is not set
CONFIG_LANTIQ_PROM_ASC1=y
CONFIG_LANTIQ_WDT=y
CONFIG_LEDS_GPIO=y
# CONFIG_LOONGSON_MC146818 is not set
CONFIG_LOONGSON_UART_BASE=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_SCSI_MOD=y
CONFIG_SOC_LANTIQ=y
CONFIG_SOC_LANTIQ_XWAY=y
CONFIG_USB_SUPPORT=y

View file

@ -0,0 +1,11 @@
ARCH:=mips
SUBTARGET:=xway
BOARDNAME:=Xway
FEATURES:=squashfs jffs2 atm
DEFAULT_PACKAGES+=uboot-lantiq-easy50712 kmod-pppoa ppp-mod-pppoa linux-atm atm-tools br2684ctl ifxmips-dsl-api ifxmips-dsl-control ifx-tapidemo
define Target/Description
Lantiq XWAY (danube/twinpass/ar9)
endef