merge 2.6.30 patches
SVN-Revision: 16926
This commit is contained in:
parent
d522d7d6e3
commit
9e6605553a
7 changed files with 78 additions and 132 deletions
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@ -1,10 +1,11 @@
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--- /dev/null
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+++ b/arch/powerpc/boot/cuboot-magicboxv2.c
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@@ -0,0 +1,41 @@
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@@ -0,0 +1,70 @@
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+/*
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+ * Old U-boot compatibility for Magicbox v2
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+ *
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+ * Author: Imre Kaloz <kaloz@openwrt.org>
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+ * Gabor Juhos <juhosg@openwrt.org>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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@ -25,8 +26,36 @@
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+
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+static bd_t bd;
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+
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+static void fixup_cf_card(void)
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+{
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+#define DCRN_CPC0_PCI_BASE 0xf9
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+#define CF_CS0_BASE 0xff100000
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+#define CF_CS1_BASE 0xff200000
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+
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+ /* Turn on PerWE instead of PCIsomething */
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+ mtdcr(DCRN_CPC0_PCI_BASE,
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+ mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27));
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+
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+ /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR);
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+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP);
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+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
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+
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+ /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR);
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+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP);
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+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
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+
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+#undef DCRN_CPC0_PCI_BASE
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+#undef CF_CS0_BASE
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+#undef CF_CS1_BASE
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+}
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+
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+static void magicboxv2_fixups(void)
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+{
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+ fixup_cf_card();
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+ ibm405ep_fixup_clocks(25000000);
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+ ibm4xx_sdram_fixup_memsize();
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+ dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
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@ -44,11 +73,12 @@
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+
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--- /dev/null
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+++ b/arch/powerpc/boot/dts/magicboxv2.dts
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@@ -0,0 +1,250 @@
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@@ -0,0 +1,259 @@
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+/*
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+ * Device Tree Source for Magicbox v2
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+ *
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+ * Copyright 2008 Imre Kaloz <kaloz@openwrt.org>
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+ * Copyright 2009 Gabor Juhos <juhosg@openwrt.org>
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+ *
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+ * Based on walnut.dts
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+ *
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@ -230,6 +260,14 @@
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+ */
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+ clock-frequency = <0>; /* Filled in by zImage */
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+
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+ cf_card@ff100000 {
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+ compatible = "magicbox-cf";
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+ reg = <0x00000000 0xff100000 0x00001000
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+ 0x00000000 0xff200000 0x00001000>;
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+ interrupt-parent = <&UIC0>;
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+ interrupts = <0x19 0x1 /* IRQ_TYPE_EDGE_RISING */ >;
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+ };
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+
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+ nor_flash@ffc00000 {
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+ compatible = "cfi-flash";
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+ bank-width = <2>;
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@ -48,7 +48,7 @@
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static int __init ppc40x_probe(void)
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--- /dev/null
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+++ b/arch/powerpc/boot/cuboot-openrb-light.c
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@@ -0,0 +1,41 @@
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@@ -0,0 +1,69 @@
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+/*
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+ * Old U-boot compatibility for OpenRB Light board
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+ *
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@ -73,8 +73,36 @@
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+
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+static bd_t bd;
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+
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+static void fixup_cf_card(void)
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+{
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+#define DCRN_CPC0_PCI_BASE 0xf9
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+#define CF_CS0_BASE 0xff100000
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+#define CF_CS1_BASE 0xff200000
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+
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+ /* Turn on PerWE instead of PCIsomething */
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+ mtdcr(DCRN_CPC0_PCI_BASE,
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+ mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27));
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+
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+ /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR);
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+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP);
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+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
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+
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+ /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR);
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+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP);
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+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
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+
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+#undef DCRN_CPC0_PCI_BASE
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+#undef CF_CS0_BASE
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+#undef CF_CS1_BASE
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+}
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+
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+static void openrb_light_fixups(void)
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+{
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+ fixup_cf_card();
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+ ibm405ep_fixup_clocks(33333000);
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+ ibm4xx_sdram_fixup_memsize();
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+ dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
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@ -92,7 +120,7 @@
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+
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--- /dev/null
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+++ b/arch/powerpc/boot/dts/openrb-light.dts
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@@ -0,0 +1,244 @@
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@@ -0,0 +1,252 @@
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+/*
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+ * Device Tree Source for OpenRB Light board
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+ *
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@ -272,6 +300,14 @@
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+ */
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+ clock-frequency = <0>; /* Filled in by zImage */
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+
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+ cf_card@ff100000 {
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+ compatible = "magicbox-cf";
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+ reg = <0x00000000 0xff100000 0x00001000
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+ 0x00000000 0xff200000 0x00001000>;
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+ interrupt-parent = <&UIC0>;
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+ interrupts = <0x19 0x1 /* IRQ_TYPE_EDGE_RISING */ >;
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+ };
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+
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+ nor_flash@ff800000 {
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+ compatible = "cfi-flash";
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+ bank-width = <2>;
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@ -1,39 +0,0 @@
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--- a/arch/powerpc/boot/cuboot-openrb-light.c
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+++ b/arch/powerpc/boot/cuboot-openrb-light.c
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@@ -22,8 +22,36 @@
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static bd_t bd;
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+static void fixup_cf_card(void)
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+{
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+#define DCRN_CPC0_PCI_BASE 0xf9
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+#define CF_CS0_BASE 0xff100000
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+#define CF_CS1_BASE 0xff200000
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+
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+ /* Turn on PerWE instead of PCIsomething */
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+ mtdcr(DCRN_CPC0_PCI_BASE,
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+ mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27));
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+
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+ /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR);
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+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP);
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+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
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+
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+ /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR);
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+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP);
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+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
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+
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+#undef DCRN_CPC0_PCI_BASE
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+#undef CF_CS0_BASE
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+#undef CF_CS1_BASE
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+}
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+
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static void openrb_light_fixups(void)
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{
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+ fixup_cf_card();
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ibm405ep_fixup_clocks(33333000);
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ibm4xx_sdram_fixup_memsize();
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dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
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@ -1,17 +0,0 @@
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--- a/arch/powerpc/boot/dts/openrb-light.dts
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+++ b/arch/powerpc/boot/dts/openrb-light.dts
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@@ -177,6 +177,14 @@
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*/
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clock-frequency = <0>; /* Filled in by zImage */
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+ cf_card@ff100000 {
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+ compatible = "magicbox-cf";
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+ reg = <0x00000000 0xff100000 0x00001000
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+ 0x00000000 0xff200000 0x00001000>;
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+ interrupt-parent = <&UIC0>;
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+ interrupts = <0x19 0x1 /* IRQ_TYPE_EDGE_RISING */ >;
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+ };
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+
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nor_flash@ff800000 {
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compatible = "cfi-flash";
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bank-width = <2>;
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@ -1,47 +0,0 @@
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--- a/arch/powerpc/boot/cuboot-magicboxv2.c
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+++ b/arch/powerpc/boot/cuboot-magicboxv2.c
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@@ -2,6 +2,7 @@
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* Old U-boot compatibility for Magicbox v2
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*
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* Author: Imre Kaloz <kaloz@openwrt.org>
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+ * Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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@@ -22,8 +23,36 @@
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static bd_t bd;
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+static void fixup_cf_card(void)
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+{
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+#define DCRN_CPC0_PCI_BASE 0xf9
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+#define CF_CS0_BASE 0xff100000
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+#define CF_CS1_BASE 0xff200000
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+
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+ /* Turn on PerWE instead of PCIsomething */
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+ mtdcr(DCRN_CPC0_PCI_BASE,
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+ mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27));
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+
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+ /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR);
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+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP);
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+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
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+
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+ /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR);
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+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP);
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+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
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+
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+#undef DCRN_CPC0_PCI_BASE
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+#undef CF_CS0_BASE
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+#undef CF_CS1_BASE
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+}
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+
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static void magicboxv2_fixups(void)
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{
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+ fixup_cf_card();
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ibm405ep_fixup_clocks(25000000);
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ibm4xx_sdram_fixup_memsize();
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dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
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@ -1,25 +0,0 @@
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--- a/arch/powerpc/boot/dts/magicboxv2.dts
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+++ b/arch/powerpc/boot/dts/magicboxv2.dts
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@@ -2,6 +2,7 @@
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* Device Tree Source for Magicbox v2
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*
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* Copyright 2008 Imre Kaloz <kaloz@openwrt.org>
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+ * Copyright 2009 Gabor Juhos <juhosg@openwrt.org>
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*
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* Based on walnut.dts
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*
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@@ -183,6 +184,14 @@
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*/
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clock-frequency = <0>; /* Filled in by zImage */
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+ cf_card@ff100000 {
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+ compatible = "magicbox-cf";
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+ reg = <0x00000000 0xff100000 0x00001000
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+ 0x00000000 0xff200000 0x00001000>;
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+ interrupt-parent = <&UIC0>;
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+ interrupts = <0x19 0x1 /* IRQ_TYPE_EDGE_RISING */ >;
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+ };
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+
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nor_flash@ffc00000 {
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compatible = "cfi-flash";
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bank-width = <2>;
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