fix SPI register definitions
SVN-Revision: 14754
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cfadb8fc40
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1 changed files with 14 additions and 6 deletions
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@ -757,7 +757,7 @@
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*************************************************************************/
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*************************************************************************/
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/* BCM 6338 SPI core */
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/* BCM 6338 SPI core */
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#define SPI_BCM_6338_SPI_CMD 0x00
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#define SPI_BCM_6338_SPI_CMD 0x00 /* 16-bits register */
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#define SPI_BCM_6338_SPI_INT_STATUS 0x02
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#define SPI_BCM_6338_SPI_INT_STATUS 0x02
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#define SPI_BCM_6338_SPI_MASK_INT_ST 0x03
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#define SPI_BCM_6338_SPI_MASK_INT_ST 0x03
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#define SPI_BCM_6338_SPI_INT_MASK 0x04
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#define SPI_BCM_6338_SPI_INT_MASK 0x04
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@ -773,16 +773,23 @@
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#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
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#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
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/* BCM 6348 SPI core */
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/* BCM 6348 SPI core */
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#define SPI_BCM_6348_SPI_CMD1 0x00
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#define SPI_BCM_6348_SPI_MASK_INT_ST 0x00
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#define SPI_BCM_6348_SPI_CMD2 0x04
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#define SPI_BCM_6348_SPI_INT_STATUS 0x01
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#define SPI_BCM_6348_SPI_TAIL 0x08
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#define SPI_BCM_6348_SPI_CMD 0x02 /* 16-bits register */
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#define SPI_BCM_6348_SPI_FILL_BYTE 0x04
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#define SPI_BCM_6348_SPI_CLK_CFG 0x05
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#define SPI_BCM_6348_SPI_ST 0x06
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#define SPI_BCM_6348_SPI_INT_MASK 0x07
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#define SPI_BCM_6348_SPI_RX_TAIL 0x08
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#define SPI_BCM_6348_SPI_MSG_TAIL 0x10
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#define SPI_BCM_6348_SPI_MSG_DATA 0x40
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#define SPI_BCM_6348_SPI_MSG_DATA 0x40
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#define SPI_BCM_6348_SPI_MSG_CTL 0x42
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#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
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#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
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#define SPI_BCM_6348_SPI_RX_DATA 0x80
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#define SPI_BCM_6348_SPI_RX_DATA 0x80
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#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
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#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
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/* BCM 6358 SPI core */
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/* BCM 6358 SPI core */
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#define SPI_BCM_6358_MSG_CTL 0x00
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#define SPI_BCM_6358_MSG_CTL 0x00 /* 16-bits register */
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#define SPI_BCM_6358_SPI_MSG_DATA 0x02
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#define SPI_BCM_6358_SPI_MSG_DATA 0x02
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#define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
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#define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
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@ -790,7 +797,7 @@
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#define SPI_BCM_6358_SPI_RX_FIFO 0x400
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#define SPI_BCM_6358_SPI_RX_FIFO 0x400
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#define SPI_BCM_6358_SPI_RX_FIFO_SIZE 0x220
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#define SPI_BCM_6358_SPI_RX_FIFO_SIZE 0x220
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#define SPI_BCM_6358_SPI_CMD 0x700
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#define SPI_BCM_6358_SPI_CMD 0x700 /* 16-bits register */
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#define SPI_BCM_6358_SPI_INT_STATUS 0x702
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#define SPI_BCM_6358_SPI_INT_STATUS 0x702
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#define SPI_BCM_6358_SPI_MASK_INT_ST 0x703
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#define SPI_BCM_6358_SPI_MASK_INT_ST 0x703
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@ -811,6 +818,7 @@
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#define SPI_FD_RW 0
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#define SPI_FD_RW 0
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#define SPI_HD_W 1
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#define SPI_HD_W 1
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#define SPI_HD_R 2
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#define SPI_HD_R 2
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#define SPI_BYTE_CNT_SHIFT 0
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#define SPI_MSG_TYPE_SHIFT 14
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#define SPI_MSG_TYPE_SHIFT 14
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/* Command */
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/* Command */
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