cns3xxx: update to linux 4.4

Signed-off-by: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 48334
This commit is contained in:
Felix Fietkau 2016-01-18 22:38:23 +00:00
parent 91278df70e
commit 87e4f9f009
28 changed files with 171 additions and 190 deletions

View file

@ -14,7 +14,7 @@ CPU_TYPE:=mpcore
CPU_SUBTYPE:=vfp
MAINTAINER:=Felix Fietkau <nbd@openwrt.org>
KERNEL_PATCHVER:=3.18
KERNEL_PATCHVER:=4.4
include $(INCLUDE_DIR)/target.mk

View file

@ -1,7 +1,8 @@
CONFIG_ALIGNMENT_TRAP=y
CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
CONFIG_ARCH_CNS3XXX=y
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
CONFIG_ARCH_HAS_SG_CHAIN=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
@ -29,6 +30,7 @@ CONFIG_ARM=y
# CONFIG_ARM_CPU_SUSPEND is not set
CONFIG_ARM_GIC=y
CONFIG_ARM_HAS_SG_CHAIN=y
CONFIG_ARM_HEAVY_MB=y
CONFIG_ARM_L1_CACHE_SHIFT=5
CONFIG_ARM_PATCH_PHYS_VIRT=y
CONFIG_ARM_THUMB=y
@ -36,17 +38,17 @@ CONFIG_ATA=y
CONFIG_ATAGS=y
# CONFIG_ATA_SFF is not set
CONFIG_ATA_VERBOSE_ERROR=y
# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
CONFIG_AUTO_ZRELADDR=y
CONFIG_BCM_NET_PHYLIB=y
CONFIG_BLK_DEV_SD=y
CONFIG_BROADCOM_PHY=y
CONFIG_CACHE_L2X0=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLKSRC_OF=y
CONFIG_CLKSRC_PROBE=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CNS3XXX_ETH=y
CONFIG_COMMON_CLK=y
# CONFIG_COMMON_CLK_PXA is not set
CONFIG_CPU_32v6=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_ABRT_EV6=y
@ -60,29 +62,33 @@ CONFIG_CPU_HAS_ASID=y
# CONFIG_CPU_ICACHE_DISABLE is not set
CONFIG_CPU_PABRT_V6=y
CONFIG_CPU_RMAP=y
# CONFIG_CPU_SW_DOMAIN_PAN is not set
CONFIG_CPU_TLB_V6=y
CONFIG_CPU_V6K=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
# CONFIG_DEBUG_UART_8250 is not set
# CONFIG_DEBUG_UART_BCM63XX is not set
# CONFIG_DEBUG_UART_PL01X is not set
# CONFIG_DEBUG_USER is not set
CONFIG_DMA_CACHE_FIQ_BROADCAST=y
CONFIG_DTC=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EEPROM_AT24=y
CONFIG_FIQ=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FRAME_POINTER=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IO=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
@ -102,12 +108,14 @@ CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
# CONFIG_HAVE_ARCH_BITREVERSE is not set
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_ARCH_PFN_VALID=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_ARM_SCU=y
CONFIG_HAVE_ARM_TWD=y
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
CONFIG_HAVE_BPF_JIT=y
CONFIG_HAVE_CC_STACKPROTECTOR=y
@ -133,8 +141,10 @@ CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_HAVE_NET_DSA=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_OPTPROBES=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
@ -152,19 +162,19 @@ CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_CNS3XXX=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_INTEL_SOC_PMIC is not set
CONFIG_IOMMU_HELPER=y
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
CONFIG_LEDS_GPIO=y
# CONFIG_LEDS_TRIGGER_NETDEV is not set
CONFIG_LIBFDT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
# CONFIG_MACH_CNS3420VB is not set
CONFIG_MACH_GW2388=y
CONFIG_MDIO_BOARDINFO=y
# CONFIG_MFD_AXP20X is not set
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGHT_HAVE_PCI=y
CONFIG_MMC=y
@ -182,7 +192,6 @@ CONFIG_MULTI_IRQ_HANDLER=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_VENDOR_CAVIUM=y
CONFIG_NLS=y
CONFIG_NO_BOOTMEM=y
CONFIG_NR_CPUS=2
@ -204,23 +213,23 @@ CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OUTER_CACHE=y
CONFIG_OUTER_CACHE_SYNC=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PCI=y
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
# CONFIG_PHY_SAMSUNG_USB2 is not set
CONFIG_PL310_ERRATA_588369=y
CONFIG_PL310_ERRATA_727915=y
CONFIG_PL310_ERRATA_753970=y
CONFIG_PL310_ERRATA_769419=y
CONFIG_PPS=y
CONFIG_PPS_CLIENT_GPIO=y
# CONFIG_PREEMPT_RCU is not set
# CONFIG_PROC_STRIPPED is not set
CONFIG_RAID_ATTRS=y
CONFIG_RATIONAL=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
@ -231,12 +240,13 @@ CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_SATA_AHCI=y
CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_SCHED_HRTICK=y
# CONFIG_SCHED_INFO is not set
CONFIG_SCSI=y
CONFIG_SENSORS_AD7418=y
CONFIG_SENSORS_GSC=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_NR_UARTS=3
CONFIG_SERIAL_8250_RUNTIME_UARTS=3
CONFIG_SERIAL_EARLYCON=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
CONFIG_SPARSE_IRQ=y
@ -244,13 +254,13 @@ CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_CNS3XXX=y
CONFIG_SPI_MASTER=y
CONFIG_SRCU=y
# CONFIG_STAGING is not set
CONFIG_STOP_MACHINE=y
# CONFIG_SUNXI_SRAM is not set
CONFIG_SWIOTLB=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TREE_RCU=y
CONFIG_UID16=y
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
@ -258,18 +268,14 @@ CONFIG_USB_CNS3XXX_EHCI=y
CONFIG_USB_CNS3XXX_OHCI=y
CONFIG_USB_COMMON=y
CONFIG_USB_DWC2=y
# CONFIG_USB_DWC2_DEBUG is not set
CONFIG_USB_DWC2_HOST=y
# CONFIG_USB_DWC2_PCI is not set
# CONFIG_USB_DWC2_PERIPHERAL is not set
CONFIG_USB_DWC2_PLATFORM=y
# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_EHCI_PCI=y
# CONFIG_USB_ETH is not set
CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_XILINX is not set
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_SUPPORT=y

View file

@ -139,10 +139,10 @@ static int cns3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
/* one interrupt per GPIO controller (GPIOA/GPIOB)
* this is called in task context, with IRQs enabled
*/
static void cns3xxx_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
static void cns3xxx_gpio_irq_handler(struct irq_desc *desc)
{
struct cns3xxx_gpio_chip *cchip = irq_get_handler_data(irq);
struct irq_chip *chip = irq_get_chip(irq);
struct cns3xxx_gpio_chip *cchip = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
u16 i;
u32 reg;
@ -211,9 +211,9 @@ static int cns3xxx_gpio_irq_set_type(struct irq_data *d, u32 irqtype)
spin_unlock_irqrestore(&cchip->lock, flags);
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
__irq_set_handler_locked(d->irq, handle_level_irq);
irq_set_handler_locked(d, handle_level_irq);
else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
__irq_set_handler_locked(d->irq, handle_edge_irq);
irq_set_handler_locked(d, handle_edge_irq);
return 0;
}

View file

@ -1,11 +0,0 @@
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -339,7 +339,7 @@ static struct usb_ohci_pdata cns3xxx_usb
.power_off = csn3xxx_usb_power_off,
};
-static struct of_dev_auxdata cns3xxx_auxdata[] __initconst = {
+static const struct of_dev_auxdata cns3xxx_auxdata[] __initconst = {
{ "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata },
{ "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata },
{ "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL },

View file

@ -1,20 +0,0 @@
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -34,6 +34,7 @@ source "drivers/net/ethernet/adi/Kconfig
source "drivers/net/ethernet/broadcom/Kconfig"
source "drivers/net/ethernet/brocade/Kconfig"
source "drivers/net/ethernet/calxeda/Kconfig"
+source "drivers/net/ethernet/cavium/Kconfig"
source "drivers/net/ethernet/chelsio/Kconfig"
source "drivers/net/ethernet/cirrus/Kconfig"
source "drivers/net/ethernet/cisco/Kconfig"
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_NET_BFIN) += adi/
obj-$(CONFIG_NET_VENDOR_BROADCOM) += broadcom/
obj-$(CONFIG_NET_VENDOR_BROCADE) += brocade/
obj-$(CONFIG_NET_CALXEDA_XGMAC) += calxeda/
+obj-$(CONFIG_NET_VENDOR_CAVIUM) += cavium/
obj-$(CONFIG_NET_VENDOR_CHELSIO) += chelsio/
obj-$(CONFIG_NET_VENDOR_CIRRUS) += cirrus/
obj-$(CONFIG_NET_VENDOR_CISCO) += cisco/

View file

@ -1,28 +1,26 @@
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -156,11 +156,19 @@ static inline void nop_dma_unmap_area(co
@@ -156,9 +156,15 @@ static inline void nop_dma_unmap_area(co
#define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
#define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
#define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
#define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area)
-#define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area)
#define dmac_map_area __glue(_CACHE,_dma_map_area)
#define dmac_unmap_area __glue(_CACHE,_dma_unmap_area)
#define dmac_flush_range __glue(_CACHE,_dma_flush_range)
-#define dmac_flush_range __glue(_CACHE,_dma_flush_range)
+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
+# define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area)
+# define dmac_flush_range __glue(_CACHE,_dma_flush_range)
+#else
+#define __cpuc_flush_dcache_area __glue(fiq,_flush_kern_dcache_area)
+# define __cpuc_flush_dcache_area __glue(fiq,_flush_kern_dcache_area)
+# define dmac_flush_range __glue(fiq,_dma_flush_range)
+#endif
+
+#define dmac_map_area __glue(fiq,_dma_map_area)
+#define dmac_unmap_area __glue(fiq,_dma_unmap_area)
+#define dmac_flush_range __glue(fiq,_dma_flush_range)
+#endif /* CONFIG_DMA_CACHE_FIQ_BROADCAST */
#endif
#endif
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -844,6 +844,17 @@ config DMA_CACHE_RWFO
@@ -866,6 +866,17 @@ config DMA_CACHE_RWFO
in hardware, other workarounds are needed (e.g. cache
maintenance broadcasting in software via FIQ).
@ -42,7 +40,7 @@
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -304,6 +304,7 @@ void __sync_icache_dcache(pte_t pteval)
@@ -319,6 +319,7 @@ void __sync_icache_dcache(pte_t pteval)
void flush_dcache_page(struct page *page)
{
struct address_space *mapping;
@ -50,7 +48,7 @@
/*
* The zero page is never written to, so never has any dirty
@@ -314,7 +315,10 @@ void flush_dcache_page(struct page *page
@@ -329,7 +330,10 @@ void flush_dcache_page(struct page *page
mapping = page_mapping(page);
@ -62,3 +60,21 @@
mapping && !page_mapped(page))
clear_bit(PG_dcache_clean, &page->flags);
else {
--- a/arch/arm/mm/dma.h
+++ b/arch/arm/mm/dma.h
@@ -4,8 +4,13 @@
#include <asm/glue-cache.h>
#ifndef MULTI_CACHE
-#define dmac_map_area __glue(_CACHE,_dma_map_area)
-#define dmac_unmap_area __glue(_CACHE,_dma_unmap_area)
+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
+# define dmac_map_area __glue(_CACHE,_dma_map_area)
+# define dmac_unmap_area __glue(_CACHE,_dma_unmap_area)
+#else
+# define dmac_map_area __glue(fiq,_dma_map_area)
+# define dmac_unmap_area __glue(fiq,_dma_unmap_area)
+#endif
/*
* These are private to the dma-mapping API. Do not use directly.

View file

@ -1,6 +1,6 @@
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -331,8 +331,6 @@ void __init cns3xxx_pcie_init_late(void)
@@ -281,8 +281,6 @@ void __init cns3xxx_pcie_init_late(void)
"imprecise external abort");
for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
@ -8,4 +8,4 @@
- cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
pci_common_init(&cns3xxx_pcie[i].hw_pci);
private_data = &cns3xxx_pcie[i];

View file

@ -0,0 +1,14 @@
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4772,7 +4772,10 @@ int pci_get_new_domain_nr(void)
void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent)
{
static int use_dt_domains = -1;
- int domain = of_get_pci_domain_nr(parent->of_node);
+ int domain = -1;
+
+ if (parent && parent->of_node)
+ domain = of_get_pci_domain_nr(parent->of_node);
/*
* Check DT domain and use_dt_domains values.

View file

@ -29,7 +29,7 @@
*/
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -827,7 +827,7 @@ config KUSER_HELPERS
@@ -849,7 +849,7 @@ config VDSO
config DMA_CACHE_RWFO
bool "Enable read/write for ownership DMA cache maintenance"

View file

@ -17,7 +17,7 @@
static struct map_desc cns3xxx_io_desc[] __initdata = {
{
.virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT,
@@ -191,6 +194,15 @@ static struct irqaction cns3xxx_timer_ir
@@ -198,6 +201,15 @@ static struct irqaction cns3xxx_timer_ir
.handler = cns3xxx_timer_interrupt,
};
@ -33,7 +33,7 @@
/*
* Set up the clock source and clock events devices
*/
@@ -244,6 +256,7 @@ static void __init __cns3xxx_timer_init(
@@ -251,6 +263,7 @@ static void __init __cns3xxx_timer_init(
setup_irq(timer_irq, &cns3xxx_timer_irq);
cns3xxx_clockevents_init(timer_irq);

View file

@ -1,6 +1,6 @@
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -88,6 +88,79 @@ static void __iomem *cns3xxx_pci_cfg_bas
@@ -86,6 +86,79 @@ static void __iomem *cns3xxx_pci_map_bus
return base + (where & 0xffc) + (devfn << 12);
}
@ -63,7 +63,7 @@
+ printk("\n");
+*/
+ pr_debug("%s failed port%d sreg=0x%04x\n", __func__,
+ cnspci->hw_pci.domain, sreg);
+ pci_domain_nr(bus), sreg);
+
+ /* make sure the status bits are reset */
+ __raw_writew(sreg, host_base + 6);
@ -80,39 +80,19 @@
static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *val)
{
@@ -104,6 +177,11 @@ static int cns3xxx_pci_read_config(struc
@@ -95,6 +168,11 @@ static int cns3xxx_pci_read_config(struc
v = __raw_readl(base);
ret = pci_generic_config_read32(bus, devfn, where, size, val);
+ if (check_master_abort(bus, devfn, where)) {
+ printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)= master_abort on read\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+
if (bus->number == 0 && devfn == 0 &&
(where & 0xffc) == PCI_CLASS_REVISION) {
if (ret == PCIBIOS_SUCCESSFUL && !bus->number && !devfn &&
(where & 0xffc) == PCI_CLASS_REVISION)
/*
@@ -133,11 +211,19 @@ static int cns3xxx_pci_write_config(stru
return PCIBIOS_SUCCESSFUL;
v = __raw_readl(base);
+ if (check_master_abort(bus, devfn, where)) {
+ printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)=0x%08x master_abort on read\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val);
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
v &= ~(mask << shift);
v |= (val & mask) << shift;
__raw_writel(v, base);
+ if (check_master_abort(bus, devfn, where)) {
+ printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)=0x%08x master_abort on write\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val);
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
return PCIBIOS_SUCCESSFUL;
}
@@ -315,8 +401,14 @@ static void __init cns3xxx_pcie_hw_init(
@@ -257,8 +335,14 @@ static void __init cns3xxx_pcie_hw_init(
static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
struct pt_regs *regs)
{

View file

@ -1,11 +1,11 @@
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -424,6 +424,8 @@ void __init cns3xxx_pcie_init_late(void)
@@ -366,6 +366,8 @@ void __init cns3xxx_pcie_init_late(void)
for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
+ if (!cns3xxx_pcie[i].linked)
+ continue;
cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
pci_common_init(&cns3xxx_pcie[i].hw_pci);
}
private_data = &cns3xxx_pcie[i];
pci_common_init(&hw_pci);

View file

@ -1,6 +1,6 @@
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -417,6 +417,18 @@ config I2C_CBUS_GPIO
@@ -440,6 +440,18 @@ config I2C_CBUS_GPIO
This driver can also be built as a module. If so, the module
will be called i2c-cbus-gpio.
@ -21,11 +21,11 @@
depends on CPM1 || CPM2
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -101,6 +101,7 @@ obj-$(CONFIG_I2C_CROS_EC_TUNNEL) += i2c-
obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o
obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o
obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o
@@ -111,6 +111,7 @@ obj-$(CONFIG_I2C_VIPERBOARD) += i2c-vipe
obj-$(CONFIG_I2C_ACORN) += i2c-acorn.o
obj-$(CONFIG_I2C_BCM_KONA) += i2c-bcm-kona.o
obj-$(CONFIG_I2C_BRCMSTB) += i2c-brcmstb.o
+obj-$(CONFIG_I2C_CNS3XXX) += i2c-cns3xxx.o
obj-$(CONFIG_SCx200_ACB) += scx200_acb.o
ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG
obj-$(CONFIG_I2C_CROS_EC_TUNNEL) += i2c-cros-ec-tunnel.o
obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o
obj-$(CONFIG_I2C_OPAL) += i2c-opal.o

View file

@ -1,6 +1,6 @@
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -171,6 +171,13 @@ config SPI_CLPS711X
@@ -183,6 +183,13 @@ config SPI_CLPS711X
This enables dedicated general purpose SPI/Microwire1-compatible
master mode interface (SSI1) for CLPS711X-based CPUs.
@ -16,40 +16,36 @@
depends on (M520x || M523x || M5249 || M525x || M527x || M528x || M532x)
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_SPI_BITBANG) += spi-bitban
@@ -26,6 +26,7 @@ obj-$(CONFIG_SPI_BITBANG) += spi-bitban
obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o
obj-$(CONFIG_SPI_CADENCE) += spi-cadence.o
obj-$(CONFIG_SPI_CLPS711X) += spi-clps711x.o
+obj-$(CONFIG_SPI_CNS3XXX) += spi-cns3xxx.o
obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o
obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o
obj-$(CONFIG_SPI_DESIGNWARE) += spi-dw.o
--- a/drivers/spi/spi-bitbang.c
+++ b/drivers/spi/spi-bitbang.c
@@ -335,6 +335,10 @@ static int spi_bitbang_transfer_one(stru
*/
if (!m->is_dma_mapped)
t->rx_dma = t->tx_dma = 0;
+
+ t->last_in_message_list =
+ list_is_last(&t->transfer_list, &m->transfers);
+
status = bitbang->txrx_bufs(spi, t);
}
if (status > 0)
obj-$(CONFIG_SPI_DLN2) += spi-dln2.o
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -630,6 +630,13 @@ struct spi_transfer {
@@ -698,6 +698,10 @@ struct spi_transfer {
u32 speed_hz;
struct list_head transfer_list;
+
+#ifdef CONFIG_ARCH_CNS3XXX
+ unsigned last_in_message_list;
+#ifdef CONFIG_SPI_CNS3XXX_2IOREAD
+ u8 dio_read;
+#endif
+#endif
};
/**
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -933,6 +933,9 @@ static int spi_transfer_one_message(stru
list_for_each_entry(xfer, &msg->transfers, transfer_list) {
trace_spi_transfer_start(msg, xfer);
+ xfer->last_in_message_list =
+ list_is_last(&xfer->transfer_list, &msg->transfers);
+
spi_statistics_add_transfer_stats(statm, xfer, master);
spi_statistics_add_transfer_stats(stats, xfer, master);

View file

@ -1,7 +1,7 @@
--- a/drivers/ata/ahci_platform.c
+++ b/drivers/ata/ahci_platform.c
@@ -29,12 +29,23 @@ static const struct ata_port_info ahci_p
.port_ops = &ahci_platform_ops,
@@ -37,12 +37,23 @@ static struct scsi_host_template ahci_pl
AHCI_SHT(DRV_NAME),
};
+static const struct ata_port_info cns3xxx_port_info = {

View file

@ -1,30 +1,32 @@
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -135,12 +135,13 @@ static void cns3xxx_timer_set_mode(enum
@@ -138,6 +138,7 @@ static int cns3xxx_set_oneshot(struct cl
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
- reload = pclk * 20 / (3 * HZ) * 0x25000;
+ reload = pclk * 1000000 / HZ;
writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
break;
case CLOCK_EVT_MODE_ONESHOT:
/* period set, and timer enabled in 'next_event' hook */
+ writel(0, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
ctrl |= (1 << 2) | (1 << 9);
break;
case CLOCK_EVT_MODE_UNUSED:
@@ -168,7 +169,7 @@ static struct clock_event_device cns3xxx
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_mode = cns3xxx_timer_set_mode,
.set_next_event = cns3xxx_timer_set_next_event,
- .rating = 350,
+ .rating = 300,
.cpumask = cpu_all_mask,
/* period set, and timer enabled in 'next_event' hook */
ctrl |= (1 << 2) | (1 << 9);
+ writel(0, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
return 0;
}
@@ -148,7 +149,7 @@ static int cns3xxx_set_periodic(struct c
int pclk = cns3xxx_cpu_clock() / 8;
int reload;
- reload = pclk * 20 / (3 * HZ) * 0x25000;
+ reload = pclk * 1000000 / HZ;
writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
@@ -175,7 +176,7 @@ static struct clock_event_device cns3xxx
.set_state_oneshot = cns3xxx_set_oneshot,
.tick_resume = cns3xxx_shutdown,
.set_next_event = cns3xxx_timer_set_next_event,
- .rating = 350,
+ .rating = 300,
.cpumask = cpu_all_mask,
};
@@ -213,6 +214,35 @@ static void __init cns3xxx_init_twd(void
@@ -220,6 +221,32 @@ static void __init cns3xxx_init_twd(void
twd_local_timer_register(&cns3xx_twd_local_timer);
}
@ -43,7 +45,6 @@
+ .rating = 200,
+ .read = cns3xxx_get_cycles,
+ .mask = CLOCKSOURCE_MASK(48),
+ .shift = 16,
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
@ -52,15 +53,13 @@
+ /* Reset the FreeRunning counter */
+ writel((1 << 16), cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
+
+ clocksource_cns3xxx.mult =
+ clocksource_khz2mult(100, clocksource_cns3xxx.shift);
+ clocksource_register(&clocksource_cns3xxx);
+ clocksource_register_khz(&clocksource_cns3xxx, 100);
+}
+
/*
* Set up the clock source and clock events devices
*/
@@ -230,13 +260,12 @@ static void __init __cns3xxx_timer_init(
@@ -237,13 +264,12 @@ static void __init __cns3xxx_timer_init(
/* stop free running timer3 */
writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
@ -77,7 +76,7 @@
/* mask irq, non-mask timer1 overflow */
irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
irq_mask &= ~(1 << 2);
@@ -248,23 +277,9 @@ static void __init __cns3xxx_timer_init(
@@ -255,23 +281,9 @@ static void __init __cns3xxx_timer_init(
val |= (1 << 9);
writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);

View file

@ -1,6 +1,6 @@
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -303,13 +303,26 @@ void __init cns3xxx_timer_init(void)
@@ -307,13 +307,26 @@ void __init cns3xxx_timer_init(void)
#ifdef CONFIG_CACHE_L2X0
@ -30,7 +30,7 @@
/*
* Tag RAM Control register
@@ -339,7 +352,10 @@ void __init cns3xxx_l2x0_init(void)
@@ -343,7 +356,10 @@ void __init cns3xxx_l2x0_init(void)
/* 32 KiB, 8-way, parity disable */
l2x0_init(base, 0x00500000, 0xfe0f0fff);

View file

@ -110,8 +110,8 @@
+ unsigned int irqs[5];
struct resource res_io;
struct resource res_mem;
struct hw_pci hw_pci;
@@ -97,7 +98,7 @@ static inline int check_master_abort(str
int port;
@@ -95,7 +96,7 @@ static inline int check_master_abort(str
void __iomem *host_base;
u32 sreg, ereg;
@ -120,7 +120,7 @@
sreg = __raw_readw(host_base + 0x6) & 0xF900;
ereg = __raw_readl(host_base + 0x104); // Uncorrectable Error Status Reg
@@ -251,7 +252,7 @@ static struct pci_ops cns3xxx_pcie_ops =
@@ -209,7 +210,7 @@ static struct pci_ops cns3xxx_pcie_ops =
static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
@ -129,21 +129,22 @@
pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
@@ -277,7 +278,12 @@ static struct cns3xxx_pcie cns3xxx_pcie[
@@ -235,7 +236,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[
.end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */
.flags = IORESOURCE_MEM,
},
- .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
+ .irqs = { IRQ_CNS3XXX_PCIE0_RC,
+ IRQ_CNS3XXX_PCIE0_DEVICE,
+ IRQ_CNS3XXX_PCIE0_DEVICE,
+ IRQ_CNS3XXX_PCIE0_DEVICE,
+ IRQ_CNS3XXX_PCIE0_DEVICE,
+ },
.hw_pci = {
.domain = 0,
.nr_controllers = 1,
@@ -302,7 +308,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[
+ .irqs = {
+ IRQ_CNS3XXX_PCIE0_RC,
+ IRQ_CNS3XXX_PCIE0_DEVICE,
+ IRQ_CNS3XXX_PCIE0_DEVICE,
+ IRQ_CNS3XXX_PCIE0_DEVICE,
+ IRQ_CNS3XXX_PCIE0_DEVICE,
+ },
.port = 0,
},
[1] = {
@@ -254,7 +261,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[
.end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */
.flags = IORESOURCE_MEM,
},
@ -155,10 +156,10 @@
+ IRQ_CNS3XXX_PCIE1_DEVICE,
+ IRQ_CNS3XXX_PCIE1_DEVICE,
+ },
.hw_pci = {
.domain = 1,
.nr_controllers = 1,
@@ -412,6 +424,14 @@ static int cns3xxx_pcie_abort_handler(un
.port = 1,
},
};
@@ -346,6 +359,14 @@ static int cns3xxx_pcie_abort_handler(un
return 0;
}

View file

@ -1,6 +1,6 @@
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -393,6 +393,11 @@ static int bcm5481_config_aneg(struct ph
@@ -332,6 +332,11 @@ static int bcm5481_config_aneg(struct ph
/* Write bits 14:0. */
reg |= (1 << 15);
phy_write(phydev, 0x18, reg);

View file

@ -1,8 +1,8 @@
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -105,6 +105,34 @@ static const struct dwc2_core_params par
.uframe_sched = -1,
};
@@ -144,6 +144,34 @@ static int __dwc2_lowlevel_hw_enable(str
return ret;
}
+static const struct dwc2_core_params params_cns3xxx = {
+ .otg_cap = 2, /* non-HNP/non-SRP capable */
@ -33,9 +33,9 @@
+};
+
/**
* dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
* DWC_otg driver
@@ -165,6 +193,9 @@ static int dwc2_driver_probe(struct plat
* dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
* @hsotg: The driver state
@@ -344,6 +372,9 @@ static int dwc2_driver_probe(struct plat
/* Default all params to autodetect */
dwc2_set_all_params(&defparams, -1);
params = &defparams;