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ralink: add support for missing mt7620 mux values

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Signed-off-by: John Crispin <blogic@openwrt.org>

SVN-Revision: 38551
This commit is contained in:
John Crispin 2013-10-28 06:47:39 +00:00
parent 43de7c1cfa
commit 7c7225a19d
1 changed files with 85 additions and 42 deletions
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127
target/linux/ramips/patches-3.10/0122-pinmux.patch
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@ -16,8 +16,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
Index: linux-3.10.17/arch/mips/Kconfig
===================================================================
--- linux-3.10.17.orig/arch/mips/Kconfig 2013-10-24 16:17:14.040072202 +0200
+++ linux-3.10.17/arch/mips/Kconfig 2013-10-24 16:17:14.964072221 +0200
--- linux-3.10.17.orig/arch/mips/Kconfig 2013-10-26 17:19:49.094708911 +0200
+++ linux-3.10.17/arch/mips/Kconfig 2013-10-26 17:19:49.926708932 +0200
@@ -446,6 +446,8 @@
select HAVE_MACH_CLKDEV
select CLKDEV_LOOKUP
@ -30,7 +30,7 @@ Index: linux-3.10.17/arch/mips/Kconfig
Index: linux-3.10.17/drivers/pinctrl/Kconfig
===================================================================
--- linux-3.10.17.orig/drivers/pinctrl/Kconfig 2013-10-18 19:44:19.000000000 +0200
+++ linux-3.10.17/drivers/pinctrl/Kconfig 2013-10-24 16:17:14.964072221 +0200
+++ linux-3.10.17/drivers/pinctrl/Kconfig 2013-10-26 17:19:49.930708931 +0200
@@ -114,6 +114,11 @@
select PINMUX
select PINCONF
@ -46,7 +46,7 @@ Index: linux-3.10.17/drivers/pinctrl/Kconfig
Index: linux-3.10.17/drivers/pinctrl/Makefile
===================================================================
--- linux-3.10.17.orig/drivers/pinctrl/Makefile 2013-10-18 19:44:19.000000000 +0200
+++ linux-3.10.17/drivers/pinctrl/Makefile 2013-10-24 16:17:14.964072221 +0200
+++ linux-3.10.17/drivers/pinctrl/Makefile 2013-10-26 17:19:49.930708931 +0200
@@ -45,6 +45,7 @@
obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o
obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
@ -58,8 +58,8 @@ Index: linux-3.10.17/drivers/pinctrl/Makefile
Index: linux-3.10.17/drivers/pinctrl/pinctrl-rt2880.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-3.10.17/drivers/pinctrl/pinctrl-rt2880.c 2013-10-24 16:46:23.556113888 +0200
@@ -0,0 +1,463 @@
+++ linux-3.10.17/drivers/pinctrl/pinctrl-rt2880.c 2013-10-27 16:22:50.132754888 +0100
@@ -0,0 +1,466 @@
+/*
+ * linux/drivers/pinctrl/pinctrl-rt2880.c
+ *
@ -283,7 +283,8 @@ Index: linux-3.10.17/drivers/pinctrl/pinctrl-rt2880.c
+ if (func == 0) {
+ int i;
+
+ mode |= p->groups[group].mask << p->groups[group].shift;
+
+ mode |= p->groups[group].gpio << p->groups[group].shift;
+ /* mark the pins as gpio */
+ for (i = 0; i < p->groups[group].func[0].pin_count; i++)
+ p->gpio[p->groups[group].func[0].pins[i]] = 1;
@ -292,6 +293,7 @@ Index: linux-3.10.17/drivers/pinctrl/pinctrl-rt2880.c
+ }
+ rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
+
+
+ return 0;
+}
+
@ -496,6 +498,7 @@ Index: linux-3.10.17/drivers/pinctrl/pinctrl-rt2880.c
+ sprintf(name, "pio");
+ range->npins = __be32_to_cpu(*ngpio);
+ range->base = __be32_to_cpu(*gpiobase);
+ range->pin_base = range->base;
+ pinctrl_add_gpio_range(dev, range);
+ }
+
@ -526,8 +529,8 @@ Index: linux-3.10.17/drivers/pinctrl/pinctrl-rt2880.c
Index: linux-3.10.17/arch/mips/include/asm/mach-ralink/pinmux.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-3.10.17/arch/mips/include/asm/mach-ralink/pinmux.h 2013-10-24 16:17:14.968072221 +0200
@@ -0,0 +1,47 @@
+++ linux-3.10.17/arch/mips/include/asm/mach-ralink/pinmux.h 2013-10-27 07:28:38.999991133 +0100
@@ -0,0 +1,53 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
@ -542,7 +545,12 @@ Index: linux-3.10.17/arch/mips/include/asm/mach-ralink/pinmux.h
+#define FUNC(name, value, pin_first, pin_count) { name, value, pin_first, pin_count }
+#define GRP(_name, _func, _mask, _shift) \
+ { .name = _name, .mask = _mask, .shift = _shift, \
+ .func = _func, \
+ .func = _func, .gpio = _mask, \
+ .func_count = ARRAY_SIZE(_func) }
+
+#define GRP_G(_name, _func, _mask, _gpio, _shift) \
+ { .name = _name, .mask = _mask, .shift = _shift, \
+ .func = _func, .gpio = _gpio, \
+ .func_count = ARRAY_SIZE(_func) }
+
+struct rt2880_pmx_group;
@ -567,6 +575,7 @@ Index: linux-3.10.17/arch/mips/include/asm/mach-ralink/pinmux.h
+
+ const u32 shift;
+ const char mask;
+ const char gpio;
+
+ struct rt2880_pmx_func *func;
+ int func_count;
@ -577,8 +586,8 @@ Index: linux-3.10.17/arch/mips/include/asm/mach-ralink/pinmux.h
+#endif
Index: linux-3.10.17/arch/mips/ralink/mt7620.c
===================================================================
--- linux-3.10.17.orig/arch/mips/ralink/mt7620.c 2013-10-24 16:17:14.428072211 +0200
+++ linux-3.10.17/arch/mips/ralink/mt7620.c 2013-10-24 16:17:14.968072221 +0200
--- linux-3.10.17.orig/arch/mips/ralink/mt7620.c 2013-10-26 17:19:49.462708921 +0200
+++ linux-3.10.17/arch/mips/ralink/mt7620.c 2013-10-27 13:33:02.148512122 +0100
@@ -17,6 +17,7 @@
#include <asm/mipsregs.h>
#include <asm/mach-ralink/ralink_regs.h>
@ -587,7 +596,7 @@ Index: linux-3.10.17/arch/mips/ralink/mt7620.c
#include "common.h"
@@ -48,118 +49,40 @@
@@ -48,118 +49,58 @@
/* the pll dividers */
static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 };
@ -656,6 +665,14 @@ Index: linux-3.10.17/arch/mips/ralink/mt7620.c
- }, {0}
+static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
+static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
+static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
+static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
+static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
+static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
+static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
+static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
+static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
+static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
+static struct rt2880_pmx_func uartf_grp[] = {
+ FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
+ FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
@ -706,40 +723,48 @@ Index: linux-3.10.17/arch/mips/ralink/mt7620.c
- .name = "gpio",
- .mask = MT7620_GPIO_MODE_GPIO,
- }, {0}
-};
-
+static struct rt2880_pmx_func wdt_grp[] = {
+ FUNC("wdt rst", 0, 17, 1),
+ FUNC("wdt refclk", 0, 17, 1),
+ };
+static struct rt2880_pmx_func pcie_rst_grp[] = {
+ FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
+ FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
+};
+static struct rt2880_pmx_func nd_sd_grp[] = {
+ FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
+ FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15)
};
-struct ralink_pinmux rt_gpio_pinmux = {
- .mode = mode_mux,
- .uart = uart_mux,
- .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
- .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
+static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
+static struct rt2880_pmx_func wdt_grp[] = { FUNC("wdt", 0, 17, 1) };
+static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
+static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
+static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
+static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
+static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
+static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
+
+static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
+ GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
+ GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
+ MT7620_GPIO_MODE_UART0_SHIFT),
+ GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
+ GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
+ GRP("wdt", wdt_grp, 1, MT7620_GPIO_MODE_WDT),
+ GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
+ MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
+ GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
+ GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
+ GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
+ GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
+ MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
+ GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
+ MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
+ GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
+ GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
+ GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
+ GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
+ MT7620_GPIO_MODE_UART0_SHIFT),
+ GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
+ GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
+ { 0 }
};
void __init ralink_clk_init(void)
@@ -281,4 +204,6 @@
@@ -281,4 +222,6 @@
(pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
pr_info("Digital PMU set to %s control\n",
(pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
@ -748,8 +773,8 @@ Index: linux-3.10.17/arch/mips/ralink/mt7620.c
}
Index: linux-3.10.17/arch/mips/ralink/rt305x.c
===================================================================
--- linux-3.10.17.orig/arch/mips/ralink/rt305x.c 2013-10-24 16:17:14.664072214 +0200
+++ linux-3.10.17/arch/mips/ralink/rt305x.c 2013-10-24 16:17:14.968072221 +0200
--- linux-3.10.17.orig/arch/mips/ralink/rt305x.c 2013-10-26 17:19:49.722708926 +0200
+++ linux-3.10.17/arch/mips/ralink/rt305x.c 2013-10-27 16:23:29.836755834 +0100
@@ -17,90 +17,71 @@
#include <asm/mipsregs.h>
#include <asm/mach-ralink/ralink_regs.h>
@ -809,7 +834,7 @@ Index: linux-3.10.17/arch/mips/ralink/rt305x.c
+ FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
+};
+static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
+static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 25) };
+static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
+static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
+static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
+static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
@ -932,7 +957,7 @@ Index: linux-3.10.17/arch/mips/ralink/rt305x.c
Index: linux-3.10.17/arch/mips/include/asm/mach-ralink/rt305x.h
===================================================================
--- linux-3.10.17.orig/arch/mips/include/asm/mach-ralink/rt305x.h 2013-10-18 19:44:19.000000000 +0200
+++ linux-3.10.17/arch/mips/include/asm/mach-ralink/rt305x.h 2013-10-24 16:17:14.968072221 +0200
+++ linux-3.10.17/arch/mips/include/asm/mach-ralink/rt305x.h 2013-10-26 17:19:49.934708931 +0200
@@ -125,24 +125,28 @@
#define RT305X_GPIO_GE0_TXD0 40
#define RT305X_GPIO_GE0_RXCLK 51
@ -979,8 +1004,8 @@ Index: linux-3.10.17/arch/mips/include/asm/mach-ralink/rt305x.h
#define RT3352_SYSC_REG_SYSCFG1 0x014
Index: linux-3.10.17/arch/mips/include/asm/mach-ralink/mt7620.h
===================================================================
--- linux-3.10.17.orig/arch/mips/include/asm/mach-ralink/mt7620.h 2013-10-24 16:17:14.220072209 +0200
+++ linux-3.10.17/arch/mips/include/asm/mach-ralink/mt7620.h 2013-10-24 16:17:14.968072221 +0200
--- linux-3.10.17.orig/arch/mips/include/asm/mach-ralink/mt7620.h 2013-10-26 17:19:49.250708916 +0200
+++ linux-3.10.17/arch/mips/include/asm/mach-ralink/mt7620.h 2013-10-27 13:13:24.892484072 +0100
@@ -59,7 +59,6 @@
#define MT7620_DDR2_SIZE_MIN 32
#define MT7620_DDR2_SIZE_MAX 256
@ -989,7 +1014,7 @@ Index: linux-3.10.17/arch/mips/include/asm/mach-ralink/mt7620.h
#define MT7620_GPIO_MODE_UART0_SHIFT 2
#define MT7620_GPIO_MODE_UART0_MASK 0x7
#define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
@@ -71,15 +70,17 @@
@@ -71,15 +70,35 @@
#define MT7620_GPIO_MODE_GPIO_UARTF 0x5
#define MT7620_GPIO_MODE_GPIO_I2S 0x6
#define MT7620_GPIO_MODE_GPIO 0x7
@ -1004,6 +1029,24 @@ Index: linux-3.10.17/arch/mips/include/asm/mach-ralink/mt7620.h
-#define MT7620_GPIO_MODE_EPHY BIT(15)
-#define MT7620_GPIO_MODE_WDT BIT(22)
+
+#define MT7620_GPIO_MODE_NAND 0
+#define MT7620_GPIO_MODE_SD 1
+#define MT7620_GPIO_MODE_ND_SD_GPIO 2
+#define MT7620_GPIO_MODE_ND_SD_MASK 0x3
+#define MT7620_GPIO_MODE_ND_SD_SHIFT 18
+
+#define MT7620_GPIO_MODE_PCIE_RST 0
+#define MT7620_GPIO_MODE_PCIE_REF 1
+#define MT7620_GPIO_MODE_PCIE_GPIO 2
+#define MT7620_GPIO_MODE_PCIE_MASK 0x3
+#define MT7620_GPIO_MODE_PCIE_SHIFT 16
+
+#define MT7620_GPIO_MODE_WDT_RST 0
+#define MT7620_GPIO_MODE_WDT_REF 1
+#define MT7620_GPIO_MODE_WDT_GPIO 2
+#define MT7620_GPIO_MODE_WDT_MASK 0x3
+#define MT7620_GPIO_MODE_WDT_SHIFT 21
+
+#define MT7620_GPIO_MODE_I2C 0
+#define MT7620_GPIO_MODE_UART1 5
+#define MT7620_GPIO_MODE_MDIO 8
@ -1014,13 +1057,13 @@ Index: linux-3.10.17/arch/mips/include/asm/mach-ralink/mt7620.h
+#define MT7620_GPIO_MODE_WLED 13
+#define MT7620_GPIO_MODE_JTAG 15
+#define MT7620_GPIO_MODE_EPHY 15
+#define MT7620_GPIO_MODE_WDT 22
+#define MT7620_GPIO_MODE_PA 20
#endif
Index: linux-3.10.17/arch/mips/include/asm/mach-ralink/rt3883.h
===================================================================
--- linux-3.10.17.orig/arch/mips/include/asm/mach-ralink/rt3883.h 2013-10-18 19:44:19.000000000 +0200
+++ linux-3.10.17/arch/mips/include/asm/mach-ralink/rt3883.h 2013-10-24 16:17:14.968072221 +0200
+++ linux-3.10.17/arch/mips/include/asm/mach-ralink/rt3883.h 2013-10-26 17:19:49.934708931 +0200
@@ -112,8 +112,6 @@
#define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
#define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
@ -1053,8 +1096,8 @@ Index: linux-3.10.17/arch/mips/include/asm/mach-ralink/rt3883.h
#define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
Index: linux-3.10.17/arch/mips/ralink/common.h
===================================================================
--- linux-3.10.17.orig/arch/mips/ralink/common.h 2013-10-24 16:17:14.040072202 +0200
+++ linux-3.10.17/arch/mips/ralink/common.h 2013-10-24 16:17:14.968072221 +0200
--- linux-3.10.17.orig/arch/mips/ralink/common.h 2013-10-26 17:19:49.094708911 +0200
+++ linux-3.10.17/arch/mips/ralink/common.h 2013-10-26 17:19:49.934708931 +0200
@@ -11,25 +11,6 @@
#define RAMIPS_SYS_TYPE_LEN 32
@ -1084,7 +1127,7 @@ Index: linux-3.10.17/arch/mips/ralink/common.h
Index: linux-3.10.17/arch/mips/ralink/rt3883.c
===================================================================
--- linux-3.10.17.orig/arch/mips/ralink/rt3883.c 2013-10-18 19:44:19.000000000 +0200
+++ linux-3.10.17/arch/mips/ralink/rt3883.c 2013-10-24 16:17:14.972072223 +0200
+++ linux-3.10.17/arch/mips/ralink/rt3883.c 2013-10-27 16:23:36.824756002 +0100
@@ -17,132 +17,50 @@
#include <asm/mipsregs.h>
#include <asm/mach-ralink/ralink_regs.h>
@ -1198,7 +1241,7 @@ Index: linux-3.10.17/arch/mips/ralink/rt3883.c
- .mask = RT3883_GPIO_MODE_GPIO,
- }, {0}
+static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
+static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 25) };
+static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
+static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
+static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
+static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna a", 0, 35, 3) };