cleanup PCI code
SVN-Revision: 8700
This commit is contained in:
Gabor Juhos
parent
af21798b77
commit
73b2555da2
4 changed files with 284 additions and 333 deletions
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@ -1,175 +0,0 @@
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/*
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* $Id$
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*
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* ADM5120 specific PCI fixups
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*
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* Copyright (C) ADMtek Incorporated.
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* Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
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* Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
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* Copyright (C) 2007 OpenWrt.org
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the
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* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <linux/pci_regs.h>
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#include <asm/delay.h>
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#include <asm/bootinfo.h>
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#include <asm/mach-adm5120/adm5120_info.h>
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#include <asm/mach-adm5120/adm5120_defs.h>
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#include <asm/mach-adm5120/adm5120_irq.h>
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struct adm5120_pci_irq {
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u8 slot;
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u8 func;
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u8 pin;
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unsigned irq;
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};
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#define PCIIRQ(s,f,p,i) { \
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.slot = (s), \
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.func = (f), \
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.pin = (p), \
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.irq = (i) \
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}
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static struct adm5120_pci_irq default_pci_irqs[] __initdata = {
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PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
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};
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static struct adm5120_pci_irq rb1xx_pci_irqs[] __initdata = {
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PCIIRQ(1, 0, 1, ADM5120_IRQ_PCI0),
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PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI1),
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PCIIRQ(3, 0, 1, ADM5120_IRQ_PCI2)
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};
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static struct adm5120_pci_irq cas771_pci_irqs[] __initdata = {
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PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
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PCIIRQ(3, 0, 1, ADM5120_IRQ_PCI1),
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PCIIRQ(3, 2, 3, ADM5120_IRQ_PCI2)
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};
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static struct adm5120_pci_irq np28g_pci_irqs[] __initdata = {
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PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
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PCIIRQ(3, 0, 1, ADM5120_IRQ_PCI0),
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PCIIRQ(3, 1, 2, ADM5120_IRQ_PCI1),
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PCIIRQ(3, 2, 3, ADM5120_IRQ_PCI2)
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};
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#define GETMAP(n) do { \
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nr_irqs = ARRAY_SIZE(n ## _pci_irqs); \
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p = n ## _pci_irqs; \
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} while (0)
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int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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struct adm5120_pci_irq *p;
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int nr_irqs;
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int i;
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int irq;
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irq = -1;
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if (slot < 1 || slot > 3) {
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printk(KERN_ALERT "PCI: slot number %u is not supported\n",
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slot);
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goto out;
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}
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GETMAP(default);
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switch (mips_machtype) {
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case MACH_ADM5120_RB_111:
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case MACH_ADM5120_RB_112:
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case MACH_ADM5120_RB_133:
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case MACH_ADM5120_RB_133C:
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case MACH_ADM5120_RB_153:
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GETMAP(rb1xx);
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break;
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case MACH_ADM5120_NP28G:
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GETMAP(np28g);
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break;
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case MACH_ADM5120_P335:
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case MACH_ADM5120_P334WT:
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/* using default mapping */
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break;
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case MACH_ADM5120_CAS771:
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GETMAP(cas771);
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break;
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case MACH_ADM5120_NP27G:
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case MACH_ADM5120_NP28GHS:
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case MACH_ADM5120_WP54AG:
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case MACH_ADM5120_WP54G:
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case MACH_ADM5120_WP54G_WRT:
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case MACH_ADM5120_WPP54AG:
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case MACH_ADM5120_WPP54G:
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default:
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printk(KERN_ALERT "PCI: irq map is unknown, using defaults.\n");
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break;
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}
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for (i=0; i<nr_irqs; i++, p++) {
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if ((p->slot == slot) && (PCI_FUNC(dev->devfn) == p->func) &&
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(p->pin == pin)) {
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irq = p->irq;
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break;
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}
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}
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if (irq < 0) {
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printk(KERN_ALERT "PCI: no irq found for %s pin:%u\n",
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pci_name(dev), pin);
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} else {
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printk(KERN_INFO "PCI: mapping irq for %s pin:%u, irq:%d\n",
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pci_name(dev), pin, irq);
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}
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out:
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return irq;
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}
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static void adm5120_pci_fixup(struct pci_dev *dev)
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{
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if (dev->devfn != 0)
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return;
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/* setup COMMAND register */
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pci_write_config_word(dev, PCI_COMMAND,
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(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
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/* setup CACHE_LINE_SIZE register */
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
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/* setting up BARS */
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADMTEK, PCI_DEVICE_ID_ADMTEK_ADM5120,
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adm5120_pci_fixup);
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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@ -1,143 +0,0 @@
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/*
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* $Id$
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*
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* ADM5120 specific PCI operations
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*
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* Copyright (C) ADMtek Incorporated.
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* Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
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* Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
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* Copyright (C) 2007 OpenWrt.org
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the
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* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#include <asm/mach-adm5120/adm5120_defs.h>
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#define DEBUG 0
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#if DEBUG
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#define DBG(f, ...) printk(f, ## __VA_ARGS__ )
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#else
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#define DBG(f, ...)
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#endif
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#define PCI_ENABLE 0x80000000
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static spinlock_t pci_lock = SPIN_LOCK_UNLOCKED;
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static inline void write_cfgaddr(u32 addr)
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{
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*(volatile u32*)KSEG1ADDR(ADM5120_PCICFG_ADDR) = (addr | PCI_ENABLE);
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}
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static inline void write_cfgdata(u32 data)
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{
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*(volatile u32*)KSEG1ADDR(ADM5120_PCICFG_DATA) = data;
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}
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static inline u32 read_cfgdata(void)
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{
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return (*(volatile u32*)KSEG1ADDR(ADM5120_PCICFG_DATA));
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}
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static inline u32 mkaddr(struct pci_bus *bus, unsigned int devfn, int where)
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{
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return (((bus->number & 0xFF) << 16) | ((devfn & 0xFF) << 8) | \
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(where & 0xFC));
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}
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static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *val)
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{
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unsigned long flags;
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u32 data;
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spin_lock_irqsave(&pci_lock, flags);
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write_cfgaddr(mkaddr(bus,devfn,where));
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data = read_cfgdata();
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DBG("PCI: cfg_read %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
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bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, data);
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switch (size) {
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case 1:
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if (where & 1)
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data >>= 8;
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if (where & 2)
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data >>= 16;
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data &= 0xFF;
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break;
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case 2:
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if (where & 2)
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data >>= 16;
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data &= 0xFFFF;
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break;
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}
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*val = data;
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DBG(", 0x%08X returned\n", data);
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spin_unlock_irqrestore(&pci_lock, flags);
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 val)
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{
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unsigned long flags;
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u32 data;
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int s;
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spin_lock_irqsave(&pci_lock, flags);
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write_cfgaddr(mkaddr(bus,devfn,where));
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data = read_cfgdata();
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DBG("PCI: cfg_write %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
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bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, data);
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switch (size) {
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case 1:
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s = ((where & 3) << 3);
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data &= ~(0xFF << s);
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data |= ((val & 0xFF) << s);
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break;
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case 2:
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s = ((where & 2) << 4);
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data &= ~(0xFFFF << s);
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data |= ((val & 0xFFFF) << s);
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break;
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case 4:
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data = val;
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break;
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}
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write_cfgdata(data);
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DBG(", 0x%08X written\n", data);
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spin_unlock_irqrestore(&pci_lock, flags);
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops adm5120_pci_ops = {
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.read = pci_config_read,
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.write = pci_config_write,
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};
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@ -25,28 +25,296 @@
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*
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <asm/mach-adm5120/adm5120_info.h>
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#include <asm/mach-adm5120/adm5120_defs.h>
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#include <asm/mach-adm5120/adm5120_irq.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <linux/pci_regs.h>
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extern struct pci_ops adm5120_pci_ops;
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#include <asm/io.h>
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#include <asm/delay.h>
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#include <asm/bootinfo.h>
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#include <adm5120_defs.h>
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#include <adm5120_info.h>
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#include <adm5120_defs.h>
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#include <adm5120_irq.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(f, a...) printk(KERN_DEBUG f, ## a )
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#else
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#define DBG(f, a...) do {} while (0)
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#endif
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#define PCI_ENABLE 0x80000000
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static spinlock_t pci_lock = SPIN_LOCK_UNLOCKED;
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/* -------------------------------------------------------------------------*/
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static inline void write_cfgaddr(u32 addr)
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{
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__raw_writel((addr | PCI_ENABLE),
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(void __iomem *)(KSEG1ADDR(ADM5120_PCICFG_ADDR)));
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}
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static inline void write_cfgdata(u32 data)
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{
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__raw_writel(data, (void __iomem *)KSEG1ADDR(ADM5120_PCICFG_DATA));
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}
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static inline u32 read_cfgdata(void)
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{
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return __raw_readl((void __iomem *)KSEG1ADDR(ADM5120_PCICFG_DATA));
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}
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static inline u32 mkaddr(struct pci_bus *bus, unsigned int devfn, int where)
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{
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return (((bus->number & 0xFF) << 16) | ((devfn & 0xFF) << 8) | \
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(where & 0xFC));
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}
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/* -------------------------------------------------------------------------*/
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static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *val)
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{
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unsigned long flags;
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u32 data;
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spin_lock_irqsave(&pci_lock, flags);
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write_cfgaddr(mkaddr(bus,devfn,where));
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data = read_cfgdata();
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DBG("PCI: cfg_read %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
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bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
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where, size, data);
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switch (size) {
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case 1:
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if (where & 1)
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data >>= 8;
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if (where & 2)
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data >>= 16;
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data &= 0xFF;
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break;
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case 2:
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if (where & 2)
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data >>= 16;
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data &= 0xFFFF;
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break;
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}
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*val = data;
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DBG(", 0x%08X returned\n", data);
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spin_unlock_irqrestore(&pci_lock, flags);
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 val)
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{
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unsigned long flags;
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u32 data;
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int s;
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spin_lock_irqsave(&pci_lock, flags);
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write_cfgaddr(mkaddr(bus,devfn,where));
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data = read_cfgdata();
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DBG("PCI: cfg_write %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
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bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
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where, size, data);
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switch (size) {
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case 1:
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s = ((where & 3) << 3);
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data &= ~(0xFF << s);
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data |= ((val & 0xFF) << s);
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break;
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case 2:
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s = ((where & 2) << 4);
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data &= ~(0xFFFF << s);
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data |= ((val & 0xFFFF) << s);
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break;
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case 4:
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data = val;
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break;
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}
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write_cfgdata(data);
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DBG(", 0x%08X written\n", data);
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spin_unlock_irqrestore(&pci_lock, flags);
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops adm5120_pci_ops = {
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.read = pci_config_read,
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.write = pci_config_write,
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};
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/* -------------------------------------------------------------------------*/
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static void adm5120_pci_fixup(struct pci_dev *dev)
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{
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if (dev->devfn != 0)
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return;
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/* setup COMMAND register */
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pci_write_config_word(dev, PCI_COMMAND,
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(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
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/* setup CACHE_LINE_SIZE register */
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
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/* setup BARS */
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADMTEK, PCI_DEVICE_ID_ADMTEK_ADM5120,
|
||||
adm5120_pci_fixup);
|
||||
|
||||
/* -------------------------------------------------------------------------*/
|
||||
|
||||
struct adm5120_pci_irq {
|
||||
u8 slot;
|
||||
u8 func;
|
||||
u8 pin;
|
||||
unsigned irq;
|
||||
};
|
||||
|
||||
#define PCIIRQ(s,f,p,i) { \
|
||||
.slot = (s), \
|
||||
.func = (f), \
|
||||
.pin = (p), \
|
||||
.irq = (i) \
|
||||
}
|
||||
|
||||
static struct adm5120_pci_irq default_pci_irqs[] __initdata = {
|
||||
PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
|
||||
};
|
||||
|
||||
static struct adm5120_pci_irq rb1xx_pci_irqs[] __initdata = {
|
||||
PCIIRQ(1, 0, 1, ADM5120_IRQ_PCI0),
|
||||
PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI1),
|
||||
PCIIRQ(3, 0, 1, ADM5120_IRQ_PCI2)
|
||||
};
|
||||
|
||||
static struct adm5120_pci_irq cas771_pci_irqs[] __initdata = {
|
||||
PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
|
||||
PCIIRQ(3, 0, 1, ADM5120_IRQ_PCI1),
|
||||
PCIIRQ(3, 2, 3, ADM5120_IRQ_PCI2)
|
||||
};
|
||||
|
||||
static struct adm5120_pci_irq np28g_pci_irqs[] __initdata = {
|
||||
PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
|
||||
PCIIRQ(3, 0, 1, ADM5120_IRQ_PCI0),
|
||||
PCIIRQ(3, 1, 2, ADM5120_IRQ_PCI1),
|
||||
PCIIRQ(3, 2, 3, ADM5120_IRQ_PCI2)
|
||||
};
|
||||
|
||||
#define GETMAP(n) do { \
|
||||
nr_irqs = ARRAY_SIZE(n ## _pci_irqs); \
|
||||
p = n ## _pci_irqs; \
|
||||
} while (0)
|
||||
|
||||
int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
struct adm5120_pci_irq *p;
|
||||
int nr_irqs;
|
||||
int i;
|
||||
int irq;
|
||||
|
||||
irq = -1;
|
||||
if (slot < 1 || slot > 3) {
|
||||
printk(KERN_ALERT "PCI: slot number %u is not supported\n",
|
||||
slot);
|
||||
goto out;
|
||||
}
|
||||
|
||||
GETMAP(default);
|
||||
|
||||
switch (mips_machtype) {
|
||||
case MACH_ADM5120_RB_111:
|
||||
case MACH_ADM5120_RB_112:
|
||||
case MACH_ADM5120_RB_133:
|
||||
case MACH_ADM5120_RB_133C:
|
||||
case MACH_ADM5120_RB_153:
|
||||
GETMAP(rb1xx);
|
||||
break;
|
||||
case MACH_ADM5120_NP28G:
|
||||
GETMAP(np28g);
|
||||
break;
|
||||
case MACH_ADM5120_P335:
|
||||
case MACH_ADM5120_P334WT:
|
||||
/* using default mapping */
|
||||
break;
|
||||
case MACH_ADM5120_CAS771:
|
||||
GETMAP(cas771);
|
||||
break;
|
||||
|
||||
case MACH_ADM5120_NP27G:
|
||||
case MACH_ADM5120_NP28GHS:
|
||||
case MACH_ADM5120_WP54AG:
|
||||
case MACH_ADM5120_WP54G:
|
||||
case MACH_ADM5120_WP54G_WRT:
|
||||
case MACH_ADM5120_WPP54AG:
|
||||
case MACH_ADM5120_WPP54G:
|
||||
default:
|
||||
printk(KERN_ALERT "PCI: irq map is unknown, using defaults.\n");
|
||||
break;
|
||||
}
|
||||
|
||||
for (i = 0; i < nr_irqs; i++, p++) {
|
||||
if ((p->slot == slot) && (PCI_FUNC(dev->devfn) == p->func) &&
|
||||
(p->pin == pin)) {
|
||||
irq = p->irq;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (irq < 0) {
|
||||
printk(KERN_ALERT "PCI: no irq found for %s pin:%u\n",
|
||||
pci_name(dev), pin);
|
||||
} else {
|
||||
printk(KERN_INFO "PCI: mapping irq for %s pin:%u, irq:%d\n",
|
||||
pci_name(dev), pin, irq);
|
||||
}
|
||||
|
||||
out:
|
||||
return irq;
|
||||
}
|
||||
|
||||
int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* -------------------------------------------------------------------------*/
|
||||
|
||||
static struct resource pci_io_resource = {
|
||||
.name = "ADM5120 PCI I/O",
|
||||
.start = ADM5120_PCIIO_BASE,
|
||||
.end = ADM5120_PCICFG_ADDR-1,
|
||||
.flags = IORESOURCE_IO
|
||||
.name = "ADM5120 PCI I/O",
|
||||
.start = ADM5120_PCIIO_BASE,
|
||||
.end = ADM5120_PCICFG_ADDR-1,
|
||||
.flags = IORESOURCE_IO
|
||||
};
|
||||
|
||||
static struct resource pci_mem_resource = {
|
||||
.name = "ADM5120 PCI MEM",
|
||||
.start = ADM5120_PCIMEM_BASE,
|
||||
.end = ADM5120_PCIIO_BASE-1,
|
||||
.flags = IORESOURCE_MEM
|
||||
.name = "ADM5120 PCI MEM",
|
||||
.start = ADM5120_PCIMEM_BASE,
|
||||
.end = ADM5120_PCIIO_BASE-1,
|
||||
.flags = IORESOURCE_MEM
|
||||
};
|
||||
|
||||
static struct pci_controller adm5120_controller = {
|
||||
|
|
@ -61,7 +329,8 @@ static int __init adm5120_pci_setup(void)
|
|||
|
||||
pci_bios = adm5120_has_pci();
|
||||
|
||||
printk("adm5120: system has %sPCI BIOS\n", pci_bios ? "" : "no ");
|
||||
printk(KERN_INFO "adm5120: system has %sPCI BIOS\n",
|
||||
pci_bios ? "" : "no ");
|
||||
if (pci_bios == 0)
|
||||
return -1;
|
||||
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ Index: linux-2.6.22.1/arch/mips/pci/Makefile
|
|||
obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
|
||||
obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
|
||||
obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
|
||||
+obj-$(CONFIG_PCI_ADM5120) += fixup-adm5120.o ops-adm5120.o pci-adm5120.o
|
||||
+obj-$(CONFIG_PCI_ADM5120) += pci-adm5120.o
|
||||
Index: linux-2.6.22.1/include/linux/pci_ids.h
|
||||
===================================================================
|
||||
--- linux-2.6.22.1.orig/include/linux/pci_ids.h
|
||||
|
|
|
|||
Loading…
Reference in a new issue