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ar71xx: fix link speed between AR7242 and AR8327 on the RB750GL/RB751G boards

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The default pll_1000 value had to be changed
in order to make it working.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 33993
This commit is contained in:
Gabor Juhos 2012-10-29 17:24:30 +00:00
parent 748427f2e4
commit 7228a91a3b
1 changed files with 2 additions and 1 deletions
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3
target/linux/ar71xx/files/arch/mips/ath79/mach-rb750.c
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@ -186,7 +186,7 @@ static struct ar8327_platform_data rb750gr3_ar8327_data = {
.pad0_cfg = &rb750gr3_ar8327_pad0_cfg, .pad0_cfg = &rb750gr3_ar8327_pad0_cfg,
.cpuport_cfg = { .cpuport_cfg = {
.force_link = 1, .force_link = 1,
.speed = AR8327_PORT_SPEED_100, .speed = AR8327_PORT_SPEED_1000,
.duplex = 1, .duplex = 1,
.txpause = 1, .txpause = 1,
.rxpause = 1, .rxpause = 1,
@ -261,6 +261,7 @@ static void __init rb750gr3_setup(void)
ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0); ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_pll_data.pll_1000 = 0x62000000;
ath79_register_eth(0); ath79_register_eth(0);