ar71xx: use AR8327 on the DB120 board
SVN-Revision: 31012
This commit is contained in:
Gabor Juhos
parent
faf82f3e10
commit
6ac12fbb3c
3 changed files with 108 additions and 49 deletions
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@ -21,9 +21,12 @@ ja76pf2)
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;;
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db120)
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ucidef_set_interfaces_lan_wan "eth1" "eth0"
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ucidef_add_switch "switch0" "1" "1"
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ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 4"
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ucidef_set_interfaces_lan_wan "eth0.1 eth1" "eth0.2"
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ucidef_add_switch "eth0" "1" "1"
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ucidef_add_switch_vlan "eth0" "1" "0t 2 3 4 5"
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ucidef_add_switch_vlan "eth0" "2" "0t 1"
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ucidef_add_switch "eth1" "1" "1"
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ucidef_add_switch_vlan "eth1" "1" "0 1 2 3 4 5"
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;;
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dir-825-b1|\
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@ -1,14 +1,25 @@
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--- a/arch/mips/ath79/mach-db120.c
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+++ b/arch/mips/ath79/mach-db120.c
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@@ -37,17 +37,26 @@
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@@ -2,7 +2,7 @@
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* Atheros DB120 reference board support
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*
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* Copyright (c) 2011 Qualcomm Atheros
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- * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org>
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+ * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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*
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* All rights reserved.
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*
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@@ -37,17 +37,28 @@
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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+#include <linux/mtd/mtd.h>
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+#include <linux/mtd/partitions.h>
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#include <linux/pci.h>
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+#include <linux/phy.h>
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+#include <linux/platform_device.h>
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#include <linux/ath9k_platform.h>
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+#include <linux/ar8216_platform.h>
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-#include "machtypes.h"
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+#include <asm/mach-ath79/ar71xx_regs.h>
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@ -29,7 +40,7 @@
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#define DB120_GPIO_LED_WLAN_5G 12
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#define DB120_GPIO_LED_WLAN_2G 13
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#define DB120_GPIO_LED_STATUS 14
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@@ -58,8 +67,50 @@
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@@ -58,8 +69,50 @@
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#define DB120_KEYS_POLL_INTERVAL 20 /* msecs */
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#define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL)
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@ -82,7 +93,7 @@
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static struct gpio_led db120_leds_gpio[] __initdata = {
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{
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@@ -82,6 +133,11 @@ static struct gpio_led db120_leds_gpio[]
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@@ -82,6 +135,11 @@ static struct gpio_led db120_leds_gpio[]
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.gpio = DB120_GPIO_LED_WLAN_2G,
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.active_low = 1,
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},
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@ -94,15 +105,21 @@
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};
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static struct gpio_keys_button db120_gpio_keys[] __initdata = {
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@@ -95,66 +151,65 @@ static struct gpio_keys_button db120_gpi
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@@ -95,66 +153,89 @@ static struct gpio_keys_button db120_gpi
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},
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};
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-static struct ath79_spi_controller_data db120_spi0_data = {
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- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
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- .cs_line = 0,
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-};
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-
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+static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = {
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+ .mode = AR8327_PAD_MAC_RGMII,
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+ .txclk_delay_en = true,
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+ .rxclk_delay_en = true,
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+ .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
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+ .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
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};
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-static struct spi_board_info db120_spi_info[] = {
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- {
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- .bus_num = 0,
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@ -110,14 +127,28 @@
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- .max_speed_hz = 25000000,
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- .modalias = "s25sl064a",
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- .controller_data = &db120_spi0_data,
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- }
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-};
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-
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+static struct ar8327_platform_data db120_ar8327_data = {
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+ .pad0_cfg = &db120_ar8327_pad0_cfg,
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+ .cpuport_cfg = {
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+ .force_link = 1,
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+ .speed = AR8327_PORT_SPEED_1000,
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+ .duplex = 1,
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+ .txpause = 1,
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+ .rxpause = 1,
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}
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};
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-static struct ath79_spi_platform_data db120_spi_data = {
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- .bus_num = 0,
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- .num_chipselect = 1,
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-};
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-
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+static struct mdio_board_info db120_mdio0_info[] = {
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+ {
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+ .bus_id = "ag71xx-mdio.0",
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+ .phy_addr = 0,
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+ .platform_data = &db120_ar8327_data,
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+ },
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};
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-#ifdef CONFIG_PCI
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-static struct ath9k_platform_data db120_ath9k_data;
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-
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@ -143,6 +174,8 @@
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+ t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
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+ t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
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+ AR934X_ETH_CFG_MII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
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+ t |= AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE;
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+
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+ __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
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- ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
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@ -174,23 +207,18 @@
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+
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+ db120_gmac_setup();
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+
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+ ath79_register_mdio(0, 0x0);
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+ ath79_register_mdio(1, 0x0);
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+ ath79_register_mdio(0, 0x0);
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+
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+ ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0);
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+#if 0
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+
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+ mdiobus_register_board_info(db120_mdio0_info,
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+ ARRAY_SIZE(db120_mdio0_info));
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+
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+ /* GMAC0 is connected to an AR8327 switch */
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+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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+ ath79_eth0_data.speed = SPEED_1000;
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+ ath79_eth0_data.duplex = DUPLEX_FULL;
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+#else
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+ /* GMAC0 is connected to PHY4 of the internal switch */
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+ ath79_switch_data.phy4_mii_en = 1;
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+
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+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
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+ ath79_eth0_data.phy_mask = BIT(4);
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+ ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
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+#endif
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+ ath79_eth0_data.phy_mask = BIT(0);
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+ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
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+ ath79_register_eth(0);
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+
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+ /* GMAC1 is connected to the internal switch */
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@ -1,14 +1,25 @@
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--- a/arch/mips/ath79/mach-db120.c
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+++ b/arch/mips/ath79/mach-db120.c
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@@ -37,17 +37,26 @@
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@@ -2,7 +2,7 @@
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* Atheros DB120 reference board support
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*
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* Copyright (c) 2011 Qualcomm Atheros
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- * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org>
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+ * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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*
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* All rights reserved.
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*
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@@ -37,17 +37,28 @@
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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+#include <linux/mtd/mtd.h>
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+#include <linux/mtd/partitions.h>
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#include <linux/pci.h>
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+#include <linux/phy.h>
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+#include <linux/platform_device.h>
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#include <linux/ath9k_platform.h>
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+#include <linux/ar8216_platform.h>
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-#include "machtypes.h"
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+#include <asm/mach-ath79/ar71xx_regs.h>
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@ -29,7 +40,7 @@
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#define DB120_GPIO_LED_WLAN_5G 12
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#define DB120_GPIO_LED_WLAN_2G 13
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#define DB120_GPIO_LED_STATUS 14
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@@ -58,8 +67,50 @@
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@@ -58,8 +69,50 @@
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#define DB120_KEYS_POLL_INTERVAL 20 /* msecs */
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#define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL)
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@ -82,7 +93,7 @@
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static struct gpio_led db120_leds_gpio[] __initdata = {
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{
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@@ -82,6 +133,11 @@ static struct gpio_led db120_leds_gpio[]
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@@ -82,6 +135,11 @@ static struct gpio_led db120_leds_gpio[]
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.gpio = DB120_GPIO_LED_WLAN_2G,
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.active_low = 1,
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},
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@ -94,15 +105,21 @@
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};
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static struct gpio_keys_button db120_gpio_keys[] __initdata = {
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@@ -95,66 +151,65 @@ static struct gpio_keys_button db120_gpi
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@@ -95,66 +153,89 @@ static struct gpio_keys_button db120_gpi
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},
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};
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-static struct ath79_spi_controller_data db120_spi0_data = {
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- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
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- .cs_line = 0,
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-};
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-
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+static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = {
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+ .mode = AR8327_PAD_MAC_RGMII,
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+ .txclk_delay_en = true,
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+ .rxclk_delay_en = true,
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+ .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
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+ .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
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};
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-static struct spi_board_info db120_spi_info[] = {
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- {
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- .bus_num = 0,
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@ -110,14 +127,28 @@
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- .max_speed_hz = 25000000,
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- .modalias = "s25sl064a",
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- .controller_data = &db120_spi0_data,
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- }
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-};
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-
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+static struct ar8327_platform_data db120_ar8327_data = {
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+ .pad0_cfg = &db120_ar8327_pad0_cfg,
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+ .cpuport_cfg = {
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+ .force_link = 1,
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+ .speed = AR8327_PORT_SPEED_1000,
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+ .duplex = 1,
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+ .txpause = 1,
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+ .rxpause = 1,
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}
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};
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-static struct ath79_spi_platform_data db120_spi_data = {
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- .bus_num = 0,
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- .num_chipselect = 1,
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-};
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-
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+static struct mdio_board_info db120_mdio0_info[] = {
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+ {
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+ .bus_id = "ag71xx-mdio.0",
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+ .phy_addr = 0,
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+ .platform_data = &db120_ar8327_data,
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+ },
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};
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-#ifdef CONFIG_PCI
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-static struct ath9k_platform_data db120_ath9k_data;
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-
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@ -143,6 +174,8 @@
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+ t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
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+ t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
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+ AR934X_ETH_CFG_MII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
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+ t |= AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE;
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+
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+ __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
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- ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
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@ -174,23 +207,18 @@
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+
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+ db120_gmac_setup();
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+
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+ ath79_register_mdio(0, 0x0);
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+ ath79_register_mdio(1, 0x0);
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+ ath79_register_mdio(0, 0x0);
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+
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+ ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0);
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+#if 0
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+
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+ mdiobus_register_board_info(db120_mdio0_info,
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+ ARRAY_SIZE(db120_mdio0_info));
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+
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+ /* GMAC0 is connected to an AR8327 switch */
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+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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+ ath79_eth0_data.speed = SPEED_1000;
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+ ath79_eth0_data.duplex = DUPLEX_FULL;
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+#else
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+ /* GMAC0 is connected to PHY4 of the internal switch */
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+ ath79_switch_data.phy4_mii_en = 1;
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+
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+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
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+ ath79_eth0_data.phy_mask = BIT(4);
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+ ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
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+#endif
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+ ath79_eth0_data.phy_mask = BIT(0);
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+ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
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+ ath79_register_eth(0);
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+
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+ /* GMAC1 is connected to the internal switch */
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