diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/ar71xx.c b/target/linux/ar71xx/files/arch/mips/ar71xx/ar71xx.c
index 31b4422a09..ef956fbf4d 100644
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/ar71xx.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/ar71xx.c
@@ -71,6 +71,14 @@ void ar71xx_device_stop(u32 mask)
 		spin_unlock_irqrestore(&ar71xx_device_lock, flags);
 		break;
 
+	case AR71XX_SOC_AR9330:
+	case AR71XX_SOC_AR9331:
+		spin_lock_irqsave(&ar71xx_device_lock, flags);
+		t = ar71xx_reset_rr(AR933X_RESET_REG_RESET_MODULE);
+		ar71xx_reset_wr(AR933X_RESET_REG_RESET_MODULE, t | mask);
+		spin_unlock_irqrestore(&ar71xx_device_lock, flags);
+		break;
+
 	case AR71XX_SOC_AR9341:
 	case AR71XX_SOC_AR9342:
 	case AR71XX_SOC_AR9344:
@@ -122,6 +130,14 @@ void ar71xx_device_start(u32 mask)
 		spin_unlock_irqrestore(&ar71xx_device_lock, flags);
 		break;
 
+	case AR71XX_SOC_AR9330:
+	case AR71XX_SOC_AR9331:
+		spin_lock_irqsave(&ar71xx_device_lock, flags);
+		t = ar71xx_reset_rr(AR933X_RESET_REG_RESET_MODULE);
+		ar71xx_reset_wr(AR933X_RESET_REG_RESET_MODULE, t & ~mask);
+		spin_unlock_irqrestore(&ar71xx_device_lock, flags);
+		break;
+
 	case AR71XX_SOC_AR9341:
 	case AR71XX_SOC_AR9342:
 	case AR71XX_SOC_AR9344:
@@ -166,6 +182,13 @@ int ar71xx_device_stopped(u32 mask)
 		spin_unlock_irqrestore(&ar71xx_device_lock, flags);
 		break;
 
+	case AR71XX_SOC_AR9330:
+	case AR71XX_SOC_AR9331:
+		spin_lock_irqsave(&ar71xx_device_lock, flags);
+		t = ar71xx_reset_rr(AR933X_RESET_REG_RESET_MODULE);
+		spin_unlock_irqrestore(&ar71xx_device_lock, flags);
+		break;
+
 	case AR71XX_SOC_AR9341:
 	case AR71XX_SOC_AR9342:
 	case AR71XX_SOC_AR9344:
diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
index 84f7c476b5..3b02d64b99 100644
--- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
@@ -604,6 +604,7 @@ void ar71xx_ddr_flush(u32 reg);
 
 #define AR724X_RESET_REG_RESET_MODULE		0x1c
 
+#define AR933X_RESET_REG_RESET_MODULE		0x1c
 #define AR933X_RESET_REG_BOOTSTRAP		0xac
 #define AR933X_BOOTSTRAP_REF_CLK_40		BIT(0)