use the recommended ARM I/O accessors
use {read,write}l_relaxed instead of the plain __raw_{read,write}l variants. SVN-Revision: 33330
This commit is contained in:
parent
95f1b6d415
commit
6771d63284
9 changed files with 55 additions and 52 deletions
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@ -54,13 +54,13 @@ static int clk_local_onoff_enable(struct clk *clk, int enable)
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if (!clk->enable_reg)
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return 0;
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tmp = __raw_readl(mcs814x_sysdbg_base + clk->enable_reg);
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tmp = readl_relaxed(mcs814x_sysdbg_base + clk->enable_reg);
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if (!enable)
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tmp &= ~clk->enable_mask;
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else
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tmp |= clk->enable_mask;
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__raw_writel(tmp, mcs814x_sysdbg_base + clk->enable_reg);
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writel_relaxed(tmp, mcs814x_sysdbg_base + clk->enable_reg);
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return 0;
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}
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@ -254,7 +254,7 @@ void __init mcs814x_clk_init(void)
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clkdev_add_table(mcs814x_chip_clks, ARRAY_SIZE(mcs814x_chip_clks));
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/* read the bootstrap registers to know the exact clocking scheme */
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bs1 = __raw_readl(mcs814x_sysdbg_base + SYSDBG_BS1);
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bs1 = readl_relaxed(mcs814x_sysdbg_base + SYSDBG_BS1);
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cpu_freq = (bs1 >> CPU_FREQ_SHIFT) & CPU_FREQ_MASK;
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pr_info("CPU frequency: %lu (kHz)\n", cpu_freq_table[cpu_freq]);
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@ -67,22 +67,22 @@ static void mcs814x_eth_hardware_filter_set(u8 value)
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{
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u32 reg;
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reg = __raw_readl(MCS814X_VIRT_BASE + MCS814X_DBGLED);
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reg = readl_relaxed(MCS814X_VIRT_BASE + MCS814X_DBGLED);
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if (value)
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reg |= 0x80;
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else
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reg &= ~0x80;
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__raw_writel(reg, MCS814X_VIRT_BASE + MCS814X_DBGLED);
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writel_relaxed(reg, MCS814X_VIRT_BASE + MCS814X_DBGLED);
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}
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static void mcs814x_eth_led_cfg_set(u8 cfg)
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{
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u32 reg;
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reg = __raw_readl(mcs814x_sysdbg_base + SYSDBG_BS2);
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reg = readl_relaxed(mcs814x_sysdbg_base + SYSDBG_BS2);
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reg &= ~LED_CFG_MASK;
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reg |= cfg;
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__raw_writel(reg, mcs814x_sysdbg_base + SYSDBG_BS2);
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writel_relaxed(reg, mcs814x_sysdbg_base + SYSDBG_BS2);
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}
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static void mcs814x_eth_buffer_shifting_set(u8 value)
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@ -134,7 +134,7 @@ void __init mcs814x_init_machine(void)
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u32 bs2, cpu_mode;
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int gpio;
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bs2 = __raw_readl(mcs814x_sysdbg_base + SYSDBG_BS2);
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bs2 = readl_relaxed(mcs814x_sysdbg_base + SYSDBG_BS2);
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cpu_mode = (bs2 >> CPU_MODE_SHIFT) & CPU_MODE_MASK;
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pr_info("CPU mode: %s\n", cpu_modes[cpu_mode].name);
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@ -161,5 +161,5 @@ void __init mcs814x_map_io(void)
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void mcs814x_restart(char mode, const char *cmd)
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{
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__raw_writel(~(1 << 31), mcs814x_sysdbg_base);
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writel_relaxed(~(1 << 31), mcs814x_sysdbg_base);
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}
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@ -40,7 +40,7 @@ static void __init mcs814x_alloc_gc(void __iomem *base, unsigned int irq_start,
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IRQ_NOREQUEST, 0);
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/* Clear all interrupts */
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__raw_writel(0xffffffff, base + MCS814X_IRQ_ICR);
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writel_relaxed(0xffffffff, base + MCS814X_IRQ_ICR);
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}
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static const struct of_device_id mcs814x_intc_ids[] = {
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@ -93,13 +93,13 @@ static int mcs8140_pci_host_status(void)
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{
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u32 host_status;
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host_status = __raw_readl(mcs8140_pci_master_base + PCI_IF_CONFIG);
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host_status = readl_relaxed(mcs8140_pci_master_base + PCI_IF_CONFIG);
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if (host_status & PCI_FATAL_ERROR) {
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__raw_writel(host_status & 0xfffffff0,
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writel_relaxed(host_status & 0xfffffff0,
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mcs8140_pci_master_base + PCI_IF_CONFIG);
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/* flush write */
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host_status =
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__raw_readl(mcs8140_pci_master_base + PCI_IF_CONFIG);
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readl_relaxed(mcs8140_pci_master_base + PCI_IF_CONFIG);
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return 1;
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}
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@ -124,7 +124,7 @@ static int mcs8140_pci_read_config(struct pci_bus *bus,
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break;
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default:
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addr &= ~3;
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v = __raw_readl(addr);
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v = readl_relaxed(addr);
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break;
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}
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} else
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@ -140,10 +140,10 @@ static int mcs8140_pci_read_config(struct pci_bus *bus,
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static void mcs8140_eeprom_emu_init(void)
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{
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__raw_writel(0x0000000F, mcs8140_eeprom_emu_base + EPRM_SDRAM_FUNC0);
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__raw_writel(0x08000000, MCS8140_PCI_CFG_VIRT_BASE + 0x10);
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writel_relaxed(0x0000000F, mcs8140_eeprom_emu_base + EPRM_SDRAM_FUNC0);
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writel_relaxed(0x08000000, MCS8140_PCI_CFG_VIRT_BASE + 0x10);
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/* Set the DONE bit of the EEPROM emulator */
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__raw_writel(0x01, mcs8140_eeprom_emu_base + EPRM_DONE);
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writel_relaxed(0x01, mcs8140_eeprom_emu_base + EPRM_DONE);
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}
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static int mcs8140_pci_write_config(struct pci_bus *bus,
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@ -161,7 +161,7 @@ static int mcs8140_pci_write_config(struct pci_bus *bus,
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__raw_writew((u16)val, addr);
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break;
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case 4:
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__raw_writel(val, addr);
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writel_relaxed(val, addr);
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break;
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}
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}
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@ -260,7 +260,7 @@ int __init pci_mcs8140_setup(int nr, struct pci_sys_data *sys)
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goto out;
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}
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val = __raw_readl(MCS8140_PCI_CFG_VIRT_BASE);
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val = readl_relaxed(MCS8140_PCI_CFG_VIRT_BASE);
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if (val != MCS8140_PCI_DEVICE_ID) {
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pr_err("cannot find MCS8140 PCI Core: %08x\n", val);
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ret = -EIO;
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@ -269,11 +269,11 @@ int __init pci_mcs8140_setup(int nr, struct pci_sys_data *sys)
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pr_info("MCS8140 PCI core found\n");
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val = __raw_readl(MCS8140_PCI_CFG_VIRT_BASE + PCI_COMMAND);
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val = readl_relaxed(MCS8140_PCI_CFG_VIRT_BASE + PCI_COMMAND);
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/* Added to support wireless cards */
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__raw_writel(0, MCS8140_PCI_CFG_VIRT_BASE + 0x40);
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__raw_writel(val | 0x147, MCS8140_PCI_CFG_VIRT_BASE + PCI_COMMAND);
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val = __raw_readl(MCS8140_PCI_CFG_VIRT_BASE + PCI_COMMAND);
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writel_relaxed(0, MCS8140_PCI_CFG_VIRT_BASE + 0x40);
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writel_relaxed(val | 0x147, MCS8140_PCI_CFG_VIRT_BASE + PCI_COMMAND);
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val = readl_relaxed(MCS8140_PCI_CFG_VIRT_BASE + PCI_COMMAND);
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ret = 1;
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out:
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return ret;
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@ -302,14 +302,14 @@ static irqreturn_t mcs8140_pci_abort_interrupt(int irq, void *dummy)
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{
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u32 word;
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word = __raw_readl(mcs8140_pci_master_base + PCI_IF_CONFIG);
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word = readl_relaxed(mcs8140_pci_master_base + PCI_IF_CONFIG);
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if (!(word & (1 << 24)))
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return IRQ_NONE;
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__raw_writel(word & 0xfffffff0,
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writel_relaxed(word & 0xfffffff0,
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mcs8140_pci_master_base + PCI_IF_CONFIG);
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/* flush write */
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word = __raw_readl(mcs8140_pci_master_base + PCI_IF_CONFIG);
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word = readl_relaxed(mcs8140_pci_master_base + PCI_IF_CONFIG);
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return IRQ_HANDLED;
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}
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@ -319,12 +319,12 @@ static int mcs8140_pci_abort_irq_init(int irq)
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u32 word;
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/* Enable Interrupt in PCI Master Core */
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word = __raw_readl(mcs8140_pci_master_base + PCI_IF_CONFIG);
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word = readl_relaxed(mcs8140_pci_master_base + PCI_IF_CONFIG);
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word |= (1 << 24);
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__raw_writel(word, mcs8140_pci_master_base + PCI_IF_CONFIG);
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writel_relaxed(word, mcs8140_pci_master_base + PCI_IF_CONFIG);
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/* flush write */
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word = __raw_readl(mcs8140_pci_master_base + PCI_IF_CONFIG);
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word = readl_relaxed(mcs8140_pci_master_base + PCI_IF_CONFIG);
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return request_irq(irq, mcs8140_pci_abort_interrupt, 0,
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"PCI abort", NULL);
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@ -22,6 +22,8 @@
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/* Timer block registers */
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#define TIMER_VAL 0x00
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#define TIMER_CTL 0x04
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#define TIMER_CTL_EN 0x01
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#define TIMER_CTL_DBG 0x02
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static u32 last_reload;
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static u32 timer_correct;
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@ -40,7 +42,7 @@ static inline unsigned long ticks2usecs(u32 x)
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*/
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static unsigned long mcs814x_gettimeoffset(void)
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{
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u32 ticks = __raw_readl(mcs814x_timer_base + TIMER_VAL);
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u32 ticks = readl_relaxed(mcs814x_timer_base + TIMER_VAL);
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if (ticks < last_reload)
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return ticks2usecs(ticks + (u32)(0xffffffff - last_reload));
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@ -51,7 +53,7 @@ static unsigned long mcs814x_gettimeoffset(void)
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static irqreturn_t mcs814x_timer_interrupt(int irq, void *dev_id)
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{
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u32 count = __raw_readl(mcs814x_timer_base + TIMER_VAL);
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u32 count = readl_relaxed(mcs814x_timer_base + TIMER_VAL);
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/* take into account delay up to this moment */
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last_reload = count + timer_correct + timer_reload_value;
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last_reload = timer_reload_value;
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} else {
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if (timer_correct == 0)
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timer_correct = __raw_readl(mcs814x_timer_base + TIMER_VAL) - count;
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timer_correct = readl_relaxed(mcs814x_timer_base + TIMER_VAL) - count;
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}
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__raw_writel(last_reload, mcs814x_timer_base + TIMER_VAL);
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writel_relaxed(last_reload, mcs814x_timer_base + TIMER_VAL);
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timer_tick();
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timer_reload_value = 0xffffffff - (clock_rate / HZ);
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/* disable timer */
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__raw_writel(0, mcs814x_timer_base + TIMER_CTL);
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__raw_writel(timer_reload_value, mcs814x_timer_base + TIMER_VAL);
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writel_relaxed(~TIMER_CTL_EN, mcs814x_timer_base + TIMER_CTL);
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writel_relaxed(timer_reload_value, mcs814x_timer_base + TIMER_VAL);
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last_reload = timer_reload_value;
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setup_irq(mcs814x_timer_irq.irq, &mcs814x_timer_irq);
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/* enable timer, stop timer in debug mode */
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__raw_writel(0x03, mcs814x_timer_base + TIMER_CTL);
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writel_relaxed(TIMER_CTL_EN | TIMER_CTL_DBG,
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mcs814x_timer_base + TIMER_CTL);
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}
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struct sys_timer mcs814x_timer = {
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@ -28,7 +28,7 @@ static int mcs814x_rng_data_read(struct hwrng *rng, u32 *buffer)
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{
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struct mcs814x_rng_priv *priv = (struct mcs814x_rng_priv *)rng->priv;
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*buffer = __raw_readl(priv->regs + RND);
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*buffer = readl_relaxed(priv->regs + RND);
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return 4;
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}
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@ -30,7 +30,7 @@ static int mcs814x_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct mcs814x_gpio_chip *mcs814x = to_mcs814x_gpio_chip(chip);
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return __raw_readl(mcs814x->regs + GPIO_PIN) & (1 << offset);
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return readl_relaxed(mcs814x->regs + GPIO_PIN) & (1 << offset);
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}
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static void mcs814x_gpio_set(struct gpio_chip *chip,
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@ -39,12 +39,12 @@ static void mcs814x_gpio_set(struct gpio_chip *chip,
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struct mcs814x_gpio_chip *mcs814x = to_mcs814x_gpio_chip(chip);
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u32 mask;
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mask = __raw_readl(mcs814x->regs + GPIO_PIN);
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mask = readl_relaxed(mcs814x->regs + GPIO_PIN);
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if (value)
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mask |= (1 << offset);
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else
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mask &= ~(1 << offset);
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__raw_writel(mask, mcs814x->regs + GPIO_PIN);
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writel_relaxed(mask, mcs814x->regs + GPIO_PIN);
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}
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static int mcs814x_gpio_direction_output(struct gpio_chip *chip,
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struct mcs814x_gpio_chip *mcs814x = to_mcs814x_gpio_chip(chip);
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u32 mask;
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mask = __raw_readl(mcs814x->regs + GPIO_DIR);
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mask = readl_relaxed(mcs814x->regs + GPIO_DIR);
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mask &= ~(1 << offset);
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__raw_writel(mask, mcs814x->regs + GPIO_DIR);
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writel_relaxed(mask, mcs814x->regs + GPIO_DIR);
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return 0;
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}
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@ -66,9 +66,9 @@ static int mcs814x_gpio_direction_input(struct gpio_chip *chip,
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struct mcs814x_gpio_chip *mcs814x = to_mcs814x_gpio_chip(chip);
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u32 mask;
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mask = __raw_readl(mcs814x->regs + GPIO_DIR);
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mask = readl_relaxed(mcs814x->regs + GPIO_DIR);
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mask |= (1 << offset);
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__raw_writel(mask, mcs814x->regs + GPIO_DIR);
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writel_relaxed(mask, mcs814x->regs + GPIO_DIR);
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return 0;
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}
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@ -112,7 +112,7 @@
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static inline u32 nuport_mac_readl(void __iomem *reg)
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{
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return __raw_readl(reg);
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return readl_relaxed(reg);
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}
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static inline u8 nuport_mac_readb(void __iomem *reg)
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@ -122,12 +122,12 @@ static inline u8 nuport_mac_readb(void __iomem *reg)
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static inline void nuport_mac_writel(u32 value, void __iomem *reg)
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{
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__raw_writel(value, reg);
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writel_relaxed(value, reg);
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}
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static inline void nuport_mac_writeb(u8 value, void __iomem *reg)
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{
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__raw_writel(value, reg);
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writel_relaxed(value, reg);
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}
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/* MAC private data */
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@ -49,9 +49,9 @@ static int mcs814x_wdt_start(struct watchdog_device *dev)
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u32 reg;
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spin_lock(&wdt->lock);
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reg = __raw_readl(wdt->regs + WDT_CTRL);
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reg = readl_relaxed(wdt->regs + WDT_CTRL);
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reg |= WDT_CTRL_EN;
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__raw_writel(reg, wdt->regs + WDT_CTRL);
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writel_relaxed(reg, wdt->regs + WDT_CTRL);
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spin_unlock(&wdt->lock);
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return 0;
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@ -63,9 +63,9 @@ static int mcs814x_wdt_stop(struct watchdog_device *dev)
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u32 reg;
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spin_lock(&wdt->lock);
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reg = __raw_readl(wdt->regs + WDT_CTRL);
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reg = readl_relaxed(wdt->regs + WDT_CTRL);
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reg &= ~WDT_CTRL_EN;
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__raw_writel(reg, wdt->regs + WDT_CTRL);
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writel_relaxed(reg, wdt->regs + WDT_CTRL);
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spin_unlock(&wdt->lock);
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return 0;
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@ -80,7 +80,7 @@ static int mcs814x_wdt_set_timeout(struct watchdog_device *dev,
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/* watchdog counts upward and rollover (0xfffffff -> 0)
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* triggers the reboot
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*/
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__raw_writel(WDT_MAX_VALUE - (new_timeout * clk_get_rate(wdt->clk)),
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writel_relaxed(WDT_MAX_VALUE - (new_timeout * clk_get_rate(wdt->clk)),
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wdt->regs + WDT_COUNT);
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spin_unlock(&wdt->lock);
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