atheros: split out the pci support patch
SVN-Revision: 14969
This commit is contained in:
Felix Fietkau
parent
df68a2199b
commit
675f7bfdd8
2 changed files with 301 additions and 438 deletions
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@ -46,7 +46,7 @@
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core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/
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--- /dev/null
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+++ b/arch/mips/ar231x/Kconfig
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@@ -0,0 +1,27 @@
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@@ -0,0 +1,17 @@
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+config ATHEROS_AR5312
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+ bool "Atheros 5312/2312+ support"
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+ depends on ATHEROS
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@ -64,19 +64,9 @@
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+ select SYS_SUPPORTS_BIG_ENDIAN
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+ select GENERIC_GPIO
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+ default y
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+
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+config ATHEROS_AR2315_PCI
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+ bool "PCI support"
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+ depends on ATHEROS_AR2315
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+ select HW_HAS_PCI
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+ select PCI
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+ select USB_ARCH_HAS_HCD
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+ select USB_ARCH_HAS_OHCI
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+ select USB_ARCH_HAS_EHCI
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+ default y
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--- /dev/null
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+++ b/arch/mips/ar231x/Makefile
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@@ -0,0 +1,14 @@
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@@ -0,0 +1,13 @@
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+#
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+# This file is subject to the terms and conditions of the GNU General Public
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+# License. See the file "COPYING" in the main directory of this archive
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@ -90,7 +80,6 @@
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+obj-y += board.o prom.o devices.o
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+obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
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+obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
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+obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o
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--- /dev/null
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+++ b/arch/mips/ar231x/board.c
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@@ -0,0 +1,247 @@
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@ -382,171 +371,6 @@
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+{
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+}
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--- /dev/null
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+++ b/arch/mips/ar231x/reset.c
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@@ -0,0 +1,162 @@
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+#include <linux/module.h>
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+#include <linux/timer.h>
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+#include <linux/interrupt.h>
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+#include <linux/kobject.h>
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+#include <linux/workqueue.h>
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+#include <linux/skbuff.h>
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+#include <linux/netlink.h>
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+#include <net/sock.h>
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+#include <asm/uaccess.h>
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+#include <ar231x.h>
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+
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+#define AR531X_RESET_GPIO_IRQ (AR531X_GPIO_IRQ(bcfg->resetConfigGpio))
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+
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+struct event_t {
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+ struct work_struct wq;
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+ int set;
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+ unsigned long jiffies;
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+};
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+
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+static struct ar231x_boarddata *bcfg;
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+static struct timer_list rst_button_timer;
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+
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+extern struct sock *uevent_sock;
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+extern u64 uevent_next_seqnum(void);
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+static unsigned long seen;
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+
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+static inline void add_msg(struct sk_buff *skb, char *msg)
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+{
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+ char *scratch;
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+ scratch = skb_put(skb, strlen(msg) + 1);
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+ sprintf(scratch, msg);
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+}
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+
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+static void hotplug_button(struct work_struct *wq)
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+{
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+ struct sk_buff *skb;
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+ struct event_t *event;
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+ size_t len;
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+ char *scratch, *s;
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+ char buf[128];
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+
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+ event = container_of(wq, struct event_t, wq);
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+ if (!uevent_sock)
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+ goto done;
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+
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+ /* allocate message with the maximum possible size */
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+ s = event->set ? "pressed" : "released";
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+ len = strlen(s) + 2;
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+ skb = alloc_skb(len + 2048, GFP_KERNEL);
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+ if (!skb)
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+ goto done;
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+
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+ /* add header */
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+ scratch = skb_put(skb, len);
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+ sprintf(scratch, "%s@",s);
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+
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+ /* copy keys to our continuous event payload buffer */
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+ add_msg(skb, "HOME=/");
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+ add_msg(skb, "PATH=/sbin:/bin:/usr/sbin:/usr/bin");
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+ add_msg(skb, "SUBSYSTEM=button");
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+ add_msg(skb, "BUTTON=reset");
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+ add_msg(skb, (event->set ? "ACTION=pressed" : "ACTION=released"));
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+ sprintf(buf, "SEEN=%ld", (event->jiffies - seen)/HZ);
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+ add_msg(skb, buf);
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+ snprintf(buf, 128, "SEQNUM=%llu", uevent_next_seqnum());
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+ add_msg(skb, buf);
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+
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+ NETLINK_CB(skb).dst_group = 1;
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+ netlink_broadcast(uevent_sock, skb, 0, 1, GFP_KERNEL);
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+
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+done:
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+ kfree(event);
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+}
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+
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+static int no_release_workaround = 1;
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+
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+static void
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+reset_button_poll(unsigned long unused)
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+{
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+ struct event_t *event;
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+ int gpio = ~0;
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+
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+ if(!no_release_workaround)
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+ return;
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+
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+ DO_AR2315(gpio = sysRegRead(AR2315_GPIO_DI);)
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+ gpio &= 1 << (AR531X_RESET_GPIO_IRQ - AR531X_GPIO_IRQ_BASE);
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+ if(gpio)
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+ {
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+ rst_button_timer.expires = jiffies + (HZ / 4);
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+ add_timer(&rst_button_timer);
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+ } else {
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+ event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC);
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+ if (!event)
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+ {
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+ printk("Could not alloc hotplug event\n");
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+ return;
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+ }
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+ event->set = 0;
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+ event->jiffies = jiffies;
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+ INIT_WORK(&event->wq, (void *)(void *)hotplug_button);
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+ schedule_work(&event->wq);
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+ }
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+}
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+
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+static irqreturn_t button_handler(int irq, void *dev_id)
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+{
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+ static int pressed = 0;
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+ struct event_t *event;
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+ u32 gpio = ~0;
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+
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+ event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC);
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+ if (!event)
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+ return IRQ_NONE;
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+
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+ pressed = !pressed;
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+
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+ DO_AR2315(gpio = sysRegRead(AR2315_GPIO_DI);)
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+ gpio &= 1 << (irq - AR531X_GPIO_IRQ_BASE);
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+
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+ event->set = gpio;
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+ if(!event->set)
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+ no_release_workaround = 0;
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+
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+ event->jiffies = jiffies;
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+
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+ INIT_WORK(&event->wq, (void *)(void *)hotplug_button);
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+ schedule_work(&event->wq);
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+
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+ seen = jiffies;
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+ if(event->set && no_release_workaround)
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+ mod_timer(&rst_button_timer, jiffies + (HZ / 4));
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+
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+ return IRQ_HANDLED;
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+}
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+
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+void ar231x_disable_reset_button(void)
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+{
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+ disable_irq(AR531X_RESET_GPIO_IRQ);
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+}
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+
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+EXPORT_SYMBOL(ar231x_disable_reset_button);
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+
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+int __init ar231x_init_reset(void)
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+{
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+ bcfg = (struct ar231x_boarddata *) board_config;
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+
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+ seen = jiffies;
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+
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+ init_timer(&rst_button_timer);
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+ rst_button_timer.function = reset_button_poll;
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+ rst_button_timer.expires = jiffies + HZ / 50;
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+ add_timer(&rst_button_timer);
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+
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+ request_irq(AR531X_RESET_GPIO_IRQ, &button_handler, IRQF_SAMPLE_RANDOM, "ar231x_reset", NULL);
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+
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+ return 0;
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+}
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+
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+
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+
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+module_init(ar231x_init_reset);
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
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@@ -0,0 +1,83 @@
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+#ifndef __AR531X_PLATFORM_H
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@ -2271,242 +2095,8 @@
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+}
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+
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--- /dev/null
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+++ b/arch/mips/ar231x/pci.c
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@@ -0,0 +1,231 @@
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+/*
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License
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+ * as published by the Free Software Foundation; either version 2
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+ * of the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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+ */
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+
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+#include <linux/types.h>
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+#include <linux/pci.h>
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/mm.h>
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+#include <linux/spinlock.h>
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+#include <linux/delay.h>
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+#include <linux/irq.h>
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+#include <asm/bootinfo.h>
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+#include <asm/paccess.h>
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+#include <asm/irq_cpu.h>
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+#include <asm/io.h>
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+#include <ar231x_platform.h>
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+#include <ar231x.h>
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+#include <ar2315_regs.h>
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+
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+#define AR531X_MEM_BASE 0x80800000UL
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+#define AR531X_MEM_SIZE 0x00ffffffUL
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+#define AR531X_IO_SIZE 0x00007fffUL
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+
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+#define IS_2315() (current_cpu_data.cputype == CPU_4KEC)
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+
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+static unsigned long configspace;
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+
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+static int config_access(int devfn, int where, int size, u32 *ptr, bool write)
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+{
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+ unsigned long flags;
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+ int func = PCI_FUNC(devfn);
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+ int dev = PCI_SLOT(devfn);
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+ u32 value = 0;
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+ int err = 0;
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+ u32 addr;
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+
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+ if (((dev != 0) && (dev != 3)) || (func > 2))
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+
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+ /* Select Configuration access */
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+ local_irq_save(flags);
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+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL);
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+ mb();
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+
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+ addr = (u32) configspace + (1 << (13 + dev)) + (func << 8) + where;
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+ if (size == 1)
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+ addr ^= 0x3;
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+ else if (size == 2)
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+ addr ^= 0x2;
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+
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+ if (write) {
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+ value = *ptr;
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+ if (size == 1)
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+ err = put_dbe(value, (u8 *) addr);
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+ else if (size == 2)
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+ err = put_dbe(value, (u16 *) addr);
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+ else if (size == 4)
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+ err = put_dbe(value, (u32 *) addr);
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+ } else {
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+ if (size == 1)
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+ err = get_dbe(value, (u8 *) addr);
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+ else if (size == 2)
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+ err = get_dbe(value, (u16 *) addr);
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+ else if (size == 4)
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+ err = get_dbe(value, (u32 *) addr);
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+ if (err)
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+ *ptr = 0xffffffff;
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+ else
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+ *ptr = value;
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+ }
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+
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+ /* Select Memory access */
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+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0);
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+ local_irq_restore(flags);
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+
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+ return (err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL);
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+}
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+
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+static int ar231x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * value)
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+{
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+ return config_access(devfn, where, size, value, 0);
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+}
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+
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+static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
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+{
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+ return config_access(devfn, where, size, &value, 1);
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+}
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+
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+struct pci_ops ar231x_pci_ops = {
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+ .read = ar231x_pci_read,
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+ .write = ar231x_pci_write,
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+};
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+
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+static struct resource ar231x_mem_resource = {
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+ .name = "AR531x PCI MEM",
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+ .start = AR531X_MEM_BASE,
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+ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1 + 0x4000000,
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+ .flags = IORESOURCE_MEM,
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+};
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+
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+static struct resource ar231x_io_resource = {
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+ .name = "AR531x PCI I/O",
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+ .start = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE,
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+ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - 1,
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+ .flags = IORESOURCE_IO,
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+};
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+
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+struct pci_controller ar231x_pci_controller = {
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+ .pci_ops = &ar231x_pci_ops,
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+ .mem_resource = &ar231x_mem_resource,
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+ .io_resource = &ar231x_io_resource,
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+ .mem_offset = 0x00000000UL,
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+ .io_offset = 0x00000000UL,
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+};
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+
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+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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+{
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+ return AR2315_IRQ_LCBUS_PCI;
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+}
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+
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+int pcibios_plat_dev_init(struct pci_dev *dev)
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+{
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+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5);
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+ pci_write_config_word(dev, 0x40, 0);
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+
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+ /* Clear any pending Abort or external Interrupts
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+ * and enable interrupt processing */
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+ ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0);
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+ ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT));
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+ ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT));
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+ ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE);
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+
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+ return 0;
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+}
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+
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+static void
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+ar2315_pci_fixup(struct pci_dev *dev)
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+{
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+ unsigned int devfn = dev->devfn;
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+
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+ if (dev->bus->number != 0)
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+ return;
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+
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+ /* Only fix up the PCI host settings */
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+ if ((PCI_SLOT(devfn) != 3) || (PCI_FUNC(devfn) != 0))
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+ return;
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+
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+ /* Fix up MBARs */
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+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0);
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+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1);
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+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2);
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+ pci_write_config_dword(dev, PCI_COMMAND,
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+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
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+ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
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+ PCI_COMMAND_FAST_BACK);
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+}
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+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup);
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+
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+static int __init
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+ar2315_pci_init(void)
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+{
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+ u32 reg;
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+
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+ if (!IS_2315())
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+ return -ENODEV;
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+
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+ configspace = (unsigned long) ioremap_nocache(0x80000000, 1*1024*1024); /* Remap PCI config space */
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+ ar231x_pci_controller.io_map_base =
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+ (unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_MEM_SIZE, AR531X_IO_SIZE);
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+ set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space */
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+
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+ reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
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+ msleep(10);
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+
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+ reg &= ~AR2315_RESET_PCIDMA;
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+ ar231x_write_reg(AR2315_RESET, reg);
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+ msleep(10);
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+
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+ ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
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+ AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
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+
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+ ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
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+ (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S));
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+ ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
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+ ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK,
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+ AR2315_IF_PCI | AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
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+ (AR2315_IF_PCI_CLK_OUTPUT_CLK << AR2315_IF_PCI_CLK_SHIFT));
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+
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||||
+ /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
|
||||
+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
|
||||
+ AR2315_PCIRST_LOW);
|
||||
+ msleep(100);
|
||||
+
|
||||
+ /* Bring the PCI out of reset */
|
||||
+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
|
||||
+ AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
|
||||
+
|
||||
+ ar231x_write_reg(AR2315_PCI_UNCACHE_CFG,
|
||||
+ 0x1E | /* 1GB uncached */
|
||||
+ (1 << 5) | /* Enable uncached */
|
||||
+ (0x2 << 30) /* Base: 0x80000000 */
|
||||
+ );
|
||||
+ ar231x_read_reg(AR2315_PCI_UNCACHE_CFG);
|
||||
+
|
||||
+ msleep(500);
|
||||
+
|
||||
+ /* dirty hack - anyone with a datasheet that knows the memory map ? */
|
||||
+ ioport_resource.start = 0x10000000;
|
||||
+ ioport_resource.end = 0xffffffff;
|
||||
+ iomem_resource.start = 0x10000000;
|
||||
+ iomem_resource.end = 0xffffffff;
|
||||
+
|
||||
+ register_pci_controller(&ar231x_pci_controller);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+arch_initcall(ar2315_pci_init);
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ar231x/ar2315.c
|
||||
@@ -0,0 +1,688 @@
|
||||
@@ -0,0 +1,663 @@
|
||||
+/*
|
||||
+ * This file is subject to the terms and conditions of the GNU General Public
|
||||
+ * License. See the file "COPYING" in the main directory of this archive
|
||||
|
|
@ -2570,27 +2160,6 @@
|
|||
+ do_IRQ(AR531X_GPIO_IRQ_BASE + fls(pend) - 1);
|
||||
+}
|
||||
+
|
||||
+#ifdef CONFIG_ATHEROS_AR2315_PCI
|
||||
+static inline void pci_abort_irq(void)
|
||||
+{
|
||||
+ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_ABORT_INT);
|
||||
+}
|
||||
+
|
||||
+static inline void pci_ack_irq(void)
|
||||
+{
|
||||
+ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT);
|
||||
+}
|
||||
+
|
||||
+void ar2315_pci_irq(int irq)
|
||||
+{
|
||||
+ if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT)
|
||||
+ pci_abort_irq();
|
||||
+ else {
|
||||
+ do_IRQ(irq);
|
||||
+ pci_ack_irq();
|
||||
+ }
|
||||
+}
|
||||
+#endif /* CONFIG_ATHEROS_AR2315_PCI */
|
||||
+
|
||||
+/*
|
||||
+ * Called when an interrupt is received, this function
|
||||
|
|
@ -2609,10 +2178,6 @@
|
|||
+ do_IRQ(AR2315_IRQ_WLAN0_INTRS);
|
||||
+ else if (pending & CAUSEF_IP4)
|
||||
+ do_IRQ(AR2315_IRQ_ENET0_INTRS);
|
||||
+#ifdef CONFIG_ATHEROS_AR2315_PCI
|
||||
+ else if (pending & CAUSEF_IP5)
|
||||
+ ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI);
|
||||
+#endif
|
||||
+ else if (pending & CAUSEF_IP2) {
|
||||
+ unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR);
|
||||
+
|
||||
|
|
|
|||
298
target/linux/atheros/patches-2.6.28/105-ar2315_pci.patch
Normal file
298
target/linux/atheros/patches-2.6.28/105-ar2315_pci.patch
Normal file
|
|
@ -0,0 +1,298 @@
|
|||
--- a/arch/mips/ar231x/Makefile
|
||||
+++ b/arch/mips/ar231x/Makefile
|
||||
@@ -11,3 +11,4 @@
|
||||
obj-y += board.o prom.o devices.o
|
||||
obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
|
||||
obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
|
||||
+obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ar231x/pci.c
|
||||
@@ -0,0 +1,231 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or
|
||||
+ * modify it under the terms of the GNU General Public License
|
||||
+ * as published by the Free Software Foundation; either version 2
|
||||
+ * of the License, or (at your option) any later version.
|
||||
+ *
|
||||
+ * This program is distributed in the hope that it will be useful,
|
||||
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
+ * GNU General Public License for more details.
|
||||
+ *
|
||||
+ * You should have received a copy of the GNU General Public License
|
||||
+ * along with this program; if not, write to the Free Software
|
||||
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/types.h>
|
||||
+#include <linux/pci.h>
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/mm.h>
|
||||
+#include <linux/spinlock.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/irq.h>
|
||||
+#include <asm/bootinfo.h>
|
||||
+#include <asm/paccess.h>
|
||||
+#include <asm/irq_cpu.h>
|
||||
+#include <asm/io.h>
|
||||
+#include <ar231x_platform.h>
|
||||
+#include <ar231x.h>
|
||||
+#include <ar2315_regs.h>
|
||||
+
|
||||
+#define AR531X_MEM_BASE 0x80800000UL
|
||||
+#define AR531X_MEM_SIZE 0x00ffffffUL
|
||||
+#define AR531X_IO_SIZE 0x00007fffUL
|
||||
+
|
||||
+#define IS_2315() (current_cpu_data.cputype == CPU_4KEC)
|
||||
+
|
||||
+static unsigned long configspace;
|
||||
+
|
||||
+static int config_access(int devfn, int where, int size, u32 *ptr, bool write)
|
||||
+{
|
||||
+ unsigned long flags;
|
||||
+ int func = PCI_FUNC(devfn);
|
||||
+ int dev = PCI_SLOT(devfn);
|
||||
+ u32 value = 0;
|
||||
+ int err = 0;
|
||||
+ u32 addr;
|
||||
+
|
||||
+ if (((dev != 0) && (dev != 3)) || (func > 2))
|
||||
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
+
|
||||
+ /* Select Configuration access */
|
||||
+ local_irq_save(flags);
|
||||
+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL);
|
||||
+ mb();
|
||||
+
|
||||
+ addr = (u32) configspace + (1 << (13 + dev)) + (func << 8) + where;
|
||||
+ if (size == 1)
|
||||
+ addr ^= 0x3;
|
||||
+ else if (size == 2)
|
||||
+ addr ^= 0x2;
|
||||
+
|
||||
+ if (write) {
|
||||
+ value = *ptr;
|
||||
+ if (size == 1)
|
||||
+ err = put_dbe(value, (u8 *) addr);
|
||||
+ else if (size == 2)
|
||||
+ err = put_dbe(value, (u16 *) addr);
|
||||
+ else if (size == 4)
|
||||
+ err = put_dbe(value, (u32 *) addr);
|
||||
+ } else {
|
||||
+ if (size == 1)
|
||||
+ err = get_dbe(value, (u8 *) addr);
|
||||
+ else if (size == 2)
|
||||
+ err = get_dbe(value, (u16 *) addr);
|
||||
+ else if (size == 4)
|
||||
+ err = get_dbe(value, (u32 *) addr);
|
||||
+ if (err)
|
||||
+ *ptr = 0xffffffff;
|
||||
+ else
|
||||
+ *ptr = value;
|
||||
+ }
|
||||
+
|
||||
+ /* Select Memory access */
|
||||
+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0);
|
||||
+ local_irq_restore(flags);
|
||||
+
|
||||
+ return (err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL);
|
||||
+}
|
||||
+
|
||||
+static int ar231x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * value)
|
||||
+{
|
||||
+ return config_access(devfn, where, size, value, 0);
|
||||
+}
|
||||
+
|
||||
+static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
|
||||
+{
|
||||
+ return config_access(devfn, where, size, &value, 1);
|
||||
+}
|
||||
+
|
||||
+struct pci_ops ar231x_pci_ops = {
|
||||
+ .read = ar231x_pci_read,
|
||||
+ .write = ar231x_pci_write,
|
||||
+};
|
||||
+
|
||||
+static struct resource ar231x_mem_resource = {
|
||||
+ .name = "AR531x PCI MEM",
|
||||
+ .start = AR531X_MEM_BASE,
|
||||
+ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1 + 0x4000000,
|
||||
+ .flags = IORESOURCE_MEM,
|
||||
+};
|
||||
+
|
||||
+static struct resource ar231x_io_resource = {
|
||||
+ .name = "AR531x PCI I/O",
|
||||
+ .start = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE,
|
||||
+ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - 1,
|
||||
+ .flags = IORESOURCE_IO,
|
||||
+};
|
||||
+
|
||||
+struct pci_controller ar231x_pci_controller = {
|
||||
+ .pci_ops = &ar231x_pci_ops,
|
||||
+ .mem_resource = &ar231x_mem_resource,
|
||||
+ .io_resource = &ar231x_io_resource,
|
||||
+ .mem_offset = 0x00000000UL,
|
||||
+ .io_offset = 0x00000000UL,
|
||||
+};
|
||||
+
|
||||
+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
+{
|
||||
+ return AR2315_IRQ_LCBUS_PCI;
|
||||
+}
|
||||
+
|
||||
+int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||
+{
|
||||
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5);
|
||||
+ pci_write_config_word(dev, 0x40, 0);
|
||||
+
|
||||
+ /* Clear any pending Abort or external Interrupts
|
||||
+ * and enable interrupt processing */
|
||||
+ ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0);
|
||||
+ ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT));
|
||||
+ ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT));
|
||||
+ ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+ar2315_pci_fixup(struct pci_dev *dev)
|
||||
+{
|
||||
+ unsigned int devfn = dev->devfn;
|
||||
+
|
||||
+ if (dev->bus->number != 0)
|
||||
+ return;
|
||||
+
|
||||
+ /* Only fix up the PCI host settings */
|
||||
+ if ((PCI_SLOT(devfn) != 3) || (PCI_FUNC(devfn) != 0))
|
||||
+ return;
|
||||
+
|
||||
+ /* Fix up MBARs */
|
||||
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0);
|
||||
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1);
|
||||
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2);
|
||||
+ pci_write_config_dword(dev, PCI_COMMAND,
|
||||
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
|
||||
+ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
|
||||
+ PCI_COMMAND_FAST_BACK);
|
||||
+}
|
||||
+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup);
|
||||
+
|
||||
+static int __init
|
||||
+ar2315_pci_init(void)
|
||||
+{
|
||||
+ u32 reg;
|
||||
+
|
||||
+ if (!IS_2315())
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ configspace = (unsigned long) ioremap_nocache(0x80000000, 1*1024*1024); /* Remap PCI config space */
|
||||
+ ar231x_pci_controller.io_map_base =
|
||||
+ (unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_MEM_SIZE, AR531X_IO_SIZE);
|
||||
+ set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space */
|
||||
+
|
||||
+ reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
|
||||
+ msleep(10);
|
||||
+
|
||||
+ reg &= ~AR2315_RESET_PCIDMA;
|
||||
+ ar231x_write_reg(AR2315_RESET, reg);
|
||||
+ msleep(10);
|
||||
+
|
||||
+ ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
|
||||
+ AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
|
||||
+
|
||||
+ ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
|
||||
+ (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S));
|
||||
+ ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
|
||||
+ ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK,
|
||||
+ AR2315_IF_PCI | AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
|
||||
+ (AR2315_IF_PCI_CLK_OUTPUT_CLK << AR2315_IF_PCI_CLK_SHIFT));
|
||||
+
|
||||
+ /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
|
||||
+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
|
||||
+ AR2315_PCIRST_LOW);
|
||||
+ msleep(100);
|
||||
+
|
||||
+ /* Bring the PCI out of reset */
|
||||
+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
|
||||
+ AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
|
||||
+
|
||||
+ ar231x_write_reg(AR2315_PCI_UNCACHE_CFG,
|
||||
+ 0x1E | /* 1GB uncached */
|
||||
+ (1 << 5) | /* Enable uncached */
|
||||
+ (0x2 << 30) /* Base: 0x80000000 */
|
||||
+ );
|
||||
+ ar231x_read_reg(AR2315_PCI_UNCACHE_CFG);
|
||||
+
|
||||
+ msleep(500);
|
||||
+
|
||||
+ /* dirty hack - anyone with a datasheet that knows the memory map ? */
|
||||
+ ioport_resource.start = 0x10000000;
|
||||
+ ioport_resource.end = 0xffffffff;
|
||||
+ iomem_resource.start = 0x10000000;
|
||||
+ iomem_resource.end = 0xffffffff;
|
||||
+
|
||||
+ register_pci_controller(&ar231x_pci_controller);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+arch_initcall(ar2315_pci_init);
|
||||
--- a/arch/mips/ar231x/Kconfig
|
||||
+++ b/arch/mips/ar231x/Kconfig
|
||||
@@ -15,3 +15,13 @@ config ATHEROS_AR2315
|
||||
select SYS_SUPPORTS_BIG_ENDIAN
|
||||
select GENERIC_GPIO
|
||||
default y
|
||||
+
|
||||
+config ATHEROS_AR2315_PCI
|
||||
+ bool "PCI support"
|
||||
+ depends on ATHEROS_AR2315
|
||||
+ select HW_HAS_PCI
|
||||
+ select PCI
|
||||
+ select USB_ARCH_HAS_HCD
|
||||
+ select USB_ARCH_HAS_OHCI
|
||||
+ select USB_ARCH_HAS_EHCI
|
||||
+ default y
|
||||
--- a/arch/mips/ar231x/ar2315.c
|
||||
+++ b/arch/mips/ar231x/ar2315.c
|
||||
@@ -61,6 +61,27 @@ static inline void ar2315_gpio_irq(void)
|
||||
do_IRQ(AR531X_GPIO_IRQ_BASE + fls(pend) - 1);
|
||||
}
|
||||
|
||||
+#ifdef CONFIG_ATHEROS_AR2315_PCI
|
||||
+static inline void pci_abort_irq(void)
|
||||
+{
|
||||
+ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_ABORT_INT);
|
||||
+}
|
||||
+
|
||||
+static inline void pci_ack_irq(void)
|
||||
+{
|
||||
+ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT);
|
||||
+}
|
||||
+
|
||||
+void ar2315_pci_irq(int irq)
|
||||
+{
|
||||
+ if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT)
|
||||
+ pci_abort_irq();
|
||||
+ else {
|
||||
+ do_IRQ(irq);
|
||||
+ pci_ack_irq();
|
||||
+ }
|
||||
+}
|
||||
+#endif /* CONFIG_ATHEROS_AR2315_PCI */
|
||||
|
||||
/*
|
||||
* Called when an interrupt is received, this function
|
||||
@@ -79,6 +100,10 @@ ar2315_irq_dispatch(void)
|
||||
do_IRQ(AR2315_IRQ_WLAN0_INTRS);
|
||||
else if (pending & CAUSEF_IP4)
|
||||
do_IRQ(AR2315_IRQ_ENET0_INTRS);
|
||||
+#ifdef CONFIG_ATHEROS_AR2315_PCI
|
||||
+ else if (pending & CAUSEF_IP5)
|
||||
+ ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI);
|
||||
+#endif
|
||||
else if (pending & CAUSEF_IP2) {
|
||||
unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR);
|
||||
|
||||
Loading…
Reference in a new issue