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AR7: IRQ handlng cleanup

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SVN-Revision: 8743
This commit is contained in:
Eugene Konev 2007-09-11 13:07:52 +00:00
parent 042186d5ab
commit 65235a2bb9
1 changed files with 77 additions and 93 deletions
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154
target/linux/ar7/files/arch/mips/ar7/irq.c
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@ -18,11 +18,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <linux/init.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/ioport.h> #include <linux/io.h>
#include <asm/irq.h>
#include <asm/irq_cpu.h> #include <asm/irq_cpu.h>
#include <asm/mipsregs.h> #include <asm/mipsregs.h>
#include <asm/ar7/ar7.h> #include <asm/ar7/ar7.h>
@ -45,76 +43,75 @@
#define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */ #define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */
#define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */ #define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */
#define REG(addr) (*(volatile u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr)) #define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr))
#define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4)) #define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4))
static void ar7_unmask_irq(unsigned int irq_nr); static void ar7_unmask_irq(unsigned int irq_nr);
static void ar7_mask_irq(unsigned int irq_nr); static void ar7_mask_irq(unsigned int irq_nr);
static void ar7_unmask_secondary_irq(unsigned int irq_nr); static void ar7_ack_irq(unsigned int irq_nr);
static void ar7_mask_secondary_irq(unsigned int irq_nr); static void ar7_unmask_sec_irq(unsigned int irq_nr);
static irqreturn_t ar7_cascade(int interrupt, void *dev); static void ar7_mask_sec_irq(unsigned int irq_nr);
static irqreturn_t ar7_secondary_cascade(int interrupt, void *dev); static void ar7_ack_sec_irq(unsigned int irq_nr);
static void ar7_cascade(void);
static void ar7_irq_init(int base); static void ar7_irq_init(int base);
static int ar7_irq_base; static int ar7_irq_base;
static struct irq_chip ar7_irq_type = { static struct irq_chip ar7_irq_type = {
.typename = "AR7",
.name = "AR7", .name = "AR7",
.unmask = ar7_unmask_irq, .unmask = ar7_unmask_irq,
.mask = ar7_mask_irq, .mask = ar7_mask_irq,
.ack = ar7_ack_irq
}; };
static struct irq_chip ar7_secondary_irq_type = { static struct irq_chip ar7_sec_irq_type = {
.name = "AR7", .name = "AR7",
.unmask = ar7_unmask_secondary_irq, .unmask = ar7_unmask_sec_irq,
.mask = ar7_mask_secondary_irq, .mask = ar7_mask_sec_irq,
.ack = ar7_ack_sec_irq,
}; };
static struct irqaction ar7_cascade_action = { static struct irqaction ar7_cascade_action = {
.handler = ar7_cascade, .handler = no_action,
.name = "AR7 cascade interrupt" .name = "AR7 cascade interrupt"
}; };
static struct irqaction ar7_secondary_cascade_action = { static struct irqaction ar7_sec_cascade_action = {
.handler = ar7_secondary_cascade, .handler = no_action,
.name = "AR7 secondary cascade interrupt" .name = "AR7 secondary cascade interrupt"
}; };
static void ar7_unmask_irq(unsigned int irq) static void ar7_unmask_irq(unsigned int irq)
{ {
unsigned long flags; writel(1 << ((irq - ar7_irq_base) % 32),
local_irq_save(flags); REG(ESR_OFFSET(irq - ar7_irq_base)));
/* enable the interrupt channel bit */
REG(ESR_OFFSET(irq)) = 1 << ((irq - ar7_irq_base) % 32);
local_irq_restore(flags);
} }
static void ar7_mask_irq(unsigned int irq) static void ar7_mask_irq(unsigned int irq)
{ {
unsigned long flags; writel(1 << ((irq - ar7_irq_base) % 32),
local_irq_save(flags); REG(ECR_OFFSET(irq - ar7_irq_base)));
/* disable the interrupt channel bit */
REG(ECR_OFFSET(irq)) = 1 << ((irq - ar7_irq_base) % 32);
local_irq_restore(flags);
} }
static void ar7_unmask_secondary_irq(unsigned int irq) static void ar7_ack_irq(unsigned int irq)
{ {
unsigned long flags; writel(1 << ((irq - ar7_irq_base) % 32),
local_irq_save(flags); REG(CR_OFFSET(irq - ar7_irq_base)));
/* enable the interrupt channel bit */
REG(SEC_ESR_OFFSET) = 1 << (irq - ar7_irq_base - 40);
local_irq_restore(flags);
} }
static void ar7_mask_secondary_irq(unsigned int irq) static void ar7_unmask_sec_irq(unsigned int irq)
{ {
unsigned long flags; writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET));
local_irq_save(flags); }
/* disable the interrupt channel bit */
REG(SEC_ECR_OFFSET) = 1 << (irq - ar7_irq_base - 40); static void ar7_mask_sec_irq(unsigned int irq)
local_irq_restore(flags); {
writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET));
}
static void ar7_ack_sec_irq(unsigned int irq)
{
writel(1 << (irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET));
} }
void __init arch_init_irq(void) { void __init arch_init_irq(void) {
@ -126,80 +123,67 @@ static void __init ar7_irq_init(int base)
{ {
int i; int i;
/* /*
Disable interrupts and clear pending * Disable interrupts and clear pending
*/ */
REG(ECR_OFFSET(0)) = 0xffffffff; writel(0xffffffff, REG(ECR_OFFSET(0)));
REG(ECR_OFFSET(32)) = 0xff; writel(0xff, REG(ECR_OFFSET(32)));
REG(SEC_ECR_OFFSET) = 0xffffffff; writel(0xffffffff, REG(SEC_ECR_OFFSET));
REG(CR_OFFSET(0)) = 0xffffffff; writel(0xffffffff, REG(CR_OFFSET(0)));
REG(CR_OFFSET(32)) = 0xff; writel(0xff, REG(CR_OFFSET(32)));
REG(SEC_CR_OFFSET) = 0xffffffff; writel(0xffffffff, REG(SEC_CR_OFFSET));
ar7_irq_base = base; ar7_irq_base = base;
for (i = 0; i < 40; i++) { for (i = 0; i < 40; i++) {
REG(CHNL_OFFSET(i)) = i; writel(i, REG(CHNL_OFFSET(i)));
/* Primary IRQ's */ /* Primary IRQ's */
irq_desc[i + base].status = IRQ_DISABLED; set_irq_chip_and_handler(base + i, &ar7_irq_type,
irq_desc[i + base].action = NULL; handle_level_irq);
irq_desc[i + base].depth = 1;
irq_desc[i + base].chip = &ar7_irq_type;
/* Secondary IRQ's */ /* Secondary IRQ's */
if (i < 32) { if (i < 32)
irq_desc[i + base + 40].status = IRQ_DISABLED; set_irq_chip_and_handler(base + i + 40,
irq_desc[i + base + 40].action = NULL; &ar7_sec_irq_type,
irq_desc[i + base + 40].depth = 1; handle_level_irq);
irq_desc[i + base + 40].chip = &ar7_secondary_irq_type;
}
} }
setup_irq(2, &ar7_cascade_action); setup_irq(2, &ar7_cascade_action);
setup_irq(ar7_irq_base, &ar7_secondary_cascade_action); setup_irq(ar7_irq_base, &ar7_sec_cascade_action);
set_c0_status(IE_IRQ0); set_c0_status(IE_IRQ0);
} }
static irqreturn_t ar7_cascade(int interrupt, void *dev) static void ar7_cascade(void)
{ {
int irq; u32 status;
int i, irq;
irq = (REG(PIR_OFFSET) & 0x3F); /* Primary IRQ's */
REG(CR_OFFSET(irq)) = 1 << (irq % 32); irq = readl(REG(PIR_OFFSET)) & 0x3f;
if (irq) {
do_IRQ(irq + ar7_irq_base); do_IRQ(ar7_irq_base + irq);
return;
return IRQ_HANDLED;
} }
static irqreturn_t ar7_secondary_cascade(int interrupt, void *dev) /* Secondary IRQ's are cascaded through primary '0' */
{ writel(1, REG(CR_OFFSET(irq)));
int irq = 0, i; status = readl(REG(SEC_SR_OFFSET));
unsigned long status; for (i = 0; i < 32; i++) {
if (status & 1) {
do_IRQ(ar7_irq_base + i + 40);
return;
}
status >>= 1;
}
status = REG(SEC_SR_OFFSET);
if (unlikely(!status)) {
spurious_interrupt(); spurious_interrupt();
return IRQ_NONE;
}
for (i = 0; i < 32; i++)
if (status & (i << 1)) {
irq = i + 40;
REG(SEC_CR_OFFSET) = 1 << i;
break;
}
do_IRQ(irq + ar7_irq_base);
return IRQ_HANDLED;
} }
asmlinkage void plat_irq_dispatch(void) asmlinkage void plat_irq_dispatch(void)
{ {
unsigned int pending = read_c0_status() & read_c0_cause(); unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & STATUSF_IP7) /* cpu timer */ if (pending & STATUSF_IP7) /* cpu timer */
do_IRQ(7); do_IRQ(7);
else if (pending & STATUSF_IP2) /* int0 hardware line */ else if (pending & STATUSF_IP2) /* int0 hardware line */
do_IRQ(2); ar7_cascade();
else else
spurious_interrupt(); spurious_interrupt();
} }