atheros: parenthesis around complex macroses value
Use parenthesis around complex macroses value as suggested by checkpatch. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> SVN-Revision: 41082
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2 changed files with 31 additions and 31 deletions
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@ -726,11 +726,11 @@
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+/*
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+ * IRQs
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+ */
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+#define AR2315_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
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+#define AR2315_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
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+#define AR2315_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
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+#define AR2315_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
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+#define AR2315_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
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+#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
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+#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
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+#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
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+#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
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+#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
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+
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+/*
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+ * Address map
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@ -1309,11 +1309,11 @@
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+ * IRQs
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+ */
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+
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+#define AR5312_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
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+#define AR5312_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
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+#define AR5312_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
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+#define AR5312_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
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+#define AR5312_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
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+#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
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+#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
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+#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
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+#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
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+#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
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+
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+
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+/* Address Map */
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@ -1403,14 +1403,14 @@
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+#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */
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+
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+#define AR531X_RESET_WMAC0_BITS \
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+ AR531X_RESET_WLAN0 |\
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+ AR531X_RESET_WARM_WLAN0_MAC |\
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+ AR531X_RESET_WARM_WLAN0_BB
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+ (AR531X_RESET_WLAN0 |\
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+ AR531X_RESET_WARM_WLAN0_MAC |\
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+ AR531X_RESET_WARM_WLAN0_BB)
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+
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+#define AR531X_RESERT_WMAC1_BITS \
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+ AR531X_RESET_WLAN1 |\
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+ AR531X_RESET_WARM_WLAN1_MAC |\
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+ AR531X_RESET_WARM_WLAN1_BB
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+ (AR531X_RESET_WLAN1 |\
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+ AR531X_RESET_WARM_WLAN1_MAC |\
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+ AR531X_RESET_WARM_WLAN1_BB)
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+
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+/* AR5312_CLOCKCTL1 register bit field definitions */
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+#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
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@ -2894,25 +2894,25 @@
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+#define AR531X_GPIO_IRQ_BASE 0x30
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+
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+/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
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+#define AR531X_IRQ_NONE MIPS_CPU_IRQ_BASE+0
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+#define AR531X_IRQ_CPU_CLOCK MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */
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+#define AR531X_IRQ_NONE (MIPS_CPU_IRQ_BASE+0)
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+#define AR531X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
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+
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+/* Miscellaneous interrupts, which share IP6 */
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+#define AR531X_MISC_IRQ_NONE AR531X_MISC_IRQ_BASE+0
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+#define AR531X_MISC_IRQ_TIMER AR531X_MISC_IRQ_BASE+1
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+#define AR531X_MISC_IRQ_AHB_PROC AR531X_MISC_IRQ_BASE+2
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+#define AR531X_MISC_IRQ_AHB_DMA AR531X_MISC_IRQ_BASE+3
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+#define AR531X_MISC_IRQ_GPIO AR531X_MISC_IRQ_BASE+4
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+#define AR531X_MISC_IRQ_UART0 AR531X_MISC_IRQ_BASE+5
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+#define AR531X_MISC_IRQ_UART0_DMA AR531X_MISC_IRQ_BASE+6
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+#define AR531X_MISC_IRQ_WATCHDOG AR531X_MISC_IRQ_BASE+7
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+#define AR531X_MISC_IRQ_LOCAL AR531X_MISC_IRQ_BASE+8
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+#define AR531X_MISC_IRQ_SPI AR531X_MISC_IRQ_BASE+9
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+#define AR531X_MISC_IRQ_NONE (AR531X_MISC_IRQ_BASE+0)
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+#define AR531X_MISC_IRQ_TIMER (AR531X_MISC_IRQ_BASE+1)
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+#define AR531X_MISC_IRQ_AHB_PROC (AR531X_MISC_IRQ_BASE+2)
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+#define AR531X_MISC_IRQ_AHB_DMA (AR531X_MISC_IRQ_BASE+3)
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+#define AR531X_MISC_IRQ_GPIO (AR531X_MISC_IRQ_BASE+4)
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+#define AR531X_MISC_IRQ_UART0 (AR531X_MISC_IRQ_BASE+5)
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+#define AR531X_MISC_IRQ_UART0_DMA (AR531X_MISC_IRQ_BASE+6)
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+#define AR531X_MISC_IRQ_WATCHDOG (AR531X_MISC_IRQ_BASE+7)
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+#define AR531X_MISC_IRQ_LOCAL (AR531X_MISC_IRQ_BASE+8)
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+#define AR531X_MISC_IRQ_SPI (AR531X_MISC_IRQ_BASE+9)
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+#define AR531X_MISC_IRQ_COUNT 10
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+
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+/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
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+#define AR531X_GPIO_IRQ_NONE AR531X_GPIO_IRQ_BASE+0
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+#define AR531X_GPIO_IRQ(n) AR531X_GPIO_IRQ_BASE+n
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+#define AR531X_GPIO_IRQ_NONE (AR531X_GPIO_IRQ_BASE+0)
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+#define AR531X_GPIO_IRQ(n) (AR531X_GPIO_IRQ_BASE+n)
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+#define AR531X_GPIO_IRQ_COUNT 22
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+
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+static inline u32
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@ -41,7 +41,7 @@
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+#include <ar231x.h>
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+
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+#define CLOCK_RATE 40000000
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+#define HEARTBEAT(x) (x < 1 || x > 90)?(20):(x)
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+#define HEARTBEAT(x) (x < 1 || x > 90 ? 20 : x)
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+
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+static int wdt_timeout = 20;
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+static int started = 0;
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