fix SPI register definitions
SVN-Revision: 14048
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5905a48169
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5ce93c07a5
1 changed files with 56 additions and 18 deletions
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@ -756,20 +756,64 @@
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* _REG relative to RSET_SPI
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*************************************************************************/
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#define SPI_MSG_CTL 0x00
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/* BCM 6338 SPI core */
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#define SPI_BCM_6338_SPI_CMD 0x00
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#define SPI_BCM_6338_SPI_INT_STATUS 0x02
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#define SPI_BCM_6338_SPI_MASK_INT_ST 0x03
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#define SPI_BCM_6338_SPI_INT_MASK 0x04
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#define SPI_BCM_6338_SPI_ST 0x05
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#define SPI_BCM_6338_SPI_CLK_CFG 0x06
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#define SPI_BCM_6338_SPI_FILL_BYTE 0x07
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#define SPI_BCM_6338_SPI_MSG_TAIL 0x09
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#define SPI_BCM_6338_SPI_RX_TAIL 0x0b
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#define SPI_BCM_6338_SPI_MSG_CTL 0x40
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#define SPI_BCM_6338_SPI_MSG_DATA 0x41
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#define SPI_BCM_6338_SPI_MSG_DATA_SIZE 0x3f
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#define SPI_BCM_6338_SPI_RX_DATA 0x80
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#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
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/* BCM 6348 SPI core */
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#define SPI_BCM_6348_SPI_CMD1 0x00
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#define SPI_BCM_6348_SPI_CMD2 0x04
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#define SPI_BCM_6348_SPI_TAIL 0x08
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#define SPI_BCM_6348_SPI_MSG_DATA 0x40
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#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
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#define SPI_BCM_6348_SPI_RX_DATA 0x80
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#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
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/* BCM 6358 SPI core */
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#define SPI_BCM_6358_MSG_CTL 0x00
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#define SPI_BCM_6358_SPI_MSG_DATA 0x02
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#define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
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#define SPI_BCM_6358_SPI_RX_FIFO 0x400
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#define SPI_BCM_6358_SPI_RX_FIFO_SIZE 0x220
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#define SPI_BCM_6358_SPI_CMD 0x700
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#define SPI_BCM_6358_SPI_INT_STATUS 0x702
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#define SPI_BCM_6358_SPI_MASK_INT_ST 0x703
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#define SPI_BCM_6358_SPI_INT_MASK 0x704
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#define SPI_BCM_6358_SPI_STATUS 0x705
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#define SPI_BCM_6358_SPI_CLK_CFG 0x706
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#define SPI_BCM_6358_SPI_FILL_BYTE 0x707
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#define SPI_BCM_6358_SPI_MSG_TAIL 0x709
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#define SPI_BCM_6358_SPI_RX_TAIL 0x70B
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/* Shared SPI definitions */
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/* Message configuration */
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#define SPI_FD_RW 0
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#define SPI_HD_W 1
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#define SPI_HD_R 2
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#define SPI_MSG_TYPE_SHIFT 14
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#define SPI_BYTE_CNT_SHIFT 0
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#define SPI_MSG_DATA 0x02
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#define SPI_MSG_DATA_SIZE 0x21e
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#define SPI_RX_FIFO 0x400
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#define SPI_RX_FIFO_SIZE 0x220
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#define SPI_CMD 0x700
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/* Command */
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#define SPI_CMD_NOOP 0
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#define SPI_CMD_SOFT_RESET 1
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#define SPI_CMD_HARD_RESET 2
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@ -785,10 +829,7 @@
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#define SPI_DEV_ID_2 2
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#define SPI_DEV_ID_3 3
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#define SPI_INT_STATUS 0x702
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#define SPI_MASK_INT_STATUS 0x703
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#define SPI_INT_MASK 0x704
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/* Interrupt mask */
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#define SPI_INTR_CMD_DONE 0x01
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#define SPI_INTR_RX_OVERFLOW 0x02
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#define SPI_INTR_TX_UNDERFLOW 0x04
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@ -796,12 +837,12 @@
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#define SPI_INTR_RX_UNDERFLOW 0x10
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#define SPI_INTR_CLEAR_ALL 0x1f
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#define SPI_STATUS 0x705
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/* Status */
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#define SPI_RX_EMPTY 0x02
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#define SPI_CMD_BUSY 0x04
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#define SPI_SERIAL_BUSY 0x08
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#define SPI_CLK_CFG 0x706
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/* Clock configuration */
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#define SPI_CLK_0_391MHZ 1
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#define SPI_CLK_0_781MHZ 2 /* default */
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#define SPI_CLK_1_563MHZ 3
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@ -813,8 +854,5 @@
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#define SPI_SSOFFTIME_SHIFT 3
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#define SPI_BYTE_SWAP 0x80
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#define SPI_FILL_BYTE 0x707
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#define SPI_MSG_TAIL 0x709
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#define SPI_RX_TAIL 0x70B
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#endif /* BCM63XX_REGS_H_ */
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