cns3xxx: move laguna.c changes out of patches, update it in files/
Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
parent
413eb04e1e
commit
58fbe07560
3 changed files with 64 additions and 133 deletions
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@ -21,6 +21,7 @@
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#include <linux/kernel.h>
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#include <linux/compiler.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/gpio.h>
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#include <linux/dma-mapping.h>
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#include <linux/serial_core.h>
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@ -864,7 +865,6 @@ static struct map_desc laguna_io_desc[] __initdata = {
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static void __init laguna_map_io(void)
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{
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cns3xxx_map_io();
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cns3xxx_pcie_iotable_init();
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iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
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laguna_early_serial_setup();
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}
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@ -888,14 +888,46 @@ static int laguna_register_gpio(struct gpio *array, size_t num)
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return ret;
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}
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static int __init laguna_pcie_init(void)
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/* allow disabling of external isolated PCIe IRQs */
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static int cns3xxx_pciextirq = 1;
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static int __init cns3xxx_pciextirq_disable(char *s)
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{
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cns3xxx_pciextirq = 0;
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return 1;
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}
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__setup("noextirq", cns3xxx_pciextirq_disable);
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static int __init laguna_pcie_init_irq(void)
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{
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u32 __iomem *mem = (void __iomem *)(CNS3XXX_GPIOB_BASE_VIRT + 0x0004);
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u32 reg = (__raw_readl(mem) >> 26) & 0xf;
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int irqs[] = {
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IRQ_CNS3XXX_EXTERNAL_PIN0,
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IRQ_CNS3XXX_EXTERNAL_PIN1,
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IRQ_CNS3XXX_EXTERNAL_PIN2,
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154,
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};
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if (!machine_is_gw2388())
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return 0;
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return cns3xxx_pcie_init();
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/* Verify GPIOB[26:29] == 0001b indicating support for ext irqs */
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if (cns3xxx_pciextirq && reg != 1)
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cns3xxx_pciextirq = 0;
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if (cns3xxx_pciextirq) {
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printk("laguna: using isolated PCI interrupts:"
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" irq%d/irq%d/irq%d/irq%d\n",
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irqs[0], irqs[1], irqs[2], irqs[3]);
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cns3xxx_pcie_set_irqs(0, irqs);
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} else {
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printk("laguna: using shared PCI interrupts: irq%d\n",
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IRQ_CNS3XXX_PCIE0_DEVICE);
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}
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return 0;
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}
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subsys_initcall(laguna_pcie_init);
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subsys_initcall(laguna_pcie_init_irq);
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static int __init laguna_model_setup(void)
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{
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@ -908,8 +940,33 @@ static int __init laguna_model_setup(void)
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printk("Running on Gateworks Laguna %s\n", laguna_info.model);
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cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
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NR_IRQS_CNS3XXX);
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cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
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NR_IRQS_CNS3XXX + 32);
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/*
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* If pcie external interrupts are supported and desired
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* configure IRQ types and configure pin function.
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* Note that cns3xxx_pciextirq is enabled by default, but can be
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* unset via the 'noextirq' kernel param or by laguna_pcie_init() if
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* the baseboard model does not support this hardware feature.
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*/
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if (cns3xxx_pciextirq) {
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mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0018);
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reg = __raw_readl(mem);
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/* GPIO26 is gpio, EXT_INT[0:2] not gpio func */
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reg &= ~0x3c000000;
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reg |= 0x38000000;
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__raw_writel(reg, mem);
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cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
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IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
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irq_set_irq_type(154, IRQ_TYPE_LEVEL_LOW);
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irq_set_irq_type(93, IRQ_TYPE_LEVEL_HIGH);
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irq_set_irq_type(94, IRQ_TYPE_LEVEL_HIGH);
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irq_set_irq_type(95, IRQ_TYPE_LEVEL_HIGH);
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} else {
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cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
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IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
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}
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if (strncmp(laguna_info.model, "GW", 2) == 0) {
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if (laguna_info.config_bitmap & ETH0_LOAD)
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@ -1099,5 +1156,6 @@ MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
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.init_irq = cns3xxx_init_irq,
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.init_time = cns3xxx_timer_init,
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.init_machine = laguna_init,
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.init_late = cns3xxx_pcie_init_late,
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.restart = cns3xxx_restart,
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MACHINE_END
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@ -1,33 +0,0 @@
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--- a/arch/arm/mach-cns3xxx/laguna.c
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+++ b/arch/arm/mach-cns3xxx/laguna.c
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@@ -864,7 +864,6 @@ static struct map_desc laguna_io_desc[]
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static void __init laguna_map_io(void)
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{
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cns3xxx_map_io();
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- cns3xxx_pcie_iotable_init();
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iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
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laguna_early_serial_setup();
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}
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@@ -888,15 +887,6 @@ static int laguna_register_gpio(struct g
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return ret;
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}
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-static int __init laguna_pcie_init(void)
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-{
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- if (!machine_is_gw2388())
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- return 0;
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-
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- return cns3xxx_pcie_init();
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-}
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-subsys_initcall(laguna_pcie_init);
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-
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static int __init laguna_model_setup(void)
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{
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u32 __iomem *mem;
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@@ -1099,5 +1089,6 @@ MACHINE_START(GW2388, "Gateworks Corpora
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.init_irq = cns3xxx_init_irq,
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.init_time = cns3xxx_timer_init,
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.init_machine = laguna_init,
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+ .init_late = cns3xxx_pcie_init_late,
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.restart = cns3xxx_restart,
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MACHINE_END
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@ -1,97 +1,3 @@
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--- a/arch/arm/mach-cns3xxx/laguna.c
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+++ b/arch/arm/mach-cns3xxx/laguna.c
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@@ -21,6 +21,7 @@
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#include <linux/kernel.h>
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#include <linux/compiler.h>
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#include <linux/io.h>
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+#include <linux/irq.h>
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#include <linux/gpio.h>
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#include <linux/dma-mapping.h>
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#include <linux/serial_core.h>
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@@ -887,6 +888,47 @@ static int laguna_register_gpio(struct g
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return ret;
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}
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+/* allow disabling of external isolated PCIe IRQs */
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+static int cns3xxx_pciextirq = 1;
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+static int __init cns3xxx_pciextirq_disable(char *s)
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+{
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+ cns3xxx_pciextirq = 0;
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+ return 1;
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+}
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+__setup("noextirq", cns3xxx_pciextirq_disable);
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+
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+static int __init laguna_pcie_init_irq(void)
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+{
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+ u32 __iomem *mem = (void __iomem *)(CNS3XXX_GPIOB_BASE_VIRT + 0x0004);
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+ u32 reg = (__raw_readl(mem) >> 26) & 0xf;
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+ int irqs[] = {
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+ IRQ_CNS3XXX_EXTERNAL_PIN0,
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+ IRQ_CNS3XXX_EXTERNAL_PIN1,
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+ IRQ_CNS3XXX_EXTERNAL_PIN2,
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+ 154,
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+ };
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+
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+ if (!machine_is_gw2388())
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+ return 0;
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+
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+ /* Verify GPIOB[26:29] == 0001b indicating support for ext irqs */
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+ if (cns3xxx_pciextirq && reg != 1)
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+ cns3xxx_pciextirq = 0;
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+
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+ if (cns3xxx_pciextirq) {
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+ printk("laguna: using isolated PCI interrupts:"
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+ " irq%d/irq%d/irq%d/irq%d\n",
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+ irqs[0], irqs[1], irqs[2], irqs[3]);
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+ cns3xxx_pcie_set_irqs(0, irqs);
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+ } else {
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+ printk("laguna: using shared PCI interrupts: irq%d\n",
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+ IRQ_CNS3XXX_PCIE0_DEVICE);
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+ }
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+
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+ return 0;
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+}
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+subsys_initcall(laguna_pcie_init_irq);
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+
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static int __init laguna_model_setup(void)
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{
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u32 __iomem *mem;
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@@ -898,8 +940,33 @@ static int __init laguna_model_setup(voi
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printk("Running on Gateworks Laguna %s\n", laguna_info.model);
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cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
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NR_IRQS_CNS3XXX);
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- cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
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- NR_IRQS_CNS3XXX + 32);
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+
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+ /*
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+ * If pcie external interrupts are supported and desired
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+ * configure IRQ types and configure pin function.
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+ * Note that cns3xxx_pciextirq is enabled by default, but can be
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+ * unset via the 'noextirq' kernel param or by laguna_pcie_init() if
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+ * the baseboard model does not support this hardware feature.
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+ */
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+ if (cns3xxx_pciextirq) {
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+ mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0018);
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+ reg = __raw_readl(mem);
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+ /* GPIO26 is gpio, EXT_INT[0:2] not gpio func */
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+ reg &= ~0x3c000000;
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+ reg |= 0x38000000;
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+ __raw_writel(reg, mem);
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+
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+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
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+ IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
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+
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+ irq_set_irq_type(154, IRQ_TYPE_LEVEL_LOW);
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+ irq_set_irq_type(93, IRQ_TYPE_LEVEL_HIGH);
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+ irq_set_irq_type(94, IRQ_TYPE_LEVEL_HIGH);
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+ irq_set_irq_type(95, IRQ_TYPE_LEVEL_HIGH);
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+ } else {
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+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
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+ IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
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+ }
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if (strncmp(laguna_info.model, "GW", 2) == 0) {
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if (laguna_info.config_bitmap & ETH0_LOAD)
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--- a/arch/arm/mach-cns3xxx/pcie.c
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+++ b/arch/arm/mach-cns3xxx/pcie.c
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@@ -18,6 +18,7 @@
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