add patches to support the advanced power management on Kirkwood socs
SVN-Revision: 16250
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132
target/linux/kirkwood/patches/003-gating.patch
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132
target/linux/kirkwood/patches/003-gating.patch
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From: Rabeeh Khoury <rabeeh@marvell.com>
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Date: Sun, 22 Mar 2009 15:30:32 +0000 (+0200)
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Subject: [ARM] Kirkwood: peripherals clock gating for power management
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X-Git-Url: http://git.marvell.com/?p=orion.git;a=commitdiff_plain;h=c0c3df02efed0e5dea9aa4d8313e06e1f68f2cb4;hp=039b97666e1335eac517c7d35a0fa1143af689f0
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[ARM] Kirkwood: peripherals clock gating for power management
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1. Enabling clock gating of unused peripherals
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2. PLL and PHY of the units are also disabled (when possible.
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Signed-off-by: Rabeeh Khoury <rabeeh@marvell.com>
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[ This needs to be revisited to make power handling dynamic and per device. -- Nico ]
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---
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--- a/arch/arm/mach-kirkwood/common.c
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+++ b/arch/arm/mach-kirkwood/common.c
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@@ -788,6 +788,38 @@ static void __init kirkwood_l2_init(void
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#endif
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}
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+void __init kirkwood_clock_gate(u32 reg)
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+{
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+ printk(KERN_INFO "Kirkwood: Gating clock using mask 0x%x\n", reg);
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+ /* First make sure that the units are accessible */
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+ writel(readl(CLOCK_GATING_CTRL) | reg, CLOCK_GATING_CTRL);
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+ /* For SATA first shutdown the phy */
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+ if (reg & CGC_SATA0) {
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+ /* Disable PLL and IVREF */
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+ writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
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+ /* Disable PHY */
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+ writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
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+ }
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+ if (reg & CGC_SATA1) {
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+ /* Disable PLL and IVREF */
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+ writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
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+ /* Disable PHY */
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+ writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
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+ }
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+ /* For PCI-E first shutdown the phy */
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+ if (reg & CGC_PEX0) {
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+ writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
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+ while (1) {
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+ if (readl(PCIE_STATUS) & 0x1)
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+ break;
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+ }
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+ writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
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+ }
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+ /* Now gate clock the required units */
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+ writel(readl(CLOCK_GATING_CTRL) & ~reg, CLOCK_GATING_CTRL);
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+ return;
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+}
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+
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void __init kirkwood_init(void)
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{
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printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
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--- a/arch/arm/mach-kirkwood/common.h
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+++ b/arch/arm/mach-kirkwood/common.h
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@@ -22,6 +22,7 @@ struct mvsdio_platform_data;
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void kirkwood_map_io(void);
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void kirkwood_init(void);
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void kirkwood_init_irq(void);
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+void __init kirkwood_clock_gate(u32 reg);
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extern struct mbus_dram_target_info kirkwood_mbus_dram_info;
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void kirkwood_setup_cpu_mbus(void);
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--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
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+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
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@@ -39,4 +39,20 @@
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#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128)
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#define L2_WRITETHROUGH 0x00000010
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+#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE | 0x11c)
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+#define CGC_GE0 0x1
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+#define CGC_PEX0 0x4
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+#define CGC_USB0 0x8
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+#define CGC_SDIO 0x10
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+#define CGC_TSU 0x20
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+#define CGC_NAND_SPI 0x80
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+#define CGC_XOR0 0x100
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+#define CGC_AUDIO 0x200
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+#define CGC_SATA0 0x4000
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+#define CGC_SATA1 0x8000
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+#define CGC_XOR1 0x10000
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+#define CGC_CRYPTO 0x20000
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+#define CGC_GE1 0x80000
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+#define CGC_TDM 0x100000
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+
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#endif
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--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
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+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
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@@ -64,6 +64,8 @@
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#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
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#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
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+#define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70)
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+#define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04)
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#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
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@@ -80,6 +82,11 @@
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#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
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#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
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+#define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x80000)
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+#define SATA0_IF_CTRL (SATA_VIRT_BASE | 0x2050)
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+#define SATA0_PHY_MODE_2 (SATA_VIRT_BASE | 0x2330)
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+#define SATA1_IF_CTRL (SATA_VIRT_BASE | 0x4050)
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+#define SATA1_PHY_MODE_2 (SATA_VIRT_BASE | 0x4330)
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#define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x90000)
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--- a/arch/arm/mach-kirkwood/sheevaplug-setup.c
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+++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c
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@@ -19,6 +19,7 @@
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <mach/kirkwood.h>
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+#include <mach/bridge-regs.h>
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#include <plat/mvsdio.h>
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#include <plat/orion_nand.h>
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#include "common.h"
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@@ -122,6 +123,8 @@ static void __init sheevaplug_init(void)
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platform_device_register(&sheevaplug_nand_flash);
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platform_device_register(&sheevaplug_leds);
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+ kirkwood_clock_gate(CGC_PEX0 | CGC_TSU | CGC_AUDIO | CGC_SATA0 |\
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+ CGC_SATA1 | CGC_CRYPTO | CGC_GE1 | CGC_TDM);
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}
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MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board")
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146
target/linux/kirkwood/patches/004-cpuidle.patch
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146
target/linux/kirkwood/patches/004-cpuidle.patch
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@ -0,0 +1,146 @@
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From: Rabeeh Khoury <rabeeh@marvell.com>
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Date: Tue, 24 Mar 2009 14:10:15 +0000 (+0200)
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Subject: [ARM] Kirkwood: CPU idle driver
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X-Git-Url: http://git.marvell.com/?p=orion.git;a=commitdiff_plain;h=039b97666e1335eac517c7d35a0fa1143af689f0;hp=56a50adda49b2020156616c4eb15353e0f9ad7de
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[ARM] Kirkwood: CPU idle driver
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The patch adds support for Kirkwood cpu idle.
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Two idle states are defined:
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1. Wait-for-interrupt (replacing default kirkwood wfi)
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2. Wait-for-interrupt and DDR self refresh
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Signed-off-by: Rabeeh Khoury <rabeeh@marvell.com>
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Signed-off-by: Nicolas Pitre <nico@marvell.com>
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---
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--- a/arch/arm/configs/kirkwood_defconfig
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+++ b/arch/arm/configs/kirkwood_defconfig
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@@ -270,7 +270,9 @@ CONFIG_CMDLINE=""
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#
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# CPU Power Management
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#
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-# CONFIG_CPU_IDLE is not set
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+CONFIG_CPU_IDLE=y
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+CONFIG_CPU_IDLE_GOV_LADDER=y
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+CONFIG_CPU_IDLE_GOV_MENU=y
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#
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# Floating point emulation
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--- a/arch/arm/mach-kirkwood/Makefile
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+++ b/arch/arm/mach-kirkwood/Makefile
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@@ -5,3 +5,5 @@ obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88
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obj-$(CONFIG_MACH_RD88F6281) += rd88f6281-setup.o
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obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o
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obj-$(CONFIG_MACH_TS219) += ts219-setup.o
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+
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+obj-$(CONFIG_CPU_IDLE) += cpuidle.o
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--- /dev/null
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+++ b/arch/arm/mach-kirkwood/cpuidle.c
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@@ -0,0 +1,96 @@
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+/*
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+ * arch/arm/mach-kirkwood/cpuidle.c
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+ *
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+ * CPU idle Marvell Kirkwood SoCs
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+ *
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+ * This file is licensed under the terms of the GNU General Public
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+ * License version 2. This program is licensed "as is" without any
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+ * warranty of any kind, whether express or implied.
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+ *
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+ * The cpu idle uses wait-for-interrupt and DDR self refresh in order
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+ * to implement two idle states -
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+ * #1 wait-for-interrupt
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+ * #2 wait-for-interrupt and DDR self refresh
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/platform_device.h>
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+#include <linux/cpuidle.h>
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+#include <asm/io.h>
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+#include <asm/proc-fns.h>
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+#include <mach/kirkwood.h>
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+
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+#define KIRKWOOD_MAX_STATES 2
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+
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+static struct cpuidle_driver kirkwood_idle_driver = {
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+ .name = "kirkwood_idle",
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+ .owner = THIS_MODULE,
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+};
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+
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+static DEFINE_PER_CPU(struct cpuidle_device, kirkwood_cpuidle_device);
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+
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+/* Actual code that puts the SoC in different idle states */
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+static int kirkwood_enter_idle(struct cpuidle_device *dev,
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+ struct cpuidle_state *state)
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+{
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+ struct timeval before, after;
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+ int idle_time;
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+
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+ local_irq_disable();
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+ do_gettimeofday(&before);
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+ if (state == &dev->states[0])
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+ /* Wait for interrupt state */
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+ cpu_do_idle();
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+ else if (state == &dev->states[1]) {
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+ /*
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+ * Following write will put DDR in self refresh.
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+ * Note that we have 256 cycles before DDR puts it
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+ * self in self-refresh, so the wait-for-interrupt
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+ * call afterwards won't get the DDR from self refresh
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+ * mode.
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+ */
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+ writel(0x7, DDR_OPERATION_BASE);
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+ cpu_do_idle();
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+ }
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+ do_gettimeofday(&after);
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+ local_irq_enable();
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+ idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
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+ (after.tv_usec - before.tv_usec);
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+ return idle_time;
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+}
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+
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+/* Initialize CPU idle by registering the idle states */
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+static int kirkwood_init_cpuidle(void)
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+{
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+ struct cpuidle_device *device;
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+
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+ cpuidle_register_driver(&kirkwood_idle_driver);
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+
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+ device = &per_cpu(kirkwood_cpuidle_device, smp_processor_id());
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+ device->state_count = KIRKWOOD_MAX_STATES;
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+
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+ /* Wait for interrupt state */
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+ device->states[0].enter = kirkwood_enter_idle;
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+ device->states[0].exit_latency = 1;
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+ device->states[0].target_residency = 10000;
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+ device->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
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+ strcpy(device->states[0].name, "WFI");
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+ strcpy(device->states[0].desc, "Wait for interrupt");
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+
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+ /* Wait for interrupt and DDR self refresh state */
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+ device->states[1].enter = kirkwood_enter_idle;
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+ device->states[1].exit_latency = 10;
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+ device->states[1].target_residency = 10000;
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+ device->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
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+ strcpy(device->states[1].name, "DDR SR");
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+ strcpy(device->states[1].desc, "WFI and DDR Self Refresh");
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+
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+ if (cpuidle_register_device(device)) {
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+ printk(KERN_ERR "kirkwood_init_cpuidle: Failed registering\n");
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+ return -EIO;
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+ }
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+ return 0;
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+}
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+
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+device_initcall(kirkwood_init_cpuidle);
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--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
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+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
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@@ -48,6 +48,7 @@
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*/
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#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
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#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE | 0x1500)
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+#define DDR_OPERATION_BASE (DDR_VIRT_BASE | 0x1418)
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#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x10000)
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#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
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