ar71xx: rework chipidea controller support, add QCA9531
Rework (again) platform support for dual-role chipidea USB controller:
- include support for QCA9531
- use correct EHCI block size
- drop ar933x_usb_setup_ctrl_config() function
- simplify code after previous "register chipidea only in device mode"
change (fa22714181)
Reworked patch was tested on devices with below QCA WiSOCs (signal/GPIO
name with required bootstrap state for USB bus 0 in device mode):
- AR9331 (GPIO13 pull-down)
- AR9342 (RGMII_TXD1/ETXD1 pull-up)
- AR9344 (GPIO20 pull-up)
- QCA9531 (GPIO13 pull-up)
- QCA9558 (GPIO13 pull-up)
The only way to select device mode for bus 0 is to change SOC bootstrap
configuration which is sampled only once, at hard reset. Likely, other
models, like QCA9556 or AR9341, should also support dual-role USB mode
but they were not tested.
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
This commit is contained in:
Piotr Dymacz
parent
10ea53f900
commit
57c641ba6e
1 changed files with 31 additions and 39 deletions
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@ -29,48 +29,35 @@
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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@@ -170,6 +173,64 @@ static void __init ar913x_usb_setup(void
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@@ -170,6 +173,44 @@ static void __init ar913x_usb_setup(void
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&ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
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}
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+static void __init ar933x_usb_setup_ctrl_config(void)
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+{
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+ void __iomem *usb_ctrl_base, *usb_config_reg;
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+ u32 usb_config;
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+
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+ usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE);
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+ usb_config_reg = usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG;
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+ usb_config = __raw_readl(usb_config_reg);
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+ usb_config &= ~AR933X_USB_CONFIG_HOST_ONLY;
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+ __raw_writel(usb_config, usb_config_reg);
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+ iounmap(usb_ctrl_base);
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+}
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+
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+static void __init ar9xxx_ci_usb_setup(int irq)
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+static void __init ar9xxx_ci_usb_setup(int bus_id, int irq)
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+{
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+ struct ci_hdrc_platform_data ci_pdata;
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+ enum usb_dr_mode dr_mode;
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+ bool host_mode = true;
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+
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+ if (soc_is_ar933x())
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+ host_mode = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP) &
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+ AR933X_BOOTSTRAP_USB_MODE_HOST;
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+ else if (soc_is_ar934x() || soc_is_qca955x())
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+ else
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+ host_mode = !(ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP) &
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+ AR934X_BOOTSTRAP_USB_MODE_DEVICE);
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+
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+ if (host_mode) {
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+ dr_mode = USB_DR_MODE_HOST;
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+ } else {
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+ dr_mode = USB_DR_MODE_PERIPHERAL;
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+ if (soc_is_ar933x())
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+ ar933x_usb_setup_ctrl_config();
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+ ath79_usb_register("ehci-platform", bus_id,
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+ AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
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+ irq, &ath79_ehci_pdata_v2,
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+ sizeof(ath79_ehci_pdata_v2));
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+
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+ return;
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+ }
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+
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+ memset(&ci_pdata, 0, sizeof(ci_pdata));
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+ ci_pdata.name = "ci_hdrc_ar9xxx";
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+ ci_pdata.capoffset = DEF_CAPOFFSET;
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+ ci_pdata.dr_mode = dr_mode;
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+ ci_pdata.dr_mode = USB_DR_MODE_PERIPHERAL;
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+ ci_pdata.flags = CI_HDRC_DUAL_ROLE_NOT_OTG | CI_HDRC_DP_ALWAYS_PULLUP;
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+ ci_pdata.vbus_extcon.edev = ERR_PTR(-ENODEV);
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+ ci_pdata.id_extcon.edev = ERR_PTR(-ENODEV);
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@ -79,22 +66,15 @@
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+ platform_device_register_simple("usb_phy_generic",
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+ PLATFORM_DEVID_AUTO, NULL, 0);
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+
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+ if (!host_mode)
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+ ath79_usb_register("ci_hdrc", -1,
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+ AR933X_EHCI_BASE, AR933X_EHCI_SIZE,
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+ irq, &ci_pdata, sizeof(ci_pdata));
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+ else
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+ ath79_usb_register("ehci-platform", -1,
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+ AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
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+ irq, &ath79_ehci_pdata_v2,
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+ sizeof(ath79_ehci_pdata_v2));
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+
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+ ath79_usb_register("ci_hdrc", -1,
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+ AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
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+ irq, &ci_pdata, sizeof(ci_pdata));
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+}
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+
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static void __init ar933x_usb_setup(void)
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{
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ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE);
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@@ -181,10 +242,7 @@ static void __init ar933x_usb_setup(void
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@@ -181,10 +222,7 @@ static void __init ar933x_usb_setup(void
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ath79_device_reset_clear(AR933X_RESET_USB_PHY);
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mdelay(10);
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@ -102,11 +82,11 @@
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- AR933X_EHCI_BASE, AR933X_EHCI_SIZE,
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- ATH79_CPU_IRQ(3),
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- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
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+ ar9xxx_ci_usb_setup(ATH79_CPU_IRQ(3));
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+ ar9xxx_ci_usb_setup(-1, ATH79_CPU_IRQ(3));
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}
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static void enable_tx_tx_idp_violation_fix(unsigned base)
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@@ -230,10 +288,7 @@ static void __init ar934x_usb_setup(void
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@@ -230,10 +268,7 @@ static void __init ar934x_usb_setup(void
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if (ath79_soc_rev >= 3)
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ath79_ehci_pdata_v2.reset_notifier = ar934x_usb_reset_notifier;
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@ -114,11 +94,23 @@
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- AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
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- ATH79_CPU_IRQ(3),
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- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
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+ ar9xxx_ci_usb_setup(ATH79_CPU_IRQ(3));
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+ ar9xxx_ci_usb_setup(-1, ATH79_CPU_IRQ(3));
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}
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static void __init qca953x_usb_setup(void)
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@@ -285,10 +340,7 @@ static void __init qca955x_usb_setup(voi
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@@ -254,10 +289,7 @@ static void __init qca953x_usb_setup(voi
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ath79_device_reset_clear(QCA953X_RESET_USB_HOST);
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udelay(1000);
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- ath79_usb_register("ehci-platform", -1,
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- QCA953X_EHCI_BASE, QCA953X_EHCI_SIZE,
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- ATH79_CPU_IRQ(3),
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- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
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+ ar9xxx_ci_usb_setup(-1, ATH79_CPU_IRQ(3));
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}
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static void qca955x_usb_reset_notifier(struct platform_device *pdev)
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@@ -285,10 +317,7 @@ static void __init qca955x_usb_setup(voi
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{
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ath79_ehci_pdata_v2.reset_notifier = qca955x_usb_reset_notifier;
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@ -126,7 +118,7 @@
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- QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
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- ATH79_IP3_IRQ(0),
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- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
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+ ar9xxx_ci_usb_setup(ATH79_IP3_IRQ(0));
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+ ar9xxx_ci_usb_setup(0, ATH79_IP3_IRQ(0));
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ath79_usb_register("ehci-platform", 1,
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QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE,
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