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Delete old brcm63xx files

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SVN-Revision: 13210
This commit is contained in:
Florian Fainelli 2008-11-15 11:21:42 +00:00
parent a30ed4d09d
commit 517e3d404c
47 changed files with 0 additions and 7502 deletions
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9
target/linux/brcm63xx/files/arch/mips/bcm963xx/Makefile
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#
# Makefile for the Broadcom BCM963xx SoC specific parts of the kernel
#
# Copyright (C) 2004 Broadcom Corporation
#
obj-y := irq.o prom.o setup.o time.o ser_init.o int-handler.o info.o wdt.o
SRCBASE := $(TOPDIR)
EXTRA_CFLAGS += -I$(SRCBASE)/include

102
target/linux/brcm63xx/files/arch/mips/bcm963xx/info.c
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/*
* $Id$
*
* Copyright (C) 2007 OpenWrt.org
* Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
* Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/types.h>
#include <linux/autoconf.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <asm/bootinfo.h>
#include <asm/addrspace.h>
#include <asm/string.h>
#include <asm/mach-bcm963xx/bootloaders.h>
static char *boot_loader_names[BOOT_LOADER_LAST+1] = {
[BOOT_LOADER_UNKNOWN] = "Unknown",
[BOOT_LOADER_CFE] = "CFE",
[BOOT_LOADER_REDBOOT] = "RedBoot",
[BOOT_LOADER_CFE2] = "CFEv2"
};
/* boot loaders specific definitions */
#define CFE_EPTSEAL 0x43464531 /* CFE1 is the magic number to recognize CFE from other bootloaders */
int boot_loader_type;
/*
* Boot loader detection routines
*/
static int __init detect_cfe(void)
{
/*
* This method only works, when we are booted directly from the CFE.
*/
uint32_t cfe_handle = (uint32_t) fw_arg0;
uint32_t cfe_a1_val = (uint32_t) fw_arg1;
uint32_t cfe_entry = (uint32_t) fw_arg2;
uint32_t cfe_seal = (uint32_t) fw_arg3;
/* Check for CFE by finding the CFE magic number */
if (cfe_seal != CFE_EPTSEAL)
/* We are not booted from CFE */
return 0;
/* cfe_a1_val must be 0, because only one CPU present in the ADM5120 SoC */
if (cfe_a1_val != 0)
return 0;
/* The cfe_handle, and the cfe_entry must be kernel mode addresses */
if ((cfe_handle < KSEG0) || (cfe_entry < KSEG0))
return 0;
return 1;
}
static int __init detect_redboot(void)
{
/* On Inventel Livebox, the boot loader is passed as a command line argument, check for it */
if (!strncmp(arcs_cmdline, "boot_loader=RedBoot", 19))
return 1;
return 0;
}
void __init detect_bootloader(void)
{
if (detect_cfe()) {
boot_loader_type = BOOT_LOADER_CFE;
}
if (detect_redboot()) {
boot_loader_type = BOOT_LOADER_REDBOOT;
}
else {
/* Some devices are using CFE, but it is not detected as is */
boot_loader_type = BOOT_LOADER_CFE2;
}
printk("Boot loader is : %s\n", boot_loader_names[boot_loader_type]);
}
void __init detect_board(void)
{
switch (boot_loader_type)
{
case BOOT_LOADER_CFE:
break;
case BOOT_LOADER_REDBOOT:
break;
default:
break;
}
}
EXPORT_SYMBOL(boot_loader_type);

59
target/linux/brcm63xx/files/arch/mips/bcm963xx/int-handler.S
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/*
<:copyright-gpl
Copyright 2002 Broadcom Corp. All Rights Reserved.
This program is free software; you can distribute it and/or modify it
under the terms of the GNU General Public License (Version 2) as
published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
:>
*/
/*
* Generic interrupt handler for Broadcom MIPS boards
*/
#include <linux/autoconf.h>
#include <asm/asm.h>
#include <asm/mipsregs.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>
/*
* MIPS IRQ Source
* -------- ------
* 0 Software (ignored)
* 1 Software (ignored)
* 2 Combined hardware interrupt (hw0)
* 3 Hardware
* 4 Hardware
* 5 Hardware
* 6 Hardware
* 7 R4k timer
*/
.text
.set noreorder
.set noat
.align 5
NESTED(brcmIRQ, PT_SIZE, sp)
SAVE_ALL
CLI
.set noreorder
.set at
jal plat_irq_dispatch
move a0, sp
j ret_from_irq
nop
END(brcmIRQ)

259
target/linux/brcm63xx/files/arch/mips/bcm963xx/irq.c
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@ -1,259 +0,0 @@
/*
<:copyright-gpl
Copyright 2002 Broadcom Corp. All Rights Reserved.
This program is free software; you can distribute it and/or modify it
under the terms of the GNU General Public License (Version 2) as
published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
:>
*/
/*
* Interrupt control functions for Broadcom 963xx MIPS boards
*/
#include <asm/atomic.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/signal.h>
#include <6348_map_part.h>
#include <6348_intr.h>
#include <bcm_map_part.h>
#include <bcm_intr.h>
static void irq_dispatch_int(void)
{
unsigned int pendingIrqs;
static unsigned int irqBit;
static unsigned int isrNumber = 31;
pendingIrqs = PERF->IrqStatus & PERF->IrqMask;
if (!pendingIrqs) {
return;
}
while (1) {
irqBit <<= 1;
isrNumber++;
if (isrNumber == 32) {
isrNumber = 0;
irqBit = 0x1;
}
if (pendingIrqs & irqBit) {
PERF->IrqMask &= ~irqBit; // mask
do_IRQ(isrNumber + INTERNAL_ISR_TABLE_OFFSET);
break;
}
}
}
static void irq_dispatch_ext(uint32 irq)
{
if (!(PERF->ExtIrqCfg & (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_MASK_SHFT)))) {
printk("**** Ext IRQ mask. Should not dispatch ****\n");
}
/* disable and clear interrupt in the controller */
PERF->ExtIrqCfg |= (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_CLEAR_SHFT));
PERF->ExtIrqCfg &= ~(1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_MASK_SHFT));
do_IRQ(irq);
}
//extern void brcm_timer_interrupt(struct pt_regs *regs);
asmlinkage void plat_irq_dispatch(void)
{
unsigned long cause;
cause = read_c0_status() & read_c0_cause() & ST0_IM;
if (cause & CAUSEF_IP7)
do_IRQ(7);
else if (cause & CAUSEF_IP2)
irq_dispatch_int();
else if (cause & CAUSEF_IP3)
irq_dispatch_ext(INTERRUPT_ID_EXTERNAL_0);
else if (cause & CAUSEF_IP4)
irq_dispatch_ext(INTERRUPT_ID_EXTERNAL_1);
else if (cause & CAUSEF_IP5)
irq_dispatch_ext(INTERRUPT_ID_EXTERNAL_2);
else if (cause & CAUSEF_IP6) {
irq_dispatch_ext(INTERRUPT_ID_EXTERNAL_3);
local_irq_disable();
}
}
void enable_brcm_irq(unsigned int irq)
{
unsigned long flags;
local_irq_save(flags);
if( irq >= INTERNAL_ISR_TABLE_OFFSET ) {
PERF->IrqMask |= (1 << (irq - INTERNAL_ISR_TABLE_OFFSET));
}
else if (irq >= INTERRUPT_ID_EXTERNAL_0 && irq <= INTERRUPT_ID_EXTERNAL_3) {
/* enable and clear interrupt in the controller */
PERF->ExtIrqCfg |= (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_CLEAR_SHFT));
PERF->ExtIrqCfg |= (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_MASK_SHFT));
}
local_irq_restore(flags);
}
void disable_brcm_irq(unsigned int irq)
{
unsigned long flags;
local_irq_save(flags);
if( irq >= INTERNAL_ISR_TABLE_OFFSET ) {
PERF->IrqMask &= ~(1 << (irq - INTERNAL_ISR_TABLE_OFFSET));
}
else if (irq >= INTERRUPT_ID_EXTERNAL_0 && irq <= INTERRUPT_ID_EXTERNAL_3) {
/* disable interrupt in the controller */
PERF->ExtIrqCfg &= ~(1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_MASK_SHFT));
}
local_irq_restore(flags);
}
void ack_brcm_irq(unsigned int irq)
{
/* Already done in brcm_irq_dispatch */
}
unsigned int startup_brcm_irq(unsigned int irq)
{
enable_brcm_irq(irq);
return 0; /* never anything pending */
}
unsigned int startup_brcm_none(unsigned int irq)
{
return 0;
}
void end_brcm_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_brcm_irq(irq);
}
void end_brcm_none(unsigned int irq)
{
}
static struct hw_interrupt_type brcm_irq_type = {
.typename = "MIPS",
.startup = startup_brcm_irq,
.shutdown = disable_brcm_irq,
.enable = enable_brcm_irq,
.disable = disable_brcm_irq,
.ack = ack_brcm_irq,
.end = end_brcm_irq,
.set_affinity = NULL
};
static struct hw_interrupt_type brcm_irq_no_end_type = {
.typename = "MIPS",
.startup = startup_brcm_none,
.shutdown = disable_brcm_irq,
.enable = enable_brcm_irq,
.disable = disable_brcm_irq,
.ack = ack_brcm_irq,
.end = end_brcm_none,
.set_affinity = NULL
};
void __init arch_init_irq(void)
{
int i;
clear_c0_status(ST0_BEV);
change_c0_status(ST0_IM, (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4));
for (i = 0; i < NR_IRQS; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
irq_desc[i].chip = &brcm_irq_type;
}
}
int request_external_irq(unsigned int irq,
FN_HANDLER handler,
unsigned long irqflags,
const char * devname,
void *dev_id)
{
unsigned long flags;
local_irq_save(flags);
PERF->ExtIrqCfg |= (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_CLEAR_SHFT)); // Clear
PERF->ExtIrqCfg &= ~(1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_MASK_SHFT)); // Mask
PERF->ExtIrqCfg &= ~(1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_INSENS_SHFT)); // Edge insesnsitive
PERF->ExtIrqCfg |= (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_LEVEL_SHFT)); // Level triggered
PERF->ExtIrqCfg &= ~(1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_SENSE_SHFT)); // Low level
local_irq_restore(flags);
return( request_irq(irq, handler, irqflags, devname, dev_id) );
}
/* VxWorks compatibility function(s). */
unsigned int BcmHalMapInterrupt(FN_HANDLER pfunc, unsigned int param,
unsigned int interruptId)
{
int nRet = -1;
char *devname;
devname = kmalloc(16, GFP_KERNEL);
if (devname)
sprintf( devname, "brcm_%d", interruptId );
/* Set the IRQ description to not automatically enable the interrupt at
* the end of an ISR. The driver that handles the interrupt must
* explicitly call BcmHalInterruptEnable or enable_brcm_irq. This behavior
* is consistent with interrupt handling on VxWorks.
*/
irq_desc[interruptId].chip = &brcm_irq_no_end_type;
if( interruptId >= INTERNAL_ISR_TABLE_OFFSET )
{
printk("BcmHalMapInterrupt : internal IRQ\n");
nRet = request_irq( interruptId, pfunc, IRQF_DISABLED, devname, (void *) param );
}
else if (interruptId >= INTERRUPT_ID_EXTERNAL_0 && interruptId <= INTERRUPT_ID_EXTERNAL_3)
{
printk("BcmHalMapInterrupt : external IRQ\n");
nRet = request_external_irq( interruptId, pfunc, IRQF_DISABLED, devname, (void *) param );
}
return( nRet );
}
EXPORT_SYMBOL(enable_brcm_irq);
EXPORT_SYMBOL(disable_brcm_irq);
EXPORT_SYMBOL(request_external_irq);
EXPORT_SYMBOL(BcmHalMapInterrupt);

67
target/linux/brcm63xx/files/arch/mips/bcm963xx/prom.c
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/*
Copyright 2004 Broadcom Corp. All Rights Reserved.
Copyright 2007 OpenWrt,org, Florian Fainelli <florian@openwrt.org>
This program is free software; you can distribute it and/or modify it
under the terms of the GNU General Public License (Version 2) as
published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
/*
* prom.c: PROM library initialization code.
*
*/
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/bootmem.h>
#include <linux/blkdev.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/cpu.h>
#include <asm/time.h>
#include <asm/mach-bcm963xx/bootloaders.h>
#include <asm/mach-bcm963xx/6348_map_part.h>
#include "../cfe/cfe_private.h"
extern void __init detect_bootloader(void);
extern void serial_init(void);
extern int boot_loader_type;
#define MACH_BCM MACH_BCM96348
const char *get_system_type(void)
{
return "Broadcom BCM963xx";
}
void __init prom_init(void)
{
serial_init();
printk("%s prom init\n", get_system_type() );
PERF->IrqMask = 0;
/* Detect the bootloader */
detect_bootloader();
/* Register 16MB RAM minus the ADSL SDRAM by default */
add_memory_region(0, (0x01000000 - ADSL_SDRAM_IMAGE_SIZE), BOOT_MEM_RAM);
}
void __init prom_free_prom_memory(void)
{
/* We do not have any memory to free */
}

181
target/linux/brcm63xx/files/arch/mips/bcm963xx/ser_init.c
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/*
<:copyright-gpl
Copyright 2004 Broadcom Corp. All Rights Reserved.
This program is free software; you can distribute it and/or modify it
under the terms of the GNU General Public License (Version 2) as
published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
:>
*/
/*
* Broadcom bcm63xx serial port initialization, also prepare for printk
* by registering with console_init
*
*/
#include <linux/autoconf.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/console.h>
#include <linux/sched.h>
#include <asm/addrspace.h>
#include <asm/irq.h>
#include <asm/reboot.h>
#include <asm/gdb-stub.h>
#include <asm/mc146818rtc.h>
#include <bcm_map_part.h>
#include <6348_map_part.h>
#include <board.h>
#define SER63XX_DEFAULT_BAUD 115200
#define BD_BCM63XX_TIMER_CLOCK_INPUT (FPERIPH)
#define stUart ((volatile Uart * const) UART_BASE)
// Transmit interrupts
#define TXINT (TXFIFOEMT | TXUNDERR | TXOVFERR)
// Receive interrupts
#define RXINT (RXFIFONE | RXOVFERR)
/* --------------------------------------------------------------------------
Name: serial_init
Purpose: Initalize the UART
-------------------------------------------------------------------------- */
void __init serial_init(void)
{
u32 tmpVal = SER63XX_DEFAULT_BAUD;
ULONG clockFreqHz;
#if defined(CONFIG_BCM96345)
// Make sure clock is ticking
PERF->blkEnables |= UART_CLK_EN;
#endif
/* Dissable channel's receiver and transmitter. */
stUart->control &= ~(BRGEN|TXEN|RXEN);
/*--------------------------------------------------------------------*/
/* Write the table value to the clock select register. */
/* DPullen - this is the equation to use: */
/* value = clockFreqHz / baud / 32-1; */
/* (snmod) Actually you should also take into account any necessary */
/* rounding. Divide by 16, look at lsb, if 0, divide by 2 */
/* and subtract 1. If 1, just divide by 2 */
/*--------------------------------------------------------------------*/
clockFreqHz = BD_BCM63XX_TIMER_CLOCK_INPUT;
tmpVal = (clockFreqHz / tmpVal) / 16;
if( tmpVal & 0x01 )
tmpVal /= 2; //Rounding up, so sub is already accounted for
else
tmpVal = (tmpVal / 2) - 1; // Rounding down so we must sub 1
stUart->baudword = tmpVal;
/* Finally, re-enable the transmitter and receiver. */
stUart->control |= (BRGEN|TXEN|RXEN);
stUart->config = (BITS8SYM | ONESTOP);
// Set the FIFO interrupt depth ... stUart->fifocfg = 0xAA;
stUart->fifoctl = RSTTXFIFOS | RSTRXFIFOS;
stUart->intMask = 0;
stUart->intMask = RXINT | TXINT;
}
/* prom_putc()
* Output a character to the UART
*/
void prom_putc(char c)
{
/* Wait for Tx uffer to empty */
while (! (READ16(stUart->intStatus) & TXFIFOEMT));
/* Send character */
stUart->Data = c;
}
/* prom_puts()
* Write a string to the UART
*/
void prom_puts(const char *s)
{
while (*s) {
if (*s == '\n') {
prom_putc('\r');
}
prom_putc(*s++);
}
}
/* prom_getc_nowait()
* Returns a character from the UART
* Returns -1 if no characters available or corrupted
*/
int prom_getc_nowait(void)
{
uint16 uStatus;
int cData = -1;
uStatus = READ16(stUart->intStatus);
if (uStatus & RXFIFONE) { /* Do we have a character? */
cData = READ16(stUart->Data) & 0xff; /* Read character */
if (uStatus & (RXFRAMERR | RXPARERR)) { /* If we got an error, throw it away */
cData = -1;
}
}
return cData;
}
/* prom_getc()
* Returns a charcter from the serial port
* Will block until it receives a valid character
*/
char prom_getc(void)
{
int cData = -1;
/* Loop until we get a valid character */
while(cData == -1) {
cData = prom_getc_nowait();
}
return (char) cData;
}
/* prom_testc()
* Returns 0 if no characters available
*/
int prom_testc(void)
{
uint16 uStatus;
uStatus = READ16(stUart->intStatus);
return (uStatus & RXFIFONE);
}
#if defined (CONFIG_REMOTE_DEBUG)
/* Prevent other code from writing to the serial port */
void _putc(char c) { }
void _puts(const char *ptr) { }
#else
/* Low level outputs call prom routines */
void _putc(char c) {
prom_putc(c);
}
void _puts(const char *ptr) {
prom_puts(ptr);
}
#endif

472
target/linux/brcm63xx/files/arch/mips/bcm963xx/setup.c
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@ -1,472 +0,0 @@
/*
<:copyright-gpl
Copyright 2002 Broadcom Corp. All Rights Reserved.
This program is free software; you can distribute it and/or modify it
under the terms of the GNU General Public License (Version 2) as
published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
:>
*/
/*
* Generic setup routines for Broadcom 963xx MIPS boards
*/
#include <linux/autoconf.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/kdev_t.h>
#include <linux/types.h>
#include <linux/console.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/bootmem.h>
#include <asm/addrspace.h>
#include <asm/bcache.h>
#include <asm/irq.h>
#include <asm/time.h>
#include <asm/reboot.h>
#include <asm/gdb-stub.h>
#include <asm/bootinfo.h>
#include <asm/cpu.h>
#include <asm/mach-bcm963xx/bootloaders.h>
extern void brcm_time_init(void);
extern int boot_loader_type;
#include <linux/pci.h>
#include <linux/delay.h>
#include <bcm_map_part.h>
#include <6348_map_part.h>
#include <bcmpci.h>
static volatile MpiRegisters * mpi = (MpiRegisters *)(MPI_BASE);
/* This function should be in a board specific directory. For now,
* assume that all boards that include this file use a Broadcom chip
* with a soft reset bit in the PLL control register.
*/
static void brcm_machine_restart(char *command)
{
const unsigned long ulSoftReset = 0x00000001;
unsigned long *pulPllCtrl = (unsigned long *) 0xfffe0008;
*pulPllCtrl |= ulSoftReset;
}
static void brcm_machine_halt(void)
{
printk("System halted\n");
while (1);
}
static void mpi_SetLocalPciConfigReg(uint32 reg, uint32 value)
{
/* write index then value */
mpi->pcicfgcntrl = PCI_CFG_REG_WRITE_EN + reg;;
mpi->pcicfgdata = value;
}
static uint32 mpi_GetLocalPciConfigReg(uint32 reg)
{
/* write index then get value */
mpi->pcicfgcntrl = PCI_CFG_REG_WRITE_EN + reg;;
return mpi->pcicfgdata;
}
/*
* mpi_ResetPcCard: Set/Reset the PcCard
*/
static void mpi_ResetPcCard(int cardtype, BOOL bReset)
{
if (cardtype == MPI_CARDTYPE_NONE) {
return;
}
if (cardtype == MPI_CARDTYPE_CARDBUS) {
bReset = ! bReset;
}
if (bReset) {
mpi->pcmcia_cntl1 = (mpi->pcmcia_cntl1 & ~PCCARD_CARD_RESET);
} else {
mpi->pcmcia_cntl1 = (mpi->pcmcia_cntl1 | PCCARD_CARD_RESET);
}
}
/*
* mpi_ConfigCs: Configure an MPI/EBI chip select
*/
static void mpi_ConfigCs(uint32 cs, uint32 base, uint32 size, uint32 flags)
{
mpi->cs[cs].base = ((base & 0x1FFFFFFF) | size);
mpi->cs[cs].config = flags;
}
/*
* mpi_InitPcmciaSpace
*/
static void mpi_InitPcmciaSpace(void)
{
// ChipSelect 4 controls PCMCIA Memory accesses
mpi_ConfigCs(PCMCIA_COMMON_BASE, pcmciaMem, EBI_SIZE_1M, (EBI_WORD_WIDE|EBI_ENABLE));
// ChipSelect 5 controls PCMCIA Attribute accesses
mpi_ConfigCs(PCMCIA_ATTRIBUTE_BASE, pcmciaAttr, EBI_SIZE_1M, (EBI_WORD_WIDE|EBI_ENABLE));
// ChipSelect 6 controls PCMCIA I/O accesses
mpi_ConfigCs(PCMCIA_IO_BASE, pcmciaIo, EBI_SIZE_64K, (EBI_WORD_WIDE|EBI_ENABLE));
mpi->pcmcia_cntl2 = ((PCMCIA_ATTR_ACTIVE << RW_ACTIVE_CNT_BIT) |
(PCMCIA_ATTR_INACTIVE << INACTIVE_CNT_BIT) |
(PCMCIA_ATTR_CE_SETUP << CE_SETUP_CNT_BIT) |
(PCMCIA_ATTR_CE_HOLD << CE_HOLD_CNT_BIT));
mpi->pcmcia_cntl2 |= (PCMCIA_HALFWORD_EN | PCMCIA_BYTESWAP_DIS);
}
/*
* cardtype_vcc_detect: PC Card's card detect and voltage sense connection
*
* CD1#/ CD2#/ VS1#/ VS2#/ Card Initial Vcc
* CCD1# CCD2# CVS1 CVS2 Type
*
* GND GND open open 16-bit 5 vdc
*
* GND GND GND open 16-bit 3.3 vdc
*
* GND GND open GND 16-bit x.x vdc
*
* GND GND GND GND 16-bit 3.3 & x.x vdc
*
*====================================================================
*
* CVS1 GND CCD1# open CardBus 3.3 vdc
*
* GND CVS2 open CCD2# CardBus x.x vdc
*
* GND CVS1 CCD2# open CardBus y.y vdc
*
* GND CVS2 GND CCD2# CardBus 3.3 & x.x vdc
*
* CVS2 GND open CCD1# CardBus x.x & y.y vdc
*
* GND CVS1 CCD2# open CardBus 3.3, x.x & y.y vdc
*
*/
static int cardtype_vcc_detect(void)
{
uint32 data32;
int cardtype;
cardtype = MPI_CARDTYPE_NONE;
mpi->pcmcia_cntl1 = 0x0000A000; // Turn on the output enables and drive
// the CVS pins to 0.
data32 = mpi->pcmcia_cntl1;
switch (data32 & 0x00000003) // Test CD1# and CD2#, see if card is plugged in.
{
case 0x00000003: // No Card is in the slot.
printk("mpi: No Card is in the PCMCIA slot\n");
break;
case 0x00000002: // Partial insertion, No CD2#.
printk("mpi: Card in the PCMCIA slot partial insertion, no CD2 signal\n");
break;
case 0x00000001: // Partial insertion, No CD1#.
printk("mpi: Card in the PCMCIA slot partial insertion, no CD1 signal\n");
break;
case 0x00000000:
mpi->pcmcia_cntl1 = 0x0000A0C0; // Turn off the CVS output enables and
// float the CVS pins.
mdelay(1);
data32 = mpi->pcmcia_cntl1;
// Read the Register.
switch (data32 & 0x0000000C) // See what is on the CVS pins.
{
case 0x00000000: // CVS1 and CVS2 are tied to ground, only 1 option.
printk("mpi: Detected 3.3 & x.x 16-bit PCMCIA card\n");
cardtype = MPI_CARDTYPE_PCMCIA;
break;
case 0x00000004: // CVS1 is open or tied to CCD1/CCD2 and CVS2 is tied to ground.
// 2 valid voltage options.
switch (data32 & 0x00000003) // Test the values of CCD1 and CCD2.
{
case 0x00000003: // CCD1 and CCD2 are tied to 1 of the CVS pins.
// This is not a valid combination.
printk("mpi: Unknown card plugged into slot\n");
break;
case 0x00000002: // CCD2 is tied to either CVS1 or CVS2.
mpi->pcmcia_cntl1 = 0x0000A080; // Drive CVS1 to a 0.
mdelay(1);
data32 = mpi->pcmcia_cntl1;
if (data32 & 0x00000002) { // CCD2 is tied to CVS2, not valid.
printk("mpi: Unknown card plugged into slot\n");
} else { // CCD2 is tied to CVS1.
printk("mpi: Detected 3.3, x.x and y.y Cardbus card\n");
cardtype = MPI_CARDTYPE_CARDBUS;
}
break;
case 0x00000001: // CCD1 is tied to either CVS1 or CVS2.
// This is not a valid combination.
printk("mpi: Unknown card plugged into slot\n");
break;
case 0x00000000: // CCD1 and CCD2 are tied to ground.
printk("mpi: Detected x.x vdc 16-bit PCMCIA card\n");
cardtype = MPI_CARDTYPE_PCMCIA;
break;
}
break;
case 0x00000008: // CVS2 is open or tied to CCD1/CCD2 and CVS1 is tied to ground.
// 2 valid voltage options.
switch (data32 & 0x00000003) // Test the values of CCD1 and CCD2.
{
case 0x00000003: // CCD1 and CCD2 are tied to 1 of the CVS pins.
// This is not a valid combination.
printk("mpi: Unknown card plugged into slot\n");
break;
case 0x00000002: // CCD2 is tied to either CVS1 or CVS2.
mpi->pcmcia_cntl1 = 0x0000A040; // Drive CVS2 to a 0.
mdelay(1);
data32 = mpi->pcmcia_cntl1;
if (data32 & 0x00000002) { // CCD2 is tied to CVS1, not valid.
printk("mpi: Unknown card plugged into slot\n");
} else {// CCD2 is tied to CVS2.
printk("mpi: Detected 3.3 and x.x Cardbus card\n");
cardtype = MPI_CARDTYPE_CARDBUS;
}
break;
case 0x00000001: // CCD1 is tied to either CVS1 or CVS2.
// This is not a valid combination.
printk("mpi: Unknown card plugged into slot\n");
break;
case 0x00000000: // CCD1 and CCD2 are tied to ground.
cardtype = MPI_CARDTYPE_PCMCIA;
printk("mpi: Detected 3.3 vdc 16-bit PCMCIA card\n");
break;
}
break;
case 0x0000000C: // CVS1 and CVS2 are open or tied to CCD1/CCD2.
// 5 valid voltage options.
switch (data32 & 0x00000003) // Test the values of CCD1 and CCD2.
{
case 0x00000003: // CCD1 and CCD2 are tied to 1 of the CVS pins.
// This is not a valid combination.
printk("mpi: Unknown card plugged into slot\n");
break;
case 0x00000002: // CCD2 is tied to either CVS1 or CVS2.
// CCD1 is tied to ground.
mpi->pcmcia_cntl1 = 0x0000A040; // Drive CVS2 to a 0.
mdelay(1);
data32 = mpi->pcmcia_cntl1;
if (data32 & 0x00000002) { // CCD2 is tied to CVS1.
printk("mpi: Detected y.y vdc Cardbus card\n");
} else { // CCD2 is tied to CVS2.
printk("mpi: Detected x.x vdc Cardbus card\n");
}
cardtype = MPI_CARDTYPE_CARDBUS;
break;
case 0x00000001: // CCD1 is tied to either CVS1 or CVS2.
// CCD2 is tied to ground.
mpi->pcmcia_cntl1 = 0x0000A040; // Drive CVS2 to a 0.
mdelay(1);
data32 = mpi->pcmcia_cntl1;
if (data32 & 0x00000001) {// CCD1 is tied to CVS1.
printk("mpi: Detected 3.3 vdc Cardbus card\n");
} else { // CCD1 is tied to CVS2.
printk("mpi: Detected x.x and y.y Cardbus card\n");
}
cardtype = MPI_CARDTYPE_CARDBUS;
break;
case 0x00000000: // CCD1 and CCD2 are tied to ground.
cardtype = MPI_CARDTYPE_PCMCIA;
printk("mpi: Detected 5 vdc 16-bit PCMCIA card\n");
break;
}
break;
default:
printk("mpi: Unknown card plugged into slot\n");
break;
}
}
return cardtype;
}
/*
* mpi_DetectPcCard: Detect the plugged in PC-Card
* Return: < 0 => Unknown card detected
* 0 => No card detected
* 1 => 16-bit card detected
* 2 => 32-bit CardBus card detected
*/
static int mpi_DetectPcCard(void)
{
int cardtype;
cardtype = cardtype_vcc_detect();
switch(cardtype) {
case MPI_CARDTYPE_PCMCIA:
mpi->pcmcia_cntl1 &= ~0x0000e000; // disable enable bits
//mpi->pcmcia_cntl1 = (mpi->pcmcia_cntl1 & ~PCCARD_CARD_RESET);
mpi->pcmcia_cntl1 |= (PCMCIA_ENABLE | PCMCIA_GPIO_ENABLE);
mpi_InitPcmciaSpace();
mpi_ResetPcCard(cardtype, FALSE);
// Hold card in reset for 10ms
mdelay(10);
mpi_ResetPcCard(cardtype, TRUE);
// Let card come out of reset
mdelay(100);
break;
case MPI_CARDTYPE_CARDBUS:
// 8 => CardBus Enable
// 1 => PCI Slot Number
// C => Float VS1 & VS2
mpi->pcmcia_cntl1 = (mpi->pcmcia_cntl1 & 0xFFFF0000) |
CARDBUS_ENABLE |
(CARDBUS_SLOT << 8)|
VS2_OEN |
VS1_OEN;
/* access to this memory window will be to/from CardBus */
mpi->l2pmremap1 |= CARDBUS_MEM;
// Need to reset the Cardbus Card. There's no CardManager to do this,
// and we need to be ready for PCI configuration.
mpi_ResetPcCard(cardtype, FALSE);
// Hold card in reset for 10ms
mdelay(10);
mpi_ResetPcCard(cardtype, TRUE);
// Let card come out of reset
mdelay(100);
break;
default:
break;
}
return cardtype;
}
static int mpi_init(void)
{
unsigned long data;
unsigned int chipid, chiprev, sdramsize;
printk("Broadcom BCM963xx MPI\n");
chipid = (PERF->RevID & 0xFFFF0000) >> 16;
chiprev = (PERF->RevID & 0xFF);
if (boot_loader_type == BOOT_LOADER_CFE)
sdramsize = boot_mem_map.map[0].size;
else
sdramsize = 0x01000000;
/*
* Init the pci interface
*/
data = GPIO->GPIOMode; // GPIO mode register
data |= GROUP2_PCI | GROUP1_MII_PCCARD; // PCI internal arbiter + Cardbus
GPIO->GPIOMode = data; // PCI internal arbiter
/*
* In the BCM6348 CardBus support is defaulted to Slot 0
* because there is no external IDSEL for CardBus. To disable
* the CardBus and allow a standard PCI card in Slot 0
* set the cbus_idsel field to 0x1f.
*/
/*
uData = mpi->pcmcia_cntl1;
uData |= CARDBUS_IDSEL;
mpi->pcmcia_cntl1 = uData;
*/
// Setup PCI I/O Window range. Give 64K to PCI I/O
mpi->l2piorange = ~(BCM_PCI_IO_SIZE_64KB-1);
// UBUS to PCI I/O base address
mpi->l2piobase = BCM_PCI_IO_BASE & BCM_PCI_ADDR_MASK;
// UBUS to PCI I/O Window remap
mpi->l2pioremap = (BCM_PCI_IO_BASE | MEM_WINDOW_EN);
// enable PCI related GPIO pins and data swap between system and PCI bus
mpi->locbuscntrl = (EN_PCI_GPIO | DIR_U2P_NOSWAP);
/* Enable 6348 BusMaster and Memory access mode */
data = mpi_GetLocalPciConfigReg(PCI_COMMAND);
data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
mpi_SetLocalPciConfigReg(PCI_COMMAND, data);
/* Configure two 16 MByte PCI to System memory regions. */
/* These memory regions are used when PCI device is a bus master */
/* Accesses to the SDRAM from PCI bus will be "byte swapped" for this region */
mpi_SetLocalPciConfigReg(PCI_BASE_ADDRESS_3, BCM_HOST_MEM_SPACE1);
mpi->sp0remap = 0x0;
/* Accesses to the SDRAM from PCI bus will not be "byte swapped" for this region */
mpi_SetLocalPciConfigReg(PCI_BASE_ADDRESS_4, BCM_HOST_MEM_SPACE2);
mpi->sp1remap = 0x0;
mpi->pcimodesel |= (PCI_BAR2_NOSWAP | 0x40);
if ((chipid == 0x6348) && (chiprev == 0xb0)) {
mpi->sp0range = ~(sdramsize-1);
mpi->sp1range = ~(sdramsize-1);
}
/*
* Change 6348 PCI Cfg Reg. offset 0x40 to PCI memory read retry count infinity
* by set 0 in bit 8~15. This resolve read Bcm4306 srom return 0xffff in
* first read.
*/
data = mpi_GetLocalPciConfigReg(BRCM_PCI_CONFIG_TIMER);
data &= ~BRCM_PCI_CONFIG_TIMER_RETRY_MASK;
data |= 0x00000080;
mpi_SetLocalPciConfigReg(BRCM_PCI_CONFIG_TIMER, data);
/* enable pci interrupt */
mpi->locintstat |= (EXT_PCI_INT << 16);
mpi_DetectPcCard();
ioport_resource.start = BCM_PCI_IO_BASE;
ioport_resource.end = BCM_PCI_IO_BASE + BCM_PCI_IO_SIZE_64KB;
#if defined(CONFIG_USB)
PERF->blkEnables |= USBH_CLK_EN;
mdelay(100);
*USBH_NON_OHCI = NON_OHCI_BYTE_SWAP;
#endif
return 0;
}
void __init plat_mem_setup(void)
{
_machine_restart = brcm_machine_restart;
_machine_halt = brcm_machine_halt;
pm_power_off = brcm_machine_halt;
//board_time_init = brcm_time_init;
/* mpi initialization */
mpi_init();
}

118
target/linux/brcm63xx/files/arch/mips/bcm963xx/time.c
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@ -1,118 +0,0 @@
/*
<:copyright-gpl
Copyright 2004 Broadcom Corp. All Rights Reserved.
This program is free software; you can distribute it and/or modify it
under the terms of the GNU General Public License (Version 2) as
published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
:>
*/
/*
* Setup time for Broadcom 963xx MIPS boards
*/
#include <linux/autoconf.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/time.h>
#include <linux/timex.h>
#include <asm/mipsregs.h>
#include <asm/ptrace.h>
#include <asm/div64.h>
#include <asm/time.h>
#include <6348_map_part.h>
#include <6348_intr.h>
#include <bcm_map_part.h>
#include <bcm_intr.h>
static unsigned long r4k_offset; /* Amount to increment compare reg each time */
static unsigned long r4k_cur; /* What counter should be at next timer irq */
/* *********************************************************************
* calculateCpuSpeed()
* Calculate the BCM6348 CPU speed by reading the PLL strap register
* and applying the following formula:
* cpu_clk = (.25 * 64MHz freq) * (N1 + 1) * (N2 + 2) / (M1_CPU + 1)
* Input parameters:
* none
* Return value:
* none
********************************************************************* */
static inline unsigned long __init calculateCpuSpeed(void)
{
u32 pllStrap = PERF->PllStrap;
int n1 = (pllStrap & PLL_N1_MASK) >> PLL_N1_SHFT;
int n2 = (pllStrap & PLL_N2_MASK) >> PLL_N2_SHFT;
int m1cpu = (pllStrap & PLL_M1_CPU_MASK) >> PLL_M1_CPU_SHFT;
return (16 * (n1 + 1) * (n2 + 2) / (m1cpu + 1)) * 1000000;
}
static inline unsigned long __init cal_r4koff(void)
{
mips_hpt_frequency = calculateCpuSpeed() / 2;
return (mips_hpt_frequency / HZ);
}
/*
* There are a lot of conceptually broken versions of the MIPS timer interrupt
* handler floating around. This one is rather different, but the algorithm
* is provably more robust.
*/
#if 0
irqreturn_t brcm_timer_interrupt(struct pt_regs *regs)
{
int irq = MIPS_TIMER_INT;
irq_enter();
kstat_this_cpu.irqs[irq]++;
timer_interrupt(irq, regs);
irq_exit();
return IRQ_HANDLED;
}
#endif
void __init plat_time_init(void)
{
unsigned int est_freq, flags;
local_irq_save(flags);
printk("calculating r4koff... ");
r4k_offset = cal_r4koff();
printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
est_freq = 2 * r4k_offset * HZ;
est_freq += 5000; /* round */
est_freq -= est_freq % 10000;
printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
(est_freq % 1000000) * 100 / 1000000);
local_irq_restore(flags);
}
#if 0
void __init plat_timer_setup(struct irqaction *irq)
{
r4k_cur = (read_c0_count() + r4k_offset);
write_c0_compare(r4k_cur);
set_c0_status(IE_IRQ5);
}
#endif

246
target/linux/brcm63xx/files/arch/mips/bcm963xx/wdt.c
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@ -1,246 +0,0 @@
/*
* Watchdog driver for the BCM963xx devices
*
* Copyright (C) 2007 OpenWrt.org
* Florian Fainelli <florian@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/miscdevice.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/notifier.h>
#include <linux/watchdog.h>
#include <linux/timer.h>
#include <linux/jiffies.h>
#include <linux/completion.h>
#include <linux/ioport.h>
typedef struct bcm963xx_timer {
unsigned short unused0;
unsigned char timer_mask;
#define TIMER0EN 0x01
#define TIMER1EN 0x02
#define TIMER2EN 0x04
unsigned char timer_ints;
#define TIMER0 0x01
#define TIMER1 0x02
#define TIMER2 0x04
#define WATCHDOG 0x08
unsigned long timer_ctl0;
unsigned long timer_ctl1;
unsigned long timer_ctl2;
#define TIMERENABLE 0x80000000
#define RSTCNTCLR 0x40000000
unsigned long timer_cnt0;
unsigned long timer_cnt1;
unsigned long timer_cnt2;
unsigned long wdt_def_count;
/* Write 0xff00 0x00ff to Start timer
* Write 0xee00 0x00ee to Stop and re-load default count
* Read from this register returns current watch dog count
*/
unsigned long wdt_ctl;
/* Number of 40-MHz ticks for WD Reset pulse to last */
unsigned long wdt_rst_count;
} bcm963xx_timer;
static struct bcm963xx_wdt_device {
struct completion stop;
volatile int running;
struct timer_list timer;
volatile int queue;
int default_ticks;
unsigned long inuse;
} bcm963xx_wdt_device;
static int ticks = 1000;
#define WDT_BASE 0xfffe0200
#define WDT ((volatile bcm963xx_timer * const) WDT_BASE)
#define BCM963XX_INTERVAL (HZ/10+1)
static void bcm963xx_wdt_trigger(unsigned long unused)
{
if (bcm963xx_wdt_device.running)
ticks--;
/* Load the default ticking value into the reset counter register */
WDT->wdt_rst_count = bcm963xx_wdt_device.default_ticks;
if (bcm963xx_wdt_device.queue && ticks) {
bcm963xx_wdt_device.timer.expires = jiffies + BCM963XX_INTERVAL;
add_timer(&bcm963xx_wdt_device.timer);
}
else {
complete(&bcm963xx_wdt_device.stop);
}
}
static void bcm963xx_wdt_reset(void)
{
ticks = bcm963xx_wdt_device.default_ticks;
/* Also reload default count */
WDT->wdt_def_count = ticks;
WDT->wdt_ctl = 0xee00;
WDT->wdt_ctl = 0x00ee;
}
static void bcm963xx_wdt_start(void)
{
if (!bcm963xx_wdt_device.queue) {
bcm963xx_wdt_device.queue;
/* Enable the watchdog by writing 0xff00 ,then 0x00ff to the control register */
WDT->wdt_ctl = 0xff00;
WDT->wdt_ctl = 0x00ff;
bcm963xx_wdt_device.timer.expires = jiffies + BCM963XX_INTERVAL;
add_timer(&bcm963xx_wdt_device.timer);
}
bcm963xx_wdt_device.running++;
}
static int bcm963xx_wdt_stop(void)
{
if (bcm963xx_wdt_device.running)
bcm963xx_wdt_device.running = 0;
ticks = bcm963xx_wdt_device.default_ticks;
/* Stop the watchdog by writing 0xee00 then 0x00ee to the control register */
WDT->wdt_ctl = 0xee00;
WDT->wdt_ctl = 0x00ee;
return -EIO;
}
static int bcm963xx_wdt_open(struct inode *inode, struct file *file)
{
if (test_and_set_bit(0, &bcm963xx_wdt_device.inuse))
return -EBUSY;
return nonseekable_open(inode, file);
}
static int bcm963xx_wdt_release(struct inode *inode, struct file *file)
{
clear_bit(0, &bcm963xx_wdt_device.inuse);
return 0;
}
static int bcm963xx_wdt_ioctl(struct inode *inode, struct file *file,
unsigned int cmd, unsigned long arg)
{
void __user *argp = (void __user *)arg;
unsigned int value;
static struct watchdog_info ident = {
.options = WDIOF_CARDRESET,
.identity = "BCM963xx WDT",
};
switch (cmd) {
case WDIOC_KEEPALIVE:
bcm963xx_wdt_reset();
break;
case WDIOC_GETSTATUS:
/* Reading from the control register will return the current value */
value = WDT->wdt_ctl;
if ( copy_to_user(argp, &value, sizeof(int)) )
return -EFAULT;
break;
case WDIOC_GETSUPPORT:
if ( copy_to_user(argp, &ident, sizeof(ident)) )
return -EFAULT;
break;
case WDIOC_SETOPTIONS:
if ( copy_from_user(&value, argp, sizeof(int)) )
return -EFAULT;
switch(value) {
case WDIOS_ENABLECARD:
bcm963xx_wdt_start();
break;
case WDIOS_DISABLECARD:
bcm963xx_wdt_stop();
break;
default:
return -EINVAL;
}
break;
default:
return -ENOTTY;
}
return 0;
}
static int bcm963xx_wdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos)
{
if (!count)
return -EIO;
bcm963xx_wdt_reset();
return count;
}
static const struct file_operations bcm963xx_wdt_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = bcm963xx_wdt_write,
.ioctl = bcm963xx_wdt_ioctl,
.open = bcm963xx_wdt_open,
.release = bcm963xx_wdt_release,
};
static struct miscdevice bcm963xx_wdt_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &bcm963xx_wdt_fops,
};
static void __exit bcm963xx_wdt_exit(void)
{
if (bcm963xx_wdt_device.queue ){
bcm963xx_wdt_device.queue = 0;
wait_for_completion(&bcm963xx_wdt_device.stop);
}
misc_deregister(&bcm963xx_wdt_miscdev);
}
static int __init bcm963xx_wdt_init(void)
{
int ret = 0;
printk("Broadcom BCM963xx Watchdog timer\n");
ret = misc_register(&bcm963xx_wdt_miscdev);
if (ret) {
printk(KERN_CRIT "Cannot register miscdev on minor=%d (err=%d)\n", WATCHDOG_MINOR, ret);
return ret;
}
init_completion(&bcm963xx_wdt_device.stop);
bcm963xx_wdt_device.queue = 0;
clear_bit(0, &bcm963xx_wdt_device.inuse);
init_timer(&bcm963xx_wdt_device.timer);
bcm963xx_wdt_device.timer.function = bcm963xx_wdt_trigger;
bcm963xx_wdt_device.timer.data = 0;
bcm963xx_wdt_device.default_ticks = ticks;
return ret;
}
module_init(bcm963xx_wdt_init);
module_exit(bcm963xx_wdt_exit);
MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
MODULE_DESCRIPTION("Broadcom BCM963xx Watchdog driver");
MODULE_LICENSE("GPL");

5
target/linux/brcm63xx/files/arch/mips/cfe/Makefile
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@ -1,5 +0,0 @@
#
# Makefile for the Broadcom Common Firmware Environment support
#
obj-y += cfe.o

533
target/linux/brcm63xx/files/arch/mips/cfe/cfe.c
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@ -1,533 +0,0 @@
/*
* Broadcom Common Firmware Environment (CFE) support
*
* Copyright 2000, 2001, 2002
* Broadcom Corporation. All rights reserved.
*
* Copyright (C) 2006 Michael Buesch
*
* Original Authors: Mitch Lichtenberg, Chris Demetriou
*
* This software is furnished under license and may be used and copied only
* in accordance with the following terms and conditions. Subject to these
* conditions, you may download, copy, install, use, modify and distribute
* modified or unmodified copies of this software in source and/or binary
* form. No title or ownership is transferred hereby.
*
* 1) Any source code used, modified or distributed must reproduce and
* retain this copyright notice and list of conditions as they appear in
* the source file.
*
* 2) No right is granted to use any trade name, trademark, or logo of
* Broadcom Corporation. The "Broadcom Corporation" name may not be
* used to endorse or promote products derived from this software
* without the prior written permission of Broadcom Corporation.
*
* 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
* FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
* LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <linux/init.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/spinlock.h>
#include <asm/cfe.h>
#include "cfe_private.h"
static cfe_uint_t cfe_handle;
static int (*cfe_trampoline)(long handle, long iocb);
#include <linux/kernel.h>
void __init cfe_setup(unsigned long fwarg0, unsigned long fwarg1,
unsigned long fwarg2, unsigned long fwarg3)
{
if (fwarg3 == 0x80300000) {
/* WRT54G workaround */
fwarg3 = CFE_EPTSEAL;
fwarg2 = 0xBFC00500;
}
if (fwarg3 != CFE_EPTSEAL) {
/* We are not booted from CFE */
return;
}
if (fwarg1 == 0) {
/* We are on the boot CPU */
cfe_handle = (cfe_uint_t)fwarg0;
cfe_trampoline = CFE_TO_PTR(fwarg2);
}
}
int cfe_vprintk(const char *fmt, va_list args)
{
static char buffer[1024];
static DEFINE_SPINLOCK(lock);
static const char pfx[] = "CFE-console: ";
static const size_t pfx_len = sizeof(pfx) - 1;
unsigned long flags;
int len, cnt, pos;
int handle;
int res;
if (!cfe_present())
return -ENODEV;
spin_lock_irqsave(&lock, flags);
handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
if (CFE_ISERR(handle)) {
len = -EIO;
goto out;
}
strcpy(buffer, pfx);
len = vscnprintf(buffer + pfx_len,
sizeof(buffer) - pfx_len - 2,
fmt, args);
len += pfx_len;
/* The CFE console requires CR-LF line-ends.
* Add a CR, if we only terminate lines with a LF.
* This does only fix CR-LF at the end of the string.
* So for multiple lines, use multiple cfe_vprintk calls.
*/
if (len > 1 &&
buffer[len - 1] == '\n' && buffer[len - 2] != '\r') {
buffer[len - 1] = '\r';
buffer[len] = '\n';
len += 1;
}
cnt = len;
pos = 0;
while (cnt > 0) {
res = cfe_write(handle, buffer + pos, len - pos);
if (CFE_ISERR(res)) {
len = -EIO;
goto out;
}
cnt -= res;
pos += res;
}
out:
spin_unlock_irqrestore(&lock, flags);
return len;
}
int cfe_printk(const char *fmt, ...)
{
va_list args;
int res;
va_start(args, fmt);
res = cfe_vprintk(fmt, args);
va_end(args);
return res;
}
static int cfe_iocb_dispatch(struct cfe_iocb *iocb)
{
if (!cfe_present())
return CFE_ERR_UNSUPPORTED;
return cfe_trampoline((long)cfe_handle, (long)iocb);
}
int cfe_present(void)
{
return (cfe_trampoline != NULL);
}
int cfe_close(int handle)
{
struct cfe_iocb iocb;
int err;
memset(&iocb, 0, sizeof(iocb));
iocb.fcode = CFE_CMD_DEV_CLOSE;
iocb.handle = handle;
err = cfe_iocb_dispatch(&iocb);
return (CFE_ISERR(err)) ? err : iocb.status;
}
int cfe_cpu_start(int cpu, void (*fn)(void), long sp, long gp, long a1)
{
struct cfe_iocb iocb;
int err;
memset(&iocb, 0, sizeof(iocb));
iocb.fcode = CFE_CMD_FW_CPUCTL;
iocb.psize = sizeof(struct cfe_iocb_cpuctl);
iocb.cpuctl.number = cpu;
iocb.cpuctl.command = CFE_CPU_CMD_START;
iocb.cpuctl.gp = gp;
iocb.cpuctl.sp = sp;
iocb.cpuctl.a1 = a1;
iocb.cpuctl.start_addr = (long)fn;
err = cfe_iocb_dispatch(&iocb);
return (CFE_ISERR(err)) ? err : iocb.status;
}
int cfe_cpu_stop(int cpu)
{
struct cfe_iocb iocb;
int err;
memset(&iocb, 0, sizeof(iocb));
iocb.fcode = CFE_CMD_FW_CPUCTL;
iocb.psize = sizeof(struct cfe_iocb_cpuctl);
iocb.cpuctl.number = cpu;
iocb.cpuctl.command = CFE_CPU_CMD_STOP;
err = cfe_iocb_dispatch(&iocb);
return (CFE_ISERR(err)) ? err : iocb.status;
}
int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen)
{
struct cfe_iocb iocb;
int err;
memset(&iocb, 0, sizeof(iocb));
iocb.fcode = CFE_CMD_ENV_ENUM;
iocb.psize = sizeof(struct cfe_iocb_envbuf);
iocb.envbuf.index = idx;
iocb.envbuf.name = PTR_TO_CFE(name);
iocb.envbuf.name_len = namelen;
iocb.envbuf.val = PTR_TO_CFE(val);
iocb.envbuf.val_len = vallen;
err = cfe_iocb_dispatch(&iocb);
return (CFE_ISERR(err)) ? err : iocb.status;
}
int cfe_enumdev(int idx, char *name, int namelen)
{
struct cfe_iocb iocb;
int err;
memset(&iocb, 0, sizeof(iocb));
iocb.fcode = CFE_CMD_DEV_ENUM;
iocb.psize = sizeof(struct cfe_iocb_envbuf);
iocb.envbuf.index = idx;
iocb.envbuf.name = PTR_TO_CFE(name);
iocb.envbuf.name_len = namelen;
err = cfe_iocb_dispatch(&iocb);
return (CFE_ISERR(err)) ? err : iocb.status;
}
int cfe_enummem(int idx, int flags, u64 *start, u64 *length,
u64 *type)
{
struct cfe_iocb iocb;
int err;
memset(&iocb, 0, sizeof(iocb));
iocb.fcode = CFE_CMD_FW_MEMENUM;
iocb.flags = flags;
iocb.psize = sizeof(struct cfe_iocb_meminfo);
iocb.meminfo.index = idx;
err = cfe_iocb_dispatch(&iocb);
if (CFE_ISERR(err))
return err;
if (!CFE_ISERR(iocb.status)) {
*start = iocb.meminfo.addr;
*length = iocb.meminfo.size;
*type = iocb.meminfo.type;
}
return iocb.status;
}
int cfe_exit(int warm, int status)
{
struct cfe_iocb iocb;
int err;
printk("CFE REBOOT\n");
memset(&iocb, 0, sizeof(iocb));
iocb.fcode = CFE_CMD_FW_RESTART;
if (warm)
iocb.flags = CFE_FLG_WARMSTART;
iocb.psize = sizeof(struct cfe_iocb_exitstat);
iocb.exitstat.status = status;
printk("CALL\n");
err = cfe_iocb_dispatch(&iocb);
printk("DONE\n");
return (CFE_ISERR(err)) ? err : iocb.status;
}
int cfe_flushcache(int flags)
{
struct cfe_iocb iocb;
int err;
memset(&iocb, 0, sizeof(iocb));
iocb.fcode = CFE_CMD_FW_FLUSHCACHE;
iocb.flags = flags;
err = cfe_iocb_dispatch(&iocb);
return (CFE_ISERR(err)) ? err : iocb.status;
}
int cfe_getdevinfo(char *name)
{
struct cfe_iocb iocb;
int err;
memset(&iocb, 0, sizeof(iocb));
iocb.fcode = CFE_CMD_DEV_GETINFO;
iocb.psize = sizeof(struct cfe_iocb_buf);
iocb.buffer.ptr = PTR_TO_CFE(name);
iocb.buffer.length = strlen(name);
err = cfe_iocb_dispatch(&iocb);
if (CFE_ISERR(err))
return err;
if (CFE_ISERR(iocb.status))
return iocb.status;
return iocb.buffer.devflags;
}
int cfe_getenv(char *name, char *dest, int destlen)
{
struct cfe_iocb iocb;
int err;
dest[0] = '\0';
memset(&iocb, 0, sizeof(iocb));
iocb.fcode = CFE_CMD_ENV_GET;
iocb.psize = sizeof(struct cfe_iocb_envbuf);
iocb.envbuf.name = PTR_TO_CFE(name);
iocb.envbuf.name_len = strlen(name);
iocb.envbuf.val = PTR_TO_CFE(dest);
iocb.envbuf.val_len = destlen;
err = cfe_iocb_dispatch(&iocb);
return (CFE_ISERR(err)) ? err : iocb.status;
}
int cfe_getfwinfo(struct cfe_fwinfo *info)
{
struct cfe_iocb iocb;
int err;
memset(&iocb, 0, sizeof(iocb));
iocb.fcode = CFE_CMD_FW_GETINFO;
iocb.psize = sizeof(struct cfe_iocb_fwinfo);
err = cfe_iocb_dispatch(&iocb);
if (CFE_ISERR(err))
return err;
if (CFE_ISERR(iocb.status))
return err;
info->version = iocb.fwinfo.version;
info->totalmem = iocb.fwinfo.totalmem;
info->flags = iocb.fwinfo.flags;
info->boardid = iocb.fwinfo.boardid;
info->bootarea_va = iocb.fwinfo.bootarea_va;
info->bootarea_pa = iocb.fwinfo.bootarea_pa;
info->bootarea_size = iocb.fwinfo.bootarea_size;
return iocb.status;
}
int cfe_getstdhandle(int handletype)
{
struct cfe_iocb iocb;
int err;
memset(&iocb, 0, sizeof(iocb));
iocb.fcode = CFE_CMD_DEV_GETHANDLE;
iocb.flags = handletype;
err = cfe_iocb_dispatch(&iocb);
if (CFE_ISERR(err))
return err;
if (CFE_ISERR(iocb.status))
return iocb.status;
return iocb.handle;
}
int cfe_getticks(s64 *ticks)
{
struct cfe_iocb iocb;
int err;
memset(&iocb, 0, sizeof(iocb));
iocb.fcode = CFE_CMD_FW_GETTIME;
iocb.psize = sizeof(struct cfe_iocb_time);
err = cfe_iocb_dispatch(&iocb);
if (CFE_ISERR(err))
return err;
if (!CFE_ISERR(iocb.status))
*ticks = iocb.time.ticks;
return iocb.status;
}
int cfe_inpstat(int handle)
{
struct cfe_iocb iocb;
int err;
memset(&iocb, 0, sizeof(iocb));
iocb.fcode = CFE_CMD_DEV_INPSTAT;
iocb.handle = handle;
iocb.psize = sizeof(struct cfe_iocb_inpstat);
err = cfe_iocb_dispatch(&iocb);
if (CFE_ISERR(err))
return err;
if (CFE_ISERR(iocb.status))
return iocb.status;
return iocb.inpstat.status;
}
int cfe_ioctl(int handle, unsigned int ioctlnum,
unsigned char *buffer, int length,
int *retlen, u64 offset)
{
struct cfe_iocb iocb;
int err;
memset(&iocb, 0, sizeof(iocb));
iocb.fcode = CFE_CMD_DEV_IOCTL;
iocb.handle = handle;
iocb.psize = sizeof(struct cfe_iocb_buf);
iocb.buffer.offset = offset;
iocb.buffer.ioctlcmd = ioctlnum;
iocb.buffer.ptr = PTR_TO_CFE(buffer);
iocb.buffer.length = length;
err = cfe_iocb_dispatch(&iocb);
if (CFE_ISERR(err))
return err;
if (CFE_ISERR(iocb.status))
return iocb.status;
if (retlen)
*retlen = iocb.buffer.retlen;
return iocb.status;
}
int cfe_open(char *name)
{
struct cfe_iocb iocb;
int err;
memset(&iocb, 0, sizeof(iocb));
iocb.fcode = CFE_CMD_DEV_OPEN;
iocb.psize = sizeof(struct cfe_iocb_buf);
iocb.buffer.ptr = PTR_TO_CFE(name);
iocb.buffer.length = strlen(name);
err = cfe_iocb_dispatch(&iocb);
if (CFE_ISERR(err))
return err;
if (CFE_ISERR(iocb.status))
return iocb.status;
return iocb.handle;
}
int cfe_read(int handle, unsigned char *buffer, int length)
{
return cfe_readblk(handle, 0, buffer, length);
}
int cfe_readblk(int handle, s64 offset, unsigned char *buffer, int length)
{
struct cfe_iocb iocb;
int err;
memset(&iocb, 0, sizeof(iocb));
iocb.fcode = CFE_CMD_DEV_READ;
iocb.handle = handle;
iocb.psize = sizeof(struct cfe_iocb_buf);
iocb.buffer.offset = offset;
iocb.buffer.ptr = PTR_TO_CFE(buffer);
iocb.buffer.length = length;
err = cfe_iocb_dispatch(&iocb);
if (CFE_ISERR(err))
return err;
if (CFE_ISERR(iocb.status))
return iocb.status;
return iocb.buffer.retlen;
}
int cfe_setenv(char *name, char *val)
{
struct cfe_iocb iocb;
int err;
memset(&iocb, 0, sizeof(iocb));
iocb.fcode = CFE_CMD_ENV_SET;
iocb.psize = sizeof(struct cfe_iocb_envbuf);
iocb.envbuf.name = PTR_TO_CFE(name);
iocb.envbuf.name_len = strlen(name);
iocb.envbuf.val = PTR_TO_CFE(val);
iocb.envbuf.val_len = strlen(val);
err = cfe_iocb_dispatch(&iocb);
return (CFE_ISERR(err)) ? err : iocb.status;
}
int cfe_write(int handle, unsigned char *buffer, int length)
{
return cfe_writeblk(handle, 0, buffer, length);
}
int cfe_writeblk(int handle, s64 offset, unsigned char *buffer, int length)
{
struct cfe_iocb iocb;
int err;
memset(&iocb, 0, sizeof(iocb));
iocb.fcode = CFE_CMD_DEV_WRITE;
iocb.handle = handle;
iocb.psize = sizeof(struct cfe_iocb_buf);
iocb.buffer.offset = offset;
iocb.buffer.ptr = PTR_TO_CFE(buffer);
iocb.buffer.length = length;
err = cfe_iocb_dispatch(&iocb);
if (CFE_ISERR(err))
return err;
if (CFE_ISERR(iocb.status))
return iocb.status;
return iocb.buffer.retlen;
}

176
target/linux/brcm63xx/files/arch/mips/cfe/cfe_private.h
View file

@ -1,176 +0,0 @@
/*
* Broadcom Common Firmware Environment (CFE) support
*
* Copyright 2000, 2001, 2002
* Broadcom Corporation. All rights reserved.
*
* Copyright (C) 2006 Michael Buesch
*
* Original Authors: Mitch Lichtenberg, Chris Demetriou
*
* This software is furnished under license and may be used and copied only
* in accordance with the following terms and conditions. Subject to these
* conditions, you may download, copy, install, use, modify and distribute
* modified or unmodified copies of this software in source and/or binary
* form. No title or ownership is transferred hereby.
*
* 1) Any source code used, modified or distributed must reproduce and
* retain this copyright notice and list of conditions as they appear in
* the source file.
*
* 2) No right is granted to use any trade name, trademark, or logo of
* Broadcom Corporation. The "Broadcom Corporation" name may not be
* used to endorse or promote products derived from this software
* without the prior written permission of Broadcom Corporation.
*
* 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
* FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
* LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef LINUX_CFE_PRIVATE_H_
#define LINUX_CFE_PRIVATE_H_
#ifndef __ASSEMBLY__
/* Seal indicating CFE's presence, passed to the kernel. */
#define CFE_EPTSEAL 0x43464531
#define CFE_CMD_FW_GETINFO 0
#define CFE_CMD_FW_RESTART 1
#define CFE_CMD_FW_BOOT 2
#define CFE_CMD_FW_CPUCTL 3
#define CFE_CMD_FW_GETTIME 4
#define CFE_CMD_FW_MEMENUM 5
#define CFE_CMD_FW_FLUSHCACHE 6
#define CFE_CMD_DEV_GETHANDLE 9
#define CFE_CMD_DEV_ENUM 10
#define CFE_CMD_DEV_OPEN 11
#define CFE_CMD_DEV_INPSTAT 12
#define CFE_CMD_DEV_READ 13
#define CFE_CMD_DEV_WRITE 14
#define CFE_CMD_DEV_IOCTL 15
#define CFE_CMD_DEV_CLOSE 16
#define CFE_CMD_DEV_GETINFO 17
#define CFE_CMD_ENV_ENUM 20
#define CFE_CMD_ENV_GET 22
#define CFE_CMD_ENV_SET 23
#define CFE_CMD_ENV_DEL 24
#define CFE_CMD_MAX 32
#define CFE_CMD_VENDOR_USE 0x8000 /* codes above this are for customer use */
typedef u64 cfe_uint_t;
typedef s64 cfe_int_t;
typedef s64 cfe_ptr_t;
/* Cast a pointer from native to CFE-API pointer and back */
#define CFE_TO_PTR(p) ((void *)(unsigned long)(p))
#define PTR_TO_CFE(p) ((cfe_ptr_t)(unsigned long)(p))
struct cfe_iocb_buf {
cfe_uint_t offset; /* offset on device (bytes) */
cfe_ptr_t ptr; /* pointer to a buffer */
cfe_uint_t length; /* length of this buffer */
cfe_uint_t retlen; /* returned length (for read ops) */
union {
cfe_uint_t ioctlcmd; /* IOCTL command (used only for IOCTLs) */
cfe_uint_t devflags; /* Returned device info flags */
};
};
struct cfe_iocb_inpstat {
cfe_uint_t status; /* 1 means input available */
};
struct cfe_iocb_envbuf {
cfe_int_t index; /* 0-based enumeration index */
cfe_ptr_t name; /* name string buffer */
cfe_int_t name_len; /* size of name buffer */
cfe_ptr_t val; /* value string buffer */
cfe_int_t val_len; /* size of value string buffer */
};
struct cfe_iocb_cpuctl {
cfe_uint_t number; /* cpu number to control */
cfe_uint_t command; /* command to issue to CPU */
cfe_uint_t start_addr; /* CPU start address */
cfe_uint_t gp; /* starting GP value */
cfe_uint_t sp; /* starting SP value */
cfe_uint_t a1; /* starting A1 value */
};
struct cfe_iocb_time {
cfe_int_t ticks; /* current time in ticks */
};
struct cfe_iocb_exitstat {
cfe_int_t status;
};
struct cfe_iocb_meminfo {
cfe_int_t index; /* 0-based enumeration index */
cfe_int_t type; /* type of memory block */
cfe_uint_t addr; /* physical start address */
cfe_uint_t size; /* block size */
};
struct cfe_iocb_fwinfo {
cfe_int_t version; /* major, minor, eco version */
cfe_int_t totalmem; /* total installed mem */
cfe_int_t flags; /* various flags */
cfe_int_t boardid; /* board ID */
cfe_int_t bootarea_va; /* VA of boot area */
cfe_int_t bootarea_pa; /* PA of boot area */
cfe_int_t bootarea_size; /* size of boot area */
cfe_int_t reserved1;
cfe_int_t reserved2;
cfe_int_t reserved3;
};
/* CFE I/O Control Block */
struct cfe_iocb {
cfe_uint_t fcode; /* IOCB function code */
cfe_int_t status; /* return status */
cfe_int_t handle; /* file/device handle */
cfe_uint_t flags; /* flags for this IOCB */
cfe_uint_t psize; /* size of parameter list */
union {
struct cfe_iocb_buf buffer; /* buffer parameters */
struct cfe_iocb_inpstat inpstat; /* input status parameters */
struct cfe_iocb_envbuf envbuf; /* environment function parameters */
struct cfe_iocb_cpuctl cpuctl; /* CPU control parameters */
struct cfe_iocb_time time; /* timer parameters */
struct cfe_iocb_meminfo meminfo; /* memory arena info parameters */
struct cfe_iocb_fwinfo fwinfo; /* firmware information */
struct cfe_iocb_exitstat exitstat; /* Exit Status */
};
};
#include <linux/init.h>
void __init cfe_setup(unsigned long fwarg0, unsigned long fwarg1,
unsigned long fwarg2, unsigned long fwarg3);
#else /* __ASSEMBLY__ */
.macro cfe_early_init
#ifdef CONFIG_CFE
jal cfe_setup
#endif
.endm
#endif /* __ASSEMBLY__ */
#endif /* LINUX_CFE_PRIVATE_H_ */

95
target/linux/brcm63xx/files/arch/mips/pci/fixup-bcm96348.c
View file

@ -1,95 +0,0 @@
/*
<:copyright-gpl
Copyright 2002 Broadcom Corp. All Rights Reserved.
This program is free software; you can distribute it and/or modify it
under the terms of the GNU General Public License (Version 2) as
published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
:>
*/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <bcmpci.h>
#include <bcm_intr.h>
#include <bcm_map_part.h>
#include <6348_intr.h>
#include <6348_map_part.h>
static volatile MpiRegisters * mpi = (MpiRegisters *)(MPI_BASE);
static char irq_tab_bcm96348[] __initdata = {
[0] = INTERRUPT_ID_MPI,
[1] = INTERRUPT_ID_MPI,
#if defined(CONFIG_USB)
[USB_HOST_SLOT] = INTERRUPT_ID_USBH
#endif
};
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
return irq_tab_bcm96348[slot];
}
static void bcm96348_fixup(struct pci_dev *dev)
{
uint32 memaddr;
uint32 size;
memaddr = pci_resource_start(dev, 0);
size = pci_resource_len(dev, 0);
switch (PCI_SLOT(dev->devfn)) {
case 0:
// UBUS to PCI address range
// Memory Window 1. Mask determines which bits are decoded.
mpi->l2pmrange1 = ~(size-1);
// UBUS to PCI Memory base address. This is akin to the ChipSelect base
// register.
mpi->l2pmbase1 = memaddr & BCM_PCI_ADDR_MASK;
// UBUS to PCI Remap Address. Replaces the masked address bits in the
// range register with this setting.
// Also, enable direct I/O and direct Memory accesses
mpi->l2pmremap1 = (memaddr | MEM_WINDOW_EN);
break;
case 1:
// Memory Window 2
mpi->l2pmrange2 = ~(size-1);
// UBUS to PCI Memory base address.
mpi->l2pmbase2 = memaddr & BCM_PCI_ADDR_MASK;
// UBUS to PCI Remap Address
mpi->l2pmremap2 = (memaddr | MEM_WINDOW_EN);
break;
#if defined(CONFIG_USB)
case USB_HOST_SLOT:
dev->resource[0].start = USB_HOST_BASE;
dev->resource[0].end = USB_HOST_BASE+USB_BAR0_MEM_SIZE-1;
break;
#endif
}
}
int pcibios_plat_dev_init(struct pci_dev *dev)
{
return 0;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_ANY_ID,
bcm96348_fixup);
/*struct pci_fixup pcibios_fixups[] = {
{ PCI_FIXUP_FINAL, PCI_ANY_ID, PCI_ANY_ID, bcm96348_fixup },
{0}
};*/

278
target/linux/brcm63xx/files/arch/mips/pci/ops-bcm96348.c
View file

@ -1,278 +0,0 @@
/*
<:copyright-gpl
Copyright 2002 Broadcom Corp. All Rights Reserved.
This program is free software; you can distribute it and/or modify it
under the terms of the GNU General Public License (Version 2) as
published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
:>
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/addrspace.h>
#include <bcm_intr.h>
#include <bcm_map_part.h>
#include <6348_intr.h>
#include <6348_map_part.h>
#include <bcmpci.h>
#include <linux/delay.h>
#if defined(CONFIG_USB)
#if 0
#define DPRINT(x...) printk(x)
#else
#define DPRINT(x...)
#endif
static int
pci63xx_int_read(unsigned int devfn, int where, u32 * value, int size);
static int
pci63xx_int_write(unsigned int devfn, int where, u32 * value, int size);
static bool usb_mem_size_rd = FALSE;
static uint32 usb_mem_base = 0;
static uint32 usb_cfg_space_cmd_reg = 0;
#endif
static bool pci_mem_size_rd = FALSE;
static volatile MpiRegisters * mpi = (MpiRegisters *)(MPI_BASE);
static void mpi_SetupPciConfigAccess(uint32 addr)
{
mpi->l2pcfgctl = (DIR_CFG_SEL | DIR_CFG_USEREG | addr) & ~CONFIG_TYPE;
}
static void mpi_ClearPciConfigAccess(void)
{
mpi->l2pcfgctl = 0x00000000;
}
#if defined(CONFIG_USB)
/* --------------------------------------------------------------------------
Name: pci63xx_int_write
Abstract: PCI Config write on internal device(s)
-------------------------------------------------------------------------- */
static int
pci63xx_int_write(unsigned int devfn, int where, u32 * value, int size)
{
if (PCI_SLOT(devfn) != USB_HOST_SLOT) {
return PCIBIOS_SUCCESSFUL;
}
switch (size) {
case 1:
DPRINT("W => Slot: %d Where: %2X Len: %d Data: %02X\n",
PCI_SLOT(devfn), where, size, *value);
break;
case 2:
DPRINT("W => Slot: %d Where: %2X Len: %d Data: %04X\n",
PCI_SLOT(devfn), where, size, *value);
switch (where) {
case PCI_COMMAND:
usb_cfg_space_cmd_reg = *value;
break;
default:
break;
}
break;
case 4:
DPRINT("W => Slot: %d Where: %2X Len: %d Data: %08lX\n",
PCI_SLOT(devfn), where, size, *value);
switch (where) {
case PCI_BASE_ADDRESS_0:
if (*value == 0xffffffff) {
usb_mem_size_rd = TRUE;
} else {
usb_mem_base = *value;
}
break;
default:
break;
}
break;
default:
break;
}
return PCIBIOS_SUCCESSFUL;
}
/* --------------------------------------------------------------------------
Name: pci63xx_int_read
Abstract: PCI Config read on internal device(s)
-------------------------------------------------------------------------- */
static int
pci63xx_int_read(unsigned int devfn, int where, u32 * value, int size)
{
uint32 retValue = 0xFFFFFFFF;
if (PCI_SLOT(devfn) != USB_HOST_SLOT) {
return PCIBIOS_SUCCESSFUL;
}
// For now, this is specific to the USB Host controller. We can
// make it more general if we have to...
// Emulate PCI Config accesses
switch (where) {
case PCI_VENDOR_ID:
case PCI_DEVICE_ID:
retValue = PCI_VENDOR_ID_BROADCOM | 0x63000000;
break;
case PCI_COMMAND:
case PCI_STATUS:
retValue = (0x0006 << 16) | usb_cfg_space_cmd_reg;
break;
case PCI_CLASS_REVISION:
case PCI_CLASS_DEVICE:
retValue = (PCI_CLASS_SERIAL_USB << 16) | (0x10 << 8) | 0x01;
break;
case PCI_BASE_ADDRESS_0:
if (usb_mem_size_rd) {
retValue = USB_BAR0_MEM_SIZE;
} else {
if (usb_mem_base != 0)
retValue = usb_mem_base;
else
retValue = USB_HOST_BASE;
}
usb_mem_size_rd = FALSE;
break;
case PCI_CACHE_LINE_SIZE:
case PCI_LATENCY_TIMER:
retValue = 0;
break;
case PCI_HEADER_TYPE:
retValue = PCI_HEADER_TYPE_NORMAL;
break;
case PCI_SUBSYSTEM_VENDOR_ID:
retValue = PCI_VENDOR_ID_BROADCOM;
break;
case PCI_SUBSYSTEM_ID:
retValue = 0x6300;
break;
case PCI_INTERRUPT_LINE:
retValue = INTERRUPT_ID_USBH;
break;
default:
break;
}
switch (size) {
case 1:
*value = (retValue >> ((where & 3) << 3)) & 0xff;
DPRINT("R <= Slot: %d Where: %2X Len: %d Data: %02X\n",
PCI_SLOT(devfn), where, size, *value);
break;
case 2:
*value = (retValue >> ((where & 3) << 3)) & 0xffff;
DPRINT("R <= Slot: %d Where: %2X Len: %d Data: %04X\n",
PCI_SLOT(devfn), where, size, *value);
break;
case 4:
*value = retValue;
DPRINT("R <= Slot: %d Where: %2X Len: %d Data: %08lX\n",
PCI_SLOT(devfn), where, size, *value);
break;
default:
break;
}
return PCIBIOS_SUCCESSFUL;
}
#endif
static int bcm96348_pcibios_read(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 * val)
{
volatile unsigned char *ioBase = (unsigned char *)(mpi->l2piobase | KSEG1);
uint32 data;
#if defined(CONFIG_USB)
if (PCI_SLOT(devfn) == USB_HOST_SLOT)
return pci63xx_int_read(devfn, where, val, size);
#endif
mpi_SetupPciConfigAccess(BCM_PCI_CFG(PCI_SLOT(devfn), PCI_FUNC(devfn), where));
data = *(uint32 *)ioBase;
switch(size) {
case 1:
*val = (data >> ((where & 3) << 3)) & 0xff;
break;
case 2:
*val = (data >> ((where & 3) << 3)) & 0xffff;
break;
case 4:
*val = data;
/* Special case for reading PCI device range */
if ((where >= PCI_BASE_ADDRESS_0) && (where <= PCI_BASE_ADDRESS_5)) {
if (pci_mem_size_rd) {
/* bcm6348 PCI memory window minimum size is 64K */
*val &= PCI_SIZE_64K;
}
}
break;
default:
break;
}
pci_mem_size_rd = FALSE;
mpi_ClearPciConfigAccess();
return PCIBIOS_SUCCESSFUL;
}
static int bcm96348_pcibios_write(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 val)
{
volatile unsigned char *ioBase = (unsigned char *)(mpi->l2piobase | KSEG1);
uint32 data;
#if defined(CONFIG_USB)
if (PCI_SLOT(devfn) == USB_HOST_SLOT)
return pci63xx_int_write(devfn, where, &val, size);
#endif
mpi_SetupPciConfigAccess(BCM_PCI_CFG(PCI_SLOT(devfn), PCI_FUNC(devfn), where));
data = *(uint32 *)ioBase;
switch(size) {
case 1:
data = (data & ~(0xff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
break;
case 2:
data = (data & ~(0xffff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
break;
case 4:
data = val;
/* Special case for reading PCI device range */
if ((where >= PCI_BASE_ADDRESS_0) && (where <= PCI_BASE_ADDRESS_5)) {
if (val == 0xffffffff)
pci_mem_size_rd = TRUE;
}
break;
default:
break;
}
*(uint32 *)ioBase = data;
udelay(500);
mpi_ClearPciConfigAccess();
return PCIBIOS_SUCCESSFUL;
}
struct pci_ops bcm96348_pci_ops = {
.read = bcm96348_pcibios_read,
.write = bcm96348_pcibios_write
};

62
target/linux/brcm63xx/files/arch/mips/pci/pci-bcm96348.c
View file

@ -1,62 +0,0 @@
/*
<:copyright-gpl
Copyright 2002 Broadcom Corp. All Rights Reserved.
This program is free software; you can distribute it and/or modify it
under the terms of the GNU General Public License (Version 2) as
published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
:>
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <bcmpci.h>
static struct resource bcm_pci_io_resource = {
.name = "bcm96348 pci IO space",
.start = BCM_PCI_IO_BASE,
.end = BCM_PCI_IO_BASE + BCM_PCI_IO_SIZE_64KB - 1,
.flags = IORESOURCE_IO
};
static struct resource bcm_pci_mem_resource = {
.name = "bcm96348 pci memory space",
.start = BCM_PCI_MEM_BASE,
.end = BCM_PCI_MEM_BASE + BCM_PCI_MEM_SIZE_16MB - 1,
.flags = IORESOURCE_MEM
};
extern struct pci_ops bcm96348_pci_ops;
struct pci_controller bcm96348_controller = {
.pci_ops = &bcm96348_pci_ops,
.io_resource = &bcm_pci_io_resource,
.mem_resource = &bcm_pci_mem_resource,
};
static __init int bcm96348_pci_init(void)
{
/* Avoid ISA compat ranges. */
PCIBIOS_MIN_IO = 0x00000000;
PCIBIOS_MIN_MEM = 0x00000000;
/* Set I/O resource limits. */
ioport_resource.end = 0x1fffffff;
iomem_resource.end = 0xffffffff;
register_pci_controller(&bcm96348_controller);
return 0;
}
arch_initcall(bcm96348_pci_init);

1041
target/linux/brcm63xx/files/drivers/serial/bcm63xx_cons.c
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File diff suppressed because it is too large Load diff

189
target/linux/brcm63xx/files/include/asm-mips/cfe.h
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@ -1,189 +0,0 @@
/*
* Broadcom Common Firmware Environment (CFE) support
*
* Copyright 2000, 2001, 2002
* Broadcom Corporation. All rights reserved.
*
* Copyright (C) 2006 Michael Buesch
*
* Original Authors: Mitch Lichtenberg, Chris Demetriou
*
* This software is furnished under license and may be used and copied only
* in accordance with the following terms and conditions. Subject to these
* conditions, you may download, copy, install, use, modify and distribute
* modified or unmodified copies of this software in source and/or binary
* form. No title or ownership is transferred hereby.
*
* 1) Any source code used, modified or distributed must reproduce and
* retain this copyright notice and list of conditions as they appear in
* the source file.
*
* 2) No right is granted to use any trade name, trademark, or logo of
* Broadcom Corporation. The "Broadcom Corporation" name may not be
* used to endorse or promote products derived from this software
* without the prior written permission of Broadcom Corporation.
*
* 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
* FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
* LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef LINUX_CFE_API_H_
#define LINUX_CFE_API_H_
#include <linux/types.h>
#define CFE_MI_RESERVED 0 /* memory is reserved, do not use */
#define CFE_MI_AVAILABLE 1 /* memory is available */
#define CFE_FLG_WARMSTART 0x00000001
#define CFE_FLG_FULL_ARENA 0x00000001
#define CFE_FLG_ENV_PERMANENT 0x00000001
#define CFE_CPU_CMD_START 1
#define CFE_CPU_CMD_STOP 0
#define CFE_STDHANDLE_CONSOLE 0
#define CFE_DEV_NETWORK 1
#define CFE_DEV_DISK 2
#define CFE_DEV_FLASH 3
#define CFE_DEV_SERIAL 4
#define CFE_DEV_CPU 5
#define CFE_DEV_NVRAM 6
#define CFE_DEV_CLOCK 7
#define CFE_DEV_OTHER 8
#define CFE_DEV_MASK 0x0F
#define CFE_CACHE_FLUSH_D 1
#define CFE_CACHE_INVAL_I 2
#define CFE_CACHE_INVAL_D 4
#define CFE_CACHE_INVAL_L2 8
#define CFE_FWI_64BIT 0x00000001
#define CFE_FWI_32BIT 0x00000002
#define CFE_FWI_RELOC 0x00000004
#define CFE_FWI_UNCACHED 0x00000008
#define CFE_FWI_MULTICPU 0x00000010
#define CFE_FWI_FUNCSIM 0x00000020
#define CFE_FWI_RTLSIM 0x00000040
struct cfe_fwinfo {
s64 version; /* major, minor, eco version */
s64 totalmem; /* total installed mem */
s64 flags; /* various flags */
s64 boardid; /* board ID */
s64 bootarea_va; /* VA of boot area */
s64 bootarea_pa; /* PA of boot area */
s64 bootarea_size; /* size of boot area */
};
/* The public CFE API */
int cfe_present(void); /* Check if we booted from CFE. Returns bool */
int cfe_getticks(s64 *ticks);
int cfe_close(int handle);
int cfe_cpu_start(int cpu, void (*fn)(void), long sp, long gp, long a1);
int cfe_cpu_stop(int cpu);
int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen);
int cfe_enumdev(int idx, char *name, int namelen);
int cfe_enummem(int idx, int flags, u64 *start, u64 *length,
u64 *type);
int cfe_exit(int warm, int status);
int cfe_flushcache(int flags);
int cfe_getdevinfo(char *name);
int cfe_getenv(char *name, char *dest, int destlen);
int cfe_getfwinfo(struct cfe_fwinfo *info);
int cfe_getstdhandle(int handletype);
int cfe_inpstat(int handle);
int cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer,
int length, int *retlen, u64 offset);
int cfe_open(char *name);
int cfe_read(int handle, unsigned char *buffer, int length);
int cfe_readblk(int handle, s64 offset, unsigned char *buffer, int length);
int cfe_setenv(char *name, char *val);
int cfe_write(int handle, unsigned char *buffer, int length);
int cfe_writeblk(int handle, s64 offset, unsigned char *buffer,
int length);
/* High level API */
/* Print some information to CFE's console (most likely serial line) */
int cfe_printk(const char *fmt, ...) __attribute__((format(printf, 1, 2)));
int cfe_vprintk(const char *fmt, va_list args);
/* Error codes returned by the low API functions */
#define CFE_ISERR(errcode) (errcode < 0)
#define CFE_OK 0
#define CFE_ERR -1 /* generic error */
#define CFE_ERR_INV_COMMAND -2
#define CFE_ERR_EOF -3
#define CFE_ERR_IOERR -4
#define CFE_ERR_NOMEM -5
#define CFE_ERR_DEVNOTFOUND -6
#define CFE_ERR_DEVOPEN -7
#define CFE_ERR_INV_PARAM -8
#define CFE_ERR_ENVNOTFOUND -9
#define CFE_ERR_ENVREADONLY -10
#define CFE_ERR_NOTELF -11
#define CFE_ERR_NOT32BIT -12
#define CFE_ERR_WRONGENDIAN -13
#define CFE_ERR_BADELFVERS -14
#define CFE_ERR_NOTMIPS -15
#define CFE_ERR_BADELFFMT -16
#define CFE_ERR_BADADDR -17
#define CFE_ERR_FILENOTFOUND -18
#define CFE_ERR_UNSUPPORTED -19
#define CFE_ERR_HOSTUNKNOWN -20
#define CFE_ERR_TIMEOUT -21
#define CFE_ERR_PROTOCOLERR -22
#define CFE_ERR_NETDOWN -23
#define CFE_ERR_NONAMESERVER -24
#define CFE_ERR_NOHANDLES -25
#define CFE_ERR_ALREADYBOUND -26
#define CFE_ERR_CANNOTSET -27
#define CFE_ERR_NOMORE -28
#define CFE_ERR_BADFILESYS -29
#define CFE_ERR_FSNOTAVAIL -30
#define CFE_ERR_INVBOOTBLOCK -31
#define CFE_ERR_WRONGDEVTYPE -32
#define CFE_ERR_BBCHECKSUM -33
#define CFE_ERR_BOOTPROGCHKSUM -34
#define CFE_ERR_LDRNOTAVAIL -35
#define CFE_ERR_NOTREADY -36
#define CFE_ERR_GETMEM -37
#define CFE_ERR_SETMEM -38
#define CFE_ERR_NOTCONN -39
#define CFE_ERR_ADDRINUSE -40
#endif /* LINUX_CFE_API_H_ */

64
target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/6338_intr.h
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@ -1,64 +0,0 @@
/*
<:copyright-gpl
Copyright 2003 Broadcom Corp. All Rights Reserved.
This program is free software; you can distribute it and/or modify it
under the terms of the GNU General Public License (Version 2) as
published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
:>
*/
#ifndef __6338_INTR_H
#define __6338_INTR_H
/*=====================================================================*/
/* BCM6338 External Interrupt Level Assignments */
/*=====================================================================*/
#define INTERRUPT_ID_EXTERNAL_0 3
#define INTERRUPT_ID_EXTERNAL_1 4
#define INTERRUPT_ID_EXTERNAL_2 5
#define INTERRUPT_ID_EXTERNAL_3 6
/*=====================================================================*/
/* BCM6338 Timer Interrupt Level Assignments */
/*=====================================================================*/
#define MIPS_TIMER_INT 7
/*=====================================================================*/
/* Peripheral ISR Table Offset */
/*=====================================================================*/
#define INTERNAL_ISR_TABLE_OFFSET 8
/*=====================================================================*/
/* Logical Peripheral Interrupt IDs */
/*=====================================================================*/
#define INTERRUPT_ID_TIMER (INTERNAL_ISR_TABLE_OFFSET + 0)
#define INTERRUPT_ID_SPI (INTERNAL_ISR_TABLE_OFFSET + 1)
#define INTERRUPT_ID_UART (INTERNAL_ISR_TABLE_OFFSET + 2)
#define INTERRUPT_ID_DG (INTERNAL_ISR_TABLE_OFFSET + 4)
#define INTERRUPT_ID_ADSL (INTERNAL_ISR_TABLE_OFFSET + 5)
#define INTERRUPT_ID_ATM (INTERNAL_ISR_TABLE_OFFSET + 6)
#define INTERRUPT_ID_USBS (INTERNAL_ISR_TABLE_OFFSET + 7)
#define INTERRUPT_ID_EMAC1 (INTERNAL_ISR_TABLE_OFFSET + 8)
#define INTERRUPT_ID_EPHY (INTERNAL_ISR_TABLE_OFFSET + 9)
#define INTERRUPT_ID_SDRAM (INTERNAL_ISR_TABLE_OFFSET + 10)
#define INTERRUPT_ID_USB_CNTL_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 11)
#define INTERRUPT_ID_USB_CNTL_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 12)
#define INTERRUPT_ID_USB_BULK_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 13)
#define INTERRUPT_ID_USB_BULK_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 14)
#define INTERRUPT_ID_EMAC1_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 15)
#define INTERRUPT_ID_EMAC1_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 16)
#define INTERRUPT_ID_SDIO (INTERNAL_ISR_TABLE_OFFSET + 17)
#endif /* __BCM6338_H */

334
target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/6338_map_part.h
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@ -1,334 +0,0 @@
/*
<:copyright-gpl
Copyright 2004 Broadcom Corp. All Rights Reserved.
This program is free software; you can distribute it and/or modify it
under the terms of the GNU General Public License (Version 2) as
published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
:>
*/
#ifndef __BCM6338_MAP_H
#define __BCM6338_MAP_H
#include "bcmtypes.h"
#define PERF_BASE 0xfffe0000
#define TIMR_BASE 0xfffe0200
#define UART_BASE 0xfffe0300
#define GPIO_BASE 0xfffe0400
#define SPI_BASE 0xfffe0c00
typedef struct PerfControl {
uint32 RevID;
uint16 testControl;
uint16 blkEnables;
#define EMAC_CLK_EN 0x0010
#define USBS_CLK_EN 0x0010
#define SAR_CLK_EN 0x0020
#define SPI_CLK_EN 0x0200
uint32 pll_control;
#define SOFT_RESET 0x00000001
uint32 IrqMask;
uint32 IrqStatus;
uint32 ExtIrqCfg;
#define EI_SENSE_SHFT 0
#define EI_STATUS_SHFT 5
#define EI_CLEAR_SHFT 10
#define EI_MASK_SHFT 15
#define EI_INSENS_SHFT 20
#define EI_LEVEL_SHFT 25
uint32 unused[4]; /* (18) */
uint32 BlockSoftReset; /* (28) */
#define BSR_SPI 0x00000001
#define BSR_EMAC 0x00000004
#define BSR_USBH 0x00000008
#define BSR_USBS 0x00000010
#define BSR_ADSL 0x00000020
#define BSR_DMAMEM 0x00000040
#define BSR_SAR 0x00000080
#define BSR_ACLC 0x00000100
#define BSR_ADSL_MIPS_PLL 0x00000400
#define BSR_ALL_BLOCKS \
(BSR_SPI | BSR_EMAC | BSR_USBH | BSR_USBS | BSR_ADSL | BSR_DMAMEM | \
BSR_SAR | BSR_ACLC | BSR_ADSL_MIPS_PLL)
} PerfControl;
#define PERF ((volatile PerfControl * const) PERF_BASE)
typedef struct Timer {
uint16 unused0;
byte TimerMask;
#define TIMER0EN 0x01
#define TIMER1EN 0x02
#define TIMER2EN 0x04
byte TimerInts;
#define TIMER0 0x01
#define TIMER1 0x02
#define TIMER2 0x04
#define WATCHDOG 0x08
uint32 TimerCtl0;
uint32 TimerCtl1;
uint32 TimerCtl2;
#define TIMERENABLE 0x80000000
#define RSTCNTCLR 0x40000000
uint32 TimerCnt0;
uint32 TimerCnt1;
uint32 TimerCnt2;
uint32 WatchDogDefCount;
/* Write 0xff00 0x00ff to Start timer
* Write 0xee00 0x00ee to Stop and re-load default count
* Read from this register returns current watch dog count
*/
uint32 WatchDogCtl;
/* Number of 40-MHz ticks for WD Reset pulse to last */
uint32 WDResetCount;
} Timer;
#define TIMER ((volatile Timer * const) TIMR_BASE)
typedef struct UartChannel {
byte unused0;
byte control;
#define BRGEN 0x80 /* Control register bit defs */
#define TXEN 0x40
#define RXEN 0x20
#define LOOPBK 0x10
#define TXPARITYEN 0x08
#define TXPARITYEVEN 0x04
#define RXPARITYEN 0x02
#define RXPARITYEVEN 0x01
byte config;
#define XMITBREAK 0x40
#define BITS5SYM 0x00
#define BITS6SYM 0x10
#define BITS7SYM 0x20
#define BITS8SYM 0x30
#define ONESTOP 0x07
#define TWOSTOP 0x0f
/* 4-LSBS represent STOP bits/char
* in 1/8 bit-time intervals. Zero
* represents 1/8 stop bit interval.
* Fifteen represents 2 stop bits.
*/
byte fifoctl;
#define RSTTXFIFOS 0x80
#define RSTRXFIFOS 0x40
/* 5-bit TimeoutCnt is in low bits of this register.
* This count represents the number of characters
* idle times before setting receive Irq when below threshold
*/
uint32 baudword;
/* When divide SysClk/2/(1+baudword) we should get 32*bit-rate
*/
byte txf_levl; /* Read-only fifo depth */
byte rxf_levl; /* Read-only fifo depth */
byte fifocfg; /* Upper 4-bits are TxThresh, Lower are
* RxThreshold. Irq can be asserted
* when rx fifo> thresh, txfifo<thresh
*/
byte prog_out; /* Set value of DTR (Bit0), RTS (Bit1)
* if these bits are also enabled to GPIO_o
*/
#define DTREN 0x01
#define RTSEN 0x02
byte unused1;
byte DeltaIPEdgeNoSense; /* Low 4-bits, set corr bit to 1 to
* detect irq on rising AND falling
* edges for corresponding GPIO_i
* if enabled (edge insensitive)
*/
byte DeltaIPConfig_Mask; /* Upper 4 bits: 1 for posedge sense
* 0 for negedge sense if
* not configured for edge
* insensitive (see above)
* Lower 4 bits: Mask to enable change
* detection IRQ for corresponding
* GPIO_i
*/
byte DeltaIP_SyncIP; /* Upper 4 bits show which bits
* have changed (may set IRQ).
* read automatically clears bit
* Lower 4 bits are actual status
*/
uint16 intMask; /* Same Bit defs for Mask and status */
uint16 intStatus;
#define DELTAIP 0x0001
#define TXUNDERR 0x0002
#define TXOVFERR 0x0004
#define TXFIFOTHOLD 0x0008
#define TXREADLATCH 0x0010
#define TXFIFOEMT 0x0020
#define RXUNDERR 0x0040
#define RXOVFERR 0x0080
#define RXTIMEOUT 0x0100
#define RXFIFOFULL 0x0200
#define RXFIFOTHOLD 0x0400
#define RXFIFONE 0x0800
#define RXFRAMERR 0x1000
#define RXPARERR 0x2000
#define RXBRK 0x4000
uint16 unused2;
uint16 Data; /* Write to TX, Read from RX */
/* bits 11:8 are BRK,PAR,FRM errors */
uint32 unused3;
uint32 unused4;
} Uart;
#define UART ((volatile Uart * const) UART_BASE)
typedef struct GpioControl {
uint32 unused0;
uint32 GPIODir; /* bits 7:0 */
uint32 unused1;
uint32 GPIOio; /* bits 7:0 */
uint32 LEDCtrl;
#define LED3_STROBE 0x08000000
#define LED2_STROBE 0x04000000
#define LED1_STROBE 0x02000000
#define LED0_STROBE 0x01000000
#define LED_TEST 0x00010000
#define LED3_DISABLE_LINK_ACT 0x00008000
#define LED2_DISABLE_LINK_ACT 0x00004000
#define LED1_DISABLE_LINK_ACT 0x00002000
#define LED0_DISABLE_LINK_ACT 0x00001000
#define LED_INTERVAL_SET_MASK 0x00000f00
#define LED_INTERVAL_SET_320MS 0x00000500
#define LED_INTERVAL_SET_160MS 0x00000400
#define LED_INTERVAL_SET_80MS 0x00000300
#define LED_INTERVAL_SET_40MS 0x00000200
#define LED_INTERVAL_SET_20MS 0x00000100
#define LED3_ON 0x00000080
#define LED2_ON 0x00000040
#define LED1_ON 0x00000020
#define LED0_ON 0x00000010
#define LED3_ENABLE 0x00000008
#define LED2_ENABLE 0x00000004
#define LED1_ENABLE 0x00000002
#define LED0_ENABLE 0x00000001
uint32 SpiSlaveCfg;
#define SPI_SLAVE_RESET 0x00010000
#define SPI_RESTRICT 0x00000400
#define SPI_DELAY_DISABLE 0x00000200
#define SPI_PROBE_MUX_SEL_MASK 0x000001e0
#define SPI_SER_ADDR_CFG_MASK 0x0000000c
#define SPI_MODE 0x00000001
uint32 vRegConfig;
} GpioControl;
#define GPIO ((volatile GpioControl * const) GPIO_BASE)
/* Number to mask conversion macro used for GPIODir and GPIOio */
#define GPIO_NUM_MAX_BITS_MASK 0x0f
#define GPIO_NUM_TO_MASK(X) (1 << ((X) & GPIO_NUM_MAX_BITS_MASK))
/*
** Spi Controller
*/
typedef struct SpiControl {
uint16 spiCmd; /* (0x0): SPI command */
#define SPI_CMD_START_IMMEDIATE 3
#define SPI_CMD_COMMAND_SHIFT 0
#define SPI_CMD_DEVICE_ID_SHIFT 4
#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
byte spiIntStatus; /* (0x2): SPI interrupt status */
byte spiMaskIntStatus; /* (0x3): SPI masked interrupt status */
byte spiIntMask; /* (0x4): SPI interrupt mask */
#define SPI_INTR_CMD_DONE 0x01
#define SPI_INTR_CLEAR_ALL 0x1f
byte spiStatus; /* (0x5): SPI status */
byte spiClkCfg; /* (0x6): SPI clock configuration */
byte spiFillByte; /* (0x7): SPI fill byte */
byte unused0;
byte spiMsgTail; /* (0x9): msgtail */
byte unused1;
byte spiRxTail; /* (0xB): rxtail */
uint32 unused2[13]; /* (0x0c - 0x3c) reserved */
byte spiMsgCtl; /* (0x40) control byte */
#define HALF_DUPLEX_W 1
#define HALF_DUPLEX_R 2
#define SPI_MSG_TYPE_SHIFT 6
#define SPI_BYTE_CNT_SHIFT 0
byte spiMsgData[63]; /* (0x41 - 0x7f) msg data */
byte spiRxDataFifo[64]; /* (0x80 - 0xbf) rx data */
byte unused3[64]; /* (0xc0 - 0xff) reserved */
} SpiControl;
#define SPI ((volatile SpiControl * const) SPI_BASE)
/*
** External Bus Interface
*/
typedef struct EbiChipSelect {
uint32 base; /* base address in upper 24 bits */
#define EBI_SIZE_8K 0
#define EBI_SIZE_16K 1
#define EBI_SIZE_32K 2
#define EBI_SIZE_64K 3
#define EBI_SIZE_128K 4
#define EBI_SIZE_256K 5
#define EBI_SIZE_512K 6
#define EBI_SIZE_1M 7
#define EBI_SIZE_2M 8
#define EBI_SIZE_4M 9
#define EBI_SIZE_8M 10
#define EBI_SIZE_16M 11
#define EBI_SIZE_32M 12
#define EBI_SIZE_64M 13
#define EBI_SIZE_128M 14
#define EBI_SIZE_256M 15
uint32 config;
#define EBI_ENABLE 0x00000001 /* .. enable this range */
#define EBI_WAIT_STATES 0x0000000e /* .. mask for wait states */
#define EBI_WTST_SHIFT 1 /* .. for shifting wait states */
#define EBI_WORD_WIDE 0x00000010 /* .. 16-bit peripheral, else 8 */
#define EBI_WREN 0x00000020 /* enable posted writes */
#define EBI_POLARITY 0x00000040 /* .. set to invert something,
** don't know what yet */
#define EBI_TS_TA_MODE 0x00000080 /* .. use TS/TA mode */
#define EBI_TS_SEL 0x00000100 /* .. drive tsize, not bs_b */
#define EBI_FIFO 0x00000200 /* .. use fifo */
#define EBI_RE 0x00000400 /* .. Reverse Endian */
} EbiChipSelect;
typedef struct MpiRegisters {
EbiChipSelect cs[1]; /* size chip select configuration */
} MpiRegisters;
#define MPI ((volatile MpiRegisters * const) MPI_BASE)
#endif

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/*
<:copyright-gpl
Copyright 2002 Broadcom Corp. All Rights Reserved.
This program is free software; you can distribute it and/or modify it
under the terms of the GNU General Public License (Version 2) as
published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
:>
*/
#ifndef __6345_INTR_H
#define __6345_INTR_H
/*=====================================================================*/
/* BCM6345 External Interrupt Level Assignments */
/*=====================================================================*/
#define INTERRUPT_ID_EXTERNAL_0 3
#define INTERRUPT_ID_EXTERNAL_1 4
#define INTERRUPT_ID_EXTERNAL_2 5
#define INTERRUPT_ID_EXTERNAL_3 6
/*=====================================================================*/
/* BCM6345 Timer Interrupt Level Assignments */
/*=====================================================================*/
#define MIPS_TIMER_INT 7
/*=====================================================================*/
/* Peripheral ISR Table Offset */
/*=====================================================================*/
#define INTERNAL_ISR_TABLE_OFFSET 8
#define DMA_ISR_TABLE_OFFSET (INTERNAL_ISR_TABLE_OFFSET + 13)
/*=====================================================================*/
/* Logical Peripheral Interrupt IDs */
/*=====================================================================*/
/* Internal peripheral interrupt IDs */
#define INTERRUPT_ID_TIMER (INTERNAL_ISR_TABLE_OFFSET + 0)
#define INTERRUPT_ID_UART (INTERNAL_ISR_TABLE_OFFSET + 2)
#define INTERRUPT_ID_ADSL (INTERNAL_ISR_TABLE_OFFSET + 3)
#define INTERRUPT_ID_ATM (INTERNAL_ISR_TABLE_OFFSET + 4)
#define INTERRUPT_ID_USB (INTERNAL_ISR_TABLE_OFFSET + 5)
#define INTERRUPT_ID_EMAC (INTERNAL_ISR_TABLE_OFFSET + 8)
#define INTERRUPT_ID_EPHY (INTERNAL_ISR_TABLE_OFFSET + 12)
/* DMA channel interrupt IDs */
#define INTERRUPT_ID_EMAC_RX_CHAN (DMA_ISR_TABLE_OFFSET + EMAC_RX_CHAN)
#define INTERRUPT_ID_EMAC_TX_CHAN (DMA_ISR_TABLE_OFFSET + EMAC_TX_CHAN)
#define INTERRUPT_ID_EBI_RX_CHAN (DMA_ISR_TABLE_OFFSET + EBI_RX_CHAN)
#define INTERRUPT_ID_EBI_TX_CHAN (DMA_ISR_TABLE_OFFSET + EBI_TX_CHAN)
#define INTERRUPT_ID_RESERVED_RX_CHAN (DMA_ISR_TABLE_OFFSET + RESERVED_RX_CHAN)
#define INTERRUPT_ID_RESERVED_TX_CHAN (DMA_ISR_TABLE_OFFSET + RESERVED_TX_CHAN)
#define INTERRUPT_ID_USB_BULK_RX_CHAN (DMA_ISR_TABLE_OFFSET + USB_BULK_RX_CHAN)
#define INTERRUPT_ID_USB_BULK_TX_CHAN (DMA_ISR_TABLE_OFFSET + USB_BULK_TX_CHAN)
#define INTERRUPT_ID_USB_CNTL_RX_CHAN (DMA_ISR_TABLE_OFFSET + USB_CNTL_RX_CHAN)
#define INTERRUPT_ID_USB_CNTL_TX_CHAN (DMA_ISR_TABLE_OFFSET + USB_CNTL_TX_CHAN)
#define INTERRUPT_ID_USB_ISO_RX_CHAN (DMA_ISR_TABLE_OFFSET + USB_ISO_RX_CHAN)
#define INTERRUPT_ID_USB_ISO_TX_CHAN (DMA_ISR_TABLE_OFFSET + USB_ISO_TX_CHAN)
#endif /* __BCM6345_H */

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/*
<:copyright-gpl
Copyright 2002 Broadcom Corp. All Rights Reserved.
This program is free software; you can distribute it and/or modify it
under the terms of the GNU General Public License (Version 2) as
published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
:>
*/
#ifndef __BCM6345_MAP_H
#define __BCM6345_MAP_H
#include "bcmtypes.h"
#include "6345_intr.h"
typedef struct IntControl {
uint32 RevID;
uint16 testControl;
uint16 blkEnables;
#define USB_CLK_EN 0x0100
#define EMAC_CLK_EN 0x0080
#define UART_CLK_EN 0x0008
#define CPU_CLK_EN 0x0001
uint32 pll_control;
#define SOFT_RESET 0x00000001
uint32 IrqMask;
uint32 IrqStatus;
uint32 ExtIrqCfg;
#define EI_SENSE_SHFT 0
#define EI_STATUS_SHFT 4
#define EI_CLEAR_SHFT 8
#define EI_MASK_SHFT 12
#define EI_INSENS_SHFT 16
#define EI_LEVEL_SHFT 20
} IntControl;
#define INTC_BASE 0xfffe0000
#define PERF ((volatile IntControl * const) INTC_BASE)
#define TIMR_BASE 0xfffe0200
typedef struct Timer {
uint16 unused0;
byte TimerMask;
#define TIMER0EN 0x01
#define TIMER1EN 0x02
#define TIMER2EN 0x04
byte TimerInts;
#define TIMER0 0x01
#define TIMER1 0x02
#define TIMER2 0x04
#define WATCHDOG 0x08
uint32 TimerCtl0;
uint32 TimerCtl1;
uint32 TimerCtl2;
#define TIMERENABLE 0x80000000
#define RSTCNTCLR 0x40000000
uint32 TimerCnt0;
uint32 TimerCnt1;
uint32 TimerCnt2;
uint32 WatchDogDefCount;
/* Write 0xff00 0x00ff to Start timer
* Write 0xee00 0x00ee to Stop and re-load default count
* Read from this register returns current watch dog count
*/
uint32 WatchDogCtl;
/* Number of 40-MHz ticks for WD Reset pulse to last */
uint32 WDResetCount;
} Timer;
#define TIMER ((volatile Timer * const) TIMR_BASE)
typedef struct UartChannel {
byte unused0;
byte control;
#define BRGEN 0x80 /* Control register bit defs */
#define TXEN 0x40
#define RXEN 0x20
#define TXPARITYEN 0x08
#define TXPARITYEVEN 0x04
#define RXPARITYEN 0x02
#define RXPARITYEVEN 0x01
byte config;
#define BITS5SYM 0x00
#define BITS6SYM 0x10
#define BITS7SYM 0x20
#define BITS8SYM 0x30
#define XMITBREAK 0x40
#define ONESTOP 0x07
#define TWOSTOP 0x0f
byte fifoctl;
#define RSTTXFIFOS 0x80
#define RSTRXFIFOS 0x40
uint32 baudword;
byte txf_levl;
byte rxf_levl;
byte fifocfg;
byte prog_out;
byte unused1;
byte DeltaIPEdgeNoSense;
byte DeltaIPConfig_Mask;
byte DeltaIP_SyncIP;
uint16 intMask;
uint16 intStatus;
#define TXUNDERR 0x0002
#define TXOVFERR 0x0004
#define TXFIFOEMT 0x0020
#define RXOVFERR 0x0080
#define RXFIFONE 0x0800
#define RXFRAMERR 0x1000
#define RXPARERR 0x2000
#define RXBRK 0x4000
uint16 unused2;
uint16 Data;
uint32 unused3;
uint32 unused4;
} Uart;
#define UART_BASE 0xfffe0300
#define UART ((volatile Uart * const) UART_BASE)
typedef struct GpioControl {
uint16 unused0;
byte unused1;
byte TBusSel;
uint16 unused2;
uint16 GPIODir;
byte unused3;
byte Leds;
uint16 GPIOio;
uint32 UartCtl;
} GpioControl;
#define GPIO_BASE 0xfffe0400
#define GPIO ((volatile GpioControl * const) GPIO_BASE)
#define GPIO_NUM_MAX_BITS_MASK 0x0f
#define GPIO_NUM_TO_MASK(X) (1 << ((X) & GPIO_NUM_MAX_BITS_MASK))
#endif

74
target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/6348_intr.h
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/*
<:copyright-gpl
Copyright 2003 Broadcom Corp. All Rights Reserved.
This program is free software; you can distribute it and/or modify it
under the terms of the GNU General Public License (Version 2) as
published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
:>
*/
#ifndef __6348_INTR_H
#define __6348_INTR_H
/*=====================================================================*/
/* BCM6348 External Interrupt Level Assignments */
/*=====================================================================*/
#define INTERRUPT_ID_EXTERNAL_0 3
#define INTERRUPT_ID_EXTERNAL_1 4
#define INTERRUPT_ID_EXTERNAL_2 5
#define INTERRUPT_ID_EXTERNAL_3 6
/*=====================================================================*/
/* BCM6348 Timer Interrupt Level Assignments */
/*=====================================================================*/
#define MIPS_TIMER_INT 7
/*=====================================================================*/
/* Peripheral ISR Table Offset */
/*=====================================================================*/
#define INTERNAL_ISR_TABLE_OFFSET 8
/*=====================================================================*/
/* Logical Peripheral Interrupt IDs */
/*=====================================================================*/
#define INTERRUPT_ID_TIMER (INTERNAL_ISR_TABLE_OFFSET + 0)
#define INTERRUPT_ID_SPI (INTERNAL_ISR_TABLE_OFFSET + 1)
#define INTERRUPT_ID_UART (INTERNAL_ISR_TABLE_OFFSET + 2)
#define INTERRUPT_ID_ADSL (INTERNAL_ISR_TABLE_OFFSET + 4)
#define INTERRUPT_ID_ATM (INTERNAL_ISR_TABLE_OFFSET + 5)
#define INTERRUPT_ID_USBS (INTERNAL_ISR_TABLE_OFFSET + 6)
#define INTERRUPT_ID_EMAC2 (INTERNAL_ISR_TABLE_OFFSET + 7)
#define INTERRUPT_ID_EMAC1 (INTERNAL_ISR_TABLE_OFFSET + 8)
#define INTERRUPT_ID_EPHY (INTERNAL_ISR_TABLE_OFFSET + 9)
#define INTERRUPT_ID_M2M (INTERNAL_ISR_TABLE_OFFSET + 10)
#define INTERRUPT_ID_ACLC (INTERNAL_ISR_TABLE_OFFSET + 11)
#define INTERRUPT_ID_USBH (INTERNAL_ISR_TABLE_OFFSET + 12)
#define INTERRUPT_ID_SDRAM (INTERNAL_ISR_TABLE_OFFSET + 13)
#define INTERRUPT_ID_USB_CNTL_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 14)
#define INTERRUPT_ID_USB_CNTL_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 15)
#define INTERRUPT_ID_USB_BULK_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 16)
#define INTERRUPT_ID_USB_BULK_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 17)
#define INTERRUPT_ID_USB_ISO_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 18)
#define INTERRUPT_ID_USB_ISO_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 19)
#define INTERRUPT_ID_EMAC1_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 20)
#define INTERRUPT_ID_EMAC1_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 21)
#define INTERRUPT_ID_EMAC2_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 22)
#define INTERRUPT_ID_EMAC2_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 23)
#define INTERRUPT_ID_MPI (INTERNAL_ISR_TABLE_OFFSET + 24)
#define INTERRUPT_ID_DG (INTERNAL_ISR_TABLE_OFFSET + 25)
#endif /* __BCM6348_H */

500
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/*
<:copyright-gpl
Copyright 2002 Broadcom Corp. All Rights Reserved.
This program is free software; you can distribute it and/or modify it
under the terms of the GNU General Public License (Version 2) as
published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
:>
*/
#ifndef __BCM6348_MAP_H
#define __BCM6348_MAP_H
#include "bcmtypes.h"
#define PERF_BASE 0xfffe0000
#define TIMR_BASE 0xfffe0200
#define UART_BASE 0xfffe0300
#define GPIO_BASE 0xfffe0400
#define MPI_BASE 0xfffe2000 /* MPI control registers */
#define USB_HOST_BASE 0xfffe1b00 /* USB host registers */
#define USB_HOST_NON_OHCI 0xfffe1c00 /* USB host non-OHCI registers */
typedef struct PerfControl {
uint32 RevID;
uint16 testControl;
uint16 blkEnables;
#define EMAC_CLK_EN 0x0010
#define SAR_CLK_EN 0x0020
#define USBS_CLK_EN 0x0040
#define USBH_CLK_EN 0x0100
uint32 pll_control;
#define SOFT_RESET 0x00000001
uint32 IrqMask;
uint32 IrqStatus;
uint32 ExtIrqCfg;
#define EI_SENSE_SHFT 0
#define EI_STATUS_SHFT 5
#define EI_CLEAR_SHFT 10
#define EI_MASK_SHFT 15
#define EI_INSENS_SHFT 20
#define EI_LEVEL_SHFT 25
uint32 unused[4]; /* (18) */
uint32 BlockSoftReset; /* (28) */
#define BSR_SPI 0x00000001
#define BSR_EMAC 0x00000004
#define BSR_USBH 0x00000008
#define BSR_USBS 0x00000010
#define BSR_ADSL 0x00000020
#define BSR_DMAMEM 0x00000040
#define BSR_SAR 0x00000080
#define BSR_ACLC 0x00000100
#define BSR_ADSL_MIPS_PLL 0x00000400
#define BSR_ALL_BLOCKS \
(BSR_SPI | BSR_EMAC | BSR_USBH | BSR_USBS | BSR_ADSL | BSR_DMAMEM | \
BSR_SAR | BSR_ACLC | BSR_ADSL_MIPS_PLL)
uint32 unused2[2]; /* (2c) */
uint32 PllStrap; /* (34) */
#define PLL_N1_SHFT 20
#define PLL_N1_MASK (7<<PLL_N1_SHFT)
#define PLL_N2_SHFT 15
#define PLL_N2_MASK (0x1f<<PLL_N2_SHFT)
#define PLL_M1_REF_SHFT 12
#define PLL_M1_REF_MASK (7<<PLL_M1_REF_SHFT)
#define PLL_M2_REF_SHFT 9
#define PLL_M2_REF_MASK (7<<PLL_M2_REF_SHFT)
#define PLL_M1_CPU_SHFT 6
#define PLL_M1_CPU_MASK (7<<PLL_M1_CPU_SHFT)
#define PLL_M1_BUS_SHFT 3
#define PLL_M1_BUS_MASK (7<<PLL_M1_BUS_SHFT)
#define PLL_M2_BUS_SHFT 0
#define PLL_M2_BUS_MASK (7<<PLL_M2_BUS_SHFT)
} PerfControl;
#define PERF ((volatile PerfControl * const) PERF_BASE)
typedef struct Timer {
uint16 unused0;
byte TimerMask;
#define TIMER0EN 0x01
#define TIMER1EN 0x02
#define TIMER2EN 0x04
byte TimerInts;
#define TIMER0 0x01
#define TIMER1 0x02
#define TIMER2 0x04
#define WATCHDOG 0x08
uint32 TimerCtl0;
uint32 TimerCtl1;
uint32 TimerCtl2;
#define TIMERENABLE 0x80000000
#define RSTCNTCLR 0x40000000
uint32 TimerCnt0;
uint32 TimerCnt1;
uint32 TimerCnt2;
uint32 WatchDogDefCount;
/* Write 0xff00 0x00ff to Start timer
* Write 0xee00 0x00ee to Stop and re-load default count
* Read from this register returns current watch dog count
*/
uint32 WatchDogCtl;
/* Number of 40-MHz ticks for WD Reset pulse to last */
uint32 WDResetCount;
} Timer;
#define TIMER ((volatile Timer * const) TIMR_BASE)
typedef struct UartChannel {
byte unused0;
byte control;
#define BRGEN 0x80 /* Control register bit defs */
#define TXEN 0x40
#define RXEN 0x20
#define LOOPBK 0x10
#define TXPARITYEN 0x08
#define TXPARITYEVEN 0x04
#define RXPARITYEN 0x02
#define RXPARITYEVEN 0x01
byte config;
#define XMITBREAK 0x40
#define BITS5SYM 0x00
#define BITS6SYM 0x10
#define BITS7SYM 0x20
#define BITS8SYM 0x30
#define ONESTOP 0x07
#define TWOSTOP 0x0f
/* 4-LSBS represent STOP bits/char
* in 1/8 bit-time intervals. Zero
* represents 1/8 stop bit interval.
* Fifteen represents 2 stop bits.
*/
byte fifoctl;
#define RSTTXFIFOS 0x80
#define RSTRXFIFOS 0x40
/* 5-bit TimeoutCnt is in low bits of this register.
* This count represents the number of characters
* idle times before setting receive Irq when below threshold
*/
uint32 baudword;
/* When divide SysClk/2/(1+baudword) we should get 32*bit-rate
*/
byte txf_levl; /* Read-only fifo depth */
byte rxf_levl; /* Read-only fifo depth */
byte fifocfg; /* Upper 4-bits are TxThresh, Lower are
* RxThreshold. Irq can be asserted
* when rx fifo> thresh, txfifo<thresh
*/
byte prog_out; /* Set value of DTR (Bit0), RTS (Bit1)
* if these bits are also enabled to GPIO_o
*/
#define DTREN 0x01
#define RTSEN 0x02
byte unused1;
byte DeltaIPEdgeNoSense; /* Low 4-bits, set corr bit to 1 to
* detect irq on rising AND falling
* edges for corresponding GPIO_i
* if enabled (edge insensitive)
*/
byte DeltaIPConfig_Mask; /* Upper 4 bits: 1 for posedge sense
* 0 for negedge sense if
* not configured for edge
* insensitive (see above)
* Lower 4 bits: Mask to enable change
* detection IRQ for corresponding
* GPIO_i
*/
byte DeltaIP_SyncIP; /* Upper 4 bits show which bits
* have changed (may set IRQ).
* read automatically clears bit
* Lower 4 bits are actual status
*/
uint16 intMask; /* Same Bit defs for Mask and status */
uint16 intStatus;
#define DELTAIP 0x0001
#define TXUNDERR 0x0002
#define TXOVFERR 0x0004
#define TXFIFOTHOLD 0x0008
#define TXREADLATCH 0x0010
#define TXFIFOEMT 0x0020
#define RXUNDERR 0x0040
#define RXOVFERR 0x0080
#define RXTIMEOUT 0x0100
#define RXFIFOFULL 0x0200
#define RXFIFOTHOLD 0x0400
#define RXFIFONE 0x0800
#define RXFRAMERR 0x1000
#define RXPARERR 0x2000
#define RXBRK 0x4000
uint16 unused2;
uint16 Data; /* Write to TX, Read from RX */
/* bits 11:8 are BRK,PAR,FRM errors */
uint32 unused3;
uint32 unused4;
} Uart;
#define UART ((volatile Uart * const) UART_BASE)
typedef struct GpioControl {
uint32 GPIODir_high; /* bits 36:32 */
uint32 GPIODir; /* bits 31:00 */
uint32 GPIOio_high; /* bits 36:32 */
uint32 GPIOio; /* bits 31:00 */
uint32 LEDCtrl;
#define LED3_STROBE 0x08000000
#define LED2_STROBE 0x04000000
#define LED1_STROBE 0x02000000
#define LED0_STROBE 0x01000000
#define LED_TEST 0x00010000
#define LED3_DISABLE_LINK_ACT 0x00008000
#define LED2_DISABLE_LINK_ACT 0x00004000
#define LED1_DISABLE_LINK_ACT 0x00002000
#define LED0_DISABLE_LINK_ACT 0x00001000
#define LED_INTERVAL_SET_MASK 0x00000f00
#define LED_INTERVAL_SET_320MS 0x00000500
#define LED_INTERVAL_SET_160MS 0x00000400
#define LED_INTERVAL_SET_80MS 0x00000300
#define LED_INTERVAL_SET_40MS 0x00000200
#define LED_INTERVAL_SET_20MS 0x00000100
#define LED3_ON 0x00000080
#define LED2_ON 0x00000040
#define LED1_ON 0x00000020
#define LED0_ON 0x00000010
#define LED3_ENABLE 0x00000008
#define LED2_ENABLE 0x00000004
#define LED1_ENABLE 0x00000002
#define LED0_ENABLE 0x00000001
uint32 SpiSlaveCfg;
#define SPI_SLAVE_RESET 0x00010000
#define SPI_RESTRICT 0x00000400
#define SPI_DELAY_DISABLE 0x00000200
#define SPI_PROBE_MUX_SEL_MASK 0x000001e0
#define SPI_SER_ADDR_CFG_MASK 0x0000000c
#define SPI_MODE 0x00000001
uint32 GPIOMode;
#define GROUP4_DIAG 0x00090000
#define GROUP4_UTOPIA 0x00080000
#define GROUP4_LEGACY_LED 0x00030000
#define GROUP4_MII_SNOOP 0x00020000
#define GROUP4_EXT_EPHY 0x00010000
#define GROUP3_DIAG 0x00009000
#define GROUP3_UTOPIA 0x00008000
#define GROUP3_EXT_MII 0x00007000
#define GROUP2_DIAG 0x00000900
#define GROUP2_PCI 0x00000500
#define GROUP1_DIAG 0x00000090
#define GROUP1_UTOPIA 0x00000080
#define GROUP1_SPI_UART 0x00000060
#define GROUP1_SPI_MASTER 0x00000060
#define GROUP1_MII_PCCARD 0x00000040
#define GROUP1_MII_SNOOP 0x00000020
#define GROUP1_EXT_EPHY 0x00000010
#define GROUP0_DIAG 0x00000009
#define GROUP0_EXT_MII 0x00000007
} GpioControl;
#define GPIO ((volatile GpioControl * const) GPIO_BASE)
/* Number to mask conversion macro used for GPIODir and GPIOio */
#define GPIO_NUM_TOTAL_BITS_MASK 0x3f
#define GPIO_NUM_MAX_BITS_MASK 0x1f
#define GPIO_NUM_TO_MASK(X) ( (((X) & GPIO_NUM_TOTAL_BITS_MASK) < 32) ? (1 << ((X) & GPIO_NUM_MAX_BITS_MASK)) : (0) )
/* Number to mask conversion macro used for GPIODir_high and GPIOio_high */
#define GPIO_NUM_MAX_BITS_MASK_HIGH 0x07
#define GPIO_NUM_TO_MASK_HIGH(X) ( (((X) & GPIO_NUM_TOTAL_BITS_MASK) >= 32) ? (1 << ((X-32) & GPIO_NUM_MAX_BITS_MASK_HIGH)) : (0) )
/*
** External Bus Interface
*/
typedef struct EbiChipSelect {
uint32 base; /* base address in upper 24 bits */
#define EBI_SIZE_8K 0
#define EBI_SIZE_16K 1
#define EBI_SIZE_32K 2
#define EBI_SIZE_64K 3
#define EBI_SIZE_128K 4
#define EBI_SIZE_256K 5
#define EBI_SIZE_512K 6
#define EBI_SIZE_1M 7
#define EBI_SIZE_2M 8
#define EBI_SIZE_4M 9
#define EBI_SIZE_8M 10
#define EBI_SIZE_16M 11
#define EBI_SIZE_32M 12
#define EBI_SIZE_64M 13
#define EBI_SIZE_128M 14
#define EBI_SIZE_256M 15
uint32 config;
#define EBI_ENABLE 0x00000001 /* .. enable this range */
#define EBI_WAIT_STATES 0x0000000e /* .. mask for wait states */
#define EBI_WTST_SHIFT 1 /* .. for shifting wait states */
#define EBI_WORD_WIDE 0x00000010 /* .. 16-bit peripheral, else 8 */
#define EBI_WREN 0x00000020 /* enable posted writes */
#define EBI_POLARITY 0x00000040 /* .. set to invert something,
** don't know what yet */
#define EBI_TS_TA_MODE 0x00000080 /* .. use TS/TA mode */
#define EBI_TS_SEL 0x00000100 /* .. drive tsize, not bs_b */
#define EBI_FIFO 0x00000200 /* .. use fifo */
#define EBI_RE 0x00000400 /* .. Reverse Endian */
} EbiChipSelect;
typedef struct MpiRegisters {
EbiChipSelect cs[7]; /* size chip select configuration */
#define EBI_CS0_BASE 0
#define EBI_CS1_BASE 1
#define EBI_CS2_BASE 2
#define EBI_CS3_BASE 3
#define PCMCIA_COMMON_BASE 4
#define PCMCIA_ATTRIBUTE_BASE 5
#define PCMCIA_IO_BASE 6
uint32 unused0[2]; /* reserved */
uint32 ebi_control; /* ebi control */
uint32 unused1[4]; /* reserved */
#define EBI_ACCESS_TIMEOUT 0x000007FF
uint32 pcmcia_cntl1; /* pcmcia control 1 */
#define PCCARD_CARD_RESET 0x00040000
#define CARDBUS_ENABLE 0x00008000
#define PCMCIA_ENABLE 0x00004000
#define PCMCIA_GPIO_ENABLE 0x00002000
#define CARDBUS_IDSEL 0x00001F00
#define VS2_OEN 0x00000080
#define VS1_OEN 0x00000040
#define VS2_OUT 0x00000020
#define VS1_OUT 0x00000010
#define VS2_IN 0x00000008
#define VS1_IN 0x00000004
#define CD2_IN 0x00000002
#define CD1_IN 0x00000001
#define VS_MASK 0x0000000C
#define CD_MASK 0x00000003
uint32 unused2; /* reserved */
uint32 pcmcia_cntl2; /* pcmcia control 2 */
#define PCMCIA_BYTESWAP_DIS 0x00000002
#define PCMCIA_HALFWORD_EN 0x00000001
#define RW_ACTIVE_CNT_BIT 2
#define INACTIVE_CNT_BIT 8
#define CE_SETUP_CNT_BIT 16
#define CE_HOLD_CNT_BIT 24
uint32 unused3[40]; /* reserved */
uint32 sp0range; /* PCI to internal system bus address space */
uint32 sp0remap;
uint32 sp0cfg;
uint32 sp1range;
uint32 sp1remap;
uint32 sp1cfg;
uint32 EndianCfg;
uint32 l2pcfgctl; /* internal system bus to PCI IO/Cfg control */
#define DIR_CFG_SEL 0x80000000 /* change from PCI I/O access to PCI config access */
#define DIR_CFG_USEREG 0x40000000 /* use this register info for PCI configuration access */
#define DEVICE_NUMBER 0x00007C00 /* device number for the PCI configuration access */
#define FUNC_NUMBER 0x00000300 /* function number for the PCI configuration access */
#define REG_NUMBER 0x000000FC /* register number for the PCI configuration access */
#define CONFIG_TYPE 0x00000003 /* configuration type for the PCI configuration access */
uint32 l2pmrange1; /* internal system bus to PCI memory space */
#define PCI_SIZE_64K 0xFFFF0000
#define PCI_SIZE_128K 0xFFFE0000
#define PCI_SIZE_256K 0xFFFC0000
#define PCI_SIZE_512K 0xFFF80000
#define PCI_SIZE_1M 0xFFF00000
#define PCI_SIZE_2M 0xFFE00000
#define PCI_SIZE_4M 0xFFC00000
#define PCI_SIZE_8M 0xFF800000
#define PCI_SIZE_16M 0xFF000000
#define PCI_SIZE_32M 0xFE000000
uint32 l2pmbase1; /* kseg0 or kseg1 address & 0x1FFFFFFF */
uint32 l2pmremap1;
#define CARDBUS_MEM 0x00000004
#define MEM_WINDOW_EN 0x00000001
uint32 l2pmrange2;
uint32 l2pmbase2;
uint32 l2pmremap2;
uint32 l2piorange; /* internal system bus to PCI I/O space */
uint32 l2piobase;
uint32 l2pioremap;
uint32 pcimodesel;
#define PCI2_INT_BUS_RD_PREFECH 0x000000F0
#define PCI_BAR2_NOSWAP 0x00000002 /* BAR at offset 0x20 */
#define PCI_BAR1_NOSWAP 0x00000001 /* BAR at affset 0x1c */
uint32 pciintstat; /* PCI interrupt mask/status */
#define MAILBOX1_SENT 0x08
#define MAILBOX0_SENT 0x04
#define MAILBOX1_MSG_RCV 0x02
#define MAILBOX0_MSG_RCV 0x01
uint32 locbuscntrl; /* internal system bus control */
#define DIR_U2P_NOSWAP 0x00000002
#define EN_PCI_GPIO 0x00000001
uint32 locintstat; /* internal system bus interrupt mask/status */
#define CSERR 0x0200
#define SERR 0x0100
#define EXT_PCI_INT 0x0080
#define DIR_FAILED 0x0040
#define DIR_COMPLETE 0x0020
#define PCI_CFG 0x0010
uint32 unused5[7];
uint32 mailbox0;
uint32 mailbox1;
uint32 pcicfgcntrl; /* internal system bus PCI configuration control */
#define PCI_CFG_REG_WRITE_EN 0x00000080
#define PCI_CFG_ADDR 0x0000003C
uint32 pcicfgdata; /* internal system bus PCI configuration data */
uint32 locch2ctl; /* PCI to interrnal system bus DMA (downstream) local control */
#define MPI_DMA_HALT 0x00000008 /* idle after finish current memory burst */
#define MPI_DMA_PKT_HALT 0x00000004 /* idle after an EOP flag is detected */
#define MPI_DMA_STALL 0x00000002 /* idle after an EOP flag is detected */
#define MPI_DMA_ENABLE 0x00000001 /* set to enable channel */
uint32 locch2intStat;
#define MPI_DMA_NO_DESC 0x00000004 /* no valid descriptors */
#define MPI_DMA_DONE 0x00000002 /* packet xfer complete */
#define MPI_DMA_BUFF_DONE 0x00000001 /* buffer done */
uint32 locch2intMask;
uint32 unused6;
uint32 locch2descaddr;
uint32 locch2status1;
#define LOCAL_DESC_STATE 0xE0000000
#define PCI_DESC_STATE 0x1C000000
#define BYTE_DONE 0x03FFC000
#define RING_ADDR 0x00003FFF
uint32 locch2status2;
#define BUFPTR_OFFSET 0x1FFF0000
#define PCI_MASTER_STATE 0x000000C0
#define LOC_MASTER_STATE 0x00000038
#define CONTROL_STATE 0x00000007
uint32 unused7;
uint32 locch1Ctl; /*internal system bus to PCI DMA (upstream) local control */
#define DMA_U2P_LE 0x00000200 /* local bus is little endian */
#define DMA_U2P_NOSWAP 0x00000100 /* lccal bus is little endian but no data swapped */
uint32 locch1intstat;
uint32 locch1intmask;
uint32 unused8;
uint32 locch1descaddr;
uint32 locch1status1;
uint32 locch1status2;
uint32 unused9;
uint32 pcich1ctl; /* internal system bus to PCI DMA PCI control */
uint32 pcich1intstat;
uint32 pcich1intmask;
uint32 pcich1descaddr;
uint32 pcich1status1;
uint32 pcich1status2;
uint32 pcich2Ctl; /* PCI to internal system bus DMA PCI control */
uint32 pcich2intstat;
uint32 pcich2intmask;
uint32 pcich2descaddr;
uint32 pcich2status1;
uint32 pcich2status2;
uint32 perm_id; /* permanent device and vendor id */
uint32 perm_rev; /* permanent revision id */
} MpiRegisters;
#define MPI ((volatile MpiRegisters * const) MPI_BASE)
/* PCI configuration address space start offset 0x40 */
#define BRCM_PCI_CONFIG_TIMER 0x40
#define BRCM_PCI_CONFIG_TIMER_RETRY_MASK 0x0000FF00
#define BRCM_PCI_CONFIG_TIMER_TRDY_MASK 0x000000FF
/* USB host non-Open HCI register, USB_HOST_NON_OHCI, bit definitions. */
#define NON_OHCI_ENABLE_PORT1 0x00000001 /* Use USB port 1 for host, not dev */
#define NON_OHCI_BYTE_SWAP 0x00000008 /* Swap USB host registers */
#define USBH_NON_OHCI ((volatile unsigned long * const) USB_HOST_NON_OHCI)
#endif

153
target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bcmTag.h
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@ -1,153 +0,0 @@
/*
<:copyright-gpl
Copyright 2002 Broadcom Corp. All Rights Reserved.
This program is free software; you can distribute it and/or modify it
under the terms of the GNU General Public License (Version 2) as
published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
:>
*/
//**************************************************************************************
// File Name : bcmTag.h
//
// Description: add tag with validation system to the firmware image file to be uploaded
// via http
//
// Created : 02/28/2002 seanl
//**************************************************************************************
#ifndef _BCMTAG_H_
#define _BCMTAG_H_
#define BCM_SIG_1 "Broadcom Corporation"
#define BCM_SIG_2 "ver. 2.0" // was "firmware version 2.0" now it is split 6 char out for chip id.
#define BCM_TAG_VER "6"
#define BCM_TAG_VER_LAST "26"
// file tag (head) structure all is in clear text except validationTokens (crc, md5, sha1, etc). Total: 128 unsigned chars
#define TAG_LEN 256
#define TAG_VER_LEN 4
#define SIG_LEN 20
#define SIG_LEN_2 14 // Original second SIG = 20 is now devided into 14 for SIG_LEN_2 and 6 for CHIP_ID
#define CHIP_ID_LEN 6
#define IMAGE_LEN 10
#define ADDRESS_LEN 12
#define FLAG_LEN 2
#define TOKEN_LEN 20
#define BOARD_ID_LEN 16
#define RESERVED_LEN (TAG_LEN - TAG_VER_LEN - SIG_LEN - SIG_LEN_2 - CHIP_ID_LEN - BOARD_ID_LEN - \
(4*IMAGE_LEN) - (3*ADDRESS_LEN) - (3*FLAG_LEN) - (2*TOKEN_LEN))
// TAG for downloadable image (kernel plus file system)
typedef struct _FILE_TAG
{
unsigned char tagVersion[TAG_VER_LEN]; // tag version. Will be 2 here.
unsigned char signiture_1[SIG_LEN]; // text line for company info
unsigned char signiture_2[SIG_LEN_2]; // additional info (can be version number)
unsigned char chipId[CHIP_ID_LEN]; // chip id
unsigned char boardId[BOARD_ID_LEN]; // board id
unsigned char bigEndian[FLAG_LEN]; // if = 1 - big, = 0 - little endia of the host
unsigned char totalImageLen[IMAGE_LEN]; // the sum of all the following length
unsigned char cfeAddress[ADDRESS_LEN]; // if non zero, cfe starting address
unsigned char cfeLen[IMAGE_LEN]; // if non zero, cfe size in clear ASCII text.
unsigned char rootfsAddress[ADDRESS_LEN]; // if non zero, filesystem starting address
unsigned char rootfsLen[IMAGE_LEN]; // if non zero, filesystem size in clear ASCII text.
unsigned char kernelAddress[ADDRESS_LEN]; // if non zero, kernel starting address
unsigned char kernelLen[IMAGE_LEN]; // if non zero, kernel size in clear ASCII text.
unsigned char dualImage[FLAG_LEN]; // if 1, dual image
unsigned char inactiveLen[FLAG_LEN]; // if 1, the image is INACTIVE; if 0, active
unsigned char reserved[RESERVED_LEN]; // reserved for later use
unsigned char imageValidationToken[TOKEN_LEN];// image validation token - can be crc, md5, sha; for
// now will be 4 unsigned char crc
unsigned char tagValidationToken[TOKEN_LEN]; // validation token for tag(from signiture_1 to end of // mageValidationToken)
} FILE_TAG, *PFILE_TAG;
#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
#define CRC_LEN 4
// only included if for bcmTag.exe program
#ifdef BCMTAG_EXE_USE
static unsigned long Crc32_table[256] = {
0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04,
0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
};
#endif // BCMTAG_USE
#endif // _BCMTAG_H_

59
target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bcm_intr.h
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@ -1,59 +0,0 @@
/*
<:copyright-gpl
Copyright 2003 Broadcom Corp. All Rights Reserved.
This program is free software; you can distribute it and/or modify it
under the terms of the GNU General Public License (Version 2) as
published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
:>
*/
#ifndef __BCM_INTR_H
#define __BCM_INTR_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(CONFIG_BCM96338)
#include <6338_intr.h>
#endif
#if defined(CONFIG_BCM96345)
#include <6345_intr.h>
#endif
#if defined(CONFIG_BCM96348)
#include <6348_intr.h>
#endif
/* defines */
struct pt_regs;
typedef int (*FN_HANDLER) (int, void *);
/* prototypes */
extern void enable_brcm_irq(unsigned int irq);
extern void disable_brcm_irq(unsigned int irq);
extern int request_external_irq(unsigned int irq,
FN_HANDLER handler, unsigned long irqflags,
const char * devname, void *dev_id);
extern unsigned int BcmHalMapInterrupt(FN_HANDLER isr, unsigned int param,
unsigned int interruptId);
extern void dump_intr_regs(void);
/* compatibility definitions */
#define BcmHalInterruptEnable(irq) enable_brcm_irq( irq )
#define BcmHalInterruptDisable(irq) disable_brcm_irq( irq )
#ifdef __cplusplus
}
#endif
#endif

34
target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bcm_map_part.h
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@ -1,34 +0,0 @@
/*
<:copyright-gpl
Copyright 2004 Broadcom Corp. All Rights Reserved.
This program is free software; you can distribute it and/or modify it
under the terms of the GNU General Public License (Version 2) as
published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
:>
*/
#ifndef __BCM_MAP_PART_H
#define __BCM_MAP_PART_H
#if defined(CONFIG_BCM96338)
#include <6338_map_part.h>
#endif
#if defined(CONFIG_BCM96345)
#include <6345_map_part.h>
#endif
#if defined(CONFIG_BCM96348)
#include <6348_map_part.h>
#endif
#endif

87
target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bcmpci.h
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@ -1,87 +0,0 @@
/*
<:copyright-gpl
Copyright 2004 Broadcom Corp. All Rights Reserved.
This program is free software; you can distribute it and/or modify it
under the terms of the GNU General Public License (Version 2) as
published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
:>
*/
//
// bcmpci.h - bcm96348 PCI, Cardbus, and PCMCIA definition
//
#ifndef BCMPCI_H
#define BCMPCI_H
/* Memory window in internal system bus address space */
#define BCM_PCI_MEM_BASE 0x08000000
/* IO window in internal system bus address space */
#define BCM_PCI_IO_BASE 0x0C000000
#define BCM_PCI_ADDR_MASK 0x1fffffff
/* Memory window size (range) */
#define BCM_PCI_MEM_SIZE_16MB 0x01000000
/* IO window size (range) */
#define BCM_PCI_IO_SIZE_64KB 0x00010000
/* PCI Configuration and I/O space acesss */
#define BCM_PCI_CFG(d, f, o) ( (d << 11) | (f << 8) | (o/4 << 2) )
/* fake USB PCI slot */
#define USB_HOST_SLOT 9
#define USB_BAR0_MEM_SIZE 0x0800
#define BCM_HOST_MEM_SPACE1 0x10000000
#define BCM_HOST_MEM_SPACE2 0x00000000
/*
* EBI bus clock is 33MHz and share with PCI bus
* each clock cycle is 30ns.
*/
/* attribute memory access wait cnt for 4306 */
#define PCMCIA_ATTR_CE_HOLD 3 // data hold time 70ns
#define PCMCIA_ATTR_CE_SETUP 3 // data setup time 50ns
#define PCMCIA_ATTR_INACTIVE 6 // time between read/write cycles 180ns. For the total cycle time 600ns (cnt1+cnt2+cnt3+cnt4)
#define PCMCIA_ATTR_ACTIVE 10 // OE/WE pulse width 300ns
/* common memory access wait cnt for 4306 */
#define PCMCIA_MEM_CE_HOLD 1 // data hold time 30ns
#define PCMCIA_MEM_CE_SETUP 1 // data setup time 30ns
#define PCMCIA_MEM_INACTIVE 2 // time between read/write cycles 40ns. For the total cycle time 250ns (cnt1+cnt2+cnt3+cnt4)
#define PCMCIA_MEM_ACTIVE 5 // OE/WE pulse width 150ns
#define PCCARD_VCC_MASK 0x00070000 // Mask Reset also
#define PCCARD_VCC_33V 0x00010000
#define PCCARD_VCC_50V 0x00020000
typedef enum {
MPI_CARDTYPE_NONE, // No Card in slot
MPI_CARDTYPE_PCMCIA, // 16-bit PCMCIA card in slot
MPI_CARDTYPE_CARDBUS, // 32-bit CardBus card in slot
} CardType;
#define CARDBUS_SLOT 0 // Slot 0 is default for CardBus
#define pcmciaAttrOffset 0x00200000
#define pcmciaMemOffset 0x00000000
// Needs to be right above PCI I/O space. Give 0x8000 (32K) to PCMCIA.
#define pcmciaIoOffset (BCM_PCI_IO_BASE + 0x80000)
// Base Address is that mapped into the MPI ChipSelect registers.
// UBUS bridge MemoryWindow 0 outputs a 0x00 for the base.
#define pcmciaBase 0xbf000000
#define pcmciaAttr (pcmciaAttrOffset | pcmciaBase)
#define pcmciaMem (pcmciaMemOffset | pcmciaBase)
#define pcmciaIo (pcmciaIoOffset | pcmciaBase)
#endif

160
target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bcmtypes.h
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@ -1,160 +0,0 @@
/*
<:copyright-gpl
Copyright 2002 Broadcom Corp. All Rights Reserved.
This program is free software; you can distribute it and/or modify it
under the terms of the GNU General Public License (Version 2) as
published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
:>
*/
//
// bcmtypes.h - misc useful typedefs
//
#ifndef BCMTYPES_H
#define BCMTYPES_H
// These are also defined in typedefs.h in the application area, so I need to
// protect against re-definition.
#ifndef _TYPEDEFS_H_
typedef unsigned char uint8;
typedef unsigned short uint16;
typedef unsigned long uint32;
typedef signed char int8;
typedef signed short int16;
typedef signed long int32;
#endif
typedef unsigned char byte;
// typedef unsigned long sem_t;
typedef unsigned long HANDLE,*PULONG,DWORD,*PDWORD;
typedef signed long LONG,*PLONG;
typedef unsigned int *PUINT;
typedef signed int INT;
typedef unsigned short *PUSHORT;
typedef signed short SHORT,*PSHORT;
typedef unsigned short WORD,*PWORD;
typedef unsigned char *PUCHAR;
typedef signed char *PCHAR;
typedef void *PVOID;
typedef unsigned char BOOLEAN, *PBOOL, *PBOOLEAN;
typedef unsigned char BYTE,*PBYTE;
//#ifndef __GNUC__
//The following has been defined in Vxworks internally: vxTypesOld.h
//redefine under vxworks will cause error
typedef signed int *PINT;
typedef signed char INT8;
typedef signed short INT16;
typedef signed long INT32;
typedef unsigned char UINT8;
typedef unsigned short UINT16;
typedef unsigned long UINT32;
typedef unsigned char UCHAR;
typedef unsigned short USHORT;
typedef unsigned int UINT;
typedef unsigned long ULONG;
typedef void VOID;
typedef unsigned char BOOL;
//#endif /* __GNUC__ */
// These are also defined in typedefs.h in the application area, so I need to
// protect against re-definition.
#ifndef TYPEDEFS_H
// Maximum and minimum values for a signed 16 bit integer.
#define MAX_INT16 32767
#define MIN_INT16 -32768
// Useful for true/false return values. This uses the
// Taligent notation (k for constant).
typedef enum
{
kFalse = 0,
kTrue = 1
} Bool;
#endif
/* macros to protect against unaligned accesses */
#if 0
/* first arg is an address, second is a value */
#define PUT16( a, d ) { \
*((byte *)a) = (byte)((d)>>8); \
*(((byte *)a)+1) = (byte)(d); \
}
#define PUT32( a, d ) { \
*((byte *)a) = (byte)((d)>>24); \
*(((byte *)a)+1) = (byte)((d)>>16); \
*(((byte *)a)+2) = (byte)((d)>>8); \
*(((byte *)a)+3) = (byte)(d); \
}
/* first arg is an address, returns a value */
#define GET16( a ) ( \
(*((byte *)a) << 8) | \
(*(((byte *)a)+1)) \
)
#define GET32( a ) ( \
(*((byte *)a) << 24) | \
(*(((byte *)a)+1) << 16) | \
(*(((byte *)a)+2) << 8) | \
(*(((byte *)a)+3)) \
)
#endif
#ifndef YES
#define YES 1
#endif
#ifndef NO
#define NO 0
#endif
#ifndef IN
#define IN
#endif
#ifndef OUT
#define OUT
#endif
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#define READ32(addr) (*(volatile UINT32 *)((ULONG)&addr))
#define READ16(addr) (*(volatile UINT16 *)((ULONG)&addr))
#define READ8(addr) (*(volatile UINT8 *)((ULONG)&addr))
#endif

373
target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/board.h
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@ -1,373 +0,0 @@
/*
<:copyright-gpl
Copyright 2002 Broadcom Corp. All Rights Reserved.
This program is free software; you can distribute it and/or modify it
under the terms of the GNU General Public License (Version 2) as
published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
:>
*/
/***********************************************************************/
/* */
/* MODULE: board.h */
/* DATE: 97/02/18 */
/* PURPOSE: Board specific information. This module should include */
/* all base device addresses and board specific macros. */
/* */
/***********************************************************************/
#ifndef _BOARD_H
#define _BOARD_H
/*****************************************************************************/
/* Misc board definitions */
/*****************************************************************************/
#define DYING_GASP_API
/*****************************************************************************/
/* Physical Memory Map */
/*****************************************************************************/
#define PHYS_DRAM_BASE 0x00000000 /* Dynamic RAM Base */
#define PHYS_FLASH_BASE 0x1FC00000 /* Flash Memory */
/*****************************************************************************/
/* Note that the addresses above are physical addresses and that programs */
/* have to use converted addresses defined below: */
/*****************************************************************************/
#define DRAM_BASE (0x80000000 | PHYS_DRAM_BASE) /* cached DRAM */
#define DRAM_BASE_NOCACHE (0xA0000000 | PHYS_DRAM_BASE) /* uncached DRAM */
#define FLASH_BASE (0xA0000000 | PHYS_FLASH_BASE) /* uncached Flash */
/*****************************************************************************/
/* Select the PLL value to get the desired CPU clock frequency. */
/* */
/* */
/*****************************************************************************/
#define FPERIPH 50000000
#define ONEK 1024
#define BLK64K (64*ONEK)
#define FLASH45_BLKS_BOOT_ROM 1
#define FLASH45_LENGTH_BOOT_ROM (FLASH45_BLKS_BOOT_ROM * BLK64K)
#define FLASH_RESERVED_AT_END (64*ONEK) /*reserved for PSI, scratch pad*/
/*****************************************************************************/
/* Note that the addresses above are physical addresses and that programs */
/* have to use converted addresses defined below: */
/*****************************************************************************/
#define DRAM_BASE (0x80000000 | PHYS_DRAM_BASE) /* cached DRAM */
#define DRAM_BASE_NOCACHE (0xA0000000 | PHYS_DRAM_BASE) /* uncached DRAM */
#define FLASH_BASE (0xA0000000 | PHYS_FLASH_BASE) /* uncached Flash */
/*****************************************************************************/
/* Select the PLL value to get the desired CPU clock frequency. */
/* */
/* */
/*****************************************************************************/
#define FPERIPH 50000000
#define SDRAM_TYPE_ADDRESS_OFFSET 16
#define NVRAM_DATA_OFFSET 0x0580
#define NVRAM_DATA_ID 0x0f1e2d3c
#define BOARD_SDRAM_TYPE *(unsigned long *) \
(FLASH_BASE + SDRAM_TYPE_ADDRESS_OFFSET)
#define ONEK 1024
#define BLK64K (64*ONEK)
// nvram and psi flash definitions for 45
#define FLASH45_LENGTH_NVRAM ONEK // 1k nvram
#define NVRAM_PSI_DEFAULT 24 // default psi in K byes
/*****************************************************************************/
/* NVRAM Offset and definition */
/*****************************************************************************/
#define NVRAM_VERSION_NUMBER 2
#define NVRAM_VERSION_NUMBER_ADDRESS 0
#define NVRAM_BOOTLINE_LEN 256
#define NVRAM_BOARD_ID_STRING_LEN 16
#define NVRAM_MAC_ADDRESS_LEN 6
#define NVRAM_MAC_COUNT_MAX 32
/*****************************************************************************/
/* Misc Offsets */
/*****************************************************************************/
#define CFE_VERSION_OFFSET 0x0570
#define CFE_VERSION_MARK_SIZE 5
#define CFE_VERSION_SIZE 5
typedef struct
{
unsigned long ulVersion;
char szBootline[NVRAM_BOOTLINE_LEN];
char szBoardId[NVRAM_BOARD_ID_STRING_LEN];
unsigned long ulReserved1[2];
unsigned long ulNumMacAddrs;
unsigned char ucaBaseMacAddr[NVRAM_MAC_ADDRESS_LEN];
char chReserved[2];
unsigned long ulCheckSum;
} NVRAM_DATA, *PNVRAM_DATA;
/*****************************************************************************/
/* board ioctl calls for flash, led and some other utilities */
/*****************************************************************************/
/* Defines. for board driver */
#define BOARD_IOCTL_MAGIC 'B'
#define BOARD_DRV_MAJOR 206
#define MAC_ADDRESS_ANY (unsigned long) -1
#define BOARD_IOCTL_FLASH_INIT \
_IOWR(BOARD_IOCTL_MAGIC, 0, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_FLASH_WRITE \
_IOWR(BOARD_IOCTL_MAGIC, 1, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_FLASH_READ \
_IOWR(BOARD_IOCTL_MAGIC, 2, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_GET_NR_PAGES \
_IOWR(BOARD_IOCTL_MAGIC, 3, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_DUMP_ADDR \
_IOWR(BOARD_IOCTL_MAGIC, 4, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_SET_MEMORY \
_IOWR(BOARD_IOCTL_MAGIC, 5, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_MIPS_SOFT_RESET \
_IOWR(BOARD_IOCTL_MAGIC, 6, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_LED_CTRL \
_IOWR(BOARD_IOCTL_MAGIC, 7, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_GET_ID \
_IOWR(BOARD_IOCTL_MAGIC, 8, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_GET_MAC_ADDRESS \
_IOWR(BOARD_IOCTL_MAGIC, 9, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_RELEASE_MAC_ADDRESS \
_IOWR(BOARD_IOCTL_MAGIC, 10, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_GET_PSI_SIZE \
_IOWR(BOARD_IOCTL_MAGIC, 11, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_GET_SDRAM_SIZE \
_IOWR(BOARD_IOCTL_MAGIC, 12, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_SET_MONITOR_FD \
_IOWR(BOARD_IOCTL_MAGIC, 13, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_WAKEUP_MONITOR_TASK \
_IOWR(BOARD_IOCTL_MAGIC, 14, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_GET_BOOTLINE \
_IOWR(BOARD_IOCTL_MAGIC, 15, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_SET_BOOTLINE \
_IOWR(BOARD_IOCTL_MAGIC, 16, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_GET_BASE_MAC_ADDRESS \
_IOWR(BOARD_IOCTL_MAGIC, 17, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_GET_CHIP_ID \
_IOWR(BOARD_IOCTL_MAGIC, 18, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_GET_NUM_ENET \
_IOWR(BOARD_IOCTL_MAGIC, 19, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_GET_CFE_VER \
_IOWR(BOARD_IOCTL_MAGIC, 20, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_GET_ENET_CFG \
_IOWR(BOARD_IOCTL_MAGIC, 21, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_GET_WLAN_ANT_INUSE \
_IOWR(BOARD_IOCTL_MAGIC, 22, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_SET_TRIGGER_EVENT \
_IOWR(BOARD_IOCTL_MAGIC, 23, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_GET_TRIGGER_EVENT \
_IOWR(BOARD_IOCTL_MAGIC, 24, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_UNSET_TRIGGER_EVENT \
_IOWR(BOARD_IOCTL_MAGIC, 25, BOARD_IOCTL_PARMS)
#define BOARD_IOCTL_SET_SES_LED \
_IOWR(BOARD_IOCTL_MAGIC, 26, BOARD_IOCTL_PARMS)
//<<JUNHON, 2004/09/15, get reset button status , tim hou , 05/04/12
#define RESET_BUTTON_UP 1
#define RESET_BUTTON_PRESSDOWN 0
#define BOARD_IOCTL_GET_RESETHOLD \
_IOWR(BOARD_IOCTL_MAGIC, 27, BOARD_IOCTL_PARMS)
//>>JUNHON, 2004/09/15
// for the action in BOARD_IOCTL_PARMS for flash operation
typedef enum
{
PERSISTENT,
NVRAM,
BCM_IMAGE_CFE,
BCM_IMAGE_FS,
BCM_IMAGE_KERNEL,
BCM_IMAGE_WHOLE,
SCRATCH_PAD,
FLASH_SIZE,
} BOARD_IOCTL_ACTION;
typedef struct boardIoctParms
{
char *string;
char *buf;
int strLen;
int offset;
BOARD_IOCTL_ACTION action; /* flash read/write: nvram, persistent, bcm image */
int result;
} BOARD_IOCTL_PARMS;
// LED defines
typedef enum
{
kLedAdsl,
kLedWireless,
kLedUsb,
kLedHpna,
kLedWanData,
kLedPPP,
kLedVoip,
kLedSes,
kLedLan,
kLedSelfTest,
kLedEnd, // NOTE: Insert the new led name before this one. Alway stay at the end.
} BOARD_LED_NAME;
typedef enum
{
kLedStateOff, /* turn led off */
kLedStateOn, /* turn led on */
kLedStateFail, /* turn led on red */
kLedStateBlinkOnce, /* blink once, ~100ms and ignore the same call during the 100ms period */
kLedStateSlowBlinkContinues, /* slow blink continues at ~600ms interval */
kLedStateFastBlinkContinues, /* fast blink continues at ~200ms interval */
} BOARD_LED_STATE;
// virtual and physical map pair defined in board.c
typedef struct ledmappair
{
BOARD_LED_NAME ledName; // virtual led name
BOARD_LED_STATE ledInitState; // initial led state when the board boots.
unsigned short ledMask; // physical GPIO pin mask
unsigned short ledActiveLow; // reset bit to turn on LED
unsigned short ledMaskFail; // physical GPIO pin mask for state failure
unsigned short ledActiveLowFail;// reset bit to turn on LED
} LED_MAP_PAIR, *PLED_MAP_PAIR;
typedef void (*HANDLE_LED_FUNC)(BOARD_LED_NAME ledName, BOARD_LED_STATE ledState);
/* Flash storage address information that is determined by the flash driver. */
typedef struct flashaddrinfo
{
int flash_persistent_start_blk;
int flash_persistent_number_blk;
int flash_persistent_length;
unsigned long flash_persistent_blk_offset;
int flash_scratch_pad_start_blk; // start before psi (SP_BUF_LEN)
int flash_scratch_pad_number_blk;
int flash_scratch_pad_length;
unsigned long flash_scratch_pad_blk_offset;
int flash_nvram_start_blk;
int flash_nvram_number_blk;
int flash_nvram_length;
unsigned long flash_nvram_blk_offset;
} FLASH_ADDR_INFO, *PFLASH_ADDR_INFO;
// scratch pad defines
/* SP - Persisten Scratch Pad format:
sp header : 32 bytes
tokenId-1 : 8 bytes
tokenId-1 len : 4 bytes
tokenId-1 data
....
tokenId-n : 8 bytes
tokenId-n len : 4 bytes
tokenId-n data
*/
#define MAGIC_NUM_LEN 8
#define MAGIC_NUMBER "gOGoBrCm"
#define TOKEN_NAME_LEN 16
#define SP_VERSION 1
#define SP_MAX_LEN 8 * 1024 // 8k buf before psi
#define SP_RESERVERD 16
typedef struct _SP_HEADER
{
char SPMagicNum[MAGIC_NUM_LEN]; // 8 bytes of magic number
int SPVersion; // version number
int SPUsedLen; // used sp len
char SPReserved[SP_RESERVERD]; // reservied, total 32 bytes
} SP_HEADER, *PSP_HEADER;
typedef struct _TOKEN_DEF
{
char tokenName[TOKEN_NAME_LEN];
int tokenLen;
} SP_TOKEN, *PSP_TOKEN;
/*****************************************************************************/
/* Function Prototypes */
/*****************************************************************************/
#if !defined(__ASM_ASM_H)
void dumpaddr( unsigned char *pAddr, int nLen );
int kerSysNvRamGet(char *string, int strLen, int offset);
int kerSysNvRamSet(char *string, int strLen, int offset);
int kerSysPersistentGet(char *string, int strLen, int offset);
int kerSysPersistentSet(char *string, int strLen, int offset);
int kerSysScratchPadGet(char *tokName, char *tokBuf, int tokLen);
int kerSysScratchPadSet(char *tokName, char *tokBuf, int tokLen);
int kerSysBcmImageSet( int flash_start_addr, char *string, int size);
int kerSysGetMacAddress( unsigned char *pucaAddr, unsigned long ulId );
int kerSysReleaseMacAddress( unsigned char *pucaAddr );
int kerSysGetSdramSize( void );
void kerSysGetBootline(char *string, int strLen);
void kerSysSetBootline(char *string, int strLen);
void kerSysMipsSoftReset(void);
void kerSysLedCtrl(BOARD_LED_NAME, BOARD_LED_STATE);
void kerSysLedRegisterHwHandler( BOARD_LED_NAME, HANDLE_LED_FUNC, int );
int kerSysFlashSizeGet(void);
void kerSysRegisterDyingGaspHandler(char *devname, void *cbfn, void *context);
void kerSysDeregisterDyingGaspHandler(char *devname);
void kerSysWakeupMonitorTask( void );
#endif
#define BOOT_CFE 0
#define BOOT_REDBOOT 1
extern int boot_loader_type;
#endif /* _BOARD_H */

7
target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/bootloaders.h
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#define ADSL_SDRAM_IMAGE_SIZE (384*1024)
#define BOOT_LOADER_UNKNOWN 0
#define BOOT_LOADER_CFE 1
#define BOOT_LOADER_REDBOOT 2
#define BOOT_LOADER_CFE2 3
#define BOOT_LOADER_LAST 3

36
target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/cpu-feature-overrides.h
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@ -1,36 +0,0 @@
#ifndef __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H
#define cpu_has_tlb 1
#define cpu_has_4kex 4
#define cpu_has_4ktlb 8
#define cpu_has_fpu 0
#define cpu_has_32fpr 0
#define cpu_has_counter 0x40
#define cpu_has_watch 0
#define cpu_has_mips16 0
#define cpu_has_divec 0x200
#define cpu_has_vce 0
#define cpu_has_cache_cdex_p 0
#define cpu_has_cache_cdex_s 0
#define cpu_has_prefetch 0x40000
#define cpu_has_mcheck 0x2000
#define cpu_has_ejtag 0x4000
#define cpu_has_llsc 0x10000
#define cpu_has_vtag_icache 0
#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_nofpuex 0
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_64bit_gp_regs 0
#define cpu_has_64bit_addresses 0
#define cpu_has_subset_pcaches 0
#define cpu_dcache_line_size() 16
#define cpu_icache_line_size() 16
#define cpu_scache_line_size() 0
#endif /* __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H */

25
target/linux/brcm63xx/files/include/asm-mips/mach-bcm963xx/war.h
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@ -1,25 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_MACH_BCM963XX_WAR_H
#define __ASM_MIPS_MACH_BCM963XX_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define RM9000_CDEX_SMP_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_BCM963XX_WAR_H */

48
target/linux/brcm63xx/files/include/linux/atmrt2684.h
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@ -1,48 +0,0 @@
#ifndef _LINUX_ATMRT2684_H
#define _LINUX_ATMRT2684_H
#include <linux/atm.h>
#include <linux/if.h> /* For IFNAMSIZ */
#define RT2684_ENCAPS_NULL (0) /* VC-mux */
#define RT2684_ENCAPS_LLC (1)
#define RT2684_ENCAPS_AUTODETECT (2) /* Unsuported */
/*
* This is for the ATM_NEWBACKENDIF call - these are like socket families:
* the first element of the structure is the backend number and the rest
* is per-backend specific
*/
struct atm_newif_rt2684 {
atm_backend_t backend_num; /* ATM_BACKEND_RT2684 */
char ifname[IFNAMSIZ];
};
/*
* This structure is used to specify a rt2684 interface - either by a
* positive integer (returned by ATM_NEWBACKENDIF) or the interfaces name
*/
#define RT2684_FIND_BYNOTHING (0)
#define RT2684_FIND_BYNUM (1)
#define RT2684_FIND_BYIFNAME (2)
struct rt2684_if_spec {
int method; /* RT2684_FIND_* */
union {
char ifname[IFNAMSIZ];
int devnum;
} spec;
};
/*
* This is for the ATM_SETBACKEND call - these are like socket families:
* the first element of the structure is the backend number and the rest
* is per-backend specific
*/
struct atm_backend_rt2684 {
atm_backend_t backend_num; /* ATM_BACKEND_RT2684 */
struct rt2684_if_spec ifspec;
unsigned char encaps; /* RT2684_ENCAPS_* */
};
#endif /* _LINUX_ATMRT2684_H */

170
target/linux/brcm63xx/patches-2.6.25/001-bcm963xx.patch
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@ -1,170 +0,0 @@
From 2b2b8e163d28646cbbfde81c900fbb57d6572a11 Mon Sep 17 00:00:00 2001
From: Axel Gembe <ago@bastart.eu.org>
Date: Thu, 15 May 2008 11:00:43 +0200
Subject: [PATCH] bcm963xx: board support
Signed-off-by: Axel Gembe <ago@bastart.eu.org>
---
arch/mips/Kconfig | 11 +++++++++++
arch/mips/Makefile | 4 ++++
arch/mips/kernel/cpu-probe.c | 16 ++++++++++++++++
arch/mips/mm/c-r4k.c | 7 +++++++
arch/mips/mm/tlbex.c | 4 ++++
arch/mips/pci/Makefile | 1 +
include/asm-mips/bootinfo.h | 12 ++++++++++++
include/asm-mips/cpu.h | 7 ++++++-
8 files changed, 61 insertions(+), 1 deletions(-)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -59,6 +59,17 @@
help
Support for BCM47XX based boards
+config BCM963XX
+ bool "Support for Broadcom BCM963xx SoC"
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_HAS_CPU_MIPS32_R1
+ select HW_HAS_PCI
+ select DMA_NONCOHERENT
+ select IRQ_CPU
+ help
+ This is a fmaily of boards based on the Broadcom MIPS32
+
config MIPS_COBALT
bool "Cobalt Server"
select CEVT_R4K
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -560,6 +560,10 @@
cflags-$(CONFIG_BCM47XX) += -Iinclude/asm-mips/mach-bcm47xx
load-$(CONFIG_BCM47XX) := 0xffffffff80001000
+core-$(CONFIG_BCM963XX) += arch/mips/bcm963xx/
+cflags-$(CONFIG_BCM963XX) += -Iinclude/asm-mips/mach-bcm963xx
+load-$(CONFIG_BCM963XX) := 0xffffffff8001000
+
#
# SNI RM
#
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -803,6 +803,21 @@
case PRID_IMP_BCM4710:
c->cputype = CPU_BCM4710;
break;
+// case PRID_IMP_BCM6338:
+// c->cputype = CPU_BCM6338;
+// break;
+ case PRID_IMP_BCM6345:
+ c->cputype = CPU_BCM6345;
+ break;
+ case PRID_IMP_BCM6348:
+ c->cputype = CPU_BCM6348;
+ break;
+ case PRID_IMP_BCM6358:
+ c->cputype = CPU_BCM6358;
+ break;
+ case PRID_IMP_BCM3350:
+ c->cputype = CPU_BCM3350;
+ break;
default:
c->cputype = CPU_UNKNOWN;
break;
@@ -887,6 +902,11 @@
case CPU_SR71000: name = "Sandcraft SR71000"; break;
case CPU_BCM3302: name = "Broadcom BCM3302"; break;
case CPU_BCM4710: name = "Broadcom BCM4710"; break;
+ case CPU_BCM6338: name = "Broadcom BCM6338"; break;
+ case CPU_BCM6345: name = "Broadcom BCM6345"; break;
+ case CPU_BCM6348: name = "Broadcom BCM6348"; break;
+ case CPU_BCM6358: name = "Broadcom BCM6358"; break;
+ case CPU_BCM3350: name = "Broadcom BCM3350"; break;
case CPU_PR4450: name = "Philips PR4450"; break;
case CPU_LOONGSON2: name = "ICT Loongson-2"; break;
default:
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -882,6 +882,13 @@
if (!(config & MIPS_CONF_M))
panic("Don't know how to probe P-caches on this cpu.");
+ if (c->cputype == CPU_BCM6338 || c->cputype == CPU_BCM6345 || c->cputype == CPU_BCM6348 || c->cputype == CPU_BCM6358 || c->cputype == CPU_BCM3350)
+ {
+ printk("bcm963xx: enabling icache and dcache...\n");
+ /* Enable caches */
+ write_c0_diag(read_c0_diag() | 0xC0000000);
+ }
+
/*
* So we seem to be a MIPS32 or MIPS64 CPU
* So let's probe the I-cache ...
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -315,6 +315,11 @@
case CPU_25KF:
case CPU_BCM3302:
case CPU_BCM4710:
+// case CPU_BCM6338:
+ case CPU_BCM6345:
+ case CPU_BCM6348:
+ case CPU_BCM6358:
+ case CPU_BCM3350:
case CPU_LOONGSON2:
if (m4kc_tlbp_war())
uasm_i_nop(p);
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -48,3 +48,4 @@
obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
+obj-$(CONFIG_BCM963XX) += fixup-bcm96348.o pci-bcm96348.o ops-bcm96348.o
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -94,6 +94,19 @@
#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
+#define MACH_WRPPMC 1
+
+/*
+ * Valid machtype for group Broadcom
+ */
+#define MACH_GROUP_BRCM 23 /* Broadcom */
+#define MACH_BCM47XX 1 /* Broadcom BCM47XX */
+#define MACH_BCM96338 2
+#define MACH_BCM96345 3
+#define MACH_BCM96348 4
+#define MACH_BCM96358 5
+#define MACH_BCM3350 6
+
#define CL_SIZE COMMAND_LINE_SIZE
extern char *system_type;
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -111,6 +111,11 @@
#define PRID_IMP_BCM4710 0x4000
#define PRID_IMP_BCM3302 0x9000
+//#define PRID_IMP_BCM6338 0x9000
+#define PRID_IMP_BCM6345 0x8000
+#define PRID_IMP_BCM6348 0x9100
+#define PRID_IMP_BCM6358 0xA000
+#define PRID_IMP_BCM3350 0x28000
/*
* Definitions for 7:0 on legacy processors
@@ -196,7 +201,8 @@
*/
CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_74K, CPU_AU1000,
CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500, CPU_AU1550,
- CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
+ CPU_PR4450, CPU_BCM3302, CPU_BCM4710, CPU_BCM6338, CPU_BCM6345, CPU_BCM6348,
+ CPU_BCM6358, CPU_BCM3350,
/*
* MIPS64 class processors

18
target/linux/brcm63xx/patches-2.6.25/002-bcm963xx_serial.patch
View file

@ -1,18 +0,0 @@
From 53bc5316c1123689dddf2c78a4cdfd15834237e8 Mon Sep 17 00:00:00 2001
From: Axel Gembe <ago@bastart.eu.org>
Date: Mon, 12 May 2008 18:53:47 +0200
Subject: [PATCH] bcm963xx: serial port support
Signed-off-by: Axel Gembe <ago@bastart.eu.org>
---
drivers/serial/Makefile | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -67,3 +67,4 @@
obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o
obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
obj-$(CONFIG_SERIAL_QE) += ucc_uart.o
+obj-$(CONFIG_BCM963XX) += bcm63xx_cons.o

73
target/linux/brcm63xx/patches-2.6.25/040-bcm963xx_flashmap.patch
View file

@ -1,73 +0,0 @@
From e734ace5baa04e0e8af1d4483475fbd6bd2b32a1 Mon Sep 17 00:00:00 2001
From: Axel Gembe <ago@bastart.eu.org>
Date: Mon, 12 May 2008 18:54:09 +0200
Subject: [PATCH] bcm963xx: flashmap support
Signed-off-by: Axel Gembe <ago@bastart.eu.org>
---
drivers/mtd/maps/Kconfig | 7 +++++++
drivers/mtd/maps/Makefile | 1 +
drivers/mtd/redboot.c | 13 ++++++++++---
3 files changed, 18 insertions(+), 3 deletions(-)
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -262,6 +262,13 @@
Flash memory access on 4G Systems MTX-1 Board. If you have one of
these boards and would like to use the flash chips on it, say 'Y'.
+config MTD_BCM963XX
+ tristate "BCM963xx Flash device"
+ depends on MIPS && BCM963XX
+ help
+ Flash memory access on BCM963xx boards. Currently only works with
+ RedBoot and CFE.
+
config MTD_DILNETPC
tristate "CFI Flash device mapped on DIL/Net PC"
depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -68,3 +68,4 @@
obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o
obj-$(CONFIG_MTD_MTX1) += mtx-1_flash.o
obj-$(CONFIG_MTD_INTEL_VR_NOR) += intel_vr_nor.o
+obj-$(CONFIG_MTD_BCM963XX) += bcm963xx-flash.o
--- a/drivers/mtd/redboot.c
+++ b/drivers/mtd/redboot.c
@@ -39,7 +39,7 @@
return 1;
}
-static int parse_redboot_partitions(struct mtd_info *master,
+int parse_redboot_partitions(struct mtd_info *master,
struct mtd_partition **pparts,
unsigned long fis_origin)
{
@@ -161,6 +161,14 @@
goto out;
}
+ if (!fis_origin) {
+ for (i = 0; i < numslots; i++) {
+ if (!strncmp(buf[i].name, "RedBoot", 8)) {
+ fis_origin = (buf[i].flash_base & (master->size << 1) - 1);
+ }
+ }
+ }
+
for (i = 0; i < numslots; i++) {
struct fis_list *new_fl, **prev;
@@ -183,9 +191,8 @@
new_fl->img = &buf[i];
if (fis_origin) {
buf[i].flash_base -= fis_origin;
- } else {
- buf[i].flash_base &= master->size-1;
}
+ buf[i].flash_base &= (master->size << 1) - 1;
/* I'm sure the JFFS2 code has done me permanent damage.
* I now think the following is _normal_

24
target/linux/brcm63xx/patches-2.6.25/050-bcm963xx_add_trailing_zero.patch
View file

@ -1,24 +0,0 @@
From 40dd38388c3d1c87efe254cee533fc5db5ffc4ed Mon Sep 17 00:00:00 2001
From: Axel Gembe <ago@bastart.eu.org>
Date: Wed, 14 May 2008 12:43:34 +0200
Subject: [PATCH] bcm963xx: add missing trailing zero to load address
The load address for BCM963xx is 0x80010000, not 0xf8001000 as in the current
sources. I think this is just a typo, so this patch fixes it (tested on 96345).
Signed-off-by: Axel Gembe <ago@bastart.eu.org>
---
arch/mips/Makefile | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -562,7 +562,7 @@
core-$(CONFIG_BCM963XX) += arch/mips/bcm963xx/
cflags-$(CONFIG_BCM963XX) += -Iinclude/asm-mips/mach-bcm963xx
-load-$(CONFIG_BCM963XX) := 0xffffffff8001000
+load-$(CONFIG_BCM963XX) := 0xffffffff80010000
#
# SNI RM

452
target/linux/brcm63xx/patches-2.6.25/060-bcm963xx_rewrite_irq_handling_code.patch
View file

@ -1,452 +0,0 @@
From 9a70f2dcb24a5aab29386373c86ba035acba4891 Mon Sep 17 00:00:00 2001
From: Axel Gembe <ago@bastart.eu.org>
Date: Sun, 18 May 2008 12:07:21 +0200
Subject: [PATCH] bcm963xx: rewrite irq handling code
This patch adds interrupt handling as on AR7. The old code was very messy and
didn't work too well.
Signed-off-by: Axel Gembe <ago@bastart.eu.org>
---
arch/mips/bcm963xx/irq.c | 308 ++++++++++-------------------
drivers/serial/bcm63xx_cons.c | 13 +-
include/asm-mips/mach-bcm963xx/bcm_intr.h | 18 +--
3 files changed, 119 insertions(+), 220 deletions(-)
--- a/arch/mips/bcm963xx/irq.c
+++ b/arch/mips/bcm963xx/irq.c
@@ -1,259 +1,159 @@
/*
-<:copyright-gpl
- Copyright 2002 Broadcom Corp. All Rights Reserved.
-
- This program is free software; you can distribute it and/or modify it
- under the terms of the GNU General Public License (Version 2) as
- published by the Free Software Foundation.
-
- This program is distributed in the hope it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- for more details.
-
- You should have received a copy of the GNU General Public License along
- with this program; if not, write to the Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-:>
-*/
-/*
- * Interrupt control functions for Broadcom 963xx MIPS boards
+ * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
+ * Copyright (C) 2008 Axel Gembe <ago@bastart.eu.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <asm/atomic.h>
-
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/irq.h>
#include <linux/interrupt.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/module.h>
+#include <linux/io.h>
-#include <asm/irq.h>
+#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
-#include <asm/addrspace.h>
-#include <asm/signal.h>
+
#include <6348_map_part.h>
#include <6348_intr.h>
#include <bcm_map_part.h>
#include <bcm_intr.h>
-static void irq_dispatch_int(void)
-{
- unsigned int pendingIrqs;
- static unsigned int irqBit;
- static unsigned int isrNumber = 31;
-
- pendingIrqs = PERF->IrqStatus & PERF->IrqMask;
- if (!pendingIrqs) {
- return;
- }
+static int bcm963xx_irq_base;
- while (1) {
- irqBit <<= 1;
- isrNumber++;
- if (isrNumber == 32) {
- isrNumber = 0;
- irqBit = 0x1;
- }
- if (pendingIrqs & irqBit) {
- PERF->IrqMask &= ~irqBit; // mask
- do_IRQ(isrNumber + INTERNAL_ISR_TABLE_OFFSET);
- break;
- }
- }
+void bcm963xx_unmask_irq(unsigned int irq)
+{
+ PERF->IrqMask |= (1 << (irq - bcm963xx_irq_base));
}
-static void irq_dispatch_ext(uint32 irq)
+void bcm963xx_mask_irq(unsigned int irq)
{
- if (!(PERF->ExtIrqCfg & (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_MASK_SHFT)))) {
- printk("**** Ext IRQ mask. Should not dispatch ****\n");
- }
- /* disable and clear interrupt in the controller */
- PERF->ExtIrqCfg |= (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_CLEAR_SHFT));
- PERF->ExtIrqCfg &= ~(1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_MASK_SHFT));
- do_IRQ(irq);
+ PERF->IrqMask &= ~(1 << (irq - bcm963xx_irq_base));
}
-
-//extern void brcm_timer_interrupt(struct pt_regs *regs);
-
-asmlinkage void plat_irq_dispatch(void)
+void bcm963xx_ack_irq(unsigned int irq)
{
- unsigned long cause;
-
- cause = read_c0_status() & read_c0_cause() & ST0_IM;
- if (cause & CAUSEF_IP7)
- do_IRQ(7);
- else if (cause & CAUSEF_IP2)
- irq_dispatch_int();
- else if (cause & CAUSEF_IP3)
- irq_dispatch_ext(INTERRUPT_ID_EXTERNAL_0);
- else if (cause & CAUSEF_IP4)
- irq_dispatch_ext(INTERRUPT_ID_EXTERNAL_1);
- else if (cause & CAUSEF_IP5)
- irq_dispatch_ext(INTERRUPT_ID_EXTERNAL_2);
- else if (cause & CAUSEF_IP6) {
- irq_dispatch_ext(INTERRUPT_ID_EXTERNAL_3);
- local_irq_disable();
- }
+ PERF->IrqStatus &= ~(1 << (irq - bcm963xx_irq_base));
}
-
-void enable_brcm_irq(unsigned int irq)
+void bcm963xx_unmask_ext_irq(unsigned int irq)
{
- unsigned long flags;
-
- local_irq_save(flags);
- if( irq >= INTERNAL_ISR_TABLE_OFFSET ) {
- PERF->IrqMask |= (1 << (irq - INTERNAL_ISR_TABLE_OFFSET));
- }
- else if (irq >= INTERRUPT_ID_EXTERNAL_0 && irq <= INTERRUPT_ID_EXTERNAL_3) {
- /* enable and clear interrupt in the controller */
- PERF->ExtIrqCfg |= (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_CLEAR_SHFT));
PERF->ExtIrqCfg |= (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_MASK_SHFT));
- }
- local_irq_restore(flags);
}
-void disable_brcm_irq(unsigned int irq)
+void bcm963xx_mask_ext_irq(unsigned int irq)
{
- unsigned long flags;
-
- local_irq_save(flags);
- if( irq >= INTERNAL_ISR_TABLE_OFFSET ) {
- PERF->IrqMask &= ~(1 << (irq - INTERNAL_ISR_TABLE_OFFSET));
- }
- else if (irq >= INTERRUPT_ID_EXTERNAL_0 && irq <= INTERRUPT_ID_EXTERNAL_3) {
- /* disable interrupt in the controller */
PERF->ExtIrqCfg &= ~(1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_MASK_SHFT));
- }
- local_irq_restore(flags);
}
-void ack_brcm_irq(unsigned int irq)
+void bcm963xx_ack_ext_irq(unsigned int irq)
{
- /* Already done in brcm_irq_dispatch */
+ PERF->ExtIrqCfg |= (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_CLEAR_SHFT));
}
-unsigned int startup_brcm_irq(unsigned int irq)
+static void bcm963xx_dispatch_ext_irq(unsigned int irq)
{
- enable_brcm_irq(irq);
-
- return 0; /* never anything pending */
+ bcm963xx_ack_ext_irq(irq);
+ bcm963xx_mask_ext_irq(irq);
+ do_IRQ(irq);
}
-unsigned int startup_brcm_none(unsigned int irq)
+static void bcm963xx_cascade(void)
{
- return 0;
-}
+ uint32_t pending, bit, irq;
-void end_brcm_irq(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
- enable_brcm_irq(irq);
-}
+ if (!(pending = PERF->IrqStatus & PERF->IrqMask))
+ return;
-void end_brcm_none(unsigned int irq)
-{
-}
+ for (irq = 0, bit = 1; irq < 32; irq++, bit <<= 1) {
+ if (pending & bit) {
+ bcm963xx_ack_irq(irq + bcm963xx_irq_base);
+ bcm963xx_mask_irq(irq + bcm963xx_irq_base);
+ do_IRQ(irq + bcm963xx_irq_base);
+ return;
+ }
+ }
+
+ spurious_interrupt();
+}
+
+static struct irq_chip bcm963xx_irq_type = {
+ .name = "bcm963xx",
+ .unmask = bcm963xx_unmask_irq,
+ .mask = bcm963xx_mask_irq,
+ .ack = bcm963xx_ack_irq
+};
-static struct hw_interrupt_type brcm_irq_type = {
- .typename = "MIPS",
- .startup = startup_brcm_irq,
- .shutdown = disable_brcm_irq,
- .enable = enable_brcm_irq,
- .disable = disable_brcm_irq,
- .ack = ack_brcm_irq,
- .end = end_brcm_irq,
- .set_affinity = NULL
+static struct irq_chip bcm963xx_ext_irq_type = {
+ .name = "bcm963xx_ext",
+ .unmask = bcm963xx_unmask_ext_irq,
+ .mask = bcm963xx_mask_ext_irq,
+ .ack = bcm963xx_ack_ext_irq,
};
-static struct hw_interrupt_type brcm_irq_no_end_type = {
- .typename = "MIPS",
- .startup = startup_brcm_none,
- .shutdown = disable_brcm_irq,
- .enable = enable_brcm_irq,
- .disable = disable_brcm_irq,
- .ack = ack_brcm_irq,
- .end = end_brcm_none,
- .set_affinity = NULL
+static struct irqaction bcm963xx_cascade_action = {
+ .handler = no_action,
+ .name = "BCM963xx cascade interrupt"
};
-void __init arch_init_irq(void)
+static void __init bcm963xx_irq_init(int base)
{
int i;
- clear_c0_status(ST0_BEV);
- change_c0_status(ST0_IM, (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4));
+ bcm963xx_irq_base = base;
- for (i = 0; i < NR_IRQS; i++) {
- irq_desc[i].status = IRQ_DISABLED;
- irq_desc[i].action = 0;
- irq_desc[i].depth = 1;
- irq_desc[i].chip = &brcm_irq_type;
- }
+ /* External IRQs */
+ set_irq_chip_and_handler(INTERRUPT_ID_EXTERNAL_0, &bcm963xx_ext_irq_type,
+ handle_level_irq);
+ set_irq_chip_and_handler(INTERRUPT_ID_EXTERNAL_1, &bcm963xx_ext_irq_type,
+ handle_level_irq);
+ set_irq_chip_and_handler(INTERRUPT_ID_EXTERNAL_2, &bcm963xx_ext_irq_type,
+ handle_level_irq);
+ set_irq_chip_and_handler(INTERRUPT_ID_EXTERNAL_3, &bcm963xx_ext_irq_type,
+ handle_level_irq);
+
+ for (i = 0; i < 32; i++) {
+ set_irq_chip_and_handler(base + i, &bcm963xx_irq_type,
+ handle_level_irq);
+ }
+
+ setup_irq(2, &bcm963xx_cascade_action);
+ setup_irq(bcm963xx_irq_base, &bcm963xx_cascade_action);
+ set_c0_status(IE_IRQ0);
}
-int request_external_irq(unsigned int irq,
- FN_HANDLER handler,
- unsigned long irqflags,
- const char * devname,
- void *dev_id)
+asmlinkage void plat_irq_dispatch(void)
{
- unsigned long flags;
-
- local_irq_save(flags);
+ unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
- PERF->ExtIrqCfg |= (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_CLEAR_SHFT)); // Clear
- PERF->ExtIrqCfg &= ~(1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_MASK_SHFT)); // Mask
- PERF->ExtIrqCfg &= ~(1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_INSENS_SHFT)); // Edge insesnsitive
- PERF->ExtIrqCfg |= (1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_LEVEL_SHFT)); // Level triggered
- PERF->ExtIrqCfg &= ~(1 << (irq - INTERRUPT_ID_EXTERNAL_0 + EI_SENSE_SHFT)); // Low level
-
- local_irq_restore(flags);
-
- return( request_irq(irq, handler, irqflags, devname, dev_id) );
+ if (pending & STATUSF_IP7) /* cpu timer */
+ do_IRQ(7);
+ else if (pending & STATUSF_IP2) /* internal interrupt cascade */
+ bcm963xx_cascade();
+ else if (pending & STATUSF_IP3)
+ bcm963xx_dispatch_ext_irq(INTERRUPT_ID_EXTERNAL_0);
+ else if (pending & STATUSF_IP4)
+ bcm963xx_dispatch_ext_irq(INTERRUPT_ID_EXTERNAL_1);
+ else if (pending & STATUSF_IP5)
+ bcm963xx_dispatch_ext_irq(INTERRUPT_ID_EXTERNAL_2);
+ else if (pending & STATUSF_IP6)
+ bcm963xx_dispatch_ext_irq(INTERRUPT_ID_EXTERNAL_3);
+ else
+ spurious_interrupt();
}
-/* VxWorks compatibility function(s). */
-
-unsigned int BcmHalMapInterrupt(FN_HANDLER pfunc, unsigned int param,
- unsigned int interruptId)
+void __init arch_init_irq(void)
{
- int nRet = -1;
- char *devname;
-
- devname = kmalloc(16, GFP_KERNEL);
- if (devname)
- sprintf( devname, "brcm_%d", interruptId );
-
- /* Set the IRQ description to not automatically enable the interrupt at
- * the end of an ISR. The driver that handles the interrupt must
- * explicitly call BcmHalInterruptEnable or enable_brcm_irq. This behavior
- * is consistent with interrupt handling on VxWorks.
- */
- irq_desc[interruptId].chip = &brcm_irq_no_end_type;
-
- if( interruptId >= INTERNAL_ISR_TABLE_OFFSET )
- {
- printk("BcmHalMapInterrupt : internal IRQ\n");
- nRet = request_irq( interruptId, pfunc, IRQF_DISABLED, devname, (void *) param );
- }
- else if (interruptId >= INTERRUPT_ID_EXTERNAL_0 && interruptId <= INTERRUPT_ID_EXTERNAL_3)
- {
- printk("BcmHalMapInterrupt : external IRQ\n");
- nRet = request_external_irq( interruptId, pfunc, IRQF_DISABLED, devname, (void *) param );
- }
-
- return( nRet );
+ mips_cpu_irq_init();
+ bcm963xx_irq_init(INTERNAL_ISR_TABLE_OFFSET);
}
-
-
-EXPORT_SYMBOL(enable_brcm_irq);
-EXPORT_SYMBOL(disable_brcm_irq);
-EXPORT_SYMBOL(request_external_irq);
-EXPORT_SYMBOL(BcmHalMapInterrupt);
-
--- a/drivers/serial/bcm63xx_cons.c
+++ b/drivers/serial/bcm63xx_cons.c
@@ -267,7 +267,7 @@
}
// Clear the interrupt
- enable_brcm_irq(INTERRUPT_ID_UART);
+// bcm963xx_unmask_irq(INTERRUPT_ID_UART);
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
return IRQ_HANDLED;
#endif
@@ -880,7 +880,7 @@
info->count++;
tty->driver_data = info;
info->tty = tty;
- enable_brcm_irq(INTERRUPT_ID_UART);
+ bcm963xx_unmask_irq(INTERRUPT_ID_UART);
// Start up serial port
retval = startup(info);
@@ -927,7 +927,7 @@
-------------------------------------------------------------------------- */
static int __init bcm63xx_serialinit(void)
{
- int i, flags;
+ int i, flags, res;
struct bcm_serial *info;
// Print the driver version information
@@ -981,7 +981,12 @@
*/
if (!info->port)
return 0;
- BcmHalMapInterrupt(bcm_interrupt, 0, INTERRUPT_ID_UART);
+
+ res = request_irq(INTERRUPT_ID_UART, bcm_interrupt, 0, "bcm-uart", NULL);
+ if (res) {
+ spin_unlock_irqrestore(&bcm963xx_serial_lock, flags);
+ return res;
+ }
}
/* order matters here... the trick is that flags
--- a/include/asm-mips/mach-bcm963xx/bcm_intr.h
+++ b/include/asm-mips/mach-bcm963xx/bcm_intr.h
@@ -39,18 +39,12 @@
typedef int (*FN_HANDLER) (int, void *);
/* prototypes */
-extern void enable_brcm_irq(unsigned int irq);
-extern void disable_brcm_irq(unsigned int irq);
-extern int request_external_irq(unsigned int irq,
- FN_HANDLER handler, unsigned long irqflags,
- const char * devname, void *dev_id);
-extern unsigned int BcmHalMapInterrupt(FN_HANDLER isr, unsigned int param,
- unsigned int interruptId);
-extern void dump_intr_regs(void);
-
-/* compatibility definitions */
-#define BcmHalInterruptEnable(irq) enable_brcm_irq( irq )
-#define BcmHalInterruptDisable(irq) disable_brcm_irq( irq )
+extern void bcm963xx_unmask_irq(unsigned int irq);
+extern void bcm963xx_mask_irq(unsigned int irq);
+extern void bcm963xx_ack_irq(unsigned int irq);
+extern void bcm963xx_unmask_ext_irq(unsigned int irq);
+extern void bcm963xx_mask_ext_irq(unsigned int irq);
+extern void bcm963xx_ack_ext_irq(unsigned int irq);
#ifdef __cplusplus
}

31
target/linux/brcm63xx/patches-2.6.25/070-bcm963xx_fix_uart_isr.patch
View file

@ -1,31 +0,0 @@
From 7bc3950017d2c54883591367723b7fd84cc65d6f Mon Sep 17 00:00:00 2001
From: Axel Gembe <ago@bastart.eu.org>
Date: Sun, 18 May 2008 12:09:14 +0200
Subject: [PATCH] bcm963xx: fix uart isr
The ISR ended up in an endless loop because the TX ISR never got used or masked.
This patch basically makes the TX ISR mask the the TX interrupt when it
encounters it, because it doesn't even use the TX interrupt.
Signed-off-by: Axel Gembe <ago@bastart.eu.org>
---
drivers/serial/bcm63xx_cons.c | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
--- a/drivers/serial/bcm63xx_cons.c
+++ b/drivers/serial/bcm63xx_cons.c
@@ -258,8 +258,14 @@
while (intStat) {
if (intStat & RXINT)
receive_chars(info);
+
+#if 0 /* This code is total bullshit, TXINT doesn't get masked anywhere, so this will give an endless loop */
+
else if (intStat & TXINT)
info->port->intStatus = TXINT;
+
+#endif /* 0 */
+
else /* don't know what it was, so let's mask it */
info->port->intMask &= ~intStat;

87
target/linux/brcm63xx/patches-2.6.25/080-bcm963xx_remove_unused_int_handler.patch
View file

@ -1,87 +0,0 @@
From e3abd028e7631ee952fe73d8f9ee97bc615526a8 Mon Sep 17 00:00:00 2001
From: Axel Gembe <ago@bastart.eu.org>
Date: Sat, 17 May 2008 16:07:46 +0200
Subject: [PATCH] bcm963xx: remove unused int-handler.S
The code is not used anymore.
Signed-off-by: Axel Gembe <ago@bastart.eu.org>
---
arch/mips/bcm963xx/Makefile | 2 +-
arch/mips/bcm963xx/int-handler.S | 59 --------------------------------------
2 files changed, 1 insertions(+), 60 deletions(-)
delete mode 100644 arch/mips/bcm963xx/int-handler.S
--- a/arch/mips/bcm963xx/Makefile
+++ b/arch/mips/bcm963xx/Makefile
@@ -3,7 +3,7 @@
#
# Copyright (C) 2004 Broadcom Corporation
#
-obj-y := irq.o prom.o setup.o time.o ser_init.o int-handler.o info.o wdt.o
+obj-y := irq.o prom.o setup.o time.o ser_init.o info.o wdt.o
SRCBASE := $(TOPDIR)
EXTRA_CFLAGS += -I$(SRCBASE)/include
--- a/arch/mips/bcm963xx/int-handler.S
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
-<:copyright-gpl
- Copyright 2002 Broadcom Corp. All Rights Reserved.
-
- This program is free software; you can distribute it and/or modify it
- under the terms of the GNU General Public License (Version 2) as
- published by the Free Software Foundation.
-
- This program is distributed in the hope it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- for more details.
-
- You should have received a copy of the GNU General Public License along
- with this program; if not, write to the Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-:>
-*/
-/*
- * Generic interrupt handler for Broadcom MIPS boards
- */
-
-#include <linux/autoconf.h>
-
-#include <asm/asm.h>
-#include <asm/mipsregs.h>
-#include <asm/regdef.h>
-#include <asm/stackframe.h>
-
-/*
- * MIPS IRQ Source
- * -------- ------
- * 0 Software (ignored)
- * 1 Software (ignored)
- * 2 Combined hardware interrupt (hw0)
- * 3 Hardware
- * 4 Hardware
- * 5 Hardware
- * 6 Hardware
- * 7 R4k timer
- */
-
- .text
- .set noreorder
- .set noat
- .align 5
- NESTED(brcmIRQ, PT_SIZE, sp)
- SAVE_ALL
- CLI
- .set noreorder
- .set at
-
- jal plat_irq_dispatch
- move a0, sp
-
- j ret_from_irq
- nop
-
- END(brcmIRQ)

66
target/linux/brcm63xx/patches-2.6.25/090-bcm963xx_remove_obsolete_timer_code.patch
View file

@ -1,66 +0,0 @@
From 42ecc15386869684cf29881a3a6941bafaa3bf69 Mon Sep 17 00:00:00 2001
From: Axel Gembe <ago@bastart.eu.org>
Date: Wed, 14 May 2008 00:25:28 +0200
Subject: [PATCH] bcm963xx: remove obsolete timer code
This removes some code that has been deprecated in kernels >= 2.6.24.
Signed-off-by: Axel Gembe <ago@bastart.eu.org>
---
arch/mips/bcm963xx/setup.c | 2 --
arch/mips/bcm963xx/time.c | 29 -----------------------------
2 files changed, 0 insertions(+), 31 deletions(-)
--- a/arch/mips/bcm963xx/setup.c
+++ b/arch/mips/bcm963xx/setup.c
@@ -465,8 +465,6 @@
_machine_halt = brcm_machine_halt;
pm_power_off = brcm_machine_halt;
- //board_time_init = brcm_time_init;
-
/* mpi initialization */
mpi_init();
}
--- a/arch/mips/bcm963xx/time.c
+++ b/arch/mips/bcm963xx/time.c
@@ -71,26 +71,6 @@
return (mips_hpt_frequency / HZ);
}
-
-/*
- * There are a lot of conceptually broken versions of the MIPS timer interrupt
- * handler floating around. This one is rather different, but the algorithm
- * is provably more robust.
- */
-#if 0
-irqreturn_t brcm_timer_interrupt(struct pt_regs *regs)
-{
- int irq = MIPS_TIMER_INT;
-
- irq_enter();
- kstat_this_cpu.irqs[irq]++;
-
- timer_interrupt(irq, regs);
- irq_exit();
- return IRQ_HANDLED;
-}
-#endif
-
void __init plat_time_init(void)
{
unsigned int est_freq, flags;
@@ -107,12 +87,3 @@
(est_freq % 1000000) * 100 / 1000000);
local_irq_restore(flags);
}
-
-#if 0
-void __init plat_timer_setup(struct irqaction *irq)
-{
- r4k_cur = (read_c0_count() + r4k_offset);
- write_c0_compare(r4k_cur);
- set_c0_status(IE_IRQ5);
-}
-#endif

115
target/linux/brcm63xx/patches-2.6.25/100-bcm963xx_add_new_timer_code.patch
View file

@ -1,115 +0,0 @@
From 7d6656dc127b54e53e507e8f264bb7e14e620cad Mon Sep 17 00:00:00 2001
From: Axel Gembe <ago@bastart.eu.org>
Date: Sat, 17 May 2008 15:02:39 +0200
Subject: [PATCH] bcm963xx: add new timer code
This basically selects the new generic MIPS timer code for BCM963xx and
simplifies the timer setup code.
Signed-off-by: Axel Gembe <ago@bastart.eu.org>
---
arch/mips/Kconfig | 2 +
arch/mips/bcm963xx/time.c | 64 ++++++++++++++++++++------------------------
2 files changed, 31 insertions(+), 35 deletions(-)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -67,6 +67,8 @@
select HW_HAS_PCI
select DMA_NONCOHERENT
select IRQ_CPU
+ select CEVT_R4K
+ select CSRC_R4K
help
This is a fmaily of boards based on the Broadcom MIPS32
--- a/arch/mips/bcm963xx/time.c
+++ b/arch/mips/bcm963xx/time.c
@@ -1,6 +1,7 @@
/*
<:copyright-gpl
Copyright 2004 Broadcom Corp. All Rights Reserved.
+ Copyright (C) 2008 Axel Gembe <ago@bastart.eu.org>
This program is free software; you can distribute it and/or modify it
under the terms of the GNU General Public License (Version 2) as
@@ -40,50 +41,43 @@
#include <bcm_map_part.h>
#include <bcm_intr.h>
-static unsigned long r4k_offset; /* Amount to increment compare reg each time */
-static unsigned long r4k_cur; /* What counter should be at next timer irq */
-
-/* *********************************************************************
- * calculateCpuSpeed()
- * Calculate the BCM6348 CPU speed by reading the PLL strap register
- * and applying the following formula:
- * cpu_clk = (.25 * 64MHz freq) * (N1 + 1) * (N2 + 2) / (M1_CPU + 1)
- * Input parameters:
- * none
- * Return value:
- * none
- ********************************************************************* */
-
+/*
+ * calculateCpuSpeed()
+ *
+ * Calculate the BCM6348 CPU speed by reading the PLL strap register and applying
+ * the following formula:
+ *
+ * cpu_clk = (.25 * 64MHz freq) * (N1 + 1) * (N2 + 2) / (M1_CPU + 1)
+ */
static inline unsigned long __init calculateCpuSpeed(void)
{
- u32 pllStrap = PERF->PllStrap;
- int n1 = (pllStrap & PLL_N1_MASK) >> PLL_N1_SHFT;
- int n2 = (pllStrap & PLL_N2_MASK) >> PLL_N2_SHFT;
- int m1cpu = (pllStrap & PLL_M1_CPU_MASK) >> PLL_M1_CPU_SHFT;
+ u32 pllStrap;
+ int n1, n2, m1cpu;
+
+ pllStrap = PERF->PllStrap;
+ n1 = (pllStrap & PLL_N1_MASK) >> PLL_N1_SHFT;
+ n2 = (pllStrap & PLL_N2_MASK) >> PLL_N2_SHFT;
+ m1cpu = (pllStrap & PLL_M1_CPU_MASK) >> PLL_M1_CPU_SHFT;
return (16 * (n1 + 1) * (n2 + 2) / (m1cpu + 1)) * 1000000;
}
-static inline unsigned long __init cal_r4koff(void)
-{
- mips_hpt_frequency = calculateCpuSpeed() / 2;
- return (mips_hpt_frequency / HZ);
-}
-
void __init plat_time_init(void)
{
- unsigned int est_freq, flags;
- local_irq_save(flags);
+ unsigned long cpu_clock;
+
+ cpu_clock = calculateCpuSpeed();
+
+ printk("CPU frequency %lu.%02lu MHz\n", cpu_clock / 1000000,
+ (cpu_clock % 1000000) * 100 / 1000000);
+
+ mips_hpt_frequency = cpu_clock / 2;
- printk("calculating r4koff... ");
- r4k_offset = cal_r4koff();
- printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
-
- est_freq = 2 * r4k_offset * HZ;
- est_freq += 5000; /* round */
- est_freq -= est_freq % 10000;
- printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
- (est_freq % 1000000) * 100 / 1000000);
- local_irq_restore(flags);
+ /*
+ * Use deterministic values for initial counter interrupt
+ * so that calibrate delay avoids encountering a counter wrap.
+ */
+ write_c0_count(0);
+ write_c0_compare(0xffff);
}

41
target/linux/brcm63xx/patches-2.6.25/110-bcm963xx_fix_cfe_detection.patch
View file

@ -1,41 +0,0 @@
From f1a605c36cf1659f5f486ae4135de1e285fdf86c Mon Sep 17 00:00:00 2001
From: Axel Gembe <ago@bastart.eu.org>
Date: Sat, 17 May 2008 16:17:22 +0200
Subject: [PATCH] bcm963xx: fix cfe detection
The CFE detection failed to account for zero termination.
Signed-off-by: Axel Gembe <ago@bastart.eu.org>
---
drivers/mtd/maps/bcm963xx-flash.c | 11 ++++++-----
1 files changed, 6 insertions(+), 5 deletions(-)
--- a/drivers/mtd/maps/bcm963xx-flash.c
+++ b/drivers/mtd/maps/bcm963xx-flash.c
@@ -1,8 +1,7 @@
/*
- * $Id$
* Copyright (C) 2006 Florian Fainelli <florian@openwrt.org>
- * Mike Albon <malbon@openwrt.org>
- * Copyright (C) $Date$ $Author$
+ * Mike Albon <malbon@openwrt.org>
+ * Copyright (C) 2008 Axel Gembe <ago@bastart.eu.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -184,11 +183,13 @@
static int bcm963xx_detect_cfe(struct mtd_info *master)
{
int idoffset = 0x4e0;
- static char idstring[8] = "CFE1CFE1";
- char buf[8];
+ static char idstring[9] = "CFE1CFE1";
+ char buf[9];
int ret;
size_t retlen;
+ memset(buf, 0, sizeof(buf));
+
ret = master->read(master, idoffset, 8, &retlen, (void *)buf);
printk("bcm963xx: Read Signature value of %s\n", buf);
return strcmp(idstring,buf);

116
target/linux/brcm63xx/patches-2.6.25/500-bcm96345_fixes.patch
View file

@ -1,116 +0,0 @@
From d1259cf42ce84246c695f06b44d58e3aca0a480b Mon Sep 17 00:00:00 2001
From: Axel Gembe <ago@bastart.eu.org>
Date: Sat, 17 May 2008 14:59:35 +0200
Subject: [PATCH] bcm96345: correct some 6345 specific stuff
This fixes some problems with the 6345 support and adds a macro for CPU
identification that is easier on the eyes. The first thing it does is to not
initialize MPI on the 6345 as it does not have PCI. The second thing it does is
to use a static value for the CPU frequency of the 6345 chip to provide an
accurate timer.
Signed-off-by: Axel Gembe <ago@bastart.eu.org>
---
arch/mips/bcm963xx/setup.c | 8 ++++++--
arch/mips/bcm963xx/time.c | 5 ++++-
arch/mips/pci/pci-bcm96348.c | 21 +++++++++++++--------
include/asm-mips/mach-bcm963xx/board.h | 2 ++
4 files changed, 25 insertions(+), 11 deletions(-)
--- a/arch/mips/bcm963xx/setup.c
+++ b/arch/mips/bcm963xx/setup.c
@@ -43,6 +43,7 @@
#include <asm/bootinfo.h>
#include <asm/cpu.h>
#include <asm/mach-bcm963xx/bootloaders.h>
+#include <asm/mach-bcm963xx/board.h>
extern void brcm_time_init(void);
extern int boot_loader_type;
@@ -465,6 +466,9 @@
_machine_halt = brcm_machine_halt;
pm_power_off = brcm_machine_halt;
- /* mpi initialization */
- mpi_init();
+ /* BCM96345 has no MPI */
+ if (!ISBCM(0x6345)) {
+ /* mpi initialization */
+ mpi_init();
+ }
}
--- a/arch/mips/bcm963xx/time.c
+++ b/arch/mips/bcm963xx/time.c
@@ -40,6 +40,8 @@
#include <6348_intr.h>
#include <bcm_map_part.h>
#include <bcm_intr.h>
+#include <asm/mach-bcm963xx/board.h>
+
/*
* calculateCpuSpeed()
@@ -63,11 +65,12 @@
}
+#define BCM96345_CPU_CLOCK 140000000
void __init plat_time_init(void)
{
unsigned long cpu_clock;
- cpu_clock = calculateCpuSpeed();
+ cpu_clock = ISBCM(0x6345) ? BCM96345_CPU_CLOCK : calculateCpuSpeed();
printk("CPU frequency %lu.%02lu MHz\n", cpu_clock / 1000000,
(cpu_clock % 1000000) * 100 / 1000000);
--- a/arch/mips/pci/pci-bcm96348.c
+++ b/arch/mips/pci/pci-bcm96348.c
@@ -21,6 +21,8 @@
#include <linux/kernel.h>
#include <linux/init.h>
+#include <asm/mach-bcm963xx/6348_map_part.h>
+#include <asm/mach-bcm963xx/board.h>
#include <bcmpci.h>
static struct resource bcm_pci_io_resource = {
@@ -47,16 +49,19 @@
static __init int bcm96348_pci_init(void)
{
- /* Avoid ISA compat ranges. */
- PCIBIOS_MIN_IO = 0x00000000;
- PCIBIOS_MIN_MEM = 0x00000000;
-
- /* Set I/O resource limits. */
- ioport_resource.end = 0x1fffffff;
- iomem_resource.end = 0xffffffff;
+ if (!ISBCM(0x6345)) {
+ /* Avoid ISA compat ranges. */
+ PCIBIOS_MIN_IO = 0x00000000;
+ PCIBIOS_MIN_MEM = 0x00000000;
+
+ /* Set I/O resource limits. */
+ ioport_resource.end = 0x1fffffff;
+ iomem_resource.end = 0xffffffff;
- register_pci_controller(&bcm96348_controller);
- return 0;
+ register_pci_controller(&bcm96348_controller);
+ }
+
+ return 0;
}
arch_initcall(bcm96348_pci_init);
--- a/include/asm-mips/mach-bcm963xx/board.h
+++ b/include/asm-mips/mach-bcm963xx/board.h
@@ -369,5 +369,7 @@
extern int boot_loader_type;
+#define ISBCM(x) (((PERF->RevID & 0xFFFF0000) >> 16) == x)
+
#endif /* _BOARD_H */

153
target/linux/brcm63xx/patches/001-bcm963xx.patch
View file

@ -1,153 +0,0 @@
Index: linux-2.6.24.7/arch/mips/Kconfig
===================================================================
--- linux-2.6.24.7.orig/arch/mips/Kconfig
+++ linux-2.6.24.7/arch/mips/Kconfig
@@ -67,6 +67,17 @@ config BCM47XX
help
Support for BCM47XX based boards
+config BCM963XX
+ bool "Support for Broadcom BCM963xx SoC"
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_HAS_CPU_MIPS32_R1
+ select HW_HAS_PCI
+ select DMA_NONCOHERENT
+ select IRQ_CPU
+ help
+ This is a fmaily of boards based on the Broadcom MIPS32
+
config MIPS_COBALT
bool "Cobalt Server"
select CEVT_R4K
Index: linux-2.6.24.7/arch/mips/kernel/cpu-probe.c
===================================================================
--- linux-2.6.24.7.orig/arch/mips/kernel/cpu-probe.c
+++ linux-2.6.24.7/arch/mips/kernel/cpu-probe.c
@@ -796,6 +796,18 @@ static inline void cpu_probe_broadcom(st
case PRID_IMP_BCM4710:
c->cputype = CPU_BCM4710;
break;
+// case PRID_IMP_BCM6338:
+// c->cputype = CPU_BCM6338;
+// break;
+ case PRID_IMP_BCM6345:
+ c->cputype = CPU_BCM6345;
+ break;
+ case PRID_IMP_BCM6348:
+ c->cputype = CPU_BCM6348;
+ break;
+ case PRID_IMP_BCM6358:
+ c->cputype = CPU_BCM6358;
+ break;
default:
c->cputype = CPU_UNKNOWN;
break;
@@ -878,6 +890,10 @@ static __init const char *cpu_to_name(st
case CPU_SR71000: name = "Sandcraft SR71000"; break;
case CPU_BCM3302: name = "Broadcom BCM3302"; break;
case CPU_BCM4710: name = "Broadcom BCM4710"; break;
+ case CPU_BCM6338: name = "Broadcom BCM6338"; break;
+ case CPU_BCM6345: name = "Broadcom BCM6345"; break;
+ case CPU_BCM6348: name = "Broadcom BCM6348"; break;
+ case CPU_BCM6358: name = "Broadcom BCM6358"; break;
case CPU_PR4450: name = "Philips PR4450"; break;
case CPU_LOONGSON2: name = "ICT Loongson-2"; break;
default:
Index: linux-2.6.24.7/arch/mips/Makefile
===================================================================
--- linux-2.6.24.7.orig/arch/mips/Makefile
+++ linux-2.6.24.7/arch/mips/Makefile
@@ -543,6 +543,10 @@ core-$(CONFIG_BCM47XX) += arch/mips/bcm
cflags-$(CONFIG_BCM47XX) += -Iinclude/asm-mips/mach-bcm47xx
load-$(CONFIG_BCM47XX) := 0xffffffff80001000
+core-$(CONFIG_BCM963XX) += arch/mips/bcm963xx/
+cflags-$(CONFIG_BCM963XX) += -Iinclude/asm-mips/mach-bcm963xx
+load-$(CONFIG_BCM963XX) := 0xffffffff8001000
+
#
# SNI RM
#
Index: linux-2.6.24.7/arch/mips/mm/c-r4k.c
===================================================================
--- linux-2.6.24.7.orig/arch/mips/mm/c-r4k.c
+++ linux-2.6.24.7/arch/mips/mm/c-r4k.c
@@ -878,6 +878,13 @@ static void __init probe_pcache(void)
if (!(config & MIPS_CONF_M))
panic("Don't know how to probe P-caches on this cpu.");
+ if (c->cputype == CPU_BCM6338 || c->cputype == CPU_BCM6345 || c->cputype == CPU_BCM6348 || c->cputype == CPU_BCM6358)
+ {
+ printk("bcm963xx: enabling icache and dcache...\n");
+ /* Enable caches */
+ write_c0_diag(read_c0_diag() | 0xC0000000);
+ }
+
/*
* So we seem to be a MIPS32 or MIPS64 CPU
* So let's probe the I-cache ...
Index: linux-2.6.24.7/arch/mips/mm/tlbex.c
===================================================================
--- linux-2.6.24.7.orig/arch/mips/mm/tlbex.c
+++ linux-2.6.24.7/arch/mips/mm/tlbex.c
@@ -909,6 +909,10 @@ static __init void build_tlb_write_entry
case CPU_25KF:
case CPU_BCM3302:
case CPU_BCM4710:
+// case CPU_BCM6338:
+ case CPU_BCM6345:
+ case CPU_BCM6348:
+ case CPU_BCM6358:
case CPU_LOONGSON2:
if (m4kc_tlbp_war())
i_nop(p);
Index: linux-2.6.24.7/arch/mips/pci/Makefile
===================================================================
--- linux-2.6.24.7.orig/arch/mips/pci/Makefile
+++ linux-2.6.24.7/arch/mips/pci/Makefile
@@ -48,3 +48,4 @@ obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-
obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
+obj-$(CONFIG_BCM963XX) += fixup-bcm96348.o pci-bcm96348.o ops-bcm96348.o
Index: linux-2.6.24.7/include/asm-mips/bootinfo.h
===================================================================
--- linux-2.6.24.7.orig/include/asm-mips/bootinfo.h
+++ linux-2.6.24.7/include/asm-mips/bootinfo.h
@@ -197,6 +197,10 @@
*/
#define MACH_GROUP_BRCM 23 /* Broadcom */
#define MACH_BCM47XX 1 /* Broadcom BCM47XX */
+#define MACH_BCM96338 2
+#define MACH_BCM96345 3
+#define MACH_BCM96348 4
+#define MACH_BCM96358 5
#define CL_SIZE COMMAND_LINE_SIZE
Index: linux-2.6.24.7/include/asm-mips/cpu.h
===================================================================
--- linux-2.6.24.7.orig/include/asm-mips/cpu.h
+++ linux-2.6.24.7/include/asm-mips/cpu.h
@@ -111,6 +111,10 @@
#define PRID_IMP_BCM4710 0x4000
#define PRID_IMP_BCM3302 0x9000
+//#define PRID_IMP_BCM6338 0x9000
+#define PRID_IMP_BCM6345 0x8000
+#define PRID_IMP_BCM6348 0x9100
+#define PRID_IMP_BCM6358 0xA000
/*
* Definitions for 7:0 on legacy processors
@@ -196,7 +200,8 @@ enum cpu_type_enum {
*/
CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_74K, CPU_AU1000,
CPU_AU1100, CPU_AU1200, CPU_AU1500, CPU_AU1550, CPU_PR4450,
- CPU_BCM3302, CPU_BCM4710,
+ CPU_BCM3302, CPU_BCM4710, CPU_BCM6338, CPU_BCM6345, CPU_BCM6348,
+ CPU_BCM6358,
/*
* MIPS64 class processors

9
target/linux/brcm63xx/patches/002-bcm963xx_serial.patch
View file

@ -1,9 +0,0 @@
Index: linux-2.6.24.7/drivers/serial/Makefile
===================================================================
--- linux-2.6.24.7.orig/drivers/serial/Makefile
+++ linux-2.6.24.7/drivers/serial/Makefile
@@ -65,3 +65,4 @@ obj-$(CONFIG_SERIAL_NETX) += netx-serial
obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o
obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
obj-$(CONFIG_SERIAL_QE) += ucc_uart.o
+obj-$(CONFIG_BCM963XX) += bcm63xx_cons.o

66
target/linux/brcm63xx/patches/040-bcm963xx_flashmap.patch
View file

@ -1,66 +0,0 @@
Index: linux-2.6.24.7/drivers/mtd/maps/Kconfig
===================================================================
--- linux-2.6.24.7.orig/drivers/mtd/maps/Kconfig
+++ linux-2.6.24.7/drivers/mtd/maps/Kconfig
@@ -269,6 +269,13 @@ config MTD_MTX1
Flash memory access on 4G Systems MTX-1 Board. If you have one of
these boards and would like to use the flash chips on it, say 'Y'.
+config MTD_BCM963XX
+ tristate "BCM963xx Flash device"
+ depends on MIPS && BCM963XX
+ help
+ Flash memory access on BCM963xx boards. Currently only works with
+ RedBoot and CFE.
+
config MTD_DILNETPC
tristate "CFI Flash device mapped on DIL/Net PC"
depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT
Index: linux-2.6.24.7/drivers/mtd/redboot.c
===================================================================
--- linux-2.6.24.7.orig/drivers/mtd/redboot.c
+++ linux-2.6.24.7/drivers/mtd/redboot.c
@@ -39,7 +39,7 @@ static inline int redboot_checksum(struc
return 1;
}
-static int parse_redboot_partitions(struct mtd_info *master,
+int parse_redboot_partitions(struct mtd_info *master,
struct mtd_partition **pparts,
unsigned long fis_origin)
{
@@ -146,6 +146,14 @@ static int parse_redboot_partitions(stru
goto out;
}
+ if (!fis_origin) {
+ for (i = 0; i < numslots; i++) {
+ if (!strncmp(buf[i].name, "RedBoot", 8)) {
+ fis_origin = (buf[i].flash_base & (master->size << 1) - 1);
+ }
+ }
+ }
+
for (i = 0; i < numslots; i++) {
struct fis_list *new_fl, **prev;
@@ -168,9 +176,8 @@ static int parse_redboot_partitions(stru
new_fl->img = &buf[i];
if (fis_origin) {
buf[i].flash_base -= fis_origin;
- } else {
- buf[i].flash_base &= master->size-1;
}
+ buf[i].flash_base &= (master->size << 1) - 1;
/* I'm sure the JFFS2 code has done me permanent damage.
* I now think the following is _normal_
Index: linux-2.6.24.7/drivers/mtd/maps/Makefile
===================================================================
--- linux-2.6.24.7.orig/drivers/mtd/maps/Makefile
+++ linux-2.6.24.7/drivers/mtd/maps/Makefile
@@ -69,3 +69,4 @@ obj-$(CONFIG_MTD_PLATRAM) += plat-ram.o
obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o
obj-$(CONFIG_MTD_MTX1) += mtx-1_flash.o
obj-$(CONFIG_MTD_INTEL_VR_NOR) += intel_vr_nor.o
+obj-$(CONFIG_MTD_BCM963XX) += bcm963xx-flash.o