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brcm47xx: remove 2.6.25 support

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SVN-Revision: 15448
This commit is contained in:
Felix Fietkau 2009-04-27 15:47:46 +00:00
parent c2696fb706
commit 4f88f8de81
29 changed files with 0 additions and 4259 deletions
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228
target/linux/brcm47xx/config-2.6.25
View file

@ -1,228 +0,0 @@
CONFIG_32BIT=y
# CONFIG_64BIT is not set
# CONFIG_8139TOO is not set
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_ARCH_POPULATES_NODE_MAP=y
# CONFIG_ARCH_SUPPORTS_MSI is not set
CONFIG_ARCH_SUPPORTS_OPROFILE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# CONFIG_ARPD is not set
CONFIG_B44=y
CONFIG_B44_PCI=y
CONFIG_B44_PCICORE_AUTOSELECT=y
CONFIG_B44_PCI_AUTOSELECT=y
CONFIG_BASE_SMALL=0
CONFIG_BCM47XX=y
CONFIG_BITREVERSE=y
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_CEVT_R4K=y
CONFIG_CFE=y
CONFIG_CLASSIC_RCU=y
CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 init=/etc/preinit noinitrd console=ttyS0,115200"
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_CPU_LITTLE_ENDIAN=y
# CONFIG_CPU_LOONGSON2 is not set
CONFIG_CPU_MIPS32=y
CONFIG_CPU_MIPS32_R1=y
# CONFIG_CPU_MIPS32_R2 is not set
# CONFIG_CPU_MIPS64_R1 is not set
# CONFIG_CPU_MIPS64_R2 is not set
CONFIG_CPU_MIPSR1=y
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_RM9000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_VR41XX is not set
CONFIG_CSRC_R4K=y
CONFIG_DEVPORT=y
# CONFIG_DM9000 is not set
CONFIG_DMA_NEED_PCI_MAP_STATE=y
CONFIG_DMA_NONCOHERENT=y
# CONFIG_E1000E_ENABLED is not set
CONFIG_EARLY_PRINTK=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_GPIO=y
# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
# CONFIG_HAMRADIO is not set
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAVE_IDE=y
# CONFIG_HAVE_KPROBES is not set
# CONFIG_HAVE_KRETPROBES is not set
CONFIG_HAVE_OPROFILE=y
CONFIG_HW_HAS_PCI=y
CONFIG_HW_RANDOM=y
CONFIG_HZ=250
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
# CONFIG_I2C is not set
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
# CONFIG_IBM_NEW_EMAC_RGMII is not set
# CONFIG_IBM_NEW_EMAC_TAH is not set
# CONFIG_IBM_NEW_EMAC_ZMII is not set
# CONFIG_IDE is not set
CONFIG_INITRAMFS_SOURCE=""
CONFIG_INPUT=y
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_POLLDEV=y
# CONFIG_IP_ROUTE_VERBOSE is not set
CONFIG_IRQ_CPU=y
# CONFIG_LEDS_ALIX is not set
CONFIG_LEDS_GPIO=y
# CONFIG_LEMOTE_FULONG is not set
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_MEMSTICK is not set
CONFIG_MIPS=y
# CONFIG_MIPS_ATLAS is not set
# CONFIG_MIPS_COBALT is not set
CONFIG_MIPS_L1_CACHE_SHIFT=5
# CONFIG_MIPS_MALTA is not set
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_SEAD is not set
# CONFIG_MIPS_SIM is not set
CONFIG_MTD=y
# CONFIG_MTD_ABSENT is not set
CONFIG_MTD_BCM47XX=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_MTD_BLOCK2MTD is not set
CONFIG_MTD_CFI=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
CONFIG_MTD_CFI_INTELEXT=y
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
CONFIG_MTD_CHAR=y
# CONFIG_MTD_CMDLINE_PARTS is not set
CONFIG_MTD_COMPLEX_MAPPINGS=y
# CONFIG_MTD_CONCAT is not set
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
CONFIG_MTD_MAP_BANK_WIDTH_2=y
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_ONENAND is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_PCI is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_PHYSMAP is not set
# CONFIG_MTD_PLATRAM is not set
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_NATSEMI is not set
# CONFIG_NE2K_PCI is not set
# CONFIG_NET_EMATCH is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NO_IOPORT is not set
# CONFIG_PAGE_SIZE_16KB is not set
CONFIG_PAGE_SIZE_4KB=y
# CONFIG_PAGE_SIZE_64KB is not set
# CONFIG_PAGE_SIZE_8KB is not set
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PROC_KCORE is not set
# CONFIG_R6040 is not set
CONFIG_RFKILL=y
CONFIG_RFKILL_INPUT=y
CONFIG_RFKILL_LEDS=y
# CONFIG_RTC is not set
CONFIG_RTC_LIB=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
# CONFIG_SCSI_DMA is not set
# CONFIG_SERIAL_8250_DETECT_IRQ is not set
CONFIG_SERIAL_8250_EXTENDED=y
# CONFIG_SERIAL_8250_MANY_PORTS is not set
# CONFIG_SERIAL_8250_RSA is not set
CONFIG_SERIAL_8250_SHARE_IRQ=y
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP28 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_SWARM is not set
CONFIG_SLABINFO=y
# CONFIG_SPARSEMEM_STATIC is not set
# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_SSB=y
CONFIG_SSB_B43_PCI_BRIDGE=y
CONFIG_SSB_DEBUG=y
CONFIG_SSB_DRIVER_EXTIF=y
# CONFIG_SSB_DRIVER_GIGE is not set
CONFIG_SSB_DRIVER_MIPS=y
CONFIG_SSB_DRIVER_PCICORE=y
CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
CONFIG_SSB_EMBEDDED=y
CONFIG_SSB_PCICORE_HOSTMODE=y
CONFIG_SSB_PCIHOST=y
CONFIG_SSB_PCIHOST_POSSIBLE=y
CONFIG_SSB_POSSIBLE=y
CONFIG_SSB_SERIAL=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_SYS_HAS_EARLY_PRINTK=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
# CONFIG_TC35815 is not set
CONFIG_TICK_ONESHOT=y
# CONFIG_TOSHIBA_JMR3927 is not set
# CONFIG_TOSHIBA_RBTX4927 is not set
# CONFIG_TOSHIBA_RBTX4938 is not set
CONFIG_TRAD_SIGNALS=y
CONFIG_USB_SUPPORT=y
# CONFIG_VGASTATE is not set
# CONFIG_VIA_RHINE is not set
# CONFIG_WATCHDOG is not set
CONFIG_ZONE_DMA_FLAG=0

229
target/linux/brcm47xx/files-2.6.25/arch/mips/bcm47xx/cfe_env.c
View file

@ -1,229 +0,0 @@
/*
* CFE environment variable access
*
* Copyright 2001-2003, Broadcom Corporation
* Copyright 2006, Felix Fietkau <nbd@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#define NVRAM_SIZE (0x1ff0)
static char _nvdata[NVRAM_SIZE];
static char _valuestr[256];
/*
* TLV types. These codes are used in the "type-length-value"
* encoding of the items stored in the NVRAM device (flash or EEPROM)
*
* The layout of the flash/nvram is as follows:
*
* <type> <length> <data ...> <type> <length> <data ...> <type_end>
*
* The type code of "ENV_TLV_TYPE_END" marks the end of the list.
* The "length" field marks the length of the data section, not
* including the type and length fields.
*
* Environment variables are stored as follows:
*
* <type_env> <length> <flags> <name> = <value>
*
* If bit 0 (low bit) is set, the length is an 8-bit value.
* If bit 0 (low bit) is clear, the length is a 16-bit value
*
* Bit 7 set indicates "user" TLVs. In this case, bit 0 still
* indicates the size of the length field.
*
* Flags are from the constants below:
*
*/
#define ENV_LENGTH_16BITS 0x00 /* for low bit */
#define ENV_LENGTH_8BITS 0x01
#define ENV_TYPE_USER 0x80
#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
/*
* The actual TLV types we support
*/
#define ENV_TLV_TYPE_END 0x00
#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
/*
* Environment variable flags
*/
#define ENV_FLG_NORMAL 0x00 /* normal read/write */
#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
/* *********************************************************************
* _nvram_read(buffer,offset,length)
*
* Read data from the NVRAM device
*
* Input parameters:
* buffer - destination buffer
* offset - offset of data to read
* length - number of bytes to read
*
* Return value:
* number of bytes read, or <0 if error occured
********************************************************************* */
static int
_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
{
int i;
if (offset > NVRAM_SIZE)
return -1;
for ( i = 0; i < length; i++) {
buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
}
return length;
}
static char*
_strnchr(const char *dest,int c,size_t cnt)
{
while (*dest && (cnt > 0)) {
if (*dest == c) return (char *) dest;
dest++;
cnt--;
}
return NULL;
}
/*
* Core support API: Externally visible.
*/
/*
* Get the value of an NVRAM variable
* @param name name of variable to get
* @return value of variable or NULL if undefined
*/
char*
cfe_env_get(unsigned char *nv_buf, char* name)
{
int size;
unsigned char *buffer;
unsigned char *ptr;
unsigned char *envval;
unsigned int reclen;
unsigned int rectype;
int offset;
int flg;
if (!strcmp(name, "nvram_type"))
return "cfe";
size = NVRAM_SIZE;
buffer = &_nvdata[0];
ptr = buffer;
offset = 0;
/* Read the record type and length */
if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
goto error;
}
while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
/* Adjust pointer for TLV type */
rectype = *(ptr);
offset++;
size--;
/*
* Read the length. It can be either 1 or 2 bytes
* depending on the code
*/
if (rectype & ENV_LENGTH_8BITS) {
/* Read the record type and length - 8 bits */
if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
goto error;
}
reclen = *(ptr);
size--;
offset++;
}
else {
/* Read the record type and length - 16 bits, MSB first */
if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
goto error;
}
reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
size -= 2;
offset += 2;
}
if (reclen > size)
break; /* should not happen, bad NVRAM */
switch (rectype) {
case ENV_TLV_TYPE_ENV:
/* Read the TLV data */
if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
goto error;
flg = *ptr++;
envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
if (envval) {
*envval++ = '\0';
memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
_valuestr[(reclen-1)-(envval-ptr)] = '\0';
#if 0
printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
#endif
if(!strcmp(ptr, name)){
return _valuestr;
}
if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
return _valuestr;
}
break;
default:
/* Unknown TLV type, skip it. */
break;
}
/*
* Advance to next TLV
*/
size -= (int)reclen;
offset += reclen;
/* Read the next record type */
ptr = buffer;
if (_nvram_read(nv_buf, ptr,offset,1) != 1)
goto error;
}
error:
return NULL;
}

37
target/linux/brcm47xx/files-2.6.25/arch/mips/bcm47xx/include/nvram.h
View file

@ -1,37 +0,0 @@
/*
* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __NVRAM_H
#define __NVRAM_H
struct nvram_header {
u32 magic;
u32 len;
u32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
u32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
u32 config_ncdl; /* ncdl values for memc */
};
struct nvram_tuple {
char *name;
char *value;
struct nvram_tuple *next;
};
#define NVRAM_HEADER 0x48534C46 /* 'FLSH' */
#define NVRAM_VERSION 1
#define NVRAM_HEADER_SIZE 20
#define NVRAM_SPACE 0x8000
#define NVRAM_MAX_VALUE_LEN 255
#define NVRAM_MAX_PARAM_LEN 64
char *nvram_get(const char *name);
#endif

125
target/linux/brcm47xx/files-2.6.25/arch/mips/bcm47xx/nvram.c
View file

@ -1,125 +0,0 @@
/*
* BCM947xx nvram variable access
*
* Copyright 2005, Broadcom Corporation
* Copyright 2006, Felix Fietkau <nbd@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/ssb/ssb.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
#include <asm/byteorder.h>
#include <asm/bootinfo.h>
#include <asm/addrspace.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <nvram.h>
#define MB * 1048576
extern struct ssb_bus ssb;
static char nvram_buf[NVRAM_SPACE];
static int cfe_env;
extern char *cfe_env_get(char *nv_buf, const char *name);
/* Probe for NVRAM header */
static void __init early_nvram_init(void)
{
struct ssb_mipscore *mcore = &ssb.mipscore;
struct nvram_header *header;
int i;
u32 base, lim, off;
u32 *src, *dst;
base = mcore->flash_window;
lim = mcore->flash_window_size;
cfe_env = 0;
/* XXX: hack for supporting the CFE environment stuff on WGT634U */
if (lim >= 8 MB) {
src = (u32 *) KSEG1ADDR(base + 8 MB - 0x2000);
dst = (u32 *) nvram_buf;
if ((*src & 0xff00ff) == 0x000001) {
printk("early_nvram_init: WGT634U NVRAM found.\n");
for (i = 0; i < 0x1ff0; i++) {
if (*src == 0xFFFFFFFF)
break;
*dst++ = *src++;
}
cfe_env = 1;
return;
}
}
off = 0x20000;
while (off <= lim) {
/* Windowed flash access */
header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
if (header->magic == NVRAM_HEADER)
goto found;
off <<= 1;
}
/* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
header = (struct nvram_header *) KSEG1ADDR(base + 4096);
if (header->magic == NVRAM_HEADER)
goto found;
header = (struct nvram_header *) KSEG1ADDR(base + 1024);
if (header->magic == NVRAM_HEADER)
goto found;
return;
found:
src = (u32 *) header;
dst = (u32 *) nvram_buf;
for (i = 0; i < sizeof(struct nvram_header); i += 4)
*dst++ = *src++;
for (; i < header->len && i < NVRAM_SPACE; i += 4)
*dst++ = le32_to_cpu(*src++);
}
char *nvram_get(const char *name)
{
char *var, *value, *end, *eq;
if (!name)
return NULL;
if (!nvram_buf[0])
early_nvram_init();
if (cfe_env)
return cfe_env_get(nvram_buf, name);
/* Look for name=value and return value */
var = &nvram_buf[sizeof(struct nvram_header)];
end = nvram_buf + sizeof(nvram_buf) - 2;
end[0] = end[1] = '\0';
for (; *var; var = value + strlen(value) + 1) {
if (!(eq = strchr(var, '=')))
break;
value = eq + 1;
if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
return value;
}
return NULL;
}
EXPORT_SYMBOL(nvram_get);

439
target/linux/brcm47xx/files-2.6.25/drivers/mtd/maps/bcm47xx-flash.c
View file

@ -1,439 +0,0 @@
/*
* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
* Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
* Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
*
* original functions for finding root filesystem from Mike Baker
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Copyright 2001-2003, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* Flash mapping for BCM947XX boards
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/wait.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#ifdef CONFIG_MTD_PARTITIONS
#include <linux/mtd/partitions.h>
#endif
#include <linux/crc32.h>
#ifdef CONFIG_SSB
#include <linux/ssb/ssb.h>
#endif
#include <asm/io.h>
#define TRX_MAGIC 0x30524448 /* "HDR0" */
#define TRX_VERSION 1
#define TRX_MAX_LEN 0x3A0000
#define TRX_NO_HEADER 1 /* Do not write TRX header */
#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
#define TRX_MAX_OFFSET 3
struct trx_header {
u32 magic; /* "HDR0" */
u32 len; /* Length of file including header */
u32 crc32; /* 32-bit CRC from flag_version to end of file */
u32 flag_version; /* 0:15 flags, 16:31 version */
u32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
};
#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
#define NVRAM_SPACE 0x8000
#define WINDOW_ADDR 0x1fc00000
#define WINDOW_SIZE 0x400000
#define BUSWIDTH 2
#ifdef CONFIG_SSB
extern struct ssb_bus ssb_bcm47xx;
#endif
static struct mtd_info *bcm47xx_mtd;
static void bcm47xx_map_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
{
if (len==1) {
memcpy_fromio(to, map->virt + from, len);
} else {
int i;
u16 *dest = (u16 *) to;
u16 *src = (u16 *) (map->virt + from);
for (i = 0; i < (len / 2); i++) {
dest[i] = src[i];
}
if (len & 1)
*((u8 *)dest+len-1) = src[i] & 0xff;
}
}
static struct map_info bcm47xx_map = {
name: "Physically mapped flash",
size: WINDOW_SIZE,
bankwidth: BUSWIDTH,
phys: WINDOW_ADDR,
};
#ifdef CONFIG_MTD_PARTITIONS
static struct mtd_partition bcm47xx_parts[] = {
{ name: "cfe", offset: 0, size: 0, mask_flags: MTD_WRITEABLE, },
{ name: "linux", offset: 0, size: 0, },
{ name: "rootfs", offset: 0, size: 0, },
{ name: "nvram", offset: 0, size: 0, },
{ name: NULL, },
};
static int __init
find_cfe_size(struct mtd_info *mtd, size_t size)
{
struct trx_header *trx;
unsigned char buf[512];
int off;
size_t len;
int blocksize;
trx = (struct trx_header *) buf;
blocksize = mtd->erasesize;
if (blocksize < 0x10000)
blocksize = 0x10000;
for (off = (128*1024); off < size; off += blocksize) {
memset(buf, 0xe5, sizeof(buf));
/*
* Read into buffer
*/
if (mtd->read(mtd, off, sizeof(buf), &len, buf) ||
len != sizeof(buf))
continue;
/* found a TRX header */
if (le32_to_cpu(trx->magic) == TRX_MAGIC) {
goto found;
}
}
printk(KERN_NOTICE
"%s: Couldn't find bootloader size\n",
mtd->name);
return -1;
found:
printk(KERN_NOTICE "bootloader size: %d\n", off);
return off;
}
/*
* Copied from mtdblock.c
*
* Cache stuff...
*
* Since typical flash erasable sectors are much larger than what Linux's
* buffer cache can handle, we must implement read-modify-write on flash
* sectors for each block write requests. To avoid over-erasing flash sectors
* and to speed things up, we locally cache a whole flash sector while it is
* being written to until a different sector is required.
*/
static void erase_callback(struct erase_info *done)
{
wait_queue_head_t *wait_q = (wait_queue_head_t *)done->priv;
wake_up(wait_q);
}
static int erase_write (struct mtd_info *mtd, unsigned long pos,
int len, const char *buf)
{
struct erase_info erase;
DECLARE_WAITQUEUE(wait, current);
wait_queue_head_t wait_q;
size_t retlen;
int ret;
/*
* First, let's erase the flash block.
*/
init_waitqueue_head(&wait_q);
erase.mtd = mtd;
erase.callback = erase_callback;
erase.addr = pos;
erase.len = len;
erase.priv = (u_long)&wait_q;
set_current_state(TASK_INTERRUPTIBLE);
add_wait_queue(&wait_q, &wait);
ret = mtd->erase(mtd, &erase);
if (ret) {
set_current_state(TASK_RUNNING);
remove_wait_queue(&wait_q, &wait);
printk (KERN_WARNING "erase of region [0x%lx, 0x%x] "
"on \"%s\" failed\n",
pos, len, mtd->name);
return ret;
}
schedule(); /* Wait for erase to finish. */
remove_wait_queue(&wait_q, &wait);
/*
* Next, writhe data to flash.
*/
ret = mtd->write (mtd, pos, len, &retlen, buf);
if (ret)
return ret;
if (retlen != len)
return -EIO;
return 0;
}
static int __init
find_root(struct mtd_info *mtd, size_t size, struct mtd_partition *part)
{
struct trx_header trx, *trx2;
unsigned char buf[512], *block;
int off, blocksize;
u32 i, crc = ~0;
size_t len;
struct squashfs_super_block *sb = (struct squashfs_super_block *) buf;
blocksize = mtd->erasesize;
if (blocksize < 0x10000)
blocksize = 0x10000;
for (off = (128*1024); off < size; off += blocksize) {
memset(&trx, 0xe5, sizeof(trx));
/*
* Read into buffer
*/
if (mtd->read(mtd, off, sizeof(trx), &len, (char *) &trx) ||
len != sizeof(trx))
continue;
/* found a TRX header */
if (le32_to_cpu(trx.magic) == TRX_MAGIC) {
part->offset = le32_to_cpu(trx.offsets[2]) ? :
le32_to_cpu(trx.offsets[1]);
part->size = le32_to_cpu(trx.len);
part->size -= part->offset;
part->offset += off;
goto found;
}
}
printk(KERN_NOTICE
"%s: Couldn't find root filesystem\n",
mtd->name);
return -1;
found:
if (part->size == 0)
return 0;
if (mtd->read(mtd, part->offset, sizeof(buf), &len, buf) || len != sizeof(buf))
return 0;
/* Move the fs outside of the trx */
part->size = 0;
if (trx.len != part->offset + part->size - off) {
/* Update the trx offsets and length */
trx.len = part->offset + part->size - off;
/* Update the trx crc32 */
for (i = (u32) &(((struct trx_header *)NULL)->flag_version); i <= trx.len; i += sizeof(buf)) {
if (mtd->read(mtd, off + i, sizeof(buf), &len, buf) || len != sizeof(buf))
return 0;
crc = crc32_le(crc, buf, min(sizeof(buf), trx.len - i));
}
trx.crc32 = crc;
/* read first eraseblock from the trx */
block = kmalloc(mtd->erasesize, GFP_KERNEL);
trx2 = (struct trx_header *) block;
if (mtd->read(mtd, off, mtd->erasesize, &len, block) || len != mtd->erasesize) {
printk("Error accessing the first trx eraseblock\n");
return 0;
}
printk("Updating TRX offsets and length:\n");
printk("old trx = [0x%08x, 0x%08x, 0x%08x], len=0x%08x crc32=0x%08x\n", trx2->offsets[0], trx2->offsets[1], trx2->offsets[2], trx2->len, trx2->crc32);
printk("new trx = [0x%08x, 0x%08x, 0x%08x], len=0x%08x crc32=0x%08x\n", trx.offsets[0], trx.offsets[1], trx.offsets[2], trx.len, trx.crc32);
/* Write updated trx header to the flash */
memcpy(block, &trx, sizeof(trx));
if (mtd->unlock)
mtd->unlock(mtd, off, mtd->erasesize);
erase_write(mtd, off, mtd->erasesize, block);
if (mtd->sync)
mtd->sync(mtd);
kfree(block);
printk("Done\n");
}
return part->size;
}
struct mtd_partition * __init
init_mtd_partitions(struct mtd_info *mtd, size_t size)
{
int cfe_size;
if ((cfe_size = find_cfe_size(mtd,size)) < 0)
return NULL;
/* boot loader */
bcm47xx_parts[0].offset = 0;
bcm47xx_parts[0].size = cfe_size;
/* nvram */
if (cfe_size != 384 * 1024) {
bcm47xx_parts[3].offset = size - ROUNDUP(NVRAM_SPACE, mtd->erasesize);
bcm47xx_parts[3].size = ROUNDUP(NVRAM_SPACE, mtd->erasesize);
} else {
/* nvram (old 128kb config partition on netgear wgt634u) */
bcm47xx_parts[3].offset = bcm47xx_parts[0].size;
bcm47xx_parts[3].size = ROUNDUP(NVRAM_SPACE, mtd->erasesize);
}
/* linux (kernel and rootfs) */
if (cfe_size != 384 * 1024) {
bcm47xx_parts[1].offset = bcm47xx_parts[0].size;
bcm47xx_parts[1].size = bcm47xx_parts[3].offset -
bcm47xx_parts[1].offset;
} else {
/* do not count the elf loader, which is on one block */
bcm47xx_parts[1].offset = bcm47xx_parts[0].size +
bcm47xx_parts[3].size + mtd->erasesize;
bcm47xx_parts[1].size = size -
bcm47xx_parts[0].size -
(2*bcm47xx_parts[3].size) -
mtd->erasesize;
}
/* find and size rootfs */
find_root(mtd,size,&bcm47xx_parts[2]);
bcm47xx_parts[2].size = size - bcm47xx_parts[2].offset - bcm47xx_parts[3].size;
return bcm47xx_parts;
}
#endif
int __init init_bcm47xx_map(void)
{
#ifdef CONFIG_SSB
struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore;
#endif
size_t size;
int ret = 0;
#ifdef CONFIG_MTD_PARTITIONS
struct mtd_partition *parts;
int i;
#endif
#ifdef CONFIG_SSB
u32 window = mcore->flash_window;
u32 window_size = mcore->flash_window_size;
printk("flash init: 0x%08x 0x%08x\n", window, window_size);
bcm47xx_map.phys = window;
bcm47xx_map.size = window_size;
bcm47xx_map.virt = ioremap_nocache(window, window_size);
#else
printk("flash init: 0x%08x 0x%08x\n", WINDOW_ADDR, WINDOW_SIZE);
bcm47xx_map.virt = ioremap_nocache(WINDOW_ADDR, WINDOW_SIZE);
#endif
if (!bcm47xx_map.virt) {
printk("Failed to ioremap\n");
return -EIO;
}
simple_map_init(&bcm47xx_map);
if (!(bcm47xx_mtd = do_map_probe("cfi_probe", &bcm47xx_map))) {
printk("Failed to do_map_probe\n");
iounmap((void *)bcm47xx_map.virt);
return -ENXIO;
}
/* override copy_from routine */
bcm47xx_map.copy_from = bcm47xx_map_copy_from;
bcm47xx_mtd->owner = THIS_MODULE;
size = bcm47xx_mtd->size;
printk(KERN_NOTICE "Flash device: 0x%x at 0x%x\n", size, WINDOW_ADDR);
#ifdef CONFIG_MTD_PARTITIONS
parts = init_mtd_partitions(bcm47xx_mtd, size);
for (i = 0; parts[i].name; i++);
ret = add_mtd_partitions(bcm47xx_mtd, parts, i);
if (ret) {
printk(KERN_ERR "Flash: add_mtd_partitions failed\n");
goto fail;
}
#endif
return 0;
fail:
if (bcm47xx_mtd)
map_destroy(bcm47xx_mtd);
if (bcm47xx_map.virt)
iounmap((void *)bcm47xx_map.virt);
bcm47xx_map.virt = 0;
return ret;
}
void __exit cleanup_bcm47xx_map(void)
{
#ifdef CONFIG_MTD_PARTITIONS
del_mtd_partitions(bcm47xx_mtd);
#endif
map_destroy(bcm47xx_mtd);
iounmap((void *)bcm47xx_map.virt);
}
module_init(init_bcm47xx_map);
module_exit(cleanup_bcm47xx_map);

26
target/linux/brcm47xx/files-2.6.25/include/asm-mips/mach-bcm47xx/kernel-entry-init.h
View file

@ -1,26 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2005 Embedded Alley Solutions, Inc
* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
* Copyright (C) 2006 Michael Buesch
*/
#ifndef __ASM_MACH_GENERIC_KERNEL_ENTRY_H
#define __ASM_MACH_GENERIC_KERNEL_ENTRY_H
/* Intentionally empty macro, used in head.S. Override in
* arch/mips/mach-xxx/kernel-entry-init.h when necessary.
*/
.macro kernel_entry_setup
.endm
/*
* Do SMP slave processor setup necessary before we can savely execute C code.
*/
.macro smp_slave_setup
.endm
#endif /* __ASM_MACH_GENERIC_KERNEL_ENTRY_H */

46
target/linux/brcm47xx/patches-2.6.25/100-board_support.patch
View file

@ -1,46 +0,0 @@
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -50,8 +50,10 @@ config BCM47XX
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SSB
+ select SSB_SERIAL
select SSB_DRIVER_MIPS
select SSB_DRIVER_EXTIF
+ select SSB_DRIVER_PCICORE
select SSB_PCICORE_HOSTMODE if PCI
select GENERIC_GPIO
select SYS_HAS_EARLY_PRINTK
@@ -790,6 +792,7 @@ config CSRC_SB1250
config CFE
bool
+ # Common Firmware Environment
config DMA_COHERENT
bool
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -94,6 +94,12 @@
#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
+/*
+ * Valid machtype for group Broadcom
+ */
+#define MACH_GROUP_BRCM 23 /* Broadcom */
+#define MACH_BCM47XX 1 /* Broadcom BCM47xx */
+
#define CL_SIZE COMMAND_LINE_SIZE
extern char *system_type;
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2001,6 +2001,7 @@
#define PCI_DEVICE_ID_TIGON3_5906M 0x1713
#define PCI_DEVICE_ID_BCM4401 0x4401
#define PCI_DEVICE_ID_BCM4401B0 0x4402
+#define PCI_DEVICE_ID_BCM4713 0x4713
#define PCI_VENDOR_ID_TOPIC 0x151f
#define PCI_DEVICE_ID_TOPIC_TP560 0x0000

25
target/linux/brcm47xx/patches-2.6.25/110-flash_map.patch
View file

@ -1,25 +0,0 @@
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -337,6 +337,12 @@ config MTD_CFI_FLAGADM
Mapping for the Flaga digital module. If you don't have one, ignore
this setting.
+config MTD_BCM47XX
+ tristate "BCM47xx flash device"
+ depends on MIPS && MTD_CFI && BCM47XX
+ help
+ Support for the flash chips on the BCM947xx board.
+
config MTD_WALNUT
tristate "Flash device mapped on IBM 405GP Walnut"
depends on MTD_JEDECPROBE && WALNUT && !PPC_MERGE
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_MTD_PMC_MSP_RAMROOT)+= pmcm
obj-$(CONFIG_MTD_PCMCIA) += pcmciamtd.o
obj-$(CONFIG_MTD_RPXLITE) += rpxlite.o
obj-$(CONFIG_MTD_TQM8XXL) += tqm8xxl.o
+obj-$(CONFIG_MTD_BCM47XX) += bcm47xx-flash.o
obj-$(CONFIG_MTD_SA1100) += sa1100-flash.o
obj-$(CONFIG_MTD_IPAQ) += ipaq-flash.o
obj-$(CONFIG_MTD_SBC_GXX) += sbc_gxx.o

89
target/linux/brcm47xx/patches-2.6.25/130-remove_scache.patch
View file

@ -1,89 +0,0 @@
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -228,7 +228,6 @@ config MIPS_MALTA
select I8259
select MIPS_BOARDS_GEN
select MIPS_BONITO64
- select MIPS_CPU_SCACHE
select PCI_GT64XXX_PCI0
select MIPS_MSC
select SWAP_IO_SPACE
@@ -1421,13 +1420,6 @@ config IP22_CPU_SCACHE
bool
select BOARD_SCACHE
-#
-# Support for a MIPS32 / MIPS64 style S-caches
-#
-config MIPS_CPU_SCACHE
- bool
- select BOARD_SCACHE
-
config R5000_CPU_SCACHE
bool
select BOARD_SCACHE
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -704,6 +704,8 @@ static inline void cpu_probe_mips(struct
break;
case PRID_IMP_25KF:
c->cputype = CPU_25KF;
+ /* Probe for L2 cache */
+ c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
break;
case PRID_IMP_34K:
c->cputype = CPU_34K;
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1103,7 +1103,6 @@ static void __init loongson2_sc_init(voi
extern int r5k_sc_init(void);
extern int rm7k_sc_init(void);
-extern int mips_sc_init(void);
static void __cpuinit setup_scache(void)
{
@@ -1157,29 +1156,17 @@ static void __cpuinit setup_scache(void)
#endif
default:
- if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
- c->isa_level == MIPS_CPU_ISA_M32R2 ||
- c->isa_level == MIPS_CPU_ISA_M64R1 ||
- c->isa_level == MIPS_CPU_ISA_M64R2) {
-#ifdef CONFIG_MIPS_CPU_SCACHE
- if (mips_sc_init ()) {
- scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
- printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
- scache_size >> 10,
- way_string[c->scache.ways], c->scache.linesz);
- }
-#else
- if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
- panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
-#endif
- return;
- }
sc_present = 0;
}
if (!sc_present)
return;
+ if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
+ c->isa_level == MIPS_CPU_ISA_M64R1) &&
+ !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
+ panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
+
/* compute a couple of other cache variables */
c->scache.waysize = scache_size / c->scache.ways;
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -32,6 +32,5 @@ obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-
obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o
-obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o
EXTRA_CFLAGS += -Werror

365
target/linux/brcm47xx/patches-2.6.25/150-cpu_fixes.patch
View file

@ -1,365 +0,0 @@
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -51,6 +51,10 @@ NESTED(except_vec1_generic, 0, sp)
NESTED(except_vec3_generic, 0, sp)
.set push
.set noat
+#ifdef CONFIG_BCM47XX
+ nop
+ nop
+#endif
#if R5432_CP0_INTERRUPT_WAR
mfc0 k0, CP0_INDEX
#endif
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -33,6 +33,9 @@
#include <asm/cacheflush.h> /* for run_uncached() */
+/* For enabling BCM4710 cache workarounds */
+int bcm4710 = 0;
+
/*
* Special Variant of smp_call_function for use by cache functions:
*
@@ -97,6 +100,9 @@ static void __cpuinit r4k_blast_dcache_p
{
unsigned long dc_lsize = cpu_dcache_line_size();
+ if (bcm4710)
+ r4k_blast_dcache_page = blast_dcache_page;
+ else
if (dc_lsize == 0)
r4k_blast_dcache_page = (void *)cache_noop;
else if (dc_lsize == 16)
@@ -111,6 +117,9 @@ static void __cpuinit r4k_blast_dcache_p
{
unsigned long dc_lsize = cpu_dcache_line_size();
+ if (bcm4710)
+ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
+ else
if (dc_lsize == 0)
r4k_blast_dcache_page_indexed = (void *)cache_noop;
else if (dc_lsize == 16)
@@ -125,6 +134,9 @@ static void __cpuinit r4k_blast_dcache_s
{
unsigned long dc_lsize = cpu_dcache_line_size();
+ if (bcm4710)
+ r4k_blast_dcache = blast_dcache;
+ else
if (dc_lsize == 0)
r4k_blast_dcache = (void *)cache_noop;
else if (dc_lsize == 16)
@@ -630,6 +642,8 @@ static void local_r4k_flush_cache_sigtra
unsigned long addr = (unsigned long) arg;
R4600_HIT_CACHEOP_WAR_IMPL;
+ BCM4710_PROTECTED_FILL_TLB(addr);
+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
if (dc_lsize)
protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
if (!cpu_icache_snoops_remote_store && scache_size)
@@ -1215,6 +1229,17 @@ static void __cpuinit coherency_setup(vo
* silly idea of putting something else there ...
*/
switch (current_cpu_type()) {
+ case CPU_BCM3302:
+ {
+ u32 cm;
+ cm = read_c0_diag();
+ /* Enable icache */
+ cm |= (1 << 31);
+ /* Enable dcache */
+ cm |= (1 << 30);
+ write_c0_diag(cm);
+ }
+ break;
case CPU_R4000PC:
case CPU_R4000SC:
case CPU_R4000MC:
@@ -1254,6 +1279,15 @@ void __cpuinit r4k_cache_init(void)
break;
}
+ /* Check if special workarounds are required */
+#ifdef CONFIG_BCM47XX
+ if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
+ printk("Enabling BCM4710A0 cache workarounds.\n");
+ bcm4710 = 1;
+ } else
+#endif
+ bcm4710 = 0;
+
probe_pcache();
setup_scache();
@@ -1303,5 +1337,13 @@ void __cpuinit r4k_cache_init(void)
build_clear_page();
build_copy_page();
local_r4k___flush_cache_all(NULL);
+#ifdef CONFIG_BCM47XX
+ {
+ static void (*_coherency_setup)(void);
+ _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
+ _coherency_setup();
+ }
+#else
coherency_setup();
+#endif
}
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -677,6 +677,9 @@ static void __cpuinit build_r4000_tlb_re
/* No need for uasm_i_nop */
}
+#ifdef CONFIG_BCM47XX
+ uasm_i_nop(&p);
+#endif
#ifdef CONFIG_64BIT
build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
#else
@@ -1084,6 +1087,9 @@ build_r4000_tlbchange_handler_head(u32 *
struct uasm_reloc **r, unsigned int pte,
unsigned int ptr)
{
+#ifdef CONFIG_BCM47XX
+ uasm_i_nop(p);
+#endif
#ifdef CONFIG_64BIT
build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
#else
--- a/include/asm-mips/r4kcache.h
+++ b/include/asm-mips/r4kcache.h
@@ -17,6 +17,20 @@
#include <asm/cpu-features.h>
#include <asm/mipsmtregs.h>
+#ifdef CONFIG_BCM47XX
+#include <asm/paccess.h>
+#include <linux/ssb/ssb.h>
+#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE + SSB_IMSTATE)))
+
+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
+#else
+#define BCM4710_DUMMY_RREG()
+
+#define BCM4710_FILL_TLB(addr)
+#define BCM4710_PROTECTED_FILL_TLB(addr)
+#endif
+
/*
* This macro return a properly sign-extended address suitable as base address
* for indexed cache operations. Two issues here:
@@ -150,6 +164,7 @@ static inline void flush_icache_line_ind
static inline void flush_dcache_line_indexed(unsigned long addr)
{
__dflush_prologue
+ BCM4710_DUMMY_RREG();
cache_op(Index_Writeback_Inv_D, addr);
__dflush_epilogue
}
@@ -169,6 +184,7 @@ static inline void flush_icache_line(uns
static inline void flush_dcache_line(unsigned long addr)
{
__dflush_prologue
+ BCM4710_DUMMY_RREG();
cache_op(Hit_Writeback_Inv_D, addr);
__dflush_epilogue
}
@@ -176,6 +192,7 @@ static inline void flush_dcache_line(uns
static inline void invalidate_dcache_line(unsigned long addr)
{
__dflush_prologue
+ BCM4710_DUMMY_RREG();
cache_op(Hit_Invalidate_D, addr);
__dflush_epilogue
}
@@ -208,6 +225,7 @@ static inline void flush_scache_line(uns
*/
static inline void protected_flush_icache_line(unsigned long addr)
{
+ BCM4710_DUMMY_RREG();
protected_cache_op(Hit_Invalidate_I, addr);
}
@@ -219,6 +237,7 @@ static inline void protected_flush_icach
*/
static inline void protected_writeback_dcache_line(unsigned long addr)
{
+ BCM4710_DUMMY_RREG();
protected_cache_op(Hit_Writeback_Inv_D, addr);
}
@@ -339,8 +358,52 @@ static inline void invalidate_tcache_pag
: "r" (base), \
"i" (op));
+static inline void blast_dcache(void)
+{
+ unsigned long start = KSEG0;
+ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
+ unsigned long end = (start + dcache_size);
+
+ do {
+ BCM4710_DUMMY_RREG();
+ cache_op(Index_Writeback_Inv_D, start);
+ start += current_cpu_data.dcache.linesz;
+ } while(start < end);
+}
+
+static inline void blast_dcache_page(unsigned long page)
+{
+ unsigned long start = page;
+ unsigned long end = start + PAGE_SIZE;
+
+ BCM4710_FILL_TLB(start);
+ do {
+ BCM4710_DUMMY_RREG();
+ cache_op(Hit_Writeback_Inv_D, start);
+ start += current_cpu_data.dcache.linesz;
+ } while(start < end);
+}
+
+static inline void blast_dcache_page_indexed(unsigned long page)
+{
+ unsigned long start = page;
+ unsigned long end = start + PAGE_SIZE;
+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
+ unsigned long ws_end = current_cpu_data.dcache.ways <<
+ current_cpu_data.dcache.waybit;
+ unsigned long ws, addr;
+ for (ws = 0; ws < ws_end; ws += ws_inc) {
+ start = page + ws;
+ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
+ BCM4710_DUMMY_RREG();
+ cache_op(Index_Writeback_Inv_D, addr);
+ }
+ }
+}
+
+
/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, war) \
static inline void blast_##pfx##cache##lsize(void) \
{ \
unsigned long start = INDEX_BASE; \
@@ -352,6 +415,7 @@ static inline void blast_##pfx##cache##l
\
__##pfx##flush_prologue \
\
+ war \
for (ws = 0; ws < ws_end; ws += ws_inc) \
for (addr = start; addr < end; addr += lsize * 32) \
cache##lsize##_unroll32(addr|ws, indexop); \
@@ -366,6 +430,7 @@ static inline void blast_##pfx##cache##l
\
__##pfx##flush_prologue \
\
+ war \
do { \
cache##lsize##_unroll32(start, hitop); \
start += lsize * 32; \
@@ -384,6 +449,8 @@ static inline void blast_##pfx##cache##l
current_cpu_data.desc.waybit; \
unsigned long ws, addr; \
\
+ war \
+ \
__##pfx##flush_prologue \
\
for (ws = 0; ws < ws_end; ws += ws_inc) \
@@ -393,35 +460,37 @@ static inline void blast_##pfx##cache##l
__##pfx##flush_epilogue \
}
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
-
-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);)
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, BCM4710_FILL_TLB(start);)
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);)
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
+
+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
/* build blast_xxx_range, protected_blast_xxx_range */
-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war, war2) \
static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
unsigned long end) \
{ \
unsigned long lsize = cpu_##desc##_line_size(); \
unsigned long addr = start & ~(lsize - 1); \
unsigned long aend = (end - 1) & ~(lsize - 1); \
+ war \
\
__##pfx##flush_prologue \
\
while (1) { \
+ war2 \
prot##cache_op(hitop, addr); \
if (addr == aend) \
break; \
@@ -431,13 +500,13 @@ static inline void prot##blast_##pfx##ca
__##pfx##flush_epilogue \
}
-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_,, )
+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_,, )
+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D,, BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD,,, )
/* blast_inv_dcache_range */
-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D,,,BCM4710_DUMMY_RREG();)
+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
#endif /* _ASM_R4KCACHE_H */
--- a/include/asm-mips/stackframe.h
+++ b/include/asm-mips/stackframe.h
@@ -359,6 +359,10 @@
.macro RESTORE_SP_AND_RET
LONG_L sp, PT_R29(sp)
.set mips3
+#ifdef CONFIG_BCM47XX
+ nop
+ nop
+#endif
eret
.set mips0
.endm

77
target/linux/brcm47xx/patches-2.6.25/160-kmap_coherent.patch
View file

@ -1,77 +0,0 @@
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -211,7 +211,7 @@ void copy_user_highpage(struct page *to,
void *vfrom, *vto;
vto = kmap_atomic(to, KM_USER1);
- if (cpu_has_dc_aliases &&
+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
page_mapped(from) && !Page_dcache_dirty(from)) {
vfrom = kmap_coherent(from, vaddr);
copy_page(vto, vfrom);
@@ -235,7 +235,7 @@ void copy_to_user_page(struct vm_area_st
struct page *page, unsigned long vaddr, void *dst, const void *src,
unsigned long len)
{
- if (cpu_has_dc_aliases &&
+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
page_mapped(page) && !Page_dcache_dirty(page)) {
void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
memcpy(vto, src, len);
@@ -255,7 +255,7 @@ void copy_from_user_page(struct vm_area_
struct page *page, unsigned long vaddr, void *dst, const void *src,
unsigned long len)
{
- if (cpu_has_dc_aliases &&
+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
page_mapped(page) && !Page_dcache_dirty(page)) {
void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
memcpy(dst, vfrom, len);
--- /dev/null
+++ b/include/asm-mips/mach-bcm47xx/cpu-feature-overrides.h
@@ -0,0 +1,13 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_use_kmap_coherent 0
+
+#endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -101,6 +101,9 @@
#ifndef cpu_has_pindexed_dcache
#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
#endif
+#ifndef cpu_use_kmap_coherent
+#define cpu_use_kmap_coherent 1
+#endif
/*
* I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -484,7 +484,7 @@ static inline void local_r4k_flush_cache
* Use kmap_coherent or kmap_atomic to do flushes for
* another ASID than the current one.
*/
- if (cpu_has_dc_aliases)
+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent)
vaddr = kmap_coherent(page, addr);
else
vaddr = kmap_atomic(page, KM_USER0);
@@ -505,7 +505,7 @@ static inline void local_r4k_flush_cache
}
if (vaddr) {
- if (cpu_has_dc_aliases)
+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent)
kunmap_coherent();
else
kunmap_atomic(vaddr, KM_USER0);

31
target/linux/brcm47xx/patches-2.6.25/210-b44_phy_fix.patch
View file

@ -1,31 +0,0 @@
--- a/drivers/net/b44.c
+++ b/drivers/net/b44.c
@@ -339,7 +339,7 @@ static int b44_phy_reset(struct b44 *bp)
}
}
- return 0;
+ return err;
}
static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
@@ -384,7 +384,7 @@ static void b44_set_flow_ctrl(struct b44
__b44_set_flow_ctrl(bp, pause_enab);
}
-#ifdef SSB_DRIVER_MIPS
+#ifdef CONFIG_SSB_DRIVER_MIPS
extern char *nvram_get(char *name);
static void b44_wap54g10_workaround(struct b44 *bp)
{
@@ -2211,6 +2211,10 @@ static int __devinit b44_init_one(struct
*/
b44_chip_reset(bp, B44_CHIP_RESET_FULL);
+ /* do a phy reset to test if there is an active phy */
+ if (b44_phy_reset(bp) < 0)
+ bp->phy_addr = B44_PHY_ADDR_NO_PHY;
+
printk(KERN_INFO "%s: Broadcom 44xx/47xx 10/100BaseT Ethernet %s\n",
dev->name, print_mac(mac, dev->dev_addr));

14
target/linux/brcm47xx/patches-2.6.25/211-b44_bcm4713_phy.patch
View file

@ -1,14 +0,0 @@
--- a/drivers/net/b44.c
+++ b/drivers/net/b44.c
@@ -2094,6 +2094,11 @@ static int __devinit b44_get_invariants(
return -EINVAL;
}
+ if (bp->sdev->id.coreid == 0x806 && bp->sdev->id.revision == 0x0) {
+ bp->phy_addr = B44_PHY_ADDR_NO_PHY;
+ bp->dma_offset = 0;
+ }
+
memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
bp->imask = IMASK_DEF;

48
target/linux/brcm47xx/patches-2.6.25/212-b44_alignment_fix.patch
View file

@ -1,48 +0,0 @@
--- a/drivers/net/b44.c
+++ b/drivers/net/b44.c
@@ -73,8 +73,8 @@
(BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
#define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
-#define RX_PKT_OFFSET 30
-#define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET + 64)
+#define RX_PKT_OFFSET (RX_HEADER_LEN + 2)
+#define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET)
/* minimum number of free TX descriptors required to wake up TX process */
#define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
@@ -682,7 +682,6 @@ static int b44_alloc_rx_skb(struct b44 *
}
rh = (struct rx_header *) skb->data;
- skb_reserve(skb, RX_PKT_OFFSET);
rh->len = 0;
rh->flags = 0;
@@ -693,13 +692,13 @@ static int b44_alloc_rx_skb(struct b44 *
if (src_map != NULL)
src_map->skb = NULL;
- ctrl = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - RX_PKT_OFFSET));
+ ctrl = (DESC_CTRL_LEN & RX_PKT_BUF_SZ);
if (dest_idx == (B44_RX_RING_SIZE - 1))
ctrl |= DESC_CTRL_EOT;
dp = &bp->rx_ring[dest_idx];
dp->ctrl = cpu_to_le32(ctrl);
- dp->addr = cpu_to_le32((u32) mapping + RX_PKT_OFFSET + bp->dma_offset);
+ dp->addr = cpu_to_le32((u32) mapping + bp->dma_offset);
if (bp->flags & B44_FLAG_RX_RING_HACK)
b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
@@ -809,8 +808,8 @@ static int b44_rx(struct b44 *bp, int bu
dma_unmap_single(bp->sdev->dma_dev, map,
skb_size, DMA_FROM_DEVICE);
/* Leave out rx_header */
- skb_put(skb, len + RX_PKT_OFFSET);
- skb_pull(skb, RX_PKT_OFFSET);
+ skb_put(skb, len + RX_PKT_OFFSET);
+ skb_pull(skb, RX_PKT_OFFSET);
} else {
struct sk_buff *copy_skb;

42
target/linux/brcm47xx/patches-2.6.25/220-bcm5354.patch
View file

@ -1,42 +0,0 @@
--- a/drivers/ssb/driver_chipcommon.c
+++ b/drivers/ssb/driver_chipcommon.c
@@ -270,6 +270,8 @@ void ssb_chipco_resume(struct ssb_chipco
void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
u32 *plltype, u32 *n, u32 *m)
{
+ if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
+ return;
*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
switch (*plltype) {
@@ -293,6 +295,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
u32 *plltype, u32 *n, u32 *m)
{
+ if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
+ return;
*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
switch (*plltype) {
--- a/drivers/ssb/driver_mipscore.c
+++ b/drivers/ssb/driver_mipscore.c
@@ -161,6 +161,8 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
rate = 200000000;
+ } else if (bus->chip_id == 0x5354) {
+ rate = 240000000;
} else {
rate = ssb_calc_clock_rate(pll_type, n, m);
}
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
@@ -867,6 +867,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
if (bus->chip_id == 0x5365) {
rate = 100000000;
+ } else if (bus->chip_id == 0x5354) {
+ rate = 120000000;
} else {
rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */

72
target/linux/brcm47xx/patches-2.6.25/250-ohci-ssb-usb2.patch
View file

@ -1,72 +0,0 @@
--- a/drivers/usb/host/ohci-ssb.c
+++ b/drivers/usb/host/ohci-ssb.c
@@ -142,10 +142,59 @@ static int ssb_ohci_attach(struct ssb_de
int err = -ENOMEM;
u32 tmp, flags = 0;
- if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV)
+ /*
+ * THE FOLLOWING COMMENTS PRESERVED FROM GPL SOURCE RELEASE
+ *
+ * The USB core requires a special bit to be set during core
+ * reset to enable host (OHCI) mode. Resetting the SB core in
+ * pcibios_enable_device() is a hack for compatibility with
+ * vanilla usb-ohci so that it does not have to know about
+ * SB. A driver that wants to use the USB core in device mode
+ * should know about SB and should reset the bit back to 0
+ * after calling pcibios_enable_device().
+ */
+
+ if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) {
flags |= SSB_OHCI_TMSLOW_HOSTMODE;
+ ssb_device_enable(dev, flags);
+ }
+
+ /*
+ * USB 2.0 special considerations:
+ *
+ * 1. Since the core supports both OHCI and EHCI functions, it must
+ * only be reset once.
+ *
+ * 2. In addition to the standard SB reset sequence, the Host Control
+ * Register must be programmed to bring the USB core and various
+ * phy components out of reset.
+ */
+
+ else if (dev->id.coreid == SSB_DEV_USB20_HOST) {
+#warning FIX ME need test for core being up & exit
+ ssb_device_enable(dev, 0);
+ ssb_write32(dev, 0x200, 0x7ff);
+ udelay(1);
+ if (dev->id.revision == 1) { // bug in rev 1
+
+ /* Change Flush control reg */
+ tmp = ssb_read32(dev, 0x400);
+ tmp &= ~8;
+ ssb_write32(dev, 0x400, tmp);
+ tmp = ssb_read32(dev, 0x400);
+ printk("USB20H fcr: 0x%0x\n", tmp);
+
+ /* Change Shim control reg */
+ tmp = ssb_read32(dev, 0x304);
+ tmp &= ~0x100;
+ ssb_write32(dev, 0x304, tmp);
+ tmp = ssb_read32(dev, 0x304);
+ printk("USB20H shim: 0x%0x\n", tmp);
+ }
+ }
+ else
+ ssb_device_enable(dev, 0);
- ssb_device_enable(dev, flags);
hcd = usb_create_hcd(&ssb_ohci_hc_driver, dev->dev,
dev->dev->bus_id);
@@ -236,6 +285,7 @@ static int ssb_ohci_resume(struct ssb_de
static const struct ssb_device_id ssb_ohci_table[] = {
SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOSTDEV, SSB_ANY_REV),
SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOST, SSB_ANY_REV),
+ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV),
SSB_DEVTABLE_END
};
MODULE_DEVICE_TABLE(ssb, ssb_ohci_table);

14
target/linux/brcm47xx/patches-2.6.25/260-ohci-set-dma-mask.patch
View file

@ -1,14 +0,0 @@
--- a/drivers/usb/host/ohci-ssb.c
+++ b/drivers/usb/host/ohci-ssb.c
@@ -195,6 +195,11 @@ static int ssb_ohci_attach(struct ssb_de
else
ssb_device_enable(dev, 0);
+ /*
+ * Set dma mask - 32 bit mask is just an assumption
+ */
+ if (ssb_dma_set_mask(dev, DMA_32BIT_MASK))
+ return -EOPNOTSUPP;
hcd = usb_create_hcd(&ssb_ohci_hc_driver, dev->dev,
dev->dev->bus_id);

11
target/linux/brcm47xx/patches-2.6.25/300-fork_cacheflush.patch
View file

@ -1,11 +0,0 @@
--- a/include/asm-mips/cacheflush.h
+++ b/include/asm-mips/cacheflush.h
@@ -32,7 +32,7 @@
extern void (*flush_cache_all)(void);
extern void (*__flush_cache_all)(void);
extern void (*flush_cache_mm)(struct mm_struct *mm);
-#define flush_cache_dup_mm(mm) do { (void) (mm); } while (0)
+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
extern void (*flush_cache_range)(struct vm_area_struct *vma,
unsigned long start, unsigned long end);
extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);

68
target/linux/brcm47xx/patches-2.6.25/310-no_highpage.patch
View file

@ -1,68 +0,0 @@
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -205,32 +205,6 @@ void kunmap_coherent(void)
preempt_check_resched();
}
-void copy_user_highpage(struct page *to, struct page *from,
- unsigned long vaddr, struct vm_area_struct *vma)
-{
- void *vfrom, *vto;
-
- vto = kmap_atomic(to, KM_USER1);
- if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
- page_mapped(from) && !Page_dcache_dirty(from)) {
- vfrom = kmap_coherent(from, vaddr);
- copy_page(vto, vfrom);
- kunmap_coherent();
- } else {
- vfrom = kmap_atomic(from, KM_USER0);
- copy_page(vto, vfrom);
- kunmap_atomic(vfrom, KM_USER0);
- }
- if (((vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc) ||
- pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
- flush_data_cache_page((unsigned long)vto);
- kunmap_atomic(vto, KM_USER1);
- /* Make sure this page is cleared on other CPU's too before using it */
- smp_wmb();
-}
-
-EXPORT_SYMBOL(copy_user_highpage);
-
void copy_to_user_page(struct vm_area_struct *vma,
struct page *page, unsigned long vaddr, void *dst, const void *src,
unsigned long len)
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -32,6 +32,7 @@
#ifndef __ASSEMBLY__
#include <linux/pfn.h>
+#include <asm/cpu-features.h>
#include <asm/io.h>
/*
@@ -64,13 +65,16 @@ static inline void clear_user_page(void
flush_data_cache_page((unsigned long)addr);
}
-extern void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
- struct page *to);
-struct vm_area_struct;
-extern void copy_user_highpage(struct page *to, struct page *from,
- unsigned long vaddr, struct vm_area_struct *vma);
+static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
+ struct page *to)
+{
+ extern void (*flush_data_cache_page)(unsigned long addr);
-#define __HAVE_ARCH_COPY_USER_HIGHPAGE
+ copy_page(vto, vfrom);
+ if (!cpu_has_ic_fills_f_dc ||
+ pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
+ flush_data_cache_page((unsigned long)vto);
+}
/*
* These are used to make use of C type-checking..

372
target/linux/brcm47xx/patches-2.6.25/400-arch-bcm47xx.patch
View file

@ -1,372 +0,0 @@
--- a/arch/mips/bcm47xx/irq.c
+++ b/arch/mips/bcm47xx/irq.c
@@ -1,5 +1,6 @@
/*
* Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
+ * Copyright (C) 2008 Michael Buesch <mb@bu3sch.de>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -23,10 +24,19 @@
*/
#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
+#include <linux/pci.h>
+#include <linux/ssb/ssb.h>
+
#include <asm/irq_cpu.h>
+
+extern struct ssb_bus ssb_bcm47xx;
+
+
void plat_irq_dispatch(void)
{
u32 cause;
@@ -53,3 +63,19 @@ void __init arch_init_irq(void)
{
mips_cpu_irq_init();
}
+
+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+ int res;
+
+ res = ssb_pcibios_map_irq(dev, slot, pin);
+ if (res < 0) {
+ printk(KERN_ALERT "PCI: Failed to map IRQ of device %s\n",
+ dev->dev.bus_id);
+ return 0;
+ }
+ /* IRQ-0 and IRQ-1 are software interrupts. */
+ WARN_ON((res == 0) || (res == 1));
+
+ return res;
+}
--- a/arch/mips/bcm47xx/setup.c
+++ b/arch/mips/bcm47xx/setup.c
@@ -2,7 +2,7 @@
* Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
* Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
- * Copyright (C) 2006 Michael Buesch <mb@bu3sch.de>
+ * Copyright (C) 2006-2008 Michael Buesch <mb@bu3sch.de>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -25,23 +25,52 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
+#include <linux/init.h>
#include <linux/types.h>
-#include <linux/ssb/ssb.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/serial_reg.h>
+#include <linux/serial_8250.h>
#include <asm/bootinfo.h>
-#include <asm/reboot.h>
#include <asm/time.h>
-#include <bcm47xx.h>
+#include <asm/reboot.h>
#include <asm/fw/cfe/cfe_api.h>
+#include <linux/pm.h>
+#include <linux/ssb/ssb.h>
+#include <linux/ssb/ssb_embedded.h>
+
+#include "include/nvram.h"
struct ssb_bus ssb_bcm47xx;
EXPORT_SYMBOL(ssb_bcm47xx);
+extern void bcm47xx_pci_init(void);
+
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+ int err;
+
+ err = ssb_pcibios_plat_dev_init(dev);
+ if (err) {
+ printk(KERN_ALERT "PCI: Failed to init device %s\n",
+ pci_name(dev));
+ }
+
+ return err;
+}
+
static void bcm47xx_machine_restart(char *command)
{
printk(KERN_ALERT "Please stand by while rebooting the system...\n");
local_irq_disable();
+ /* CFE has a reboot callback, but that does not work.
+ * Oopses with: Reserved instruction in kernel code.
+ */
+
/* Set the watchdog timer to reset immediately */
- ssb_chipco_watchdog_timer_set(&ssb_bcm47xx.chipco, 1);
+ if (ssb_watchdog_timer_set(&ssb_bcm47xx, 1))
+ printk(KERN_EMERG "SSB watchdog-triggered reboot failed!\n");
while (1)
cpu_relax();
}
@@ -50,12 +79,13 @@ static void bcm47xx_machine_halt(void)
{
/* Disable interrupts and watchdog and spin forever */
local_irq_disable();
- ssb_chipco_watchdog_timer_set(&ssb_bcm47xx.chipco, 0);
+ if (ssb_watchdog_timer_set(&ssb_bcm47xx, 0))
+ printk(KERN_EMERG "Failed to disable SSB watchdog!\n");
while (1)
cpu_relax();
}
-static void str2eaddr(char *str, char *dest)
+static void e_aton(char *str, char *dest)
{
int i = 0;
@@ -72,52 +102,141 @@ static void str2eaddr(char *str, char *d
}
}
-static int bcm47xx_get_invariants(struct ssb_bus *bus,
- struct ssb_init_invariants *iv)
+static void bcm47xx_fill_sprom(struct ssb_sprom *sprom)
{
- char buf[100];
+ char *s;
- /* Fill boardinfo structure */
- memset(&(iv->boardinfo), 0 , sizeof(struct ssb_boardinfo));
+ memset(sprom, 0xFF, sizeof(struct ssb_sprom));
- if (cfe_getenv("boardvendor", buf, sizeof(buf)) >= 0)
- iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0);
- if (cfe_getenv("boardtype", buf, sizeof(buf)) >= 0)
- iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0);
- if (cfe_getenv("boardrev", buf, sizeof(buf)) >= 0)
- iv->boardinfo.rev = (u16)simple_strtoul(buf, NULL, 0);
-
- /* Fill sprom structure */
- memset(&(iv->sprom), 0, sizeof(struct ssb_sprom));
- iv->sprom.revision = 3;
-
- if (cfe_getenv("et0macaddr", buf, sizeof(buf)) >= 0)
- str2eaddr(buf, iv->sprom.et0mac);
- if (cfe_getenv("et1macaddr", buf, sizeof(buf)) >= 0)
- str2eaddr(buf, iv->sprom.et1mac);
- if (cfe_getenv("et0phyaddr", buf, sizeof(buf)) >= 0)
- iv->sprom.et0phyaddr = simple_strtoul(buf, NULL, 10);
- if (cfe_getenv("et1phyaddr", buf, sizeof(buf)) >= 0)
- iv->sprom.et1phyaddr = simple_strtoul(buf, NULL, 10);
- if (cfe_getenv("et0mdcport", buf, sizeof(buf)) >= 0)
- iv->sprom.et0mdcport = simple_strtoul(buf, NULL, 10);
- if (cfe_getenv("et1mdcport", buf, sizeof(buf)) >= 0)
- iv->sprom.et1mdcport = simple_strtoul(buf, NULL, 10);
+ sprom->revision = 1;
+ if ((s = nvram_get("il0macaddr")))
+ e_aton(s, sprom->il0mac);
+ if ((s = nvram_get("et0macaddr")))
+ e_aton(s, sprom->et0mac);
+ if ((s = nvram_get("et1macaddr")))
+ e_aton(s, sprom->et1mac);
+ if ((s = nvram_get("et0phyaddr")))
+ sprom->et0phyaddr = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("et1phyaddr")))
+ sprom->et1phyaddr = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("et0mdcport")))
+ sprom->et0mdcport = !!simple_strtoul(s, NULL, 10);
+ if ((s = nvram_get("et1mdcport")))
+ sprom->et1mdcport = !!simple_strtoul(s, NULL, 10);
+ if ((s = nvram_get("pa0b0")))
+ sprom->pa0b0 = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("pa0b1")))
+ sprom->pa0b1 = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("pa0b2")))
+ sprom->pa0b2 = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("pa1b0")))
+ sprom->pa1b0 = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("pa1b1")))
+ sprom->pa1b1 = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("pa1b2")))
+ sprom->pa1b2 = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("wl0gpio0")))
+ sprom->gpio0 = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("wl0gpio1")))
+ sprom->gpio1 = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("wl0gpio2")))
+ sprom->gpio2 = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("wl0gpio3")))
+ sprom->gpio3 = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("pa0maxpwr")))
+ sprom->maxpwr_bg = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("pa1maxpwr")))
+ sprom->maxpwr_a = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("pa0itssit")))
+ sprom->itssi_bg = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("pa1itssit")))
+ sprom->itssi_a = simple_strtoul(s, NULL, 0);
+ sprom->boardflags_lo = 0;
+ if ((s = nvram_get("boardflags")))
+ sprom->boardflags_lo = simple_strtoul(s, NULL, 0);
+ sprom->boardflags_hi = 0;
+ if ((s = nvram_get("boardflags2")))
+ sprom->boardflags_hi = simple_strtoul(s, NULL, 0);
+}
+
+static int bcm47xx_get_invariants(struct ssb_bus *bus, struct ssb_init_invariants *iv)
+{
+ char *s;
+
+ iv->boardinfo.vendor = SSB_BOARDVENDOR_BCM;
+ if ((s = nvram_get("boardtype")))
+ iv->boardinfo.type = (u16)simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("boardrev")))
+ iv->boardinfo.rev = (u16)simple_strtoul(s, NULL, 0);
+
+ bcm47xx_fill_sprom(&iv->sprom);
+
+ if ((s = nvram_get("cardbus")))
+ iv->has_cardbus_slot = !!simple_strtoul(s, NULL, 10);
return 0;
}
void __init plat_mem_setup(void)
{
- int err;
+ int i, err;
+ char *s;
+ struct ssb_mipscore *mcore;
+
+ err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE, bcm47xx_get_invariants);
+ if (err) {
+ const char *msg = "Failed to initialize SSB bus (err %d)\n";
+ printk(msg, err); /* Make sure the message gets out of the box. */
+ panic(msg, err);
+ }
+ mcore = &ssb_bcm47xx.mipscore;
+
+ s = nvram_get("kernel_args");
+ if (s && !strncmp(s, "console=ttyS1", 13)) {
+ struct ssb_serial_port port;
+
+ printk("Swapping serial ports!\n");
+ /* swap serial ports */
+ memcpy(&port, &mcore->serial_ports[0], sizeof(port));
+ memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1], sizeof(port));
+ memcpy(&mcore->serial_ports[1], &port, sizeof(port));
+ }
- err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE,
- bcm47xx_get_invariants);
- if (err)
- panic("Failed to initialize SSB bus (err %d)\n", err);
+ for (i = 0; i < mcore->nr_serial_ports; i++) {
+ struct ssb_serial_port *port = &(mcore->serial_ports[i]);
+ struct uart_port s;
+
+ memset(&s, 0, sizeof(s));
+ s.line = i;
+ s.membase = port->regs;
+ s.irq = port->irq + 2;
+ s.uartclk = port->baud_base;
+ s.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
+ s.iotype = SERIAL_IO_MEM;
+ s.regshift = port->reg_shift;
+
+ early_serial_setup(&s);
+ }
+ printk("Serial init done.\n");
_machine_restart = bcm47xx_machine_restart;
_machine_halt = bcm47xx_machine_halt;
pm_power_off = bcm47xx_machine_halt;
}
+static int __init bcm47xx_register_gpiodev(void)
+{
+ static struct resource res = {
+ .start = 0xFFFFFFFF,
+ };
+ struct platform_device *pdev;
+
+ pdev = platform_device_register_simple("GPIODEV", 0, &res, 1);
+ if (!pdev) {
+ printk(KERN_ERR "bcm47xx: GPIODEV init failed\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+device_initcall(bcm47xx_register_gpiodev);
--- a/arch/mips/bcm47xx/time.c
+++ b/arch/mips/bcm47xx/time.c
@@ -22,11 +22,17 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
-
#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/serial_reg.h>
+#include <linux/interrupt.h>
#include <linux/ssb/ssb.h>
+#include <asm/addrspace.h>
+#include <asm/io.h>
#include <asm/time.h>
-#include <bcm47xx.h>
+
+extern struct ssb_bus ssb_bcm47xx;
void __init plat_time_init(void)
{
--- a/arch/mips/bcm47xx/nvram.c
+++ b/arch/mips/bcm47xx/nvram.c
@@ -24,10 +24,10 @@
#include <asm/io.h>
#include <asm/uaccess.h>
-#include <nvram.h>
+#include "include/nvram.h"
#define MB * 1048576
-extern struct ssb_bus ssb;
+extern struct ssb_bus ssb_bcm47xx;
static char nvram_buf[NVRAM_SPACE];
static int cfe_env;
@@ -36,7 +36,7 @@ extern char *cfe_env_get(char *nv_buf, c
/* Probe for NVRAM header */
static void __init early_nvram_init(void)
{
- struct ssb_mipscore *mcore = &ssb.mipscore;
+ struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore;
struct nvram_header *header;
int i;
u32 base, lim, off;
--- a/arch/mips/bcm47xx/Makefile
+++ b/arch/mips/bcm47xx/Makefile
@@ -3,4 +3,4 @@
# under Linux.
#
-obj-y := gpio.o irq.o prom.o serial.o setup.o time.o wgt634u.o
+obj-y := cfe_env.o gpio.o irq.o nvram.o prom.o serial.o setup.o time.o wgt634u.o
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -54,6 +54,7 @@ config BCM47XX
select SSB_DRIVER_MIPS
select SSB_DRIVER_EXTIF
select SSB_DRIVER_PCICORE
+ select SSB_B43_PCI_BRIDGE
select SSB_PCICORE_HOSTMODE if PCI
select GENERIC_GPIO
select SYS_HAS_EARLY_PRINTK

117
target/linux/brcm47xx/patches-2.6.25/500-lzma_initramfs.patch
View file

@ -1,117 +0,0 @@
--- a/scripts/gen_initramfs_list.sh
+++ b/scripts/gen_initramfs_list.sh
@@ -287,7 +287,7 @@ if [ ! -z ${output_file} ]; then
if [ "${is_cpio_compressed}" = "compressed" ]; then
cat ${cpio_tfile} > ${output_file}
else
- cat ${cpio_tfile} | gzip -f -9 - > ${output_file}
+ lzma e -lc1 -lp2 -pb2 ${cpio_tfile} ${output_file}
fi
[ -z ${cpio_file} ] && rm ${cpio_tfile}
fi
--- a/init/initramfs.c
+++ b/init/initramfs.c
@@ -441,6 +441,69 @@ static void __init flush_window(void)
outcnt = 0;
}
+#include <linux/LzmaDecode.h>
+static int __init lzma_unzip(void)
+{
+ unsigned int i; /* temp value */
+ unsigned int lc; /* literal context bits */
+ unsigned int lp; /* literal pos state bits */
+ unsigned int pb; /* pos state bits */
+ unsigned int osize; /* uncompressed size */
+ unsigned char *workspace;
+ unsigned char* outputbuffer;
+ unsigned int outsizeProcessed = 0;
+ int workspace_size;
+ int res;
+
+ // lzma args
+ i = get_byte();
+ lc = i % 9, i = i / 9;
+ lp = i % 5, pb = i / 5;
+
+ // skip dictionary size
+ for (i = 0; i < 4; i++)
+ get_byte();
+
+ /* read the lower half of uncompressed size in the header */
+ osize = ((unsigned int)get_byte()) +
+ ((unsigned int)get_byte() << 8) +
+ ((unsigned int)get_byte() << 16) +
+ ((unsigned int)get_byte() << 24);
+
+ /* skip rest of the header (upper half of uncompressed size) */
+ for (i = 0; i < 4; i++)
+ get_byte();
+
+ workspace_size = ((LZMA_BASE_SIZE + (LZMA_LIT_SIZE << (lc + lp))) * sizeof(CProb)) + 100;
+ printk( KERN_NOTICE "initramfs: LZMA lc=%d,lp=%d,pb=%d,origSize=%d\n",
+ lc,lp,pb,osize);
+ outputbuffer = kmalloc(osize, GFP_KERNEL);
+ if (outputbuffer == 0) {
+ printk(KERN_ERR "initramfs: Couldn't allocate lzma output buffer\n");
+ return -1;
+ }
+
+ workspace = kmalloc(workspace_size, GFP_KERNEL);
+ if (workspace == NULL) {
+ printk(KERN_ERR "initramfs: Couldn't allocate lzma workspace\n");
+ return -1;
+ }
+
+ res = LzmaDecode(workspace, workspace_size, lc, lp, pb, inbuf + inptr, insize - inptr, outputbuffer, osize, &outsizeProcessed);
+ if( res != 0 ) {
+ panic( KERN_ERR "initramfs: Lzma decode failure\n");
+ return -1;
+ }
+
+ flush_buffer(outputbuffer, outsizeProcessed);
+ inptr = insize;
+
+ kfree(outputbuffer);
+ kfree(workspace);
+ state = Reset;
+ return 0;
+}
+
static char * __init unpack_to_rootfs(char *buf, unsigned len, int check_only)
{
int written;
@@ -475,12 +538,28 @@ static char * __init unpack_to_rootfs(ch
inptr = 0;
outcnt = 0; /* bytes in output buffer */
bytes_out = 0;
- crc = (ulg)0xffffffffL; /* shift register contents */
- makecrc();
- gunzip();
- if (state != Reset)
+ if( inbuf[0] == 037 && ((inbuf[1] == 0213) || (inbuf[1] == 0236)))
+ {
+ printk( KERN_NOTICE "detected gzip initramfs\n");
+ crc = (ulg)0xffffffffL; /* shift register contents */
+ makecrc();
+ gunzip();
+ if (state != Reset)
error("junk in gzipped archive");
- this_header = saved_offset + inptr;
+ }
+ else if(!memcmp(inbuf+1, "\x00\x00\x80\x00", 4)) /* FIXME: hardcoded dictionary size */
+ {
+ printk( KERN_NOTICE "detected lzma initramfs\n");
+ lzma_unzip();
+ }
+ else
+ {
+ // skip forward ?
+ crc = (ulg)0xffffffffL; /* shift register contents */
+ makecrc();
+ gunzip();
+ }
+ this_header = saved_offset + inptr;
buf += inptr;
len -= inptr;
}

22
target/linux/brcm47xx/patches-2.6.25/601-mips-remove-pci-collision-check.patch
View file

@ -1,22 +0,0 @@
The SSB pcicore driver does create some MMIO resource collisions.
However, the pcicore PCI-fixup routine fixes these collisions afterwards.
Remove this sanity check for now until we find a better solution.
--mb
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -182,12 +182,10 @@ static int pcibios_enable_resources(stru
if ((idx == PCI_ROM_RESOURCE) &&
(!(r->flags & IORESOURCE_ROM_ENABLE)))
continue;
- if (!r->start && r->end) {
- printk(KERN_ERR "PCI: Device %s not available "
- "because of resource collisions\n",
+ if (!r->start && r->end)
+ printk(KERN_WARNING "PCI: Device %s resource"
+ "collisions detected. Ignoring...\n",
pci_name(dev));
- return -EINVAL;
- }
if (r->flags & IORESOURCE_IO)
cmd |= PCI_COMMAND_IO;
if (r->flags & IORESOURCE_MEM)

13
target/linux/brcm47xx/patches-2.6.25/620-ssb-modinit-fix.patch
View file

@ -1,13 +0,0 @@
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
@@ -1173,7 +1173,9 @@ static int __init ssb_modinit(void)
/* ssb must be initialized after PCI but before the ssb drivers.
* That means we must use some initcall between subsys_initcall
* and device_initcall. */
-fs_initcall(ssb_modinit);
+//FIXME on embedded we need to be early to make sure we can register
+// a new PCI bus, if needed.
+subsys_initcall(ssb_modinit);
static void __exit ssb_modexit(void)
{

24
target/linux/brcm47xx/patches-2.6.25/630-ssb-fix-irq-init.patch
View file

@ -1,24 +0,0 @@
Subject: [OpenWrt-Devel] [PATCH] ssb-pcicore: Fix IRQ-vector init on embedded devices
On embedded devices we must not route the interrupts through
the PCI core, if our host-bus is not PCI.
Reported-by: Steve Brown <sbrown@cortland.com>
Signed-off-by: Michael Buesch <mb@bu3sch.de>
--- a/drivers/ssb/driver_pcicore.c
+++ b/drivers/ssb/driver_pcicore.c
@@ -519,6 +519,13 @@ int ssb_pcicore_dev_irqvecs_enable(struc
int err = 0;
u32 tmp;
+ if (dev->bus->bustype != SSB_BUSTYPE_PCI) {
+ /* This SSB device is not on a PCI host-bus. So the IRQs are
+ * not routed through the PCI core.
+ * So we must not enable routing through the PCI core. */
+ goto out;
+ }
+
if (!pdev)
goto out;
bus = pdev->bus;

189
target/linux/brcm47xx/patches-2.6.25/680-ssb-support-8bit-writes.patch
View file

@ -1,189 +0,0 @@
Add support for 8bit reads/writes to SSB.
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
@@ -508,6 +508,14 @@ error:
return err;
}
+static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset)
+{
+ struct ssb_bus *bus = dev->bus;
+
+ offset += dev->core_index * SSB_CORE_SIZE;
+ return readb(bus->mmio + offset);
+}
+
static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
{
struct ssb_bus *bus = dev->bus;
@@ -524,6 +532,14 @@ static u32 ssb_ssb_read32(struct ssb_dev
return readl(bus->mmio + offset);
}
+static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
+{
+ struct ssb_bus *bus = dev->bus;
+
+ offset += dev->core_index * SSB_CORE_SIZE;
+ writeb(value, bus->mmio + offset);
+}
+
static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
{
struct ssb_bus *bus = dev->bus;
@@ -542,8 +558,10 @@ static void ssb_ssb_write32(struct ssb_d
/* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
static const struct ssb_bus_ops ssb_ssb_ops = {
+ .read8 = ssb_ssb_read8,
.read16 = ssb_ssb_read16,
.read32 = ssb_ssb_read32,
+ .write8 = ssb_ssb_write8,
.write16 = ssb_ssb_write16,
.write32 = ssb_ssb_write32,
};
--- a/drivers/ssb/pci.c
+++ b/drivers/ssb/pci.c
@@ -577,6 +577,19 @@ static inline int ssb_pci_assert_buspowe
}
#endif /* DEBUG */
+static u8 ssb_pci_read8(struct ssb_device *dev, u16 offset)
+{
+ struct ssb_bus *bus = dev->bus;
+
+ if (unlikely(ssb_pci_assert_buspower(bus)))
+ return 0xFF;
+ if (unlikely(bus->mapped_device != dev)) {
+ if (unlikely(ssb_pci_switch_core(bus, dev)))
+ return 0xFF;
+ }
+ return ioread8(bus->mmio + offset);
+}
+
static u16 ssb_pci_read16(struct ssb_device *dev, u16 offset)
{
struct ssb_bus *bus = dev->bus;
@@ -603,6 +616,19 @@ static u32 ssb_pci_read32(struct ssb_dev
return ioread32(bus->mmio + offset);
}
+static void ssb_pci_write8(struct ssb_device *dev, u16 offset, u8 value)
+{
+ struct ssb_bus *bus = dev->bus;
+
+ if (unlikely(ssb_pci_assert_buspower(bus)))
+ return;
+ if (unlikely(bus->mapped_device != dev)) {
+ if (unlikely(ssb_pci_switch_core(bus, dev)))
+ return;
+ }
+ iowrite8(value, bus->mmio + offset);
+}
+
static void ssb_pci_write16(struct ssb_device *dev, u16 offset, u16 value)
{
struct ssb_bus *bus = dev->bus;
@@ -631,8 +657,10 @@ static void ssb_pci_write32(struct ssb_d
/* Not "static", as it's used in main.c */
const struct ssb_bus_ops ssb_pci_ops = {
+ .read8 = ssb_pci_read8,
.read16 = ssb_pci_read16,
.read32 = ssb_pci_read32,
+ .write8 = ssb_pci_write8,
.write16 = ssb_pci_write16,
.write32 = ssb_pci_write32,
};
--- a/drivers/ssb/pcmcia.c
+++ b/drivers/ssb/pcmcia.c
@@ -172,6 +172,22 @@ static int select_core_and_segment(struc
return 0;
}
+static u8 ssb_pcmcia_read8(struct ssb_device *dev, u16 offset)
+{
+ struct ssb_bus *bus = dev->bus;
+ unsigned long flags;
+ int err;
+ u8 value = 0xFF;
+
+ spin_lock_irqsave(&bus->bar_lock, flags);
+ err = select_core_and_segment(dev, &offset);
+ if (likely(!err))
+ value = readb(bus->mmio + offset);
+ spin_unlock_irqrestore(&bus->bar_lock, flags);
+
+ return value;
+}
+
static u16 ssb_pcmcia_read16(struct ssb_device *dev, u16 offset)
{
struct ssb_bus *bus = dev->bus;
@@ -206,6 +222,20 @@ static u32 ssb_pcmcia_read32(struct ssb_
return (lo | (hi << 16));
}
+static void ssb_pcmcia_write8(struct ssb_device *dev, u16 offset, u8 value)
+{
+ struct ssb_bus *bus = dev->bus;
+ unsigned long flags;
+ int err;
+
+ spin_lock_irqsave(&bus->bar_lock, flags);
+ err = select_core_and_segment(dev, &offset);
+ if (likely(!err))
+ writeb(value, bus->mmio + offset);
+ mmiowb();
+ spin_unlock_irqrestore(&bus->bar_lock, flags);
+}
+
static void ssb_pcmcia_write16(struct ssb_device *dev, u16 offset, u16 value)
{
struct ssb_bus *bus = dev->bus;
@@ -238,8 +268,10 @@ static void ssb_pcmcia_write32(struct ss
/* Not "static", as it's used in main.c */
const struct ssb_bus_ops ssb_pcmcia_ops = {
+ .read8 = ssb_pcmcia_read8,
.read16 = ssb_pcmcia_read16,
.read32 = ssb_pcmcia_read32,
+ .write8 = ssb_pcmcia_write8,
.write16 = ssb_pcmcia_write16,
.write32 = ssb_pcmcia_write32,
};
--- a/include/linux/ssb/ssb.h
+++ b/include/linux/ssb/ssb.h
@@ -72,8 +72,10 @@ struct ssb_device;
/* Lowlevel read/write operations on the device MMIO.
* Internal, don't use that outside of ssb. */
struct ssb_bus_ops {
+ u8 (*read8)(struct ssb_device *dev, u16 offset);
u16 (*read16)(struct ssb_device *dev, u16 offset);
u32 (*read32)(struct ssb_device *dev, u16 offset);
+ void (*write8)(struct ssb_device *dev, u16 offset, u8 value);
void (*write16)(struct ssb_device *dev, u16 offset, u16 value);
void (*write32)(struct ssb_device *dev, u16 offset, u32 value);
};
@@ -348,6 +350,10 @@ void ssb_device_disable(struct ssb_devic
/* Device MMIO register read/write functions. */
+static inline u8 ssb_read8(struct ssb_device *dev, u16 offset)
+{
+ return dev->ops->read8(dev, offset);
+}
static inline u16 ssb_read16(struct ssb_device *dev, u16 offset)
{
return dev->ops->read16(dev, offset);
@@ -356,6 +362,10 @@ static inline u32 ssb_read32(struct ssb_
{
return dev->ops->read32(dev, offset);
}
+static inline void ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
+{
+ dev->ops->write8(dev, offset, value);
+}
static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
{
dev->ops->write16(dev, offset, value);

159
target/linux/brcm47xx/patches-2.6.25/690-mips-allow-pciregister-after-boot.patch
View file

@ -1,159 +0,0 @@
Allow registering PCI devices after early boot.
This is an ugly hack and needs to be rewritten before going upstream.
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -21,6 +21,17 @@
*/
int pci_probe_only;
+/*
+ * Indicate whether PCI-bios init was already done.
+ */
+static int pcibios_init_done;
+
+/*
+ * The currently used busnumber.
+ */
+static int next_busno;
+static int need_domain_info;
+
#define PCI_ASSIGN_ALL_BUSSES 1
unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
@@ -75,8 +86,32 @@ pcibios_align_resource(void *data, struc
res->start = start;
}
-void __devinit register_pci_controller(struct pci_controller *hose)
+/* Most MIPS systems have straight-forward swizzling needs. */
+
+static inline u8 bridge_swizzle(u8 pin, u8 slot)
+{
+ return (((pin - 1) + slot) % 4) + 1;
+}
+
+static u8 common_swizzle(struct pci_dev *dev, u8 *pinp)
{
+ u8 pin = *pinp;
+
+ while (dev->bus->parent) {
+ pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
+ /* Move up the chain of bridges. */
+ dev = dev->bus->self;
+ }
+ *pinp = pin;
+
+ /* The slot is the slot of the last bridge. */
+ return PCI_SLOT(dev->devfn);
+}
+
+void register_pci_controller(struct pci_controller *hose)
+{
+ struct pci_bus *bus;
+
if (request_resource(&iomem_resource, hose->mem_resource) < 0)
goto out;
if (request_resource(&ioport_resource, hose->io_resource) < 0) {
@@ -84,9 +119,6 @@ void __devinit register_pci_controller(s
goto out;
}
- *hose_tail = hose;
- hose_tail = &hose->next;
-
/*
* Do not panic here but later - this might hapen before console init.
*/
@@ -94,41 +126,47 @@ void __devinit register_pci_controller(s
printk(KERN_WARNING
"registering PCI controller with io_map_base unset\n");
}
- return;
-out:
- printk(KERN_WARNING
- "Skipping PCI bus scan due to resource conflict\n");
-}
+ if (pcibios_init_done) {
+ //TODO
-/* Most MIPS systems have straight-forward swizzling needs. */
+ printk(KERN_INFO "Registering a PCI bus after boot\n");
-static inline u8 bridge_swizzle(u8 pin, u8 slot)
-{
- return (((pin - 1) + slot) % 4) + 1;
-}
+ if (!hose->iommu)
+ PCI_DMA_BUS_IS_PHYS = 1;
-static u8 __init common_swizzle(struct pci_dev *dev, u8 *pinp)
-{
- u8 pin = *pinp;
+ bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
+ hose->bus = bus;
+ need_domain_info = need_domain_info || hose->index;
+ hose->need_domain_info = need_domain_info;
+ if (bus) {
+ next_busno = bus->subordinate + 1;
+ /* Don't allow 8-bit bus number overflow inside the hose -
+ reserve some space for bridges. */
+ if (next_busno > 224) {
+ next_busno = 0;
+ need_domain_info = 1;
+ }
+ }
+ if (!pci_probe_only)
+ pci_assign_unassigned_resources();
+ pci_fixup_irqs(common_swizzle, pcibios_map_irq);
+ } else {
+ *hose_tail = hose;
+ hose_tail = &hose->next;
+ }
- while (dev->bus->parent) {
- pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
- /* Move up the chain of bridges. */
- dev = dev->bus->self;
- }
- *pinp = pin;
+ return;
- /* The slot is the slot of the last bridge. */
- return PCI_SLOT(dev->devfn);
+out:
+ printk(KERN_WARNING
+ "Skipping PCI bus scan due to resource conflict\n");
}
static int __init pcibios_init(void)
{
struct pci_controller *hose;
struct pci_bus *bus;
- int next_busno;
- int need_domain_info = 0;
/* Scan all of the recorded PCI controllers. */
for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
@@ -157,6 +195,7 @@ static int __init pcibios_init(void)
if (!pci_probe_only)
pci_assign_unassigned_resources();
pci_fixup_irqs(common_swizzle, pcibios_map_irq);
+ pcibios_init_done = 1;
return 0;
}
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
@@ -1191,9 +1191,7 @@ static int __init ssb_modinit(void)
/* ssb must be initialized after PCI but before the ssb drivers.
* That means we must use some initcall between subsys_initcall
* and device_initcall. */
-//FIXME on embedded we need to be early to make sure we can register
-// a new PCI bus, if needed.
-subsys_initcall(ssb_modinit);
+fs_initcall(ssb_modinit);
static void __exit ssb_modexit(void)
{

1231
target/linux/brcm47xx/patches-2.6.25/700-ssb-gigabit-ethernet-driver.patch
View file

File diff suppressed because it is too large Load diff

38
target/linux/brcm47xx/patches-2.6.25/710-add-gpio-is-valid.patch
View file

@ -1,38 +0,0 @@
Add gpio_is_valid() for bcm47xx
--- a/arch/mips/bcm47xx/gpio.c
+++ b/arch/mips/bcm47xx/gpio.c
@@ -77,3 +77,15 @@ int bcm47xx_gpio_direction_output(unsign
}
EXPORT_SYMBOL_GPL(bcm47xx_gpio_direction_output);
+int bcm47xx_gpio_is_valid(int gpio)
+{
+ if (ssb_bcm47xx.chipco.dev) {
+ if (gpio >= 0 && gpio < BCM47XX_CHIPCO_GPIO_LINES)
+ return 1;
+ } else if (ssb_bcm47xx.extif.dev) {
+ if (gpio >= 0 && gpio < BCM47XX_EXTIF_GPIO_LINES)
+ return 1;
+ }
+ return 0;
+}
+EXPORT_SYMBOL_GPL(bcm47xx_gpio_is_valid);
--- a/include/asm-mips/mach-bcm47xx/gpio.h
+++ b/include/asm-mips/mach-bcm47xx/gpio.h
@@ -17,6 +17,7 @@ extern int bcm47xx_gpio_get_value(unsign
extern void bcm47xx_gpio_set_value(unsigned gpio, int value);
extern int bcm47xx_gpio_direction_input(unsigned gpio);
extern int bcm47xx_gpio_direction_output(unsigned gpio, int value);
+extern int bcm47xx_gpio_is_valid(int gpio);
static inline int gpio_request(unsigned gpio, const char *label)
{
@@ -52,6 +53,8 @@ static inline int gpio_direction_output(
return bcm47xx_gpio_direction_output(gpio, value);
}
+#define gpio_is_valid bcm47xx_gpio_is_valid
+
/* cansleep wrappers */
#include <asm-generic/gpio.h>

108
target/linux/brcm47xx/patches-2.6.25/800-fix_cfe_detection.patch
View file

@ -1,108 +0,0 @@
--- a/arch/mips/bcm47xx/prom.c
+++ b/arch/mips/bcm47xx/prom.c
@@ -32,6 +32,7 @@
#include <asm/fw/cfe/cfe_error.h>
static int cfe_cons_handle;
+static void (* __prom_putchar)(char c);
const char *get_system_type(void)
{
@@ -40,65 +41,40 @@ const char *get_system_type(void)
void prom_putchar(char c)
{
+ if (__prom_putchar)
+ __prom_putchar(c);
+}
+
+void prom_putchar_cfe(char c)
+{
while (cfe_write(cfe_cons_handle, &c, 1) == 0)
;
}
-static __init void prom_init_cfe(void)
+static __init int prom_init_cfe(void)
{
uint32_t cfe_ept;
uint32_t cfe_handle;
uint32_t cfe_eptseal;
- int argc = fw_arg0;
- char **envp = (char **) fw_arg2;
- int *prom_vec = (int *) fw_arg3;
-
- /*
- * Check if a loader was used; if NOT, the 4 arguments are
- * what CFE gives us (handle, 0, EPT and EPTSEAL)
- */
- if (argc < 0) {
- cfe_handle = (uint32_t)argc;
- cfe_ept = (uint32_t)envp;
- cfe_eptseal = (uint32_t)prom_vec;
- } else {
- if ((int)prom_vec < 0) {
- /*
- * Old loader; all it gives us is the handle,
- * so use the "known" entrypoint and assume
- * the seal.
- */
- cfe_handle = (uint32_t)prom_vec;
- cfe_ept = 0xBFC00500;
- cfe_eptseal = CFE_EPTSEAL;
- } else {
- /*
- * Newer loaders bundle the handle/ept/eptseal
- * Note: prom_vec is in the loader's useg
- * which is still alive in the TLB.
- */
- cfe_handle = prom_vec[0];
- cfe_ept = prom_vec[2];
- cfe_eptseal = prom_vec[3];
- }
- }
- if (cfe_eptseal != CFE_EPTSEAL) {
- /* too early for panic to do any good */
- printk(KERN_ERR "CFE's entrypoint seal doesn't match.");
- while (1) ;
- }
+ cfe_eptseal = (uint32_t) fw_arg3;
+ cfe_handle = (uint32_t) fw_arg0;
+ cfe_ept = (uint32_t) fw_arg2;
+
+ if (cfe_eptseal != CFE_EPTSEAL)
+ return -1;
cfe_init(cfe_handle, cfe_ept);
+ return 0;
}
-static __init void prom_init_console(void)
+static __init void prom_init_console_cfe(void)
{
/* Initialize CFE console */
cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
}
-static __init void prom_init_cmdline(void)
+static __init void prom_init_cmdline_cfe(void)
{
char buf[CL_SIZE];
@@ -146,9 +122,12 @@ static __init void prom_init_mem(void)
void __init prom_init(void)
{
- prom_init_cfe();
- prom_init_console();
- prom_init_cmdline();
+ if (prom_init_cfe() == 0) {
+ prom_init_console_cfe();
+ prom_init_cmdline_cfe();
+ __prom_putchar = prom_putchar_cfe;
+ }
+
prom_init_mem();
}