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ar71xx: use correct fractional dividers for {CPU,DDR}_PLL on QCA955x

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SVN-Revision: 33362
This commit is contained in:
Gabor Juhos 2012-09-10 14:38:01 +00:00
parent 2e0e38ad69
commit 4ee5b528de
1 changed files with 2 additions and 2 deletions
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4
target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch
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@ -38,7 +38,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+ QCA955X_PLL_CPU_CONFIG_NFRAC_MASK; + QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
+ +
+ cpu_pll = nint * ath79_ref_clk.rate / ref_div; + cpu_pll = nint * ath79_ref_clk.rate / ref_div;
+ cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6)); + cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6));
+ cpu_pll /= (1 << out_div); + cpu_pll /= (1 << out_div);
+ +
+ pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG); + pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
@ -52,7 +52,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+ QCA955X_PLL_DDR_CONFIG_NFRAC_MASK; + QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
+ +
+ ddr_pll = nint * ath79_ref_clk.rate / ref_div; + ddr_pll = nint * ath79_ref_clk.rate / ref_div;
+ ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10)); + ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10));
+ ddr_pll /= (1 << out_div); + ddr_pll /= (1 << out_div);
+ +
+ clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG); + clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);