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preliminary support for 2.6.28 (based on the patches by Alexandros C. Couloumbis)

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SVN-Revision: 14189
This commit is contained in:
Gabor Juhos 2009-01-25 21:04:15 +00:00
parent 9a74dd2faa
commit 4e8b080d9f
40 changed files with 3291 additions and 2 deletions
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4
target/linux/adm5120/Makefile
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@ -1,5 +1,5 @@
#
# Copyright (C) 2007-2008 OpenWrt.org
# Copyright (C) 2007-2009 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
BOARD:=adm5120
BOARDNAME:=Infineon/ADMtek ADM5120
LINUX_VERSION:=2.6.27.13
LINUX_VERSION:=2.6.28
SUBTARGETS:=router_le router_be
INITRAMFS_EXTRA_FILES:=

53
target/linux/adm5120/files-2.6.28/arch/mips/include/asm/mach-adm5120/adm5120_defs.h Normal file
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/*
* ADM5120 SoC definitions
*
* This file defines some constants specific to the ADM5120 SoC
*
* Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef _ASM_MIPS_MACH_ADM5120_DEFS_H
#define _ASM_MIPS_MACH_ADM5120_DEFS_H
#define ADM5120_SDRAM0_BASE 0x00000000
#define ADM5120_SDRAM1_BASE 0x01000000
#define ADM5120_SRAM1_BASE 0x10000000
#define ADM5120_EXTIO0_BASE 0x10C00000
#define ADM5120_EXTIO0_SIZE 0x00200000
#define ADM5120_EXTIO1_BASE 0x10E00000
#define ADM5120_EXTIO1_SIZE 0x00200000
#define ADM5120_MPMC_BASE 0x11000000
#define ADM5120_MPMC_SIZE 0x00200000
#define ADM5120_USBC_BASE 0x11200000
#define ADM5120_USBC_SIZE 0x00200000
#define ADM5120_PCIMEM_BASE 0x11400000
#define ADM5120_PCIMEM_SIZE 0x00100000
#define ADM5120_PCIIO_BASE 0x11500000
#define ADM5120_PCIIO_SIZE 0x000FFFF0
#define ADM5120_PCICFG_ADDR 0x115FFFF0
#define ADM5120_PCICFG_DATA 0x115FFFF8
#define ADM5120_PCICFG_SIZE 0x00000010
#define ADM5120_SWITCH_BASE 0x12000000
#define ADM5120_SWITCH_SIZE 0x00200000
#define ADM5120_INTC_BASE 0x12200000
#define ADM5120_INTC_SIZE 0x00200000
#define ADM5120_UART0_BASE 0x12600000
#define ADM5120_UART1_BASE 0x12800000
#define ADM5120_UART_SIZE 0x00200000
#define ADM5120_SRAM0_BASE 0x1FC00000
#define ADM5120_NAND_BASE ADM5120_SRAM1_BASE
#define ADM5120_NAND_SIZE 0xB
#define ADM5120_CLK_175 175000000
#define ADM5120_CLK_200 200000000
#define ADM5120_CLK_225 225000000
#define ADM5120_CLK_250 250000000
#define ADM5120_UART_CLOCK 62500000
#endif /* _ASM_MIPS_MACH_ADM5120_DEFS_H */

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target/linux/adm5120/files-2.6.28/arch/mips/include/asm/mach-adm5120/adm5120_info.h Normal file
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/*
* Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef _MACH_ADM5120_INFO_H
#define _MACH_ADM5120_INFO_H
#include <linux/types.h>
extern unsigned int adm5120_prom_type;
#define ADM5120_PROM_GENERIC 0
#define ADM5120_PROM_CFE 1
#define ADM5120_PROM_MYLOADER 2
#define ADM5120_PROM_ROUTERBOOT 3
#define ADM5120_PROM_BOOTBASE 4
#define ADM5120_PROM_UBOOT 5
#define ADM5120_PROM_LAST 5
extern unsigned int adm5120_product_code;
extern unsigned int adm5120_revision;
extern unsigned int adm5120_nand_boot;
extern unsigned long adm5120_speed;
#define ADM5120_SPEED_175 175000000
#define ADM5120_SPEED_200 200000000
#define ADM5120_SPEED_225 225000000
#define ADM5120_SPEED_250 250000000
extern unsigned int adm5120_package;
#define ADM5120_PACKAGE_PQFP 0
#define ADM5120_PACKAGE_BGA 1
extern unsigned long adm5120_memsize;
extern unsigned long adm5120_mach_type;
#define MACH_ADM5120_GENERIC 0 /* Generic board */
#define MACH_ADM5120_WP54G_WRT 1 /* Compex WP54G-WRT */
#define MACH_ADM5120_WP54 2 /* Compex WP54G/WP54AG/WPP54G/WPP54AG */
#define MACH_ADM5120_NP28G 3 /* Compex NP28G */
#define MACH_ADM5120_NP28GHS 4 /* Compex NP28G HotSpot */
#define MACH_ADM5120_NP27G 5 /* Compex NP27G */
#define MACH_ADM5120_WP54Gv1C 6 /* Compex WP54G version 1C */
#define MACH_ADM5120_RB_11X 7 /* Mikrotik RouterBOARD 111/112 */
#define MACH_ADM5120_RB_133 8 /* Mikrotik RouterBOARD 133 */
#define MACH_ADM5120_RB_133C 9 /* Mikrotik RouterBOARD 133c */
#define MACH_ADM5120_RB_150 10 /* Mikrotik RouterBOARD 150 */
#define MACH_ADM5120_RB_153 11 /* Mikrotik RouterBOARD 153 */
#define MACH_ADM5120_RB_192 12 /* Mikrotik RouterBOARD 192 */
#define MACH_ADM5120_HS100 13 /* ZyXEL HomeSafe 100/100W */
#define MACH_ADM5120_P334U 14 /* ZyXEL Prestige 334U */
#define MACH_ADM5120_P334W 15 /* ZyXEL Prestige 334W */
#define MACH_ADM5120_P334WH 16 /* ZyXEL Prestige 334WH */
#define MACH_ADM5120_P334WHD 17 /* ZyXEL Prestige 334WHD */
#define MACH_ADM5120_P334WT 18 /* ZyXEL Prestige 334WT */
#define MACH_ADM5120_P335 19 /* ZyXEL Prestige 335/335WT */
#define MACH_ADM5120_P335PLUS 20 /* ZyXEL Prestige 335Plus */
#define MACH_ADM5120_P335U 21 /* ZyXEL Prestige 335U */
#define MACH_ADM5120_ES2108 22 /* ZyXEL Ethernet Switch 2108 */
#define MACH_ADM5120_ES2108F 23 /* ZyXEL Ethernet Switch 2108-F */
#define MACH_ADM5120_ES2108G 24 /* ZyXEL Ethernet Switch 2108-G */
#define MACH_ADM5120_ES2108LC 25 /* ZyXEL Ethernet Switch 2108-LC */
#define MACH_ADM5120_ES2108PWR 26 /* ZyXEL Ethernet Switch 2108-PWR */
#define MACH_ADM5120_ES2024A 27 /* ZyXEL Ethernet Switch 2024A */
#define MACH_ADM5120_ES2024PWR 28 /* ZyXEL Ethernet Switch 2024PWR */
#define MACH_ADM5120_CAS630 29 /* Cellvision CAS-630/630W */
#define MACH_ADM5120_CAS670 30 /* Cellvision CAS-670/670W */
#define MACH_ADM5120_CAS700 31 /* Cellvision CAS-700/700W */
#define MACH_ADM5120_CAS771 32 /* Cellvision CAS-771/771W */
#define MACH_ADM5120_CAS790 33 /* Cellvision CAS-790 */
#define MACH_ADM5120_CAS861 34 /* Cellvision CAS-861/861W */
#define MACH_ADM5120_NFS101U 35 /* Cellvision NFS-101U/101WU */
#define MACH_ADM5120_NFS202U 36 /* Cellvision NFS-202U/202WU */
#define MACH_ADM5120_EASY5120PATA 37 /* Infineon EASY 5120P-ATA */
#define MACH_ADM5120_EASY5120RT 38 /* Infineon EASY 5120-RT */
#define MACH_ADM5120_EASY5120WVOIP 39 /* Infineon EASY 5120-WVoIP */
#define MACH_ADM5120_EASY83000 40 /* Infineon EASY-83000 */
#define MACH_ADM5120_BR6104K 41 /* Edimax BR-6104K */
#define MACH_ADM5120_BR6104KP 42 /* Edimax BR-6104KP */
#define MACH_ADM5120_BR61X4WG 43 /* Edimax BR-6104Wg/BR-6114WG */
#define MACH_ADM5120_PMUGW 44 /* Motorola Powerline MU Gateway */
/*
* TODO:remove adm5120_eth* variables when the switch driver will be
* converted into a real platform driver
*/
extern unsigned int adm5120_eth_num_ports;
extern unsigned char adm5120_eth_macs[6][6];
extern unsigned char adm5120_eth_vlans[6];
extern void adm5120_soc_init(void) __init;
extern void adm5120_mem_init(void) __init;
extern void adm5120_ndelay(u32 ns);
extern void (*adm5120_board_reset)(void);
extern void adm5120_gpio_init(void) __init;
extern void adm5120_gpio_csx0_enable(void) __init;
extern void adm5120_gpio_csx1_enable(void) __init;
extern void adm5120_gpio_ew_enable(void) __init;
static inline int adm5120_package_pqfp(void)
{
return (adm5120_package == ADM5120_PACKAGE_PQFP);
}
static inline int adm5120_package_bga(void)
{
return (adm5120_package == ADM5120_PACKAGE_BGA);
}
static inline int adm5120_has_pci(void)
{
return (adm5120_package == ADM5120_PACKAGE_BGA);
}
static inline int adm5120_has_gmii(void)
{
return (adm5120_package == ADM5120_PACKAGE_BGA);
}
#endif /* _MACH_ADM5120_INFO_H */

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target/linux/adm5120/files-2.6.28/arch/mips/include/asm/mach-adm5120/adm5120_intc.h Normal file
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/*
* ADM5120 interrupt controller definitions
*
* This header file defines the hardware registers of the ADM5120 SoC
* built-in interrupt controller.
*
* Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef _MACH_ADM5120_INTC_H
#define _MACH_ADM5120_INTC_H
/*
* INTC register offsets
*/
#define INTC_REG_IRQ_STATUS 0x00 /* Interrupt status after masking */
#define INTC_REG_IRQ_RAW_STATUS 0x04 /* Interrupt status before masking */
#define INTC_REG_IRQ_ENABLE 0x08 /* Used to enable the interrupt sources */
#define INTC_REG_IRQ_ENABLE_CLEAR 0x0C /* Used to disable the interrupt sources */
#define INTC_REG_IRQ_DISABLE INTC_REG_IRQ_ENABLE_CLEAR
#define INTC_REG_INT_MODE 0x14 /* The interrupt mode of the sources */
#define INTC_REG_FIQ_STATUS 0x18 /* FIQ status */
#define INTC_REG_IRQ_TEST_SOURCE 0x1C
#define INTC_REG_IRQ_SOURCE_SELECT 0x20
#define INTC_REG_INT_LEVEL 0x24
/*
* INTC IRQ numbers
*/
#define INTC_IRQ_TIMER 0 /* built in timer */
#define INTC_IRQ_UART0 1 /* built-in UART0 */
#define INTC_IRQ_UART1 2 /* built-in UART1 */
#define INTC_IRQ_USBC 3 /* USB Host Controller */
#define INTC_IRQ_GPIO2 4 /* GPIO line 2 */
#define INTC_IRQ_GPIO4 5 /* GPIO line 4 */
#define INTC_IRQ_PCI0 6 /* PCI slot 2 */
#define INTC_IRQ_PCI1 7 /* PCI slot 3 */
#define INTC_IRQ_PCI2 8 /* PCI slot 4 */
#define INTC_IRQ_SWITCH 9 /* built-in ethernet switch */
#define INTC_IRQ_LAST INTC_IRQ_SWITCH
#define INTC_IRQ_COUNT 10
/*
* INTC register bits
*/
#define INTC_INT_TIMER ( 1 << INTC_IRQ_TIMER )
#define INTC_INT_UART0 ( 1 << INTC_IRQ_UART0 )
#define INTC_INT_UART1 ( 1 << INTC_IRQ_UART1 )
#define INTC_INT_USBC ( 1 << INTC_IRQ_USBC )
#define INTC_INT_INTX0 ( 1 << INTC_IRQ_INTX0 )
#define INTC_INT_INTX1 ( 1 << INTC_IRQ_INTX1 )
#define INTC_INT_PCI0 ( 1 << INTC_IRQ_PCI0 )
#define INTC_INT_PCI1 ( 1 << INTC_IRQ_PCI1 )
#define INTC_INT_PCI2 ( 1 << INTC_IRQ_PCI2 )
#define INTC_INT_SWITCH ( 1 << INTC_IRQ_SWITCH )
#define INTC_INT_ALL (( 1 << INTC_IRQ_COUNT)-1)
#endif /* _MACH_ADM5120_INTC_H */

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target/linux/adm5120/files-2.6.28/arch/mips/include/asm/mach-adm5120/adm5120_mpmc.h Normal file
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/*
* ADM5120 MPMC (Multiport Memory Controller) register definitions
*
* Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef _MACH_ADM5120_MPMC_H
#define _MACH_ADM5120_MPMC_H
#define MPMC_READ_REG(r) __raw_readl( \
(void __iomem *)KSEG1ADDR(ADM5120_MPMC_BASE) + MPMC_REG_ ## r)
#define MPMC_WRITE_REG(r, v) __raw_writel((v), \
(void __iomem *)KSEG1ADDR(ADM5120_MPMC_BASE) + MPMC_REG_ ## r)
#define MPMC_REG_CTRL 0x0000
#define MPMC_REG_STATUS 0x0004
#define MPMC_REG_CONF 0x0008
#define MPMC_REG_DC 0x0020
#define MPMC_REG_DR 0x0024
#define MPMC_REG_DRP 0x0030
#define MPMC_REG_DC0 0x0100
#define MPMC_REG_DRC0 0x0104
#define MPMC_REG_DC1 0x0120
#define MPMC_REG_DRC1 0x0124
#define MPMC_REG_DC2 0x0140
#define MPMC_REG_DRC2 0x0144
#define MPMC_REG_DC3 0x0160
#define MPMC_REG_DRC3 0x0164
#define MPMC_REG_SC0 0x0200 /* for F_CS1_N */
#define MPMC_REG_SC1 0x0220 /* for F_CS0_N */
#define MPMC_REG_SC2 0x0240
#define MPMC_REG_WEN2 0x0244
#define MPMC_REG_OEN2 0x0248
#define MPMC_REG_RD2 0x024C
#define MPMC_REG_PG2 0x0250
#define MPMC_REG_WR2 0x0254
#define MPMC_REG_TN2 0x0258
#define MPMC_REG_SC3 0x0260
/* Control register bits */
#define MPMC_CTRL_AM ( 1 << 1 ) /* Address Mirror */
#define MPMC_CTRL_LPM ( 1 << 2 ) /* Low Power Mode */
#define MPMC_CTRL_DWB ( 1 << 3 ) /* Drain Write Buffers */
/* Status register bits */
#define MPMC_STATUS_BUSY ( 1 << 0 ) /* Busy */
#define MPMC_STATUS_WBS ( 1 << 1 ) /* Write Buffer Status */
#define MPMC_STATUS_SRA ( 1 << 2 ) /* Self-Refresh Acknowledge*/
/* Dynamic Control register bits */
#define MPMC_DC_CE ( 1 << 0 )
#define MPMC_DC_DMC ( 1 << 1 )
#define MPMC_DC_SRR ( 1 << 2 )
#define MPMC_DC_SI_SHIFT 7
#define MPMC_DC_SI_MASK ( 3 << 7 )
#define MPMC_DC_SI_NORMAL ( 0 << 7 )
#define MPMC_DC_SI_MODE ( 1 << 7 )
#define MPMC_DC_SI_PALL ( 2 << 7 )
#define MPMC_DC_SI_NOP ( 3 << 7 )
#define SRAM_REG_CONF 0x00
#define SRAM_REG_WWE 0x04
#define SRAM_REG_WOE 0x08
#define SRAM_REG_WRD 0x0C
#define SRAM_REG_WPG 0x10
#define SRAM_REG_WWR 0x14
#define SRAM_REG_WTR 0x18
/* Dynamic Configuration register bits */
#define DC_BE (1 << 19) /* buffer enable */
#define DC_RW_SHIFT 28 /* shift for number of rows */
#define DC_RW_MASK 0x03
#define DC_NB_SHIFT 26 /* shift for number of banks */
#define DC_NB_MASK 0x01
#define DC_CW_SHIFT 22 /* shift for number of columns */
#define DC_CW_MASK 0x07
#define DC_DW_SHIFT 7 /* shift for device width */
#define DC_DW_MASK 0x03
/* Static Configuration register bits */
#define SC_MW_MASK 0x03 /* memory width mask */
#define SC_MW_8 0x00 /* 8 bit memory width */
#define SC_MW_16 0x01 /* 16 bit memory width */
#define SC_MW_32 0x02 /* 32 bit memory width */
#endif /* _MACH_ADM5120_MPMC_H */

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target/linux/adm5120/files-2.6.28/arch/mips/include/asm/mach-adm5120/adm5120_nand.h Normal file
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/*
* ADM5120 NAND interface definitions
*
* This header file defines the hardware registers of the ADM5120 SoC
* built-in NAND interface.
*
* Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
*
* NAND interface routines was based on a driver for Linux 2.6.19+ which
* was derived from the driver for Linux 2.4.xx published by Mikrotik for
* their RouterBoard 1xx and 5xx series boards.
* Copyright (C) 2007 David Goodenough <david.goodenough@linkchoose.co.uk>
* Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef _MACH_ADM5120_NAND_H
#define _MACH_ADM5120_NAND_H
#include <linux/types.h>
#include <linux/io.h>
#include <asm/mach-adm5120/adm5120_defs.h>
#include <asm/mach-adm5120/adm5120_switch.h>
/* NAND control registers */
#define NAND_REG_DATA 0x0 /* data register */
#define NAND_REG_SET_CEn 0x1 /* CE# low */
#define NAND_REG_CLR_CEn 0x2 /* CE# high */
#define NAND_REG_CLR_CLE 0x3 /* CLE low */
#define NAND_REG_SET_CLE 0x4 /* CLE high */
#define NAND_REG_CLR_ALE 0x5 /* ALE low */
#define NAND_REG_SET_ALE 0x6 /* ALE high */
#define NAND_REG_SET_SPn 0x7 /* SP# low (use spare area) */
#define NAND_REG_CLR_SPn 0x8 /* SP# high (do not use spare area) */
#define NAND_REG_SET_WPn 0x9 /* WP# low */
#define NAND_REG_CLR_WPn 0xA /* WP# high */
#define NAND_REG_STATUS 0xB /* Status register */
#define ADM5120_NAND_STATUS_READY 0x80
#define NAND_READ_REG(r) \
readb((void __iomem *)KSEG1ADDR(ADM5120_NAND_BASE) + (r))
#define NAND_WRITE_REG(r, v) \
writeb((v),(void __iomem *)KSEG1ADDR(ADM5120_NAND_BASE) + (r))
/*-------------------------------------------------------------------------*/
static inline void adm5120_nand_enable(void)
{
SW_WRITE_REG(SWITCH_REG_BW_CNTL1, BW_CNTL1_NAND_ENABLE);
SW_WRITE_REG(SWITCH_REG_BOOT_DONE, 1);
}
static inline void adm5120_nand_set_wpn(unsigned int set)
{
NAND_WRITE_REG((set) ? NAND_REG_SET_WPn : NAND_REG_CLR_WPn, 1);
}
static inline void adm5120_nand_set_spn(unsigned int set)
{
NAND_WRITE_REG((set) ? NAND_REG_SET_SPn : NAND_REG_CLR_SPn, 1);
}
static inline void adm5120_nand_set_cle(unsigned int set)
{
NAND_WRITE_REG((set) ? NAND_REG_SET_CLE : NAND_REG_CLR_CLE, 1);
}
static inline void adm5120_nand_set_ale(unsigned int set)
{
NAND_WRITE_REG((set) ? NAND_REG_SET_ALE : NAND_REG_CLR_ALE, 1);
}
static inline void adm5120_nand_set_cen(unsigned int set)
{
NAND_WRITE_REG((set) ? NAND_REG_SET_CEn : NAND_REG_CLR_CEn, 1);
}
static inline u8 adm5120_nand_get_status(void)
{
return NAND_READ_REG(NAND_REG_STATUS);
}
#endif /* _MACH_ADM5120_NAND_H */

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/*
* ADM5120 specific platform definitions
*
* Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef _ASM_MIPS_MACH_ADM5120_PLATFORM_H
#define _ASM_MIPS_MACH_ADM5120_PLATFORM_H
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/leds.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/nand.h>
#include <linux/gpio_buttons.h>
#include <linux/amba/bus.h>
#include <linux/amba/serial.h>
struct adm5120_flash_platform_data {
void (*set_vpp)(struct map_info *, int);
void (*switch_bank)(unsigned);
u32 window_size;
#ifdef CONFIG_MTD_PARTITIONS
unsigned int nr_parts;
struct mtd_partition *parts;
#endif
};
struct adm5120_switch_platform_data {
/* TODO: not yet implemented */
};
struct adm5120_pci_irq {
u8 slot;
u8 func;
u8 pin;
unsigned irq;
};
#define PCIIRQ(s,f,p,i) {.slot = (s), .func = (f), .pin = (p), .irq = (i)}
#ifdef CONFIG_PCI
extern void adm5120_pci_set_irq_map(unsigned int nr_irqs,
struct adm5120_pci_irq *map) __init;
#else
static inline void adm5120_pci_set_irq_map(unsigned int nr_irqs,
struct adm5120_pci_irq *map)
{
}
#endif
extern void adm5120_setup_eth_macs(u8 *mac_base) __init;
extern struct adm5120_flash_platform_data adm5120_flash0_data;
extern struct adm5120_flash_platform_data adm5120_flash1_data;
extern void adm5120_add_device_flash(unsigned id) __init;
extern void adm5120_add_device_usb(void) __init;
extern void adm5120_add_device_uart(unsigned id) __init;
extern void adm5120_add_device_nand(struct platform_nand_data *pdata) __init;
extern void adm5120_add_device_switch(unsigned num_ports, u8 *vlan_map) __init;
extern void adm5120_add_device_gpio(u32 disable_mask) __init;
extern void adm5120_add_device_gpio_buttons(unsigned nbuttons,
struct gpio_button *buttons) __init;
#define GPIO_LED_DEF(g, n, t, a) { \
.name = (n), \
.default_trigger = (t), \
.gpio = (g), \
.active_low = (a) \
}
#define GPIO_LED_STD(g, n, t) GPIO_LED_DEF((g), (n), (t), 0)
#define GPIO_LED_INV(g, n, t) GPIO_LED_DEF((g), (n), (t), 1)
extern void adm5120_add_device_gpio_leds(unsigned num_leds,
struct gpio_led *leds) __init;
#endif /* _ASM_MIPS_MACH_ADM5120_PLATFORM_H */

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/*
* ADM5120 ethernet switch definitions
*
* This header file defines the hardware registers of the ADM5120 SoC
* built-in Ethernet switch.
*
* Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef _MACH_ADM5120_SWITCH_H
#define _MACH_ADM5120_SWITCH_H
#ifndef BIT
# define BIT(at) (1 << (at))
#endif
#define BITMASK(len) (BIT(len)-1)
#define SW_READ_REG(r) __raw_readl( \
(void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + r)
#define SW_WRITE_REG(r, v) __raw_writel((v), \
(void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + r)
/* Switch register offsets */
#define SWITCH_REG_CODE 0x0000
#define SWITCH_REG_SOFT_RESET 0x0004 /* Soft Reset */
#define SWITCH_REG_BOOT_DONE 0x0008 /* Boot Done */
#define SWITCH_REG_SW_RESET 0x000C /* Switch Reset */
#define SWITCH_REG_PHY_STATUS 0x0014 /* PHY Status */
#define SWITCH_REG_MEMCTRL 0x001C /* Memory Control */
#define SWITCH_REG_CPUP_CONF 0x0024 /* CPU Port Configuration */
#define SWITCH_REG_PORT_CONF0 0x0028 /* Port Configuration 0 */
#define SWITCH_REG_PORT_CONF1 0x002C /* Port Configuration 1 */
#define SWITCH_REG_PORT_CONF2 0x0030 /* Port Configuration 2 */
#define SWITCH_REG_VLAN_G1 0x0040 /* VLAN group 1 */
#define SWITCH_REG_VLAN_G2 0x0044 /* VLAN group 2 */
#define SWITCH_REG_SEND_TRIG 0x0048 /* Send Trigger */
#define SWITCH_REG_MAC_WT0 0x0058 /* MAC Write Address 0 */
#define SWITCH_REG_MAC_WT1 0x005C /* MAC Write Address 1 */
#define SWITCH_REG_BW_CNTL0 0x0060 /* Bandwidth Control 0 */
#define SWITCH_REG_BW_CNTL1 0x0064 /* Bandwidth Control 1 */
#define SWITCH_REG_PHY_CNTL0 0x0068 /* PHY Control 0 */
#define SWITCH_REG_PHY_CNTL1 0x006C /* PHY Control 1 */
#define SWITCH_REG_PORT_TH 0x0078 /* Port Threshold */
#define SWITCH_REG_PHY_CNTL2 0x007C /* PHY Control 2 */
#define SWITCH_REG_PHY_CNTL3 0x0080 /* PHY Control 3 */
#define SWITCH_REG_PRI_CNTL 0x0084 /* Priority Control */
#define SWITCH_REG_PHY_CNTL4 0x00A0 /* PHY Control 4 */
#define SWITCH_REG_EMPTY_CNT 0x00A4 /* Empty Count */
#define SWITCH_REG_PORT_CNTLS 0x00A8 /* Port Control Select */
#define SWITCH_REG_PORT_CNTL 0x00AC /* Port Control */
#define SWITCH_REG_INT_STATUS 0x00B0 /* Interrupt Status */
#define SWITCH_REG_INT_MASK 0x00B4 /* Interrupt Mask */
#define SWITCH_REG_GPIO_CONF0 0x00B8 /* GPIO Configuration 0 */
#define SWITCH_REG_GPIO_CONF2 0x00BC /* GPIO Configuration 1 */
#define SWITCH_REG_WDOG0 0x00C0 /* Watchdog 0 */
#define SWITCH_REG_WDOG1 0x00C4 /* Watchdog 1 */
#define SWITCH_REG_SHDA 0x00D0 /* Send High Descriptors Address */
#define SWITCH_REG_SLDA 0x00D4 /* Send Low Descriptors Address */
#define SWITCH_REG_RHDA 0x00D8 /* Receive High Descriptor Address */
#define SWITCH_REG_RLDA 0x00DC /* Receive Low Descriptor Address */
#define SWITCH_REG_SHWA 0x00E0 /* Send High Working Address */
#define SWITCH_REG_SLWA 0x00E4 /* Send Low Working Address */
#define SWITCH_REG_RHWA 0x00E8 /* Receive High Working Address */
#define SWITCH_REG_RLWA 0x00EC /* Receive Low Working Address */
#define SWITCH_REG_TIMER_INT 0x00F0 /* Timer */
#define SWITCH_REG_TIMER 0x00F4 /* Timer Interrupt */
#define SWITCH_REG_PORT0_LED 0x0100
#define SWITCH_REG_PORT1_LED 0x0104
#define SWITCH_REG_PORT2_LED 0x0108
#define SWITCH_REG_PORT3_LED 0x010C
#define SWITCH_REG_PORT4_LED 0x0110
/* CODE register bits */
#define CODE_PC_MASK BITMASK(16) /* Product Code */
#define CODE_REV_SHIFT 16
#define CODE_REV_MASK BITMASK(4) /* Product Revision */
#define CODE_CLKS_SHIFT 20
#define CODE_CLKS_MASK BITMASK(2) /* Clock Speed */
#define CODE_CLKS_175 0 /* 175 MHz */
#define CODE_CLKS_200 1 /* 200 MHz */
#define CODE_CLKS_225 2 /* 225 MHz */
#define CODE_CLKS_250 3 /* 250 MHz */
#define CODE_NAB BIT(24) /* NAND boot */
#define CODE_PK_MASK BITMASK(1) /* Package type */
#define CODE_PK_SHIFT 29
#define CODE_PK_BGA 0 /* BGA package */
#define CODE_PK_PQFP 1 /* PQFP package */
/* MEMCTRL register bits */
#define MEMCTRL_SDRS_MASK BITMASK(3) /* SDRAM bank size */
#define MEMCTRL_SDRS_4M 0x01
#define MEMCTRL_SDRS_8M 0x02
#define MEMCTRL_SDRS_16M 0x03
#define MEMCTRL_SDRS_64M 0x04
#define MEMCTRL_SDRS_128M 0x05
#define MEMCTRL_SDR1_ENABLE BIT(5) /* enable SDRAM bank 1 */
#define MEMCTRL_SRS0_SHIFT 8 /* shift for SRAM0 size */
#define MEMCTRL_SRS1_SHIFT 16 /* shift for SRAM1 size */
#define MEMCTRL_SRS_MASK BITMASK(3) /* SRAM size mask */
#define MEMCTRL_SRS_DISABLED 0x00 /* Disabled */
#define MEMCTRL_SRS_512K 0x01 /* 512KB*/
#define MEMCTRL_SRS_1M 0x02 /* 1MB */
#define MEMCTRL_SRS_2M 0x03 /* 2MB */
#define MEMCTRL_SRS_4M 0x04 /* 4MB */
/* Port bits used in various registers */
#define SWITCH_PORT_PHY0 BIT(0)
#define SWITCH_PORT_PHY1 BIT(1)
#define SWITCH_PORT_PHY2 BIT(2)
#define SWITCH_PORT_PHY3 BIT(3)
#define SWITCH_PORT_PHY4 BIT(4)
#define SWITCH_PORT_MII BIT(5)
#define SWITCH_PORT_CPU BIT(6)
/* Port bit shorthands */
#define SWITCH_PORTS_PHY 0x1F /* phy ports */
#define SWITCH_PORTS_NOCPU 0x3F /* physical ports */
#define SWITCH_PORTS_ALL 0x7F /* all ports */
/* CPUP_CONF register bits */
#define CPUP_CONF_DCPUP BIT(0) /* Disable CPU port */
#define CPUP_CONF_CRCP BIT(1) /* CRC padding from CPU */
#define CPUP_CONF_BTM BIT(2) /* Bridge Testing Mode */
#define CPUP_CONF_DUNP_SHIFT 9 /* Disable Unknown Packets for portX */
#define CPUP_CONF_DMCP_SHIFT 16 /* Disable Mcast Packets form portX */
#define CPUP_CONF_DBCP_SHIFT 24 /* Disable Bcast Packets form portX */
/* PORT_CONF0 register bits */
#define PORT_CONF0_DP_SHIFT 0 /* Disable Port */
#define PORT_CONF0_EMCP_SHIFT 8 /* Enable All MC Packets */
#define PORT_CONF0_BP_SHIFT 16 /* Enable Back Pressure */
/* PORT_CONF1 register bits */
#define PORT_CONF1_DISL_SHIFT 0 /* Disable Learning */
#define PORT_CONF1_BS_SHIFT 6 /* Blocking State */
#define PORT_CONF1_BM_SHIFT 12 /* Blocking Mode */
/* SEND_TRIG register bits */
#define SEND_TRIG_STL BIT(0) /* Send Trigger Low */
#define SEND_TRIG_STH BIT(1) /* Send Trigger High */
/* MAC_WT0 register bits */
#define MAC_WT0_MAWC BIT(0) /* MAC address write command */
#define MAC_WT0_MWD_SHIFT 1
#define MAC_WT0_MWD BIT(1) /* MAC write done */
#define MAC_WT0_WFB BIT(2) /* Write Filter Bit */
#define MAC_WT0_WVN_SHIFT 3 /* Write Vlan Number shift */
#define MAC_WT0_WVE BIT(6) /* Write VLAN enable */
#define MAC_WT0_WPMN_SHIFT 7
#define MAC_WT0_WAF_SHIFT 13 /* Write Age Field shift */
#define MAC_WT0_WAF_EMPTY 0
#define MAC_WT0_WAF_STATIC 7 /* age: static */
#define MAC_WT0_MAC0_SHIFT 16
#define MAC_WT0_MAC1_SHIFT 24
/* MAC_WT1 register bits */
#define MAC_WT1_MAC2_SHIFT 0
#define MAC_WT1_MAC3_SHIFT 8
#define MAC_WT1_MAC4_SHIFT 16
#define MAC_WT1_MAC5_SHIFT 24
/* BW_CNTL0/BW_CNTL1 register bits */
#define BW_CNTL_DISABLE 0x00
#define BW_CNTL_64K 0x01
#define BW_CNTL_128K 0x02
#define BW_CNTL_256K 0x03
#define BW_CNTL_512K 0x04
#define BW_CNTL_1M 0x05
#define BW_CNTL_4M 0x06
#define BW_CNTL_10M 0x07
#define P4TBC_SHIFT 0
#define P4RBC_SHIFT 4
#define P5TBC_SHIFT 8
#define P5RBC_SHIFT 12
#define BW_CNTL1_NAND_ENABLE 0x100
/* PHY_CNTL0 register bits */
#define PHY_CNTL0_PHYA_MASK BITMASK(5)
#define PHY_CNTL0_PHYR_MASK BITMASK(5)
#define PHY_CNTL0_PHYR_SHIFT 8
#define PHY_CNTL0_WC BIT(13) /* Write Command */
#define PHY_CNTL0_RC BIT(14) /* Read Command */
#define PHY_CNTL0_WTD_MASK BIT(16) /* Read Command */
#define PHY_CNTL0_WTD_SHIFT 16
/* PHY_CNTL1 register bits */
#define PHY_CNTL1_WOD BIT(0) /* Write Operation Done */
#define PHY_CNTL1_ROD BIT(1) /* Read Operation Done */
#define PHY_CNTL1_RD_MASK BITMASK(16)
#define PHY_CNTL1_RD_SHIFT 16
/* PHY_CNTL2 register bits */
#define PHY_CNTL2_ANE_SHIFT 0 /* Auto Negotiation Enable */
#define PHY_CNTL2_SC_SHIFT 5 /* Speed Control */
#define PHY_CNTL2_DC_SHIFT 10 /* Duplex Control */
#define PHY_CNTL2_FNCV_SHIFT 15 /* Recommended FC Value */
#define PHY_CNTL2_PHYR_SHIFT 20 /* PHY reset */
#define PHY_CNTL2_AMDIX_SHIFT 25 /* Auto MDIX enable */
/* PHY_CNTL2_RMAE is bad in datasheet */
#define PHY_CNTL2_RMAE BIT(31) /* Recommended MCC Average enable */
/* PHY_CNTL3 register bits */
#define PHY_CNTL3_RNT BIT(10) /* Recommend Normal Threshold */
/* PORT_TH register bits */
#define PORT_TH_PPT_MASK BITMASK(8) /* Per Port Threshold */
#define PORT_TH_CPUT_SHIFT 8 /* CPU Port Buffer Threshold */
#define PORT_TH_CPUT_MASK BITMASK(8)
#define PORT_TH_CPUHT_SHIFT 16 /* CPU Hold Threshold */
#define PORT_TH_CPUHT_MASK BITMASK(8)
#define PORT_TH_CPURT_SHIFT 24 /* CPU Release Threshold */
#define PORT_TH_CPURT_MASK BITMASK(8)
/* EMPTY_CNT register bits */
#define EMPTY_CNT_EBGB_MASK BITMASK(9) /* Empty Blocks in the Global Buffer */
/* GPIO_CONF0 register bits */
#define GPIO_CONF0_MASK BITMASK(8)
#define GPIO_CONF0_IM_SHIFT 0
#define GPIO_CONF0_IV_SHIFT 8
#define GPIO_CONF0_OE_SHIFT 16
#define GPIO_CONF0_OV_SHIFT 24
#define GPIO_CONF0_IM_MASK (0xFF << GPIO_CONF0_IM_SHIFT)
#define GPIO_CONF0_IV_MASK (0xFF << GPIO_CONF0_IV_SHIFT)
#define GPIO_CONF0_OE_MASK (0xFF << GPIO_CONF0_OE_SHIFT)
#define GPIO_CONF0_OV_MASK (0xFF << GPIO_CONF0_OV_SHIFT)
/* GPIO_CONF2 register bits */
#define GPIO_CONF2_CSX0 BIT(4) /* enable CSX0:INTX0 on GPIO 1:2 */
#define GPIO_CONF2_CSX1 BIT(5) /* enable CSX1:INTX1 on GPIO 3:4 */
#define GPIO_CONF2_EW BIT(6) /* enable wait state pin for CSX0/1 */
/* INT_STATUS/INT_MASK register bits */
#define SWITCH_INT_SHD BIT(0) /* Send High Done */
#define SWITCH_INT_SLD BIT(1) /* Send Low Done */
#define SWITCH_INT_RHD BIT(2) /* Receive High Done */
#define SWITCH_INT_RLD BIT(3) /* Receive Low Done */
#define SWITCH_INT_HDF BIT(4) /* High Descriptor Full */
#define SWITCH_INT_LDF BIT(5) /* Low Descriptor Full */
#define SWITCH_INT_P0QF BIT(6) /* Port0 Queue Full */
#define SWITCH_INT_P1QF BIT(7) /* Port1 Queue Full */
#define SWITCH_INT_P2QF BIT(8) /* Port2 Queue Full */
#define SWITCH_INT_P3QF BIT(9) /* Port3 Queue Full */
#define SWITCH_INT_P4QF BIT(10) /* Port4 Queue Full */
#define SWITCH_INT_P5QF BIT(11) /* Port5 Queue Full */
#define SWITCH_INT_CPQF BIT(13) /* CPU Queue Full */
#define SWITCH_INT_GQF BIT(14) /* Global Queue Full */
#define SWITCH_INT_MD BIT(15) /* Must Drop */
#define SWITCH_INT_BCS BIT(16) /* BC Storm */
#define SWITCH_INT_PSC BIT(18) /* Port Status Change */
#define SWITCH_INT_ID BIT(19) /* Intruder Detected */
#define SWITCH_INT_W0TE BIT(20) /* Watchdog 0 Timer Expired */
#define SWITCH_INT_W1TE BIT(21) /* Watchdog 1 Timer Expired */
#define SWITCH_INT_RDE BIT(22) /* Receive Descriptor Error */
#define SWITCH_INT_SDE BIT(23) /* Send Descriptor Error */
#define SWITCH_INT_CPUH BIT(24) /* CPU Hold */
/* TIMER_INT register bits */
#define TIMER_INT_TOS BIT(0) /* time-out status */
#define TIMER_INT_TOM BIT(16) /* mask time-out interrupt */
/* TIMER register bits */
#define TIMER_PERIOD_MASK BITMASK(16) /* mask for timer period */
#define TIMER_PERIOD_DEFAULT 0xFFFF /* default timer period */
#define TIMER_TE BIT(16) /* timer enable bit */
/* PORTx_LED register bits */
#define LED_MODE_MASK BITMASK(4)
#define LED_MODE_INPUT 0
#define LED_MODE_FLASH 1
#define LED_MODE_OUT_HIGH 2
#define LED_MODE_OUT_LOW 3
#define LED_MODE_LINK 4
#define LED_MODE_SPEED 5
#define LED_MODE_DUPLEX 6
#define LED_MODE_ACT 7
#define LED_MODE_COLL 8
#define LED_MODE_LINK_ACT 9
#define LED_MODE_DUPLEX_COLL 10
#define LED_MODE_10M_ACT 11
#define LED_MODE_100M_ACT 12
#define LED0_MODE_SHIFT 0 /* LED0 mode shift */
#define LED1_MODE_SHIFT 4 /* LED1 mode shift */
#define LED2_MODE_SHIFT 8 /* LED2 mode shift */
#define LED0_IV_SHIFT 12 /* LED0 input value shift */
#define LED1_IV_SHIFT 13 /* LED1 input value shift */
#define LED2_IV_SHIFT 14 /* LED2 input value shift */
#endif /* _MACH_ADM5120_SWITCH_H */

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/*
* ADM5120 UART definitions
*
* This header file defines the hardware registers of the ADM5120 SoC
* built-in UARTs.
*
* Copyright (C) 2007 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef _MACH_ADM5120_UART_H
#define _MACH_ADM5120_UART_H
#define UART_BAUDDIV(clk, baud) ((clk/(16 * (baud)))-1)
#define UART_REG_DATA 0x00
#define UART_REG_RSR 0x04
#define UART_REG_ECR UART_REG_RSR
#define UART_REG_LCRH 0x08
#define UART_REG_LCRM 0x0C
#define UART_REG_LCRL 0x10
#define UART_REG_CTRL 0x14
#define UART_REG_FLAG 0x18
/* Receive Status Register bits */
#define UART_RSR_FE ( 1 << 0 )
#define UART_RSR_PE ( 1 << 1 )
#define UART_RSR_BE ( 1 << 2 )
#define UART_RSR_OE ( 1 << 3 )
#define UART_RSR_ERR ( UART_RSR_FE | UART_RSR_PE | UART_RSR_BE )
#define UART_ECR_ALL 0xFF
/* Line Control High register bits */
#define UART_LCRH_BRK ( 1 << 0 ) /* send break */
#define UART_LCRH_PEN ( 1 << 1 ) /* parity enable */
#define UART_LCRH_EPS ( 1 << 2 ) /* even parity select */
#define UART_LCRH_STP1 ( 0 << 3 ) /* one stop bits select */
#define UART_LCRH_STP2 ( 1 << 3 ) /* two stop bits select */
#define UART_LCRH_FEN ( 1 << 4 ) /* FIFO enable */
#define UART_LCRH_WLEN5 ( 0 << 5 )
#define UART_LCRH_WLEN6 ( 1 << 5 )
#define UART_LCRH_WLEN7 ( 2 << 5 )
#define UART_LCRH_WLEN8 ( 3 << 5 )
/* Control register bits */
#define UART_CTRL_EN ( 1 << 0 )
/* Flag register bits */
#define UART_FLAG_CTS ( 1 << 0 )
#define UART_FLAG_DSR ( 1 << 1 )
#define UART_FLAG_DCD ( 1 << 2 )
#define UART_FLAG_BUSY ( 1 << 3 )
#define UART_FLAG_RXFE ( 1 << 4 )
#define UART_FLAG_TXFF ( 1 << 5 )
#define UART_FLAG_RXFF ( 1 << 6 )
#define UART_FLAG_TXFE ( 1 << 7 )
#endif /* _MACH_ADM5120_UART_H */

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/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/* DO NOT EDIT!! - this file automatically generated
* from .s file by awk -f s2h.awk
*/
/* Size definitions
* Copyright (C) ARM Limited 1998. All rights reserved.
*/
#ifndef __sizes_h
#define __sizes_h 1
/* handy sizes */
#define SZ_16 0x00000010
#define SZ_256 0x00000100
#define SZ_512 0x00000200
#define SZ_1K 0x00000400
#define SZ_4K 0x00001000
#define SZ_8K 0x00002000
#define SZ_16K 0x00004000
#define SZ_64K 0x00010000
#define SZ_128K 0x00020000
#define SZ_256K 0x00040000
#define SZ_512K 0x00080000
#define SZ_1M 0x00100000
#define SZ_2M 0x00200000
#define SZ_4M 0x00400000
#define SZ_8M 0x00800000
#define SZ_16M 0x01000000
#define SZ_32M 0x02000000
#define SZ_64M 0x04000000
#define SZ_128M 0x08000000
#define SZ_256M 0x10000000
#define SZ_512M 0x20000000
#define SZ_1G 0x40000000
#define SZ_2G 0x80000000
#endif
/* END */

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/*
* ADM5120 specific CPU feature overrides
*
* Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
*
* This file was derived from: include/asm-mips/cpu-features.h
* Copyright (C) 2003, 2004 Ralf Baechle
* Copyright (C) 2004 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef __ASM_MACH_ADM5120_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_ADM5120_CPU_FEATURE_OVERRIDES_H
/*
* The ADM5120 SOC has a built-in MIPS 4Kc core.
*/
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 1
#define cpu_has_tx39_cache 0
#define cpu_has_sb1_cache 0
#define cpu_has_fpu 0
#define cpu_has_32fpr 0
#define cpu_has_counter 1
#define cpu_has_watch 1
#define cpu_has_divec 1
/* #define cpu_has_vce ? */
/* #define cpu_has_cache_cdex_p ? */
/* #define cpu_has_cache_cdex_s ? */
#define cpu_has_prefetch 1
/* #define cpu_has_mcheck ? */
#define cpu_has_ejtag 1
#define cpu_has_llsc 1
#define cpu_has_mips16 0
#define cpu_has_mdmx 0
#define cpu_has_mips3d 0
#define cpu_has_smartmips 0
/* #define cpu_has_vtag_icache ? */
/* #define cpu_has_dc_aliases ? */
/* #define cpu_has_ic_fills_f_dc ? */
/* #define cpu_has_pindexed_dcache ? */
/* #define cpu_icache_snoops_remote_store ? */
#define cpu_has_mips32r1 1
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#define cpu_has_dsp 0
#define cpu_has_mipsmt 0
/* #define cpu_has_nofpuex ? */
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_64bit_gp_regs 0
#define cpu_has_64bit_addresses 0
/* #define cpu_has_inclusive_pcaches ? */
#define cpu_dcache_line_size() 16
#define cpu_icache_line_size() 16
#endif /* __ASM_MACH_ADM5120_CPU_FEATURE_OVERRIDES_H */

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/*
* ADM5120 GPIO wrappers for arch-neutral GPIO calls
*
* Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef _ASM_MIPS_MACH_ADM5120_GPIO_H
#define _ASM_MIPS_MACH_ADM5120_GPIO_H
#define ARCH_NR_GPIOS 64
#include <asm-generic/gpio.h>
#include <asm/mach-adm5120/adm5120_switch.h>
#define ADM5120_GPIO_PIN0 0
#define ADM5120_GPIO_PIN1 1
#define ADM5120_GPIO_PIN2 2
#define ADM5120_GPIO_PIN3 3
#define ADM5120_GPIO_PIN4 4
#define ADM5120_GPIO_PIN5 5
#define ADM5120_GPIO_PIN6 6
#define ADM5120_GPIO_PIN7 7
#define ADM5120_GPIO_P0L0 8
#define ADM5120_GPIO_P0L1 9
#define ADM5120_GPIO_P0L2 10
#define ADM5120_GPIO_P1L0 11
#define ADM5120_GPIO_P1L1 12
#define ADM5120_GPIO_P1L2 13
#define ADM5120_GPIO_P2L0 14
#define ADM5120_GPIO_P2L1 15
#define ADM5120_GPIO_P2L2 16
#define ADM5120_GPIO_P3L0 17
#define ADM5120_GPIO_P3L1 18
#define ADM5120_GPIO_P3L2 19
#define ADM5120_GPIO_P4L0 20
#define ADM5120_GPIO_P4L1 21
#define ADM5120_GPIO_P4L2 22
#define ADM5120_GPIO_MAX 22
#define ADM5120_GPIO_COUNT ADM5120_GPIO_MAX+1
#define ADM5120_GPIO_LOW 0
#define ADM5120_GPIO_HIGH 1
#define ADM5120_GPIO_SWITCH 0x10
#define ADM5120_GPIO_FLASH (ADM5120_GPIO_SWITCH | LED_MODE_FLASH)
#define ADM5120_GPIO_LINK (ADM5120_GPIO_SWITCH | LED_MODE_LINK)
#define ADM5120_GPIO_SPEED (ADM5120_GPIO_SWITCH | LED_MODE_SPEED)
#define ADM5120_GPIO_DUPLEX (ADM5120_GPIO_SWITCH | LED_MODE_DUPLEX)
#define ADM5120_GPIO_ACT (ADM5120_GPIO_SWITCH | LED_MODE_ACT)
#define ADM5120_GPIO_COLL (ADM5120_GPIO_SWITCH | LED_MODE_COLL)
#define ADM5120_GPIO_LINK_ACT (ADM5120_GPIO_SWITCH | LED_MODE_LINK_ACT)
#define ADM5120_GPIO_DUPLEX_COLL (ADM5120_GPIO_SWITCH | LED_MODE_DUPLEX_COLL)
#define ADM5120_GPIO_10M_ACT (ADM5120_GPIO_SWITCH | LED_MODE_10M_ACT)
#define ADM5120_GPIO_100M_ACT (ADM5120_GPIO_SWITCH | LED_MODE_100M_ACT)
extern int __adm5120_gpio0_get_value(unsigned gpio);
extern void __adm5120_gpio0_set_value(unsigned gpio, int value);
extern int __adm5120_gpio1_get_value(unsigned gpio);
extern void __adm5120_gpio1_set_value(unsigned gpio, int value);
extern int adm5120_gpio_to_irq(unsigned gpio);
extern int adm5120_irq_to_gpio(unsigned irq);
static inline int gpio_get_value(unsigned gpio)
{
int ret;
switch (gpio) {
case ADM5120_GPIO_PIN0 ... ADM5120_GPIO_PIN7:
ret = __adm5120_gpio0_get_value(gpio);
break;
case ADM5120_GPIO_P0L0 ... ADM5120_GPIO_P4L2:
ret = __adm5120_gpio1_get_value(gpio - ADM5120_GPIO_P0L0);
break;
default:
ret = __gpio_get_value(gpio);
break;
}
return ret;
}
static inline void gpio_set_value(unsigned gpio, int value)
{
switch (gpio) {
case ADM5120_GPIO_PIN0 ... ADM5120_GPIO_PIN7:
__adm5120_gpio0_set_value(gpio, value);
break;
case ADM5120_GPIO_P0L0 ... ADM5120_GPIO_P4L2:
__adm5120_gpio1_set_value(gpio - ADM5120_GPIO_P0L0, value);
break;
default:
__gpio_set_value(gpio, value);
break;
}
}
static inline int gpio_to_irq(unsigned gpio)
{
return adm5120_gpio_to_irq(gpio);
}
static inline int irq_to_gpio(unsigned irq)
{
return adm5120_irq_to_gpio(irq);
}
#define gpio_cansleep __gpio_cansleep
#endif /* _ASM_MIPS_MACH_ADM5120_GPIO_H */

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/*
* ADM5120 specific IRQ numbers
*
* Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef _ASM_MIPS_MACH_ADM5120_IRQ_H
#define _ASM_MIPS_MACH_ADM5120_IRQ_H
#define MIPS_CPU_IRQ_BASE 0
#define NR_IRQS 24
#include_next <irq.h>
#include <asm/mach-adm5120/adm5120_intc.h>
#define NO_IRQ (-1)
#define MIPS_CPU_IRQ_COUNT 8
#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
#define ADM5120_INTC_IRQ_BASE (MIPS_CPU_IRQ_BASE + MIPS_CPU_IRQ_COUNT)
#define ADM5120_INTC_IRQ(x) (ADM5120_INTC_IRQ_BASE + (x))
#define ADM5120_IRQ_INTC MIPS_CPU_IRQ(2)
#define ADM5120_IRQ_COUNTER MIPS_CPU_IRQ(7)
#define ADM5120_IRQ_TIMER ADM5120_INTC_IRQ(INTC_IRQ_TIMER)
#define ADM5120_IRQ_UART0 ADM5120_INTC_IRQ(INTC_IRQ_UART0)
#define ADM5120_IRQ_UART1 ADM5120_INTC_IRQ(INTC_IRQ_UART1)
#define ADM5120_IRQ_USBC ADM5120_INTC_IRQ(INTC_IRQ_USBC)
#define ADM5120_IRQ_GPIO2 ADM5120_INTC_IRQ(INTC_IRQ_GPIO2)
#define ADM5120_IRQ_GPIO4 ADM5120_INTC_IRQ(INTC_IRQ_GPIO4)
#define ADM5120_IRQ_PCI0 ADM5120_INTC_IRQ(INTC_IRQ_PCI0)
#define ADM5120_IRQ_PCI1 ADM5120_INTC_IRQ(INTC_IRQ_PCI1)
#define ADM5120_IRQ_PCI2 ADM5120_INTC_IRQ(INTC_IRQ_PCI2)
#define ADM5120_IRQ_SWITCH ADM5120_INTC_IRQ(INTC_IRQ_SWITCH)
#endif /* _ASM_MIPS_MACH_ADM5120_IRQ_H */

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/*
* ADMBoot specific definitions
*
* Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef _ADMBOOT_H
#define _ADMBOOT_H
extern int admboot_get_mac_base(u32 offset, u32 len, u8 *mac) __init;
#endif /* _ADMBOOT_H */

18
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/*
* Broadcom's CFE definitions
*
* Copyright (C) 2006-2008 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef _PROM_CFE_H_
#define _PROM_CFE_H_
extern int cfe_present(void) __init;
extern char *cfe_getenv(char *);
#endif /*_PROM_CFE_H_*/

18
target/linux/adm5120/files-2.6.28/arch/mips/include/asm/mach-adm5120/prom/generic.h Normal file
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/*
* Generic prom definitions
*
* Copyright (C) 2006-2008 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef _PROM_GENERIC_H_
#define _PROM_GENERIC_H_
extern int generic_prom_present(void) __init;
extern char *generic_prom_getenv(char *);
#endif /*_PROM_GENERIC_H_*/

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/*
* Compex's MyLoader specific definitions
*
* Copyright (C) 2006-2008 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef _MYLOADER_H_
#define _MYLOADER_H_
/*
* Firmware file format:
*
* <header>
* [<block descriptor 0>]
* ...
* [<block descriptor n>]
* <null block descriptor>
* [<block data 0>]
* ...
* [<block data n>]
*
*
*/
/* Myloader specific magic numbers */
#define MYLO_MAGIC_FIRMWARE 0x4C594D00
#define MYLO_MAGIC_20021103 0x20021103
#define MYLO_MAGIC_20021107 0x20021107
#define MYLO_MAGIC_SYS_PARAMS MYLO_MAGIC_20021107
#define MYLO_MAGIC_PARTITIONS MYLO_MAGIC_20021103
#define MYLO_MAGIC_BOARD_PARAMS MYLO_MAGIC_20021103
/*
* Addresses of the data structures provided by MyLoader
*/
#define MYLO_MIPS_SYS_PARAMS 0x80000800 /* System Parameters */
#define MYLO_MIPS_BOARD_PARAMS 0x80000A00 /* Board Parameters */
#define MYLO_MIPS_PARTITIONS 0x80000C00 /* Partition Table */
#define MYLO_MIPS_BOOT_PARAMS 0x80000E00 /* Boot Parameters */
/* Vendor ID's (seems to be same as the PCI vendor ID's) */
#define VENID_COMPEX 0x11F6
/* Devices based on the ADM5120 */
#define DEVID_COMPEX_NP27G 0x0078
#define DEVID_COMPEX_NP28G 0x044C
#define DEVID_COMPEX_NP28GHS 0x044E
#define DEVID_COMPEX_WP54Gv1C 0x0514
#define DEVID_COMPEX_WP54G 0x0515
#define DEVID_COMPEX_WP54AG 0x0546
#define DEVID_COMPEX_WPP54AG 0x0550
#define DEVID_COMPEX_WPP54G 0x0555
/* Devices based on the IXP422 */
#define DEVID_COMPEX_WP18 0x047E
#define DEVID_COMPEX_NP18A 0x0489
/* Other devices */
#define DEVID_COMPEX_NP26G8M 0x03E8
#define DEVID_COMPEX_NP26G16M 0x03E9
struct mylo_fw_header {
uint32_t magic; /* must be MYLO_MAGIC_FIRMWARE */
uint32_t crc; /* CRC of the whole firmware */
uint32_t res0; /* unknown/unused */
uint32_t res1; /* unknown/unused */
uint16_t vid; /* vendor ID */
uint16_t did; /* device ID */
uint16_t svid; /* sub vendor ID */
uint16_t sdid; /* sub device ID */
uint32_t rev; /* device revision */
uint32_t fwhi; /* FIXME: firmware version high? */
uint32_t fwlo; /* FIXME: firmware version low? */
uint32_t flags; /* firmware flags */
};
#define FW_FLAG_BOARD_PARAMS_WP 0x01 /* board parameters are write protected */
#define FW_FLAG_BOOT_SECTOR_WE 0x02 /* enable of write boot sectors (below 64K) */
struct mylo_fw_blockdesc {
uint32_t type; /* block type */
uint32_t addr; /* relative address to flash start */
uint32_t dlen; /* size of block data in bytes */
uint32_t blen; /* total size of block in bytes */
};
#define FW_DESC_TYPE_UNUSED 0
#define FW_DESC_TYPE_USED 1
struct mylo_partition {
uint16_t flags; /* partition flags */
uint16_t type; /* type of the partition */
uint32_t addr; /* relative address of the partition from the
flash start */
uint32_t size; /* size of the partition in bytes */
uint32_t param; /* if this is the active partition, the
MyLoader load code to this address */
};
#define PARTITION_FLAG_ACTIVE 0x8000 /* this is the active partition,
* MyLoader loads firmware from here */
#define PARTITION_FLAG_ISRAM 0x2000 /* FIXME: this is a RAM partition? */
#define PARTIIION_FLAG_RAMLOAD 0x1000 /* FIXME: load this partition into the RAM? */
#define PARTITION_FLAG_PRELOAD 0x0800 /* the partition data preloaded to RAM
* before decompression */
#define PARTITION_FLAG_HAVEHDR 0x0002 /* the partition data have a header */
#define PARTITION_TYPE_FREE 0
#define PARTITION_TYPE_USED 1
#define MYLO_MAX_PARTITIONS 8 /* maximum number of partitions in the
partition table */
struct mylo_partition_table {
uint32_t magic; /* must be MYLO_MAGIC_PARTITIONS */
uint32_t res0; /* unknown/unused */
uint32_t res1; /* unknown/unused */
uint32_t res2; /* unknown/unused */
struct mylo_partition partitions[MYLO_MAX_PARTITIONS];
};
struct mylo_partition_header {
uint32_t len; /* length of the partition data */
uint32_t crc; /* CRC value of the partition data */
};
struct mylo_system_params {
uint32_t magic; /* must be MYLO_MAGIC_SYS_PARAMS */
uint32_t res0;
uint32_t res1;
uint32_t mylo_ver;
uint16_t vid; /* Vendor ID */
uint16_t did; /* Device ID */
uint16_t svid; /* Sub Vendor ID */
uint16_t sdid; /* Sub Device ID */
uint32_t rev; /* device revision */
uint32_t fwhi;
uint32_t fwlo;
uint32_t tftp_addr;
uint32_t prog_start;
uint32_t flash_size; /* Size of boot FLASH in bytes */
uint32_t dram_size; /* Size of onboard RAM in bytes */
};
struct mylo_eth_addr {
uint8_t mac[6];
uint8_t csum[2];
};
#define MYLO_ETHADDR_COUNT 8 /* maximum number of ethernet address
in the board parameters */
struct mylo_board_params {
uint32_t magic; /* must be MYLO_MAGIC_BOARD_PARAMS */
uint32_t res0;
uint32_t res1;
uint32_t res2;
struct mylo_eth_addr addr[MYLO_ETHADDR_COUNT];
};
struct myloader_info {
u32 vid;
u32 did;
u32 svid;
u32 sdid;
uint8_t macs[MYLO_ETHADDR_COUNT][6];
};
extern struct myloader_info myloader_info;
extern int myloader_present(void) __init;
#endif /* _MYLOADER_H_*/

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/*
* Mikrotik's RouterBOOT definitions
*
* Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef _ROUTERBOOT_H
#define _ROUTERBOOT_H
#define RB_MAC_SIZE 6
struct rb_bios_settings {
u32 hs_offs; /* hard settings offset */
u32 hs_size; /* hard settings size */
u32 fw_offs; /* firmware offset */
u32 ss_offs; /* soft settings offset */
u32 ss_size; /* soft settings size */
};
struct rb_hard_settings {
char *name; /* board name */
char *bios_ver; /* BIOS version */
u32 mem_size; /* memory size in bytes */
u32 mac_count; /* number of mac addresses */
u8 *mac_base; /* mac address base */
};
/*
* Magic numbers
*/
#define RB_MAGIC_HARD 0x64726148 /* "Hard" */
#define RB_MAGIC_SOFT 0x74666F53 /* "Soft" */
#define RB_MAGIC_DAWN 0x6E776144 /* "Dawn" */
#define RB_ID_TERMINATOR 0
/*
* ID values for Hardware settings
*/
#define RB_ID_HARD_01 1
#define RB_ID_HARD_02 2
#define RB_ID_FLASH_INFO 3
#define RB_ID_MAC_ADDRESS_PACK 4
#define RB_ID_BOARD_NAME 5
#define RB_ID_BIOS_VERSION 6
#define RB_ID_HARD_07 7
#define RB_ID_SDRAM_TIMINGS 8
#define RB_ID_DEVICE_TIMINGS 9
#define RB_ID_SOFTWARE_ID 10
#define RB_ID_SERIAL_NUMBER 11
#define RB_ID_HARD_12 12
#define RB_ID_MEMORY_SIZE 13
#define RB_ID_MAC_ADDRESS_COUNT 14
/*
* ID values for Software settings
*/
#define RB_ID_UART_SPEED 1
#define RB_ID_BOOT_DELAY 2
#define RB_ID_BOOT_DEVICE 3
#define RB_ID_BOOT_KEY 4
#define RB_ID_CPU_MODE 5
#define RB_ID_FW_VERSION 6
#define RB_ID_SOFT_07 7
#define RB_ID_SOFT_08 8
#define RB_ID_BOOT_PROTOCOL 9
#define RB_ID_SOFT_10 10
#define RB_ID_SOFT_11 11
/*
* UART_SPEED values
*/
#define RB_UART_SPEED_115200 0
#define RB_UART_SPEED_57600 1
#define RB_UART_SPEED_38400 2
#define RB_UART_SPEED_19200 3
#define RB_UART_SPEED_9600 4
#define RB_UART_SPEED_4800 5
#define RB_UART_SPEED_2400 6
#define RB_UART_SPEED_1200 7
/*
* BOOT_DELAY values
*/
#define RB_BOOT_DELAY_0SEC 0
#define RB_BOOT_DELAY_1SEC 1
#define RB_BOOT_DELAY_2SEC 2
/*
* BOOT_DEVICE values
*/
#define RB_BOOT_DEVICE_ETHER 0
#define RB_BOOT_DEVICE_NANDETH 1
#define RB_BOOT_DEVICE_ETHONCE 2
#define RB_BOOT_DEVICE_NANDONLY 3
/*
* BOOT_KEY values
*/
#define RB_BOOT_KEY_ANY 0
#define RB_BOOT_KEY_DEL 1
/*
* CPU_MODE values
*/
#define RB_CPU_MODE_POWERSAVE 0
#define RB_CPU_MODE_REGULAR 1
/*
* BOOT_PROTOCOL values
*/
#define RB_BOOT_PROTOCOL_BOOTP 0
#define RB_BOOT_PROTOCOL_DHCP 1
extern int routerboot_present(void) __init;
extern char *routerboot_get_boardname(void);
extern struct rb_hard_settings rb_hs;
#endif /* _ROUTERBOOT_H */

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/*
* ZyNOS (ZyXEL's Networking OS) definitions
*
* Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef _ZYNOS_H
#define _ZYNOS_H
#define ZYNOS_NAME_LEN 32
#define ZYNOS_FEAT_BYTES 22
#define ZYNOS_MAC_LEN 6
struct zynos_board_info {
unsigned char vendor[ZYNOS_NAME_LEN];
unsigned char product[ZYNOS_NAME_LEN];
u32 bootext_addr;
u32 res0;
u16 board_id;
u8 res1[6];
u8 feat_other[ZYNOS_FEAT_BYTES];
u8 feat_main;
u8 res2;
u8 mac[ZYNOS_MAC_LEN];
u8 country;
u8 dbgflag;
} __attribute__ ((packed));
/*
* Vendor IDs
*/
#define ZYNOS_VENDOR_ID_ZYXEL 0
#define ZYNOS_VENDOR_ID_NETGEAR 1
#define ZYNOS_VENDOR_ID_DLINK 2
#define ZYNOS_VENDOR_ID_OTHER 3
#define ZYNOS_VENDOR_ID_LUCENT 4
/*
* Vendor names
*/
#define ZYNOS_VENDOR_DLINK "D-Link"
#define ZYNOS_VENDOR_LUCENT "LUCENT"
#define ZYNOS_VENDOR_NETGEAR "NetGear"
#define ZYNOS_VENDOR_ZYXEL "ZyXEL"
/*
* Board IDs (big-endian)
*/
#define ZYNOS_BOARD_ES2108 0x00F2 /* Ethernet Switch 2108 */
#define ZYNOS_BOARD_ES2108F 0x01AF /* Ethernet Switch 2108-F */
#define ZYNOS_BOARD_ES2108G 0x00F3 /* Ethernet Switch 2108-G */
#define ZYNOS_BOARD_ES2108LC 0x00FC /* Ethernet Switch 2108-LC */
#define ZYNOS_BOARD_ES2108PWR 0x00F4 /* Ethernet Switch 2108PWR */
#define ZYNOS_BOARD_HS100 0x9FF1 /* HomeSafe 100/100W */
#define ZYNOS_BOARD_P334 0x9FF5 /* Prestige 334 */
#define ZYNOS_BOARD_P334U 0x9FDD /* Prestige 334U */
#define ZYNOS_BOARD_P334W 0x9FF3 /* Prestige 334W */
#define ZYNOS_BOARD_P334WH 0x00E0 /* Prestige 334WH */
#define ZYNOS_BOARD_P334WHD 0x00E1 /* Prestige 334WHD */
#define ZYNOS_BOARD_P334WT 0x9FEF /* Prestige 334WT */
#define ZYNOS_BOARD_P334WT_ALT 0x9F02 /* Prestige 334WT alternative*/
#define ZYNOS_BOARD_P335 0x9FED /* Prestige 335/335WT */
#define ZYNOS_BOARD_P335PLUS 0x0025 /* Prestige 335Plus */
#define ZYNOS_BOARD_P335U 0x9FDC /* Prestige 335U */
/*
* Some magic numbers (big-endian)
*/
#define ZYNOS_MAGIC_DBGAREA1 0x48646267 /* "Hdbg" */
#define ZYNOS_MAGIC_DBGAREA2 0x61726561 /* "area" */
struct bootbase_info {
u16 vendor_id;
u16 board_id;
u8 mac[6];
};
extern struct bootbase_info bootbase_info;
extern int bootbase_present(void) __init;
#endif /* _ZYNOS_H */

25
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_MACH_ADM5120_WAR_H
#define __ASM_MIPS_MACH_ADM5120_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define RM9000_CDEX_SMP_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_ADM5120_WAR_H */

56
target/linux/adm5120/patches-2.6.28/001-adm5120.patch Normal file
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@ -0,0 +1,56 @@
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -19,6 +19,21 @@ choice
prompt "System type"
default SGI_IP22
+config ADM5120
+ bool "Infineon/ADMtek ADM5120 SoC based machines"
+ select CEVT_R4K
+ select CSRC_R4K
+ select SYS_HAS_CPU_MIPS32_R1
+ select SYS_HAS_EARLY_PRINTK
+ select DMA_NONCOHERENT
+ select IRQ_CPU
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select ARCH_REQUIRE_GPIOLIB
+ select SWAP_IO_SPACE if CPU_BIG_ENDIAN
+ select MIPS_MACHINE
+
config MACH_ALCHEMY
bool "Alchemy processor based machines"
@@ -597,6 +612,7 @@ config WR_PPMC
endchoice
+source "arch/mips/adm5120/Kconfig"
source "arch/mips/alchemy/Kconfig"
source "arch/mips/basler/excite/Kconfig"
source "arch/mips/emma/Kconfig"
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -176,6 +176,21 @@ cflags-$(CONFIG_MACH_JAZZ) += -I$(srctre
load-$(CONFIG_MACH_JAZZ) += 0xffffffff80080000
#
+# Infineon/ADMtek ADM5120
+#
+libs-$(CONFIG_ADM5120) += arch/mips/adm5120/prom/
+core-$(CONFIG_ADM5120) += arch/mips/adm5120/common/
+core-$(CONFIG_ADM5120_OEM_CELLVISION) += arch/mips/adm5120/cellvision/
+core-$(CONFIG_ADM5120_OEM_COMPEX) += arch/mips/adm5120/compex/
+core-$(CONFIG_ADM5120_OEM_EDIMAX) += arch/mips/adm5120/edimax/
+core-$(CONFIG_ADM5120_OEM_INFINEON) += arch/mips/adm5120/infineon/
+core-$(CONFIG_ADM5120_OEM_MIKROTIK) += arch/mips/adm5120/mikrotik/
+core-$(CONFIG_ADM5120_OEM_MOTOROLA) += arch/mips/adm5120/motorola/
+core-$(CONFIG_ADM5120_OEM_ZYXEL) += arch/mips/adm5120/zyxel/
+cflags-$(CONFIG_ADM5120) += -I$(srctree)/arch/mips/include/asm/mach-adm5120
+load-$(CONFIG_ADM5120) += 0xffffffff80001000
+
+#
# Common Alchemy Au1x00 stuff
#
core-$(CONFIG_SOC_AU1X00) += arch/mips/alchemy/common/

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target/linux/adm5120/patches-2.6.28/002-adm5120_flash.patch Normal file
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--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -540,5 +540,9 @@ config MTD_PLATRAM
This selection automatically selects the map_ram driver.
+config MTD_ADM5120
+ tristate "Map driver for ADM5120 based boards"
+ depends on ADM5120
+
endmenu
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_MTD_DBOX2) += dbox2-flash.
obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o
obj-$(CONFIG_MTD_PCI) += pci.o
obj-$(CONFIG_MTD_ALCHEMY) += alchemy-flash.o
+obj-$(CONFIG_MTD_ADM5120) += adm5120-flash.o
obj-$(CONFIG_MTD_AUTCPU12) += autcpu12-nvram.o
obj-$(CONFIG_MTD_EDB7312) += edb7312.o
obj-$(CONFIG_MTD_IMPA7) += impa7.o

23
target/linux/adm5120/patches-2.6.28/003-adm5120_switch.patch Normal file
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@ -0,0 +1,23 @@
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -602,6 +602,10 @@ config MIPS_AU1X00_ENET
If you have an Alchemy Semi AU1X00 based system
say Y. Otherwise, say N.
+config ADM5120_ENET
+ tristate "ADM5120 Ethernet switch support"
+ depends on ADM5120
+
config SGI_IOC3_ETH
bool "SGI IOC3 Ethernet"
depends on PCI && SGI_IP27
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -191,6 +191,7 @@ obj-$(CONFIG_SC92031) += sc92031.o
# This is also a 82596 and should probably be merged
obj-$(CONFIG_LP486E) += lp486e.o
+obj-$(CONFIG_ADM5120_ENET) += adm5120sw.o
obj-$(CONFIG_ETH16I) += eth16i.o
obj-$(CONFIG_ZORRO8390) += zorro8390.o
obj-$(CONFIG_HPLANCE) += hplance.o 7990.o

33
target/linux/adm5120/patches-2.6.28/005-adm5120_usb.patch Normal file
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@ -0,0 +1,33 @@
--- a/drivers/usb/Makefile
+++ b/drivers/usb/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_USB_SL811_HCD) += host/
obj-$(CONFIG_USB_U132_HCD) += host/
obj-$(CONFIG_USB_R8A66597_HCD) += host/
obj-$(CONFIG_USB_HWA_HCD) += host/
+obj-$(CONFIG_USB_ADM5120_HCD) += host/
obj-$(CONFIG_USB_C67X00_HCD) += c67x00/
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -4,6 +4,10 @@
comment "USB Host Controller Drivers"
depends on USB
+config USB_ADM5120_HCD
+ tristate "ADM5120 HCD support (EXPERIMENTAL)"
+ depends on USB && ADM5120 && EXPERIMENTAL
+
config USB_C67X00_HCD
tristate "Cypress C67x00 HCD support"
depends on USB
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_USB_WHCI_HCD) += whci/
obj-$(CONFIG_PCI) += pci-quirks.o
+obj-$(CONFIG_USB_ADM5120_HCD) += adm5120-hcd.o
obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o
obj-$(CONFIG_USB_OHCI_HCD) += ohci-hcd.o

19
target/linux/adm5120/patches-2.6.28/007-adm5120_pci.patch Normal file
View file

@ -0,0 +1,19 @@
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -52,3 +52,4 @@ obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc
obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
+obj-$(CONFIG_ADM5120) += pci-adm5120.o
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1723,6 +1723,9 @@
#define PCI_VENDOR_ID_ESDGMBH 0x12fe
#define PCI_DEVICE_ID_ESDGMBH_CPCIASIO4 0x0111
+#define PCI_VENDOR_ID_ADMTEK 0x1317
+#define PCI_DEVICE_ID_ADMTEK_ADM5120 0x5120
+
#define PCI_VENDOR_ID_SIIG 0x131f
#define PCI_SUBVENDOR_ID_SIIG 0x131f
#define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000

22
target/linux/adm5120/patches-2.6.28/009-adm5120_leds_switch_trigger.patch Normal file
View file

@ -0,0 +1,22 @@
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -223,4 +223,12 @@ config LEDS_TRIGGER_NETDEV
This allows LEDs to be controlled by network device activity.
If unsure, say Y.
+config LEDS_TRIGGER_ADM5120_SWITCH
+ tristate "LED ADM5120 Switch Port Status Trigger"
+ depends on LEDS_TRIGGERS && ADM5120
+ help
+ This allows LEDs to be controlled by the port states of
+ the ADM5120 built-in Ethernet Switch
+ If unsure, say N.
+
endif # NEW_LEDS
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -32,3 +32,4 @@ obj-$(CONFIG_LEDS_TRIGGER_HEARTBEAT) +=
obj-$(CONFIG_LEDS_TRIGGER_DEFAULT_ON) += ledtrig-default-on.o
obj-$(CONFIG_LEDS_TRIGGER_MORSE) += ledtrig-morse.o
obj-$(CONFIG_LEDS_TRIGGER_NETDEV) += ledtrig-netdev.o
+obj-$(CONFIG_LEDS_TRIGGER_ADM5120_SWITCH) += ledtrig-adm5120-switch.o

91
target/linux/adm5120/patches-2.6.28/101-cfi_fixup_macronix_bootloc.patch Normal file
View file

@ -0,0 +1,91 @@
--- a/drivers/mtd/chips/cfi_cmdset_0002.c
+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
@@ -44,12 +44,19 @@
#define MANUFACTURER_AMD 0x0001
#define MANUFACTURER_ATMEL 0x001F
#define MANUFACTURER_SST 0x00BF
+#define MANUFACTURER_MACRONIX 0x00C2
#define SST49LF004B 0x0060
#define SST49LF040B 0x0050
#define SST49LF008A 0x005a
#define AT49BV6416 0x00d6
#define MANUFACTURER_SAMSUNG 0x00ec
+/* Macronix */
+#define MX29LV160B 0x2249 /* MX29LV160 Bottom-boot chip */
+#define MX29LV160T 0x22C4 /* MX29LV160 Top-boot chip */
+#define MX29LV320B 0x22A8 /* MX29LV320 Bottom-boot chip */
+#define MX29LV320T 0x22A7 /* MX29LV320 Top-boot chip */
+
static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
@@ -240,6 +247,41 @@ static void fixup_s29gl032n_sectors(stru
}
}
+#ifdef CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC
+/*
+ * Some Macronix chips has no/bad bootblock information in the CFI table
+ */
+static void fixup_macronix_bootloc(struct mtd_info *mtd, void* param)
+{
+ struct map_info *map = mtd->priv;
+ struct cfi_private *cfi = map->fldrv_priv;
+ struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
+ __u8 t;
+
+ switch (cfi->id) {
+ /* TODO: put affected chip ids here */
+ case MX29LV160B:
+ case MX29LV320B:
+ t = 2; /* Bottom boot */
+ break;
+ case MX29LV160T:
+ case MX29LV320T:
+ t = 3; /* Top boot */
+ break;
+ default:
+ return;
+ }
+
+ if (extp->TopBottom == t)
+ /* boot location detected by the CFI layer is correct */
+ return;
+
+ extp->TopBottom = t;
+ printk("%s: Macronix chip detected, id:0x%04X, boot location forced "
+ "to %s\n", map->name, cfi->id, (t == 2) ? "bottom" : "top");
+}
+#endif /* CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC */
+
static struct cfi_fixup cfi_fixup_table[] = {
{ CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
#ifdef AMD_BOOTLOC_BUG
@@ -275,6 +317,9 @@ static struct cfi_fixup fixup_table[] =
*/
{ CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip, NULL },
{ CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock, NULL },
+#ifdef CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC
+ { MANUFACTURER_MACRONIX, CFI_ID_ANY, fixup_macronix_bootloc, NULL, },
+#endif
{ 0, 0, NULL, NULL }
};
--- a/drivers/mtd/chips/Kconfig
+++ b/drivers/mtd/chips/Kconfig
@@ -196,6 +196,14 @@ config MTD_CFI_AMDSTD
provides support for one of those command sets, used on chips
including the AMD Am29LV320.
+config MTD_CFI_FIXUP_MACRONIX_BOOTLOC
+ bool "Fix boot-block location for Macronix flash chips"
+ depends on MTD_CFI_AMDSTD
+ help
+ Some Macronix flash chips have no/wrong boot-block location in the
+ CFI table, and the driver may detect the type incorrectly. Select
+ this if your board has such chip.
+
config MTD_CFI_STAA
tristate "Support for ST (Advanced Architecture) flash chips"
depends on MTD_GEN_PROBE

68
target/linux/adm5120/patches-2.6.28/102-jedec_pmc_39lvxxx_chips.patch Normal file
View file

@ -0,0 +1,68 @@
--- a/drivers/mtd/chips/jedec_probe.c
+++ b/drivers/mtd/chips/jedec_probe.c
@@ -128,6 +128,10 @@
#define UPD29F064115 0x221C
/* PMC */
+#define PM39LV512 0x001B
+#define PM39LV010 0x001C
+#define PM39LV020 0x003D
+#define PM39LV040 0x003E
#define PM49FL002 0x006D
#define PM49FL004 0x006E
#define PM49FL008 0x006A
@@ -1248,6 +1252,54 @@ static const struct amd_flash_info jedec
ERASEINFO(0x02000,2),
ERASEINFO(0x04000,1),
}
+ }, {
+ .mfr_id = MANUFACTURER_PMC,
+ .dev_id = PM39LV512,
+ .name = "PMC Pm39LV512",
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x02AA,
+ .dev_size = SIZE_64KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
+ .regions = {
+ ERASEINFO(0x01000,16),
+ }
+ }, {
+ .mfr_id = MANUFACTURER_PMC,
+ .dev_id = PM39LV010,
+ .name = "PMC Pm39LV010",
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x02AA,
+ .dev_size = SIZE_128KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
+ .regions = {
+ ERASEINFO(0x01000,32),
+ }
+ }, {
+ .mfr_id = MANUFACTURER_PMC,
+ .dev_id = PM39LV020,
+ .name = "PMC Pm39LV020",
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x02AA,
+ .dev_size = SIZE_256KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
+ .regions = {
+ ERASEINFO(0x01000,64),
+ }
+ }, {
+ .mfr_id = MANUFACTURER_PMC,
+ .dev_id = PM39LV040,
+ .name = "PMC Pm39LV040",
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x02AA,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
+ .regions = {
+ ERASEINFO(0x01000,128),
+ }
}, {
.mfr_id = MANUFACTURER_PMC,
.dev_id = PM49FL002,

24
target/linux/adm5120/patches-2.6.28/103-mtd_trxsplit.patch Normal file
View file

@ -0,0 +1,24 @@
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -55,6 +55,11 @@ config MTD_ROOTFS_SPLIT
depends on MTD_PARTITIONS
default y
+config MTD_TRXSPLIT
+ bool "Automatically find and split TRX partitions"
+ depends on MTD_PARTITIONS
+ default n
+
config MTD_REDBOOT_PARTS
tristate "RedBoot partition table parsing"
depends on MTD_PARTITIONS
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -8,6 +8,7 @@ mtd-y := mtdcore.o mtdsuper.o
mtd-$(CONFIG_MTD_PARTITIONS) += mtdpart.o
obj-$(CONFIG_MTD_CONCAT) += mtdconcat.o
+obj-$(CONFIG_MTD_TRXSPLIT) += trxsplit.o
obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o
obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o
obj-$(CONFIG_MTD_AFS_PARTS) += afs.o

28
target/linux/adm5120/patches-2.6.28/120-rb153_cf_driver.patch Normal file
View file

@ -0,0 +1,28 @@
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -72,6 +72,7 @@ obj-$(CONFIG_PATA_BF54X) += pata_bf54x.o
obj-$(CONFIG_PATA_PLATFORM) += pata_platform.o
obj-$(CONFIG_PATA_OF_PLATFORM) += pata_of_platform.o
obj-$(CONFIG_PATA_ICSIDE) += pata_icside.o
+obj-$(CONFIG_PATA_RB153_CF) += pata_rb153_cf.o
# Should be last but two libata driver
obj-$(CONFIG_PATA_ACPI) += pata_acpi.o
# Should be last but one libata driver
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -567,6 +567,15 @@ config PATA_RADISYS
If unsure, say N.
+config PATA_RB153_CF
+ tristate "RouterBOARD 153 Compact Flash support"
+ depends on ADM5120_MACH_RB_153
+ help
+ This option enables support for a Compact Flash connected on
+ the RouterBOARD 153.
+
+ If unsure, say N.
+
config PATA_RB532
tristate "RouterBoard 532 PATA CompactFlash support"
depends on MIKROTIK_RB532

15
target/linux/adm5120/patches-2.6.28/140-cmdline_hack.patch Normal file
View file

@ -0,0 +1,15 @@
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -127,7 +127,12 @@
/*
* Reserved space for exception handlers.
* Necessary for machines which link their kernels at KSEG0.
+ * Use as temporary storage for the kernel command line, so that it
+ * can be updated easily without having to relink the kernel.
*/
+
+EXPORT(_image_cmdline)
+ .ascii "CMDLINE:"
.fill 0x400
#endif

378
target/linux/adm5120/patches-2.6.28/200-amba_pl010_hacks.patch Normal file
View file

@ -0,0 +1,378 @@
--- a/drivers/serial/amba-pl010.c
+++ b/drivers/serial/amba-pl010.c
@@ -50,11 +50,10 @@
#include <asm/io.h>
-#define UART_NR 8
-
#define SERIAL_AMBA_MAJOR 204
#define SERIAL_AMBA_MINOR 16
-#define SERIAL_AMBA_NR UART_NR
+#define SERIAL_AMBA_NR CONFIG_SERIAL_AMBA_PL010_NUMPORTS
+#define SERIAL_AMBA_NAME CONFIG_SERIAL_AMBA_PL010_PORTNAME
#define AMBA_ISR_PASS_LIMIT 256
@@ -80,9 +79,9 @@ static void pl010_stop_tx(struct uart_po
struct uart_amba_port *uap = (struct uart_amba_port *)port;
unsigned int cr;
- cr = readb(uap->port.membase + UART010_CR);
+ cr = __raw_readl(uap->port.membase + UART010_CR);
cr &= ~UART010_CR_TIE;
- writel(cr, uap->port.membase + UART010_CR);
+ __raw_writel(cr, uap->port.membase + UART010_CR);
}
static void pl010_start_tx(struct uart_port *port)
@@ -90,9 +89,9 @@ static void pl010_start_tx(struct uart_p
struct uart_amba_port *uap = (struct uart_amba_port *)port;
unsigned int cr;
- cr = readb(uap->port.membase + UART010_CR);
+ cr = __raw_readl(uap->port.membase + UART010_CR);
cr |= UART010_CR_TIE;
- writel(cr, uap->port.membase + UART010_CR);
+ __raw_writel(cr, uap->port.membase + UART010_CR);
}
static void pl010_stop_rx(struct uart_port *port)
@@ -100,9 +99,9 @@ static void pl010_stop_rx(struct uart_po
struct uart_amba_port *uap = (struct uart_amba_port *)port;
unsigned int cr;
- cr = readb(uap->port.membase + UART010_CR);
+ cr = __raw_readl(uap->port.membase + UART010_CR);
cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
- writel(cr, uap->port.membase + UART010_CR);
+ __raw_writel(cr, uap->port.membase + UART010_CR);
}
static void pl010_enable_ms(struct uart_port *port)
@@ -110,9 +109,9 @@ static void pl010_enable_ms(struct uart_
struct uart_amba_port *uap = (struct uart_amba_port *)port;
unsigned int cr;
- cr = readb(uap->port.membase + UART010_CR);
+ cr = __raw_readl(uap->port.membase + UART010_CR);
cr |= UART010_CR_MSIE;
- writel(cr, uap->port.membase + UART010_CR);
+ __raw_writel(cr, uap->port.membase + UART010_CR);
}
static void pl010_rx_chars(struct uart_amba_port *uap)
@@ -120,9 +119,9 @@ static void pl010_rx_chars(struct uart_a
struct tty_struct *tty = uap->port.info->port.tty;
unsigned int status, ch, flag, rsr, max_count = 256;
- status = readb(uap->port.membase + UART01x_FR);
+ status = __raw_readl(uap->port.membase + UART01x_FR);
while (UART_RX_DATA(status) && max_count--) {
- ch = readb(uap->port.membase + UART01x_DR);
+ ch = __raw_readl(uap->port.membase + UART01x_DR);
flag = TTY_NORMAL;
uap->port.icount.rx++;
@@ -131,9 +130,9 @@ static void pl010_rx_chars(struct uart_a
* Note that the error handling code is
* out of the main execution path
*/
- rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
+ rsr = __raw_readl(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
if (unlikely(rsr & UART01x_RSR_ANY)) {
- writel(0, uap->port.membase + UART01x_ECR);
+ __raw_writel(0, uap->port.membase + UART01x_ECR);
if (rsr & UART01x_RSR_BE) {
rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
@@ -163,7 +162,7 @@ static void pl010_rx_chars(struct uart_a
uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag);
ignore_char:
- status = readb(uap->port.membase + UART01x_FR);
+ status = __raw_readl(uap->port.membase + UART01x_FR);
}
spin_unlock(&uap->port.lock);
tty_flip_buffer_push(tty);
@@ -176,7 +175,7 @@ static void pl010_tx_chars(struct uart_a
int count;
if (uap->port.x_char) {
- writel(uap->port.x_char, uap->port.membase + UART01x_DR);
+ __raw_writel(uap->port.x_char, uap->port.membase + UART01x_DR);
uap->port.icount.tx++;
uap->port.x_char = 0;
return;
@@ -188,7 +187,7 @@ static void pl010_tx_chars(struct uart_a
count = uap->port.fifosize >> 1;
do {
- writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
+ __raw_writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
uap->port.icount.tx++;
if (uart_circ_empty(xmit))
@@ -206,9 +205,9 @@ static void pl010_modem_status(struct ua
{
unsigned int status, delta;
- writel(0, uap->port.membase + UART010_ICR);
+ __raw_writel(0, uap->port.membase + UART010_ICR);
- status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
+ status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
delta = status ^ uap->old_status;
uap->old_status = status;
@@ -236,7 +235,7 @@ static irqreturn_t pl010_int(int irq, vo
spin_lock(&uap->port.lock);
- status = readb(uap->port.membase + UART010_IIR);
+ status = __raw_readl(uap->port.membase + UART010_IIR);
if (status) {
do {
if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
@@ -249,7 +248,7 @@ static irqreturn_t pl010_int(int irq, vo
if (pass_counter-- == 0)
break;
- status = readb(uap->port.membase + UART010_IIR);
+ status = __raw_readl(uap->port.membase + UART010_IIR);
} while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
UART010_IIR_TIS));
handled = 1;
@@ -263,7 +262,7 @@ static irqreturn_t pl010_int(int irq, vo
static unsigned int pl010_tx_empty(struct uart_port *port)
{
struct uart_amba_port *uap = (struct uart_amba_port *)port;
- unsigned int status = readb(uap->port.membase + UART01x_FR);
+ unsigned int status = __raw_readl(uap->port.membase + UART01x_FR);
return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
}
@@ -273,7 +272,7 @@ static unsigned int pl010_get_mctrl(stru
unsigned int result = 0;
unsigned int status;
- status = readb(uap->port.membase + UART01x_FR);
+ status = __raw_readl(uap->port.membase + UART01x_FR);
if (status & UART01x_FR_DCD)
result |= TIOCM_CAR;
if (status & UART01x_FR_DSR)
@@ -299,12 +298,12 @@ static void pl010_break_ctl(struct uart_
unsigned int lcr_h;
spin_lock_irqsave(&uap->port.lock, flags);
- lcr_h = readb(uap->port.membase + UART010_LCRH);
+ lcr_h = __raw_readl(uap->port.membase + UART010_LCRH);
if (break_state == -1)
lcr_h |= UART01x_LCRH_BRK;
else
lcr_h &= ~UART01x_LCRH_BRK;
- writel(lcr_h, uap->port.membase + UART010_LCRH);
+ __raw_writel(lcr_h, uap->port.membase + UART010_LCRH);
spin_unlock_irqrestore(&uap->port.lock, flags);
}
@@ -332,12 +331,12 @@ static int pl010_startup(struct uart_por
/*
* initialise the old status of the modem signals
*/
- uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
+ uap->old_status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
/*
* Finally, enable interrupts
*/
- writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
+ __raw_writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
uap->port.membase + UART010_CR);
return 0;
@@ -360,10 +359,10 @@ static void pl010_shutdown(struct uart_p
/*
* disable all interrupts, disable the port
*/
- writel(0, uap->port.membase + UART010_CR);
+ __raw_writel(0, uap->port.membase + UART010_CR);
/* disable break condition and fifos */
- writel(readb(uap->port.membase + UART010_LCRH) &
+ __raw_writel(__raw_readl(uap->port.membase + UART010_LCRH) &
~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
uap->port.membase + UART010_LCRH);
@@ -385,7 +384,7 @@ pl010_set_termios(struct uart_port *port
/*
* Ask the core to calculate the divisor for us.
*/
- baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
+ baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
quot = uart_get_divisor(port, baud);
switch (termios->c_cflag & CSIZE) {
@@ -448,25 +447,25 @@ pl010_set_termios(struct uart_port *port
uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX;
/* first, disable everything */
- old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
+ old_cr = __raw_readl(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
if (UART_ENABLE_MS(port, termios->c_cflag))
old_cr |= UART010_CR_MSIE;
- writel(0, uap->port.membase + UART010_CR);
+ __raw_writel(0, uap->port.membase + UART010_CR);
/* Set baud rate */
quot -= 1;
- writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
- writel(quot & 0xff, uap->port.membase + UART010_LCRL);
+ __raw_writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
+ __raw_writel(quot & 0xff, uap->port.membase + UART010_LCRL);
/*
* ----------v----------v----------v----------v-----
* NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
* ----------^----------^----------^----------^-----
*/
- writel(lcr_h, uap->port.membase + UART010_LCRH);
- writel(old_cr, uap->port.membase + UART010_CR);
+ __raw_writel(lcr_h, uap->port.membase + UART010_LCRH);
+ __raw_writel(old_cr, uap->port.membase + UART010_CR);
spin_unlock_irqrestore(&uap->port.lock, flags);
}
@@ -538,7 +537,7 @@ static struct uart_ops amba_pl010_pops =
.verify_port = pl010_verify_port,
};
-static struct uart_amba_port *amba_ports[UART_NR];
+static struct uart_amba_port *amba_ports[SERIAL_AMBA_NR];
#ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
@@ -548,10 +547,10 @@ static void pl010_console_putchar(struct
unsigned int status;
do {
- status = readb(uap->port.membase + UART01x_FR);
+ status = __raw_readl(uap->port.membase + UART01x_FR);
barrier();
} while (!UART_TX_READY(status));
- writel(ch, uap->port.membase + UART01x_DR);
+ __raw_writel(ch, uap->port.membase + UART01x_DR);
}
static void
@@ -565,8 +564,8 @@ pl010_console_write(struct console *co,
/*
* First save the CR then disable the interrupts
*/
- old_cr = readb(uap->port.membase + UART010_CR);
- writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
+ old_cr = __raw_readl(uap->port.membase + UART010_CR);
+ __raw_writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
uart_console_write(&uap->port, s, count, pl010_console_putchar);
@@ -575,10 +574,10 @@ pl010_console_write(struct console *co,
* and restore the TCR
*/
do {
- status = readb(uap->port.membase + UART01x_FR);
+ status = __raw_readl(uap->port.membase + UART01x_FR);
barrier();
} while (status & UART01x_FR_BUSY);
- writel(old_cr, uap->port.membase + UART010_CR);
+ __raw_writel(old_cr, uap->port.membase + UART010_CR);
clk_disable(uap->clk);
}
@@ -587,9 +586,9 @@ static void __init
pl010_console_get_options(struct uart_amba_port *uap, int *baud,
int *parity, int *bits)
{
- if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
+ if (__raw_readl(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
unsigned int lcr_h, quot;
- lcr_h = readb(uap->port.membase + UART010_LCRH);
+ lcr_h = __raw_readl(uap->port.membase + UART010_LCRH);
*parity = 'n';
if (lcr_h & UART01x_LCRH_PEN) {
@@ -604,8 +603,8 @@ pl010_console_get_options(struct uart_am
else
*bits = 8;
- quot = readb(uap->port.membase + UART010_LCRL) |
- readb(uap->port.membase + UART010_LCRM) << 8;
+ quot = __raw_readl(uap->port.membase + UART010_LCRL) |
+ __raw_readl(uap->port.membase + UART010_LCRM) << 8;
*baud = uap->port.uartclk / (16 * (quot + 1));
}
}
@@ -623,7 +622,7 @@ static int __init pl010_console_setup(st
* if so, search for the first available port that does have
* console support.
*/
- if (co->index >= UART_NR)
+ if (co->index >= SERIAL_AMBA_NR)
co->index = 0;
uap = amba_ports[co->index];
if (!uap)
@@ -641,7 +640,7 @@ static int __init pl010_console_setup(st
static struct uart_driver amba_reg;
static struct console amba_console = {
- .name = "ttyAM",
+ .name = SERIAL_AMBA_NAME,
.write = pl010_console_write,
.device = uart_console_device,
.setup = pl010_console_setup,
@@ -657,11 +656,11 @@ static struct console amba_console = {
static struct uart_driver amba_reg = {
.owner = THIS_MODULE,
- .driver_name = "ttyAM",
- .dev_name = "ttyAM",
+ .driver_name = SERIAL_AMBA_NAME,
+ .dev_name = SERIAL_AMBA_NAME,
.major = SERIAL_AMBA_MAJOR,
.minor = SERIAL_AMBA_MINOR,
- .nr = UART_NR,
+ .nr = SERIAL_AMBA_NR,
.cons = AMBA_CONSOLE,
};
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -284,10 +284,25 @@ config SERIAL_AMBA_PL010
help
This selects the ARM(R) AMBA(R) PrimeCell PL010 UART. If you have
an Integrator/AP or Integrator/PP2 platform, or if you have a
- Cirrus Logic EP93xx CPU, say Y or M here.
+ Cirrus Logic EP93xx CPU or an Infineon ADM5120 SOC, say Y or M here.
If unsure, say N.
+config SERIAL_AMBA_PL010_NUMPORTS
+ int "Maximum number of AMBA PL010 serial ports"
+ depends on SERIAL_AMBA_PL010
+ default "8"
+ ---help---
+ Set this to the number of serial ports you want the AMBA PL010 driver
+ to support.
+
+config SERIAL_AMBA_PL010_PORTNAME
+ string "Name of the AMBA PL010 serial ports"
+ depends on SERIAL_AMBA_PL010
+ default "ttyAM"
+ ---help---
+ ::: To be written :::
+
config SERIAL_AMBA_PL010_CONSOLE
bool "Support for console on AMBA serial port"
depends on SERIAL_AMBA_PL010=y

13
target/linux/adm5120/patches-2.6.28/201-amba_bus_hacks.patch Normal file
View file

@ -0,0 +1,13 @@
--- a/drivers/amba/bus.c
+++ b/drivers/amba/bus.c
@@ -17,6 +17,10 @@
#include <asm/io.h>
#include <asm/sizes.h>
+#ifndef NO_IRQ
+#define NO_IRQ (-1)
+#endif
+
#define to_amba_device(d) container_of(d, struct amba_device, dev)
#define to_amba_driver(d) container_of(d, struct amba_driver, drv)

43
target/linux/adm5120/patches-2.6.28/202-pci_disable_common_quirks.patch Normal file
View file

@ -0,0 +1,43 @@
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -42,6 +42,12 @@ config PCI_DEBUG
When in doubt, say N.
+config PCI_DISABLE_COMMON_QUIRKS
+ bool "PCI disable common quirks"
+ depends on PCI
+ help
+ If you don't know what to do here, say N.
+
config HT_IRQ
bool "Interrupts on hypertransport devices"
default y
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -33,6 +33,7 @@ int pcie_mch_quirk;
EXPORT_SYMBOL(pcie_mch_quirk);
#ifdef CONFIG_PCI_QUIRKS
+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS
/* The Mellanox Tavor device gives false positive parity errors
* Mark this device with a broken_parity_status, to allow
* PCI scanning code to "skip" this now blacklisted device.
@@ -1555,7 +1556,9 @@ static void __devinit fixup_rev1_53c810(
}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
+#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */
+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS
/* Enable 1k I/O space granularity on the Intel P64H2 */
static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
{
@@ -1945,6 +1948,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AT
quirk_msi_intx_disable_bug);
#endif /* CONFIG_PCI_MSI */
+#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */
static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
{

27
target/linux/adm5120/patches-2.6.28/203-gpio_leds_brightness.patch Normal file
View file

@ -0,0 +1,27 @@
--- a/drivers/leds/leds-gpio.c
+++ b/drivers/leds/leds-gpio.c
@@ -43,13 +43,17 @@ static void gpio_led_set(struct led_clas
container_of(led_cdev, struct gpio_led_data, cdev);
int level;
- if (value == LED_OFF)
- level = 0;
- else
- level = 1;
-
- if (led_dat->active_low)
- level = !level;
+ switch (value) {
+ case LED_OFF:
+ level = led_dat->active_low ? 1 : 0;
+ break;
+ case LED_FULL:
+ level = led_dat->active_low ? 0 : 1;
+ break;
+ default:
+ level = value;
+ break;
+ }
/* Setting GPIOs with I2C/etc requires a task context, and we don't
* seem to have a reliable way to know if we're already in one; so

31
target/linux/adm5120/patches-2.6.28/310-adm5120_wdt.patch Normal file
View file

@ -0,0 +1,31 @@
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -696,6 +696,18 @@ config RC32434_WDT
To compile this driver as a module, choose M here: the
module will be called rc32434_wdt.
+config ADM5120_WDT
+ tristate "Infineon ADM5120 SoC hardware watchdog"
+ depends on WATCHDOG && ADM5120
+ help
+ This is a driver for hardware watchdog integrated in Infineon
+ ADM5120 SoC. This watchdog simply watches your kernel to make sure
+ it doesn't freeze, and if it does, it reboots your computer after a
+ certain amount of time.
+
+ To compile this driver as a module, choose M here: the module will be
+ called adm5120_wdt.
+
config INDYDOG
tristate "Indy/I2 Hardware Watchdog"
depends on SGI_HAS_INDYDOG
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -106,6 +106,7 @@ obj-$(CONFIG_WDT_RM9K_GPI) += rm9k_wdt.o
obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
+obj-$(CONFIG_ADM5120_WDT) += adm5120_wdt.o
# PARISC Architecture

69
target/linux/adm5120/patches-2.6.28/800-usb_automatically_enable_rhsc_interrupt.patch Normal file
View file

@ -0,0 +1,69 @@
--- a/drivers/usb/host/adm5120-drv.c
+++ b/drivers/usb/host/adm5120-drv.c
@@ -174,7 +174,6 @@ static const struct hc_driver adm5120_hc
*/
.hub_status_data = admhc_hub_status_data,
.hub_control = admhc_hub_control,
- .hub_irq_enable = admhc_hub_irq_enable,
#ifdef CONFIG_PM
.bus_suspend = admhc_bus_suspend,
.bus_resume = admhc_bus_resume,
--- a/drivers/usb/host/adm5120-hub.c
+++ b/drivers/usb/host/adm5120-hub.c
@@ -63,20 +63,6 @@
/*-------------------------------------------------------------------------*/
-/* hcd->hub_irq_enable() */
-static void admhc_hub_irq_enable(struct usb_hcd *hcd)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
-
- spin_lock_irq(&ahcd->lock);
- if (!ahcd->autostop)
- del_timer(&hcd->rh_timer); /* Prevent next poll */
- admhc_intr_enable(ahcd, ADMHC_INTR_INSM);
- spin_unlock_irq(&ahcd->lock);
-}
-
-/*-------------------------------------------------------------------------*/
-
/* build "status change" packet (one or two bytes) from HC registers */
static int
--- a/drivers/usb/host/adm5120-pm.c
+++ b/drivers/usb/host/adm5120-pm.c
@@ -432,13 +432,17 @@ static inline int admhc_rh_resume(struct
static int admhc_root_hub_state_changes(struct admhcd *ahcd, int changed,
int any_connected)
{
- int poll_rh = 1;
-
- /* keep on polling until RHSC is enabled */
+ /* If INSM is enabled, don't poll */
if (admhc_readl(ahcd, &ahcd->regs->int_enable) & ADMHC_INTR_INSM)
- poll_rh = 0;
+ return 0;
+
+ /* If no status changes are pending, enable status-change interrupts */
+ if (!changed) {
+ admhc_intr_enable(ahcd, ADMHC_INTR_INSM);
+ return 0;
+ }
- return poll_rh;
+ return 1;
}
#endif /* CONFIG_PM */
--- a/drivers/usb/host/adm5120-hcd.c
+++ b/drivers/usb/host/adm5120-hcd.c
@@ -46,7 +46,7 @@
#include "../core/hcd.h"
#include "../core/hub.h"
-#define DRIVER_VERSION "0.25.0"
+#define DRIVER_VERSION "0.27.0"
#define DRIVER_AUTHOR "Gabor Juhos <juhosg@openwrt.org>"
#define DRIVER_DESC "ADMtek USB 1.1 Host Controller Driver"

11
target/linux/adm5120/patches-2.6.28/801-mtd_trxsplit_2.6.28_fix.patch Normal file
View file

@ -0,0 +1,11 @@
--- a/drivers/mtd/trxsplit.c
+++ b/drivers/mtd/trxsplit.c
@@ -18,7 +18,7 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
-#include <linux/byteorder/generic.h>
+//#include <linux/byteorder/generic.h>
#define PFX "trxsplit: "

315
target/linux/adm5120/router_be/config-2.6.28 Normal file
View file

@ -0,0 +1,315 @@
CONFIG_32BIT=y
# CONFIG_64BIT is not set
CONFIG_ADM5120=y
CONFIG_ADM5120_ENET=y
CONFIG_ADM5120_MACH_P_334WT=y
CONFIG_ADM5120_MACH_P_335=y
# CONFIG_ADM5120_OEM_CELLVISION is not set
# CONFIG_ADM5120_OEM_COMPEX is not set
# CONFIG_ADM5120_OEM_EDIMAX is not set
# CONFIG_ADM5120_OEM_INFINEON is not set
# CONFIG_ADM5120_OEM_MIKROTIK is not set
# CONFIG_ADM5120_OEM_MOTOROLA is not set
CONFIG_ADM5120_OEM_ZYXEL=y
CONFIG_ADM5120_SOC_BGA=y
CONFIG_ADM5120_WDT=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_ARCH_REQUIRE_GPIOLIB=y
# CONFIG_ARCH_SUPPORTS_MSI is not set
CONFIG_ARCH_SUPPORTS_OPROFILE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM_AMBA=y
CONFIG_BASE_SMALL=0
CONFIG_BAYCOM_SER_FDX=m
CONFIG_BAYCOM_SER_HDX=m
# CONFIG_BCM47XX is not set
CONFIG_BINFMT_MISC=m
CONFIG_BITREVERSE=y
CONFIG_CEVT_R4K=y
CONFIG_CIFS_DEBUG2=y
CONFIG_CIFS_EXPERIMENTAL=y
CONFIG_CIFS_STATS2=y
CONFIG_CIFS_WEAK_PW_HASH=y
CONFIG_CIFS_XATTR=y
CONFIG_CLASSIC_RCU=y
CONFIG_CMDLINE="console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit"
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_SYNC=y
# CONFIG_CPU_LITTLE_ENDIAN is not set
# CONFIG_CPU_LOONGSON2 is not set
CONFIG_CPU_MIPS32=y
CONFIG_CPU_MIPS32_R1=y
# CONFIG_CPU_MIPS32_R2 is not set
# CONFIG_CPU_MIPS64_R1 is not set
# CONFIG_CPU_MIPS64_R2 is not set
CONFIG_CPU_MIPSR1=y
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R5500 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_RM9000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_VR41XX is not set
CONFIG_CRYPTO_AEAD2=m
CONFIG_CRYPTO_ALGAPI2=m
CONFIG_CRYPTO_BLKCIPHER2=m
CONFIG_CRYPTO_HASH2=m
CONFIG_CRYPTO_MANAGER2=m
CONFIG_CRYPTO_RNG2=m
CONFIG_CSRC_R4K=y
CONFIG_DEVPORT=y
# CONFIG_DM9000 is not set
CONFIG_DMA_NEED_PCI_MAP_STATE=y
CONFIG_DMA_NONCOHERENT=y
CONFIG_EARLY_PRINTK=y
CONFIG_ELF_CORE=y
# CONFIG_EXT3_FS_POSIX_ACL is not set
# CONFIG_EXT3_FS_SECURITY is not set
CONFIG_EXT3_FS_XATTR=y
CONFIG_FIRMWARE_IN_KERNEL=y
# CONFIG_FREEZER is not set
CONFIG_FS_MBCACHE=m
CONFIG_FS_POSIX_ACL=y
CONFIG_GENERIC_ACL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_GPIO=y
# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
# CONFIG_HAVE_AOUT is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_HAVE_IDE=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HID=m
CONFIG_HID_A4TECH=m
CONFIG_HID_APPLE=m
CONFIG_HID_BELKIN=m
CONFIG_HID_BRIGHT=m
CONFIG_HID_CHERRY=m
CONFIG_HID_CHICONY=m
CONFIG_HID_COMPAT=y
CONFIG_HID_CYPRESS=m
CONFIG_HID_DELL=m
CONFIG_HID_EZKEY=m
CONFIG_HID_GYRATION=m
CONFIG_HID_LOGITECH=m
CONFIG_HID_MICROSOFT=m
CONFIG_HID_MONTEREY=m
CONFIG_HID_PANTHERLORD=m
CONFIG_HID_PETALYNX=m
# CONFIG_HID_PID is not set
CONFIG_HID_SAMSUNG=m
CONFIG_HID_SONY=m
CONFIG_HID_SUNPLUS=m
CONFIG_HID_SUPPORT=y
CONFIG_HW_HAS_PCI=y
CONFIG_HW_RANDOM=y
CONFIG_HZ=250
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
# CONFIG_I2C is not set
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
# CONFIG_IDE is not set
CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
CONFIG_INITRAMFS_SOURCE=""
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_INPUT=m
# CONFIG_INPUT_EVDEV is not set
CONFIG_IPV6_MIP6=m
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_TUNNEL=m
CONFIG_IP_NF_TARGET_CLUSTERIP=m
CONFIG_IRQ_CPU=y
# CONFIG_ISDN is not set
# CONFIG_JOLIET is not set
CONFIG_KMOD=y
# CONFIG_LEDS_ALIX is not set
CONFIG_LEDS_GPIO=m
CONFIG_LEDS_TRIGGER_ADM5120_SWITCH=m
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_LEMOTE_FULONG is not set
# CONFIG_LOGIRUMBLEPAD2_FF is not set
# CONFIG_LOGITECH_FF is not set
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_EMMA is not set
# CONFIG_MACH_JAZZ is not set
# CONFIG_MACH_TX39XX is not set
# CONFIG_MACH_TX49XX is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_TMIO is not set
CONFIG_MII=m
# CONFIG_MIKROTIK_RB532 is not set
# CONFIG_MINIX_FS is not set
CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
CONFIG_MIPS_L1_CACHE_SHIFT=5
CONFIG_MIPS_MACHINE=y
# CONFIG_MIPS_MALTA is not set
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_SIM is not set
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MTD=y
# CONFIG_MTD_ABSENT is not set
CONFIG_MTD_ADM5120=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_BLOCK2MTD=y
CONFIG_MTD_CFI=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
CONFIG_MTD_MAP_BANK_WIDTH_2=y
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_ONENAND is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_PCI is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_PHYSMAP is not set
# CONFIG_MTD_PLATRAM is not set
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_SLRAM is not set
CONFIG_MTD_TRXSPLIT=y
# CONFIG_NET_PCI is not set
# CONFIG_NET_PKTGEN is not set
CONFIG_NF_CT_ACCT=y
CONFIG_NF_DEFRAG_IPV4=m
# CONFIG_NO_IOPORT is not set
# CONFIG_NXP_STB220 is not set
# CONFIG_NXP_STB225 is not set
CONFIG_PAGEFLAGS_EXTENDED=y
# CONFIG_PAGE_SIZE_16KB is not set
CONFIG_PAGE_SIZE_4KB=y
# CONFIG_PAGE_SIZE_64KB is not set
# CONFIG_PAGE_SIZE_8KB is not set
# CONFIG_PANTHERLORD_FF is not set
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_PCI=y
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
# CONFIG_PCSPKR_PLATFORM is not set
# CONFIG_PHYS_ADDR_T_64BIT is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PROBE_INITRD_HEADER is not set
# CONFIG_PROM_EMU is not set
CONFIG_RFKILL_LEDS=y
CONFIG_RTC_LIB=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
CONFIG_SCSI_WAIT_SCAN=m
# CONFIG_SERIAL_8250 is not set
CONFIG_SERIAL_AMBA_PL010=y
CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
CONFIG_SERIAL_AMBA_PL010_NUMPORTS=2
CONFIG_SERIAL_AMBA_PL010_PORTNAME="ttyS"
# CONFIG_SERIAL_AMBA_PL011 is not set
CONFIG_SERIO=y
# CONFIG_SERIO_AMBAKMI is not set
# CONFIG_SERIO_I8042 is not set
# CONFIG_SERIO_LIBPS2 is not set
# CONFIG_SERIO_PCIPS2 is not set
# CONFIG_SERIO_RAW is not set
CONFIG_SERIO_SERPORT=y
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP28 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SLAB is not set
CONFIG_SLUB=y
CONFIG_SND_MIPS=y
CONFIG_SOFT_WATCHDOG=m
CONFIG_SOUND_OSS_CORE=y
CONFIG_SSB_POSSIBLE=y
# CONFIG_SUNRPC_REGISTER_V4 is not set
CONFIG_SWAP_IO_SPACE=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_SYS_HAS_EARLY_PRINTK=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
# CONFIG_THRUSTMASTER_FF is not set
CONFIG_TICK_ONESHOT=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TRAD_SIGNALS=y
CONFIG_USB=m
CONFIG_USB_ADM5120_HCD=m
CONFIG_USB_DEBUG=y
CONFIG_USB_EHCI_HCD=m
# CONFIG_USB_NET_SMSC95XX is not set
# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
CONFIG_USB_OHCI_HCD=m
CONFIG_USB_SUPPORT=y
# CONFIG_USB_UHCI_HCD is not set
# CONFIG_VGASTATE is not set
CONFIG_VIDEO_MEDIA=m
CONFIG_VIDEO_V4L2=m
CONFIG_VIDEO_V4L2_COMMON=m
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_W1_SLAVE_BQ27000 is not set
# CONFIG_ZEROPLUS_FF is not set
CONFIG_ZONE_DMA_FLAG=0

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target/linux/adm5120/router_le/config-2.6.28 Normal file
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CONFIG_32BIT=y
# CONFIG_64BIT is not set
# CONFIG_8139TOO is not set
CONFIG_ADM5120=y
CONFIG_ADM5120_ENET=y
CONFIG_ADM5120_MACH_BR_6104K=y
CONFIG_ADM5120_MACH_BR_6104KP=y
CONFIG_ADM5120_MACH_BR_61X4WG=y
CONFIG_ADM5120_MACH_CAS_771=y
CONFIG_ADM5120_MACH_EASY5120P_ATA=y
CONFIG_ADM5120_MACH_EASY5120_RT=y
CONFIG_ADM5120_MACH_EASY5120_WVOIP=y
CONFIG_ADM5120_MACH_EASY83000=y
CONFIG_ADM5120_MACH_NFS_101=y
CONFIG_ADM5120_MACH_NP27G=y
CONFIG_ADM5120_MACH_NP28G=y
CONFIG_ADM5120_MACH_PMUGW=y
CONFIG_ADM5120_MACH_RB_11X=y
CONFIG_ADM5120_MACH_RB_133=y
CONFIG_ADM5120_MACH_RB_133C=y
CONFIG_ADM5120_MACH_RB_150=y
CONFIG_ADM5120_MACH_RB_153=y
CONFIG_ADM5120_MACH_RB_192=y
CONFIG_ADM5120_MACH_WP54=y
CONFIG_ADM5120_OEM_CELLVISION=y
CONFIG_ADM5120_OEM_COMPEX=y
CONFIG_ADM5120_OEM_EDIMAX=y
CONFIG_ADM5120_OEM_INFINEON=y
CONFIG_ADM5120_OEM_MIKROTIK=y
CONFIG_ADM5120_OEM_MOTOROLA=y
# CONFIG_ADM5120_OEM_ZYXEL is not set
CONFIG_ADM5120_SOC_BGA=y
CONFIG_ADM5120_WDT=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_ARCH_REQUIRE_GPIOLIB=y
# CONFIG_ARCH_SUPPORTS_MSI is not set
CONFIG_ARCH_SUPPORTS_OPROFILE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM_AMBA=y
CONFIG_ATA=m
# CONFIG_ATA_NONSTANDARD is not set
# CONFIG_ATA_PIIX is not set
CONFIG_ATA_SFF=y
# CONFIG_ATM is not set
CONFIG_BASE_SMALL=0
# CONFIG_BCM47XX is not set
CONFIG_BITREVERSE=y
CONFIG_BRIDGE=m
# CONFIG_BT is not set
CONFIG_CEVT_R4K=y
CONFIG_CIFS_DEBUG2=y
CONFIG_CIFS_EXPERIMENTAL=y
CONFIG_CIFS_STATS2=y
CONFIG_CIFS_WEAK_PW_HASH=y
CONFIG_CIFS_XATTR=y
CONFIG_CLASSIC_RCU=y
CONFIG_CMDLINE="console=ttyS0,115200 rootfstype=squashfs,yaffs2,jffs2 init=/etc/preinit"
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_CPU_LITTLE_ENDIAN=y
# CONFIG_CPU_LOONGSON2 is not set
CONFIG_CPU_MIPS32=y
CONFIG_CPU_MIPS32_R1=y
# CONFIG_CPU_MIPS32_R2 is not set
# CONFIG_CPU_MIPS64_R1 is not set
# CONFIG_CPU_MIPS64_R2 is not set
CONFIG_CPU_MIPSR1=y
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R5500 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_RM9000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_VR41XX is not set
CONFIG_CRYPTO_AEAD2=m
CONFIG_CRYPTO_ALGAPI2=m
CONFIG_CRYPTO_BLKCIPHER2=m
CONFIG_CRYPTO_HASH2=m
CONFIG_CRYPTO_MANAGER2=m
CONFIG_CRYPTO_RNG2=m
CONFIG_CSRC_R4K=y
CONFIG_DEVPORT=y
# CONFIG_DM9000 is not set
CONFIG_DMA_NEED_PCI_MAP_STATE=y
CONFIG_DMA_NONCOHERENT=y
CONFIG_EARLY_PRINTK=y
CONFIG_ELF_CORE=y
# CONFIG_EXT3_FS_POSIX_ACL is not set
# CONFIG_EXT3_FS_SECURITY is not set
CONFIG_EXT3_FS_XATTR=y
CONFIG_FIRMWARE_IN_KERNEL=y
# CONFIG_FREEZER is not set
CONFIG_FS_MBCACHE=m
CONFIG_FS_POSIX_ACL=y
CONFIG_GENERIC_ACL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_GPIO=y
# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HAMRADIO is not set
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
# CONFIG_HAVE_AOUT is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_HAVE_IDE=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HID=m
CONFIG_HID_A4TECH=m
CONFIG_HID_APPLE=m
CONFIG_HID_BELKIN=m
CONFIG_HID_BRIGHT=m
CONFIG_HID_CHERRY=m
CONFIG_HID_CHICONY=m
CONFIG_HID_COMPAT=y
CONFIG_HID_CYPRESS=m
CONFIG_HID_DELL=m
CONFIG_HID_EZKEY=m
CONFIG_HID_GYRATION=m
CONFIG_HID_LOGITECH=m
CONFIG_HID_MICROSOFT=m
CONFIG_HID_MONTEREY=m
CONFIG_HID_PANTHERLORD=m
CONFIG_HID_PETALYNX=m
# CONFIG_HID_PID is not set
CONFIG_HID_SAMSUNG=m
CONFIG_HID_SONY=m
CONFIG_HID_SUNPLUS=m
CONFIG_HID_SUPPORT=y
CONFIG_HOSTAP=m
CONFIG_HOSTAP_FIRMWARE=y
CONFIG_HOSTAP_PCI=m
CONFIG_HW_HAS_PCI=y
CONFIG_HW_RANDOM=y
CONFIG_HZ=250
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
# CONFIG_I2C is not set
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
# CONFIG_IDE is not set
CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
CONFIG_INITRAMFS_SOURCE=""
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_INPUT=m
# CONFIG_INPUT_EVDEV is not set
CONFIG_IPV6_MIP6=m
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_TUNNEL=m
CONFIG_IP_NF_TARGET_CLUSTERIP=m
CONFIG_IRQ_CPU=y
# CONFIG_ISDN is not set
# CONFIG_JOLIET is not set
CONFIG_KEXEC=y
CONFIG_KMOD=y
# CONFIG_LEDS_ALIX is not set
CONFIG_LEDS_GPIO=m
CONFIG_LEDS_TRIGGER_ADM5120_SWITCH=m
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_LEMOTE_FULONG is not set
CONFIG_LLC=m
# CONFIG_LOGIRUMBLEPAD2_FF is not set
# CONFIG_LOGITECH_FF is not set
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_EMMA is not set
# CONFIG_MACH_JAZZ is not set
# CONFIG_MACH_TX39XX is not set
# CONFIG_MACH_TX49XX is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_TMIO is not set
CONFIG_MII=m
# CONFIG_MIKROTIK_RB532 is not set
# CONFIG_MINIX_FS is not set
CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
CONFIG_MIPS_L1_CACHE_SHIFT=5
CONFIG_MIPS_MACHINE=y
# CONFIG_MIPS_MALTA is not set
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_SIM is not set
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MTD=y
# CONFIG_MTD_ABSENT is not set
CONFIG_MTD_ADM5120=y
# CONFIG_MTD_ALAUDA is not set
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_MTD_BLOCK2MTD is not set
CONFIG_MTD_CFI=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_GEN_PROBE=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_MAP_BANK_WIDTH_1=y
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
CONFIG_MTD_MAP_BANK_WIDTH_2=y
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MTDRAM is not set
CONFIG_MTD_MYLOADER_PARTS=y
CONFIG_MTD_NAND=y
# CONFIG_MTD_NAND_CAFE is not set
# CONFIG_MTD_NAND_DISKONCHIP is not set
# CONFIG_MTD_NAND_ECC_SMC is not set
CONFIG_MTD_NAND_IDS=y
# CONFIG_MTD_NAND_MUSEUM_IDS is not set
# CONFIG_MTD_NAND_NANDSIM is not set
CONFIG_MTD_NAND_PLATFORM=y
# CONFIG_MTD_NAND_VERIFY_WRITE is not set
# CONFIG_MTD_ONENAND is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_PCI is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_PHYSMAP is not set
# CONFIG_MTD_PLATRAM is not set
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_SLRAM is not set
CONFIG_MTD_TRXSPLIT=y
# CONFIG_NATSEMI is not set
# CONFIG_NETFILTER_XT_MATCH_LAYER7 is not set
# CONFIG_NETFILTER_XT_TARGET_TARPIT is not set
# CONFIG_NET_PKTGEN is not set
CONFIG_NF_CT_ACCT=y
CONFIG_NF_DEFRAG_IPV4=m
CONFIG_NO_HZ=y
# CONFIG_NO_IOPORT is not set
# CONFIG_NXP_STB220 is not set
# CONFIG_NXP_STB225 is not set
CONFIG_PAGEFLAGS_EXTENDED=y
# CONFIG_PAGE_SIZE_16KB is not set
CONFIG_PAGE_SIZE_4KB=y
# CONFIG_PAGE_SIZE_64KB is not set
# CONFIG_PAGE_SIZE_8KB is not set
# CONFIG_PANTHERLORD_FF is not set
# CONFIG_PARTITION_ADVANCED is not set
# CONFIG_PATA_PLATFORM is not set
CONFIG_PATA_RB153_CF=m
# CONFIG_PATA_SCH is not set
CONFIG_PCI=y
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
# CONFIG_PCSPKR_PLATFORM is not set
# CONFIG_PHYS_ADDR_T_64BIT is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PROBE_INITRD_HEADER is not set
# CONFIG_PROM_EMU is not set
# CONFIG_R6040 is not set
CONFIG_RFKILL_LEDS=y
CONFIG_RTC_LIB=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
CONFIG_SCSI_WAIT_SCAN=m
# CONFIG_SERIAL_8250 is not set
CONFIG_SERIAL_AMBA_PL010=y
CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
CONFIG_SERIAL_AMBA_PL010_NUMPORTS=2
CONFIG_SERIAL_AMBA_PL010_PORTNAME="ttyS"
# CONFIG_SERIAL_AMBA_PL011 is not set
CONFIG_SERIO=y
# CONFIG_SERIO_AMBAKMI is not set
# CONFIG_SERIO_I8042 is not set
# CONFIG_SERIO_LIBPS2 is not set
# CONFIG_SERIO_PCIPS2 is not set
# CONFIG_SERIO_RAW is not set
CONFIG_SERIO_SERPORT=y
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP28 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SLAB is not set
CONFIG_SLUB=y
CONFIG_SND_MIPS=y
CONFIG_SOFT_WATCHDOG=m
CONFIG_SOUND_OSS_CORE=y
CONFIG_SSB_POSSIBLE=y
CONFIG_STP=m
# CONFIG_SUNRPC_REGISTER_V4 is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_SYS_HAS_EARLY_PRINTK=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
# CONFIG_TC35815 is not set
# CONFIG_THRUSTMASTER_FF is not set
CONFIG_TICK_ONESHOT=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TRAD_SIGNALS=y
CONFIG_USB=m
CONFIG_USB_ADM5120_HCD=m
CONFIG_USB_EHCI_HCD=m
# CONFIG_USB_NET_SMSC95XX is not set
# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
CONFIG_USB_OHCI_HCD=m
CONFIG_USB_SUPPORT=y
# CONFIG_USB_UHCI_HCD is not set
# CONFIG_VGASTATE is not set
# CONFIG_VIA_RHINE is not set
CONFIG_VIDEO_MEDIA=m
CONFIG_VIDEO_V4L2=m
CONFIG_VIDEO_V4L2_COMMON=m
CONFIG_VLAN_8021Q=m
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_W1_SLAVE_BQ27000 is not set
CONFIG_YAFFS_9BYTE_TAGS=y
# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
CONFIG_YAFFS_AUTO_YAFFS2=y
# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
CONFIG_YAFFS_FS=y
CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
CONFIG_YAFFS_YAFFS1=y
CONFIG_YAFFS_YAFFS2=y
# CONFIG_ZEROPLUS_FF is not set
CONFIG_ZONE_DMA_FLAG=0