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amazon: work on pci controller

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SVN-Revision: 19013
This commit is contained in:
Hauke Mehrtens 2010-01-02 23:08:15 +00:00
parent b1dca51ad0
commit 3478d91266
6 changed files with 54 additions and 101 deletions
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1
target/linux/amazon/config-2.6.30
View file

@ -138,6 +138,7 @@ CONFIG_SCHED_OMIT_FRAME_POINTER=y
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SLOW_WORK is not set
CONFIG_SWAP_IO_SPACE=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_SYS_HAS_CPU_MIPS32_R2=y
CONFIG_SYS_HAS_EARLY_PRINTK=y

75
target/linux/amazon/files/arch/mips/amazon/pci.c
View file

@ -36,7 +36,7 @@
#endif
#define AMAZON_PCI_MEM_SIZE 0x00400000
#define AMAZON_PCI_IO_BASE 0xb2400000
#define AMAZON_PCI_IO_SIZE 0x00002000
#define AMAZON_PCI_IO_SIZE 0x00200000
#define AMAZON_PCI_CFG_BUSNUM_SHF 16
#define AMAZON_PCI_CFG_DEVNUM_SHF 11
@ -45,27 +45,15 @@
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
static inline u32 amazon_r32(u32 addr)
{
u32 *ptr = (u32 *) addr;
return __raw_readl(ptr);
}
static inline void amazon_w32(u32 addr, u32 val)
{
u32 *ptr = (u32 *) addr;
__raw_writel(val, ptr);
}
static struct resource pci_io_resource = {
.name = "io pci IO space",
#if 0
#if 1
.start = AMAZON_PCI_IO_BASE,
.end = AMAZON_PCI_IO_BASE + AMAZON_PCI_IO_SIZE - 1,
#endif
#else
.start = 0,
.end = AMAZON_PCI_IO_SIZE - 1,
.end = 0x00002000 - 1,
#endif
.flags = IORESOURCE_IO
};
@ -76,15 +64,6 @@ static struct resource pci_mem_resource = {
.flags = IORESOURCE_MEM
};
static inline u32 amazon_pci_swap(u32 val)
{
#ifdef CONFIG_AMAZON_PCI_HW_SWAP
return swab32(val);
#else
return val;
#endif
}
static int amazon_pci_config_access(unsigned char access_type,
struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data)
{
@ -95,28 +74,40 @@ static int amazon_pci_config_access(unsigned char access_type,
/* Amazon support slot from 0 to 15 */
/* devfn 0 & 0x20 is itself */
if ((bus->number != 0) || (devfn == 0) || (devfn == 0x20))
if ((bus->number != 0) || (devfn > 0x7f) || (devfn == 0) || (devfn == 0x20))
return 1;
pci_addr=AMAZON_PCI_CFG_BASE |
local_irq_save(flags);
pci_addr = AMAZON_PCI_CFG_BASE |
bus->number << AMAZON_PCI_CFG_BUSNUM_SHF |
devfn << AMAZON_PCI_CFG_FUNNUM_SHF |
(where & ~0x3);
local_irq_save(flags);
if (access_type == PCI_ACCESS_WRITE) {
val = amazon_pci_swap(*data);
if (access_type == PCI_ACCESS_WRITE)
{
#ifdef CONFIG_SWAP_IO_SPACE
val = swab32(*data);
#endif
ret = put_dbe(val, (u32 *)pci_addr);
} else {
ret = get_dbe(val, (u32 *)pci_addr);
*data = amazon_pci_swap(val);
#ifdef CONFIG_SWAP_IO_SPACE
*data = swab32(val);
#else
*data = val;
#endif
}
amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)));
amazon_w32(STATUS_COMMAND_ADDR, amazon_r32(STATUS_COMMAND_ADDR));
amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)));
amazon_writel(amazon_readl(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)), PCI_MODE);
amazon_writel(amazon_readl(STATUS_COMMAND_ADDR), STATUS_COMMAND_ADDR);
amazon_writel(amazon_readl(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)), PCI_MODE);
mb();
local_irq_restore(flags);
if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
return 1;
return ret;
}
@ -172,7 +163,9 @@ static struct pci_ops amazon_pci_ops = {
static struct pci_controller amazon_pci_controller = {
.pci_ops = &amazon_pci_ops,
.mem_resource = &pci_mem_resource,
.io_resource = &pci_io_resource
.mem_offset = 0x00000000UL,
.io_resource = &pci_io_resource,
.io_offset = 0x00000000UL,
};
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
@ -237,13 +230,13 @@ int __init amazon_pci_init(void)
{
u32 temp_buffer;
#ifdef CONFIG_AMAZON_PCI_HW_SWAP
#ifdef CONFIG_SWAP_IO_SPACE
AMAZON_PCI_REG32(IRM) = AMAZON_PCI_REG32(IRM) | (1<<27) | (1<<28);
wmb();
#endif
AMAZON_PCI_REG32(CLOCK_CONTROL) = AMAZON_PCI_REG32(CLOCK_CONTROL) | (1<<ARB_CTRL_bit);
amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)));
amazon_writel(amazon_readl(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)), PCI_MODE);
AMAZON_PCI_REG32(STATUS_COMMAND_ADDR) = AMAZON_PCI_REG32(STATUS_COMMAND_ADDR) | (1<<BUS_MASTER_ENABLE_BIT) |(1<<MEM_SPACE_ENABLE_BIT);
@ -272,14 +265,14 @@ int __init amazon_pci_init(void)
AMAZON_PCI_REG32(FPI_ADDRESS_MAP_6) = 0xb2600000;
AMAZON_PCI_REG32(FPI_ADDRESS_MAP_7) = 0xb2700000;
AMAZON_PCI_REG32(BAR11_MASK) = 0x0f000008;
AMAZON_PCI_REG32(BAR11_MASK) = 0x0c000008;
AMAZON_PCI_REG32(PCI_ADDRESS_MAP_11) = 0x0;
AMAZON_PCI_REG32(BAR1_ADDR) = 0x0;
amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)));
amazon_writel(amazon_readl(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)), PCI_MODE);
//use 8 dw burse length
AMAZON_PCI_REG32(FPI_BURST_LENGTH) = 0x303;
amazon_pci_controller.io_map_base = (unsigned long)ioremap(AMAZON_PCI_IO_BASE, AMAZON_PCI_IO_SIZE);
amazon_pci_controller.io_map_base = (unsigned long)ioremap(AMAZON_PCI_IO_BASE, AMAZON_PCI_IO_SIZE - 1);
register_pci_controller(&amazon_pci_controller);
return 0;
}

5
target/linux/amazon/files/arch/mips/amazon/setup.c
View file

@ -155,6 +155,11 @@ void __init plat_mem_setup(void)
amazon_writel(0x3fff, AMAZON_PMU_PWDCR);
//reenable trace capability
part_no = readl(AMAZON_BCU_ECON);
ioport_resource.start = IOPORT_RESOURCE_START;
ioport_resource.end = IOPORT_RESOURCE_END;
iomem_resource.start = IOMEM_RESOURCE_START;
iomem_resource.end = IOMEM_RESOURCE_END;
}
static void amazon_machine_restart(char *command)

11
target/linux/amazon/files/include/asm-mips/amazon/amazon.h
View file

@ -25,9 +25,14 @@
other party has been advised of the possibility of such damages.
******************************************************************************/
#define amazon_readl(a) readl(((u32*)(a)))
#define amazon_writel(a,b) writel(a, ((u32*)(b)))
#define amazon_writel_masked(a,b,c) writel((readl(((u32*)(a))) & ~b) | (c & b), ((u32*)(a)))
#define amazon_readl(a) __raw_readl(((u32*)(a)))
#define amazon_writel(a,b) __raw_writel(a, ((u32*)(b)))
#define amazon_writel_masked(a,b,c) __raw_writel((__raw_readl(((u32*)(a))) & ~b) | (c & b), ((u32*)(a)))
#define IOPORT_RESOURCE_START 0x10000000
#define IOPORT_RESOURCE_END 0xffffffff
#define IOMEM_RESOURCE_START 0x10000000
#define IOMEM_RESOURCE_END 0xffffffff
/* check ADSL link status */
#define AMAZON_CHECK_LINK

52
target/linux/amazon/files/include/asm-mips/mach-amazon/mangle-port.h
View file

@ -1,52 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003, 2004 Ralf Baechle
*/
#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H
#define __ASM_MACH_GENERIC_MANGLE_PORT_H
#define __swizzle_addr_b(port) (port)
#define __swizzle_addr_w(port) ((port) ^ 2)
#define __swizzle_addr_l(port) (port)
#define __swizzle_addr_q(port) (port)
/*
* Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
* less sane hardware forces software to fiddle with this...
*
* Regardless, if the host bus endianness mismatches that of PCI/ISA, then
* you can't have the numerical value of data and byte addresses within
* multibyte quantities both preserved at the same time. Hence two
* variations of functions: non-prefixed ones that preserve the value
* and prefixed ones that preserve byte addresses. The latters are
* typically used for moving raw data between a peripheral and memory (cf.
* string I/O functions), hence the "__mem_" prefix.
*/
#if defined(CONFIG_SWAP_IO_SPACE)
# define ioswabb(a,x) (x)
# define __mem_ioswabb(a,x) (x)
# define ioswabw(a,x) le16_to_cpu(x)
# define __mem_ioswabw(a,x) (x)
# define ioswabl(a,x) le32_to_cpu(x)
# define __mem_ioswabl(a,x) (x)
# define ioswabq(a,x) le64_to_cpu(x)
# define __mem_ioswabq(a,x) (x)
#else
# define ioswabb(a,x) (x)
# define __mem_ioswabb(a,x) (x)
# define ioswabw(a,x) (x)
# define __mem_ioswabw(a,x) cpu_to_le16(x)
# define ioswabl(a,x) (x)
# define __mem_ioswabl(a,x) cpu_to_le32(x)
# define ioswabq(a,x) (x)
# define __mem_ioswabq(a,x) cpu_to_le32(x)
#endif
#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */

5
target/linux/amazon/patches-2.6.30/100-board.patch
View file

@ -1,6 +1,6 @@
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -60,6 +60,21 @@ config BCM47XX
@@ -60,6 +60,22 @@ config BCM47XX
help
Support for BCM47XX based boards
@ -18,11 +18,12 @@
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_HAS_EARLY_PRINTK
+ select HW_HAS_PCI
+ select SWAP_IO_SPACE
+
config MIPS_COBALT
bool "Cobalt Server"
select CEVT_R4K
@@ -633,6 +648,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
@@ -633,6 +649,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
endchoice