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update OCF framework to version 20100325

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SVN-Revision: 21356
This commit is contained in:
Jo-Philipp Wich 2010-05-04 20:59:19 +00:00
parent d30f29165a
commit 32e7340bf2
192 changed files with 65222 additions and 4805 deletions
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3
target/linux/generic-2.6/config-2.6.25
View file

@ -1128,10 +1128,13 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NTFS_RW is not set
# CONFIG_NVRAM is not set
# CONFIG_OCF_BENCH is not set
# CONFIG_OCF_C7108 is not set
# CONFIG_OCF_CRYPTOCTEON is not set
# CONFIG_OCF_EP80579 is not set
# CONFIG_OCF_HIFNHIPP is not set
# CONFIG_OCF_HIFN is not set
# CONFIG_OCF_IXP4XX is not set
# CONFIG_OCF_KIRKWOOD is not set
# CONFIG_OCF_OCF is not set
# CONFIG_OCF_OCFNULL is not set
# CONFIG_OCFS2_FS is not set

3
target/linux/generic-2.6/config-2.6.30
View file

@ -1525,10 +1525,13 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NTFS_RW is not set
# CONFIG_NVRAM is not set
# CONFIG_OCF_BENCH is not set
# CONFIG_OCF_C7108 is not set
# CONFIG_OCF_CRYPTOCTEON is not set
# CONFIG_OCF_EP80579 is not set
# CONFIG_OCF_HIFNHIPP is not set
# CONFIG_OCF_HIFN is not set
# CONFIG_OCF_IXP4XX is not set
# CONFIG_OCF_KIRKWOOD is not set
# CONFIG_OCF_OCF is not set
# CONFIG_OCF_OCFNULL is not set
# CONFIG_OCFS2_FS is not set

3
target/linux/generic-2.6/config-2.6.31
View file

@ -1522,10 +1522,13 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NTFS_RW is not set
# CONFIG_NVRAM is not set
# CONFIG_OCF_BENCH is not set
# CONFIG_OCF_C7108 is not set
# CONFIG_OCF_CRYPTOCTEON is not set
# CONFIG_OCF_EP80579 is not set
# CONFIG_OCF_HIFNHIPP is not set
# CONFIG_OCF_HIFN is not set
# CONFIG_OCF_IXP4XX is not set
# CONFIG_OCF_KIRKWOOD is not set
# CONFIG_OCF_OCF is not set
# CONFIG_OCF_OCFNULL is not set
# CONFIG_OCFS2_FS is not set

3
target/linux/generic-2.6/config-2.6.32
View file

@ -1603,10 +1603,13 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NTFS_RW is not set
# CONFIG_NVRAM is not set
# CONFIG_OCF_BENCH is not set
# CONFIG_OCF_C7108 is not set
# CONFIG_OCF_CRYPTOCTEON is not set
# CONFIG_OCF_EP80579 is not set
# CONFIG_OCF_HIFNHIPP is not set
# CONFIG_OCF_HIFN is not set
# CONFIG_OCF_IXP4XX is not set
# CONFIG_OCF_KIRKWOOD is not set
# CONFIG_OCF_OCF is not set
# CONFIG_OCF_OCFNULL is not set
# CONFIG_OCFS2_FS is not set

3
target/linux/generic-2.6/config-2.6.33
View file

@ -1616,10 +1616,13 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NVRAM is not set
# CONFIG_OC_ETM is not set
# CONFIG_OCF_BENCH is not set
# CONFIG_OCF_C7108 is not set
# CONFIG_OCF_CRYPTOCTEON is not set
# CONFIG_OCF_EP80579 is not set
# CONFIG_OCF_HIFNHIPP is not set
# CONFIG_OCF_HIFN is not set
# CONFIG_OCF_IXP4XX is not set
# CONFIG_OCF_KIRKWOOD is not set
# CONFIG_OCF_OCF is not set
# CONFIG_OCF_OCFNULL is not set
# CONFIG_OCFS2_FS is not set

3
target/linux/generic-2.6/config-2.6.34
View file

@ -1629,10 +1629,13 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NVRAM is not set
# CONFIG_OC_ETM is not set
# CONFIG_OCF_BENCH is not set
# CONFIG_OCF_C7108 is not set
# CONFIG_OCF_CRYPTOCTEON is not set
# CONFIG_OCF_EP80579 is not set
# CONFIG_OCF_HIFNHIPP is not set
# CONFIG_OCF_HIFN is not set
# CONFIG_OCF_IXP4XX is not set
# CONFIG_OCF_KIRKWOOD is not set
# CONFIG_OCF_OCF is not set
# CONFIG_OCF_OCFNULL is not set
# CONFIG_OCFS2_FS is not set

1960
target/linux/generic-2.6/files/crypto/ocf/ChangeLog
View file

File diff suppressed because it is too large Load diff

2
target/linux/generic-2.6/files/crypto/ocf/Config.in
View file

@ -25,6 +25,8 @@ dep_tristate ' pasemi (HW crypto engine)' \
CONFIG_OCF_PASEMI $CONFIG_OCF_OCF
dep_tristate ' ep80579 (HW crypto engine)' \
CONFIG_OCF_EP80579 $CONFIG_OCF_OCF
dep_tristate ' Micronas c7108 (HW crypto engine)' \
CONFIG_OCF_C7108 $CONFIG_OCF_OCF
dep_tristate ' ocfnull (does no crypto)' \
CONFIG_OCF_OCFNULL $CONFIG_OCF_OCF
dep_tristate ' ocf-bench (HW crypto in-kernel benchmark)' \

18
target/linux/generic-2.6/files/crypto/ocf/Kconfig
View file

@ -84,6 +84,24 @@ config OCF_EP80579
help
OCF driver for the Intel EP80579 Integrated Processor Product Line.
config OCF_CRYPTOCTEON
tristate "cryptocteon (HW crypto engine)"
depends on OCF_OCF
help
OCF driver for the Cavium OCTEON Processors.
config OCF_KIRKWOOD
tristate "kirkwood (HW crypto engine)"
depends on OCF_OCF
help
OCF driver for the Marvell Kirkwood (88F6xxx) Processors.
config OCF_C7108
tristate "Micronas 7108 (HW crypto engine)"
depends on OCF_OCF
help
OCF driver for the Microna 7108 Cipher processors.
config OCF_OCFNULL
tristate "ocfnull (fake crypto engine)"
depends on OCF_OCF

5
target/linux/generic-2.6/files/crypto/ocf/Makefile
View file

@ -43,7 +43,10 @@ $(_obj)-$(CONFIG_OCF_IXP4XX) += ixp4xx$(_slash)
$(_obj)-$(CONFIG_OCF_TALITOS) += talitos$(_slash)
$(_obj)-$(CONFIG_OCF_PASEMI) += pasemi$(_slash)
$(_obj)-$(CONFIG_OCF_EP80579) += ep80579$(_slash)
$(_obj)-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon$(_slash)
$(_obj)-$(CONFIG_OCF_KIRKWOOD) += kirkwood$(_slash)
$(_obj)-$(CONFIG_OCF_OCFNULL) += ocfnull$(_slash)
$(_obj)-$(CONFIG_OCF_C7108) += c7108$(_slash)
ocf-objs := $(OCF_OBJS)
@ -79,7 +82,7 @@ patch:
diff -Nau /dev/null $$t | sed 's?^+++ \./?+++ linux/crypto/ocf/?'; \
done > $$patch; \
cat patches/linux-2.4.35-ocf.patch $$patch > $$patch24; \
cat patches/linux-2.6.26-ocf.patch $$patch > $$patch26
cat patches/linux-2.6.33-ocf.patch $$patch > $$patch26
.PHONY: tarball
tarball:

167
target/linux/generic-2.6/files/crypto/ocf/README Normal file
View file

@ -0,0 +1,167 @@
README - ocf-linux-20100325
---------------------------
This README provides instructions for getting ocf-linux compiled and
operating in a generic linux environment. For other information you
might like to visit the home page for this project:
http://ocf-linux.sourceforge.net/
Adding OCF to linux
-------------------
Not much in this file for now, just some notes. I usually build
the ocf support as modules but it can be built into the kernel as
well. To use it:
* mknod /dev/crypto c 10 70
* to add OCF to your kernel source, you have two options. Apply
the kernel specific patch:
cd linux-2.4*; gunzip < ocf-linux-24-XXXXXXXX.patch.gz | patch -p1
cd linux-2.6*; gunzip < ocf-linux-26-XXXXXXXX.patch.gz | patch -p1
if you do one of the above, then you can proceed to the next step,
or you can do the above process by hand with using the patches against
linux-2.4.35 and 2.6.33 to include the ocf code under crypto/ocf.
Here's how to add it:
for 2.4.35 (and later)
cd linux-2.4.35/crypto
tar xvzf ocf-linux.tar.gz
cd ..
patch -p1 < crypto/ocf/patches/linux-2.4.35-ocf.patch
for 2.6.23 (and later), find the kernel patch specific (or nearest)
to your kernel versions and then:
cd linux-2.6.NN/crypto
tar xvzf ocf-linux.tar.gz
cd ..
patch -p1 < crypto/ocf/patches/linux-2.6.NN-ocf.patch
It should be easy to take this patch and apply it to other more
recent versions of the kernels. The same patches should also work
relatively easily on kernels as old as 2.6.11 and 2.4.18.
* under 2.4 if you are on a non-x86 platform, you may need to:
cp linux-2.X.x/include/asm-i386/kmap_types.h linux-2.X.x/include/asm-YYY
so that you can build the kernel crypto support needed for the cryptosoft
driver.
* For simplicity you should enable all the crypto support in your kernel
except for the test driver. Likewise for the OCF options. Do not
enable OCF crypto drivers for HW that you do not have (for example
ixp4xx will not compile on non-Xscale systems).
* make sure that cryptodev.h (from ocf-linux.tar.gz) is installed as
crypto/cryptodev.h in an include directory that is used for building
applications for your platform. For example on a host system that
might be:
/usr/include/crypto/cryptodev.h
* patch your openssl-0.9.8n code with the openssl-0.9.8n.patch.
(NOTE: there is no longer a need to patch ssh). The patch is against:
openssl-0_9_8e
If you need a patch for an older version of openssl, you should look
to older OCF releases. This patch is unlikely to work on older
openssl versions.
openssl-0.9.8n.patch
- enables --with-cryptodev for non BSD systems
- adds -cpu option to openssl speed for calculating CPU load
under linux
- fixes null pointer in openssl speed multi thread output.
- fixes test keys to work with linux crypto's more stringent
key checking.
- adds MD5/SHA acceleration (Ronen Shitrit), only enabled
with the --with-cryptodev-digests option
- fixes bug in engine code caching.
* build crypto-tools-XXXXXXXX.tar.gz if you want to try some of the BSD
tools for testing OCF (ie., cryptotest).
How to load the OCF drivers
---------------------------
First insert the base modules:
insmod ocf
insmod cryptodev
You can then install the software OCF driver with:
insmod cryptosoft
and one or more of the OCF HW drivers with:
insmod safe
insmod hifn7751
insmod ixp4xx
...
all the drivers take a debug option to enable verbose debug so that
you can see what is going on. For debug you load them as:
insmod ocf crypto_debug=1
insmod cryptodev cryptodev_debug=1
insmod cryptosoft swcr_debug=1
You may load more than one OCF crypto driver but then there is no guarantee
as to which will be used.
You can also enable debug at run time on 2.6 systems with the following:
echo 1 > /sys/module/ocf/parameters/crypto_debug
echo 1 > /sys/module/cryptodev/parameters/cryptodev_debug
echo 1 > /sys/module/cryptosoft/parameters/swcr_debug
echo 1 > /sys/module/hifn7751/parameters/hifn_debug
echo 1 > /sys/module/safe/parameters/safe_debug
echo 1 > /sys/module/ixp4xx/parameters/ixp_debug
...
Testing the OCF support
-----------------------
run "cryptotest", it should do a short test for a couple of
des packets. If it does everything is working.
If this works, then ssh will use the driver when invoked as:
ssh -c 3des username@host
to see for sure that it is operating, enable debug as defined above.
To get a better idea of performance run:
cryptotest 100 4096
There are more options to cryptotest, see the help.
It is also possible to use openssl to test the speed of the crypto
drivers.
openssl speed -evp des -engine cryptodev -elapsed
openssl speed -evp des3 -engine cryptodev -elapsed
openssl speed -evp aes128 -engine cryptodev -elapsed
and multiple threads (10) with:
openssl speed -evp des -engine cryptodev -elapsed -multi 10
openssl speed -evp des3 -engine cryptodev -elapsed -multi 10
openssl speed -evp aes128 -engine cryptodev -elapsed -multi 10
for public key testing you can try:
cryptokeytest
openssl speed -engine cryptodev rsa -elapsed
openssl speed -engine cryptodev dsa -elapsed
David McCullough
david_mccullough@mcafee.com

12
target/linux/generic-2.6/files/crypto/ocf/c7108/Makefile Normal file
View file

@ -0,0 +1,12 @@
# for SGlinux builds
-include $(ROOTDIR)/modules/.config
obj-$(CONFIG_OCF_C7108) += aes-7108.o
obj ?= .
EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/
ifdef TOPDIR
-include $(TOPDIR)/Rules.make
endif

839
target/linux/generic-2.6/files/crypto/ocf/c7108/aes-7108.c Normal file
View file

@ -0,0 +1,839 @@
/*
* Copyright (C) 2006 Micronas USA
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Effort sponsored in part by the Defense Advanced Research Projects
* Agency (DARPA) and Air Force Research Laboratory, Air Force
* Materiel Command, USAF, under agreement number F30602-01-2-0537.
*
*/
//#include <linux/config.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/wait.h>
#include <linux/crypto.h>
#include <linux/mm.h>
#include <linux/skbuff.h>
#include <linux/random.h>
#include <asm/io.h>
#include <asm/delay.h>
//#include <asm/scatterlist.h>
#include <linux/scatterlist.h>
#include <linux/dma-mapping.h>
#include <linux/highmem.h>
#include <cryptodev.h>
#include <uio.h>
#include <aes-7108.h>
/* Runtime mode */
static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR;
//static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC;
static int32_t c7108_id = -1;
static struct cipher_7108 **c7108_sessions = NULL;
static u_int32_t c7108_sesnum = 0;
static unsigned long iobar;
/* Crypto entry points */
static int c7108_process(void *, struct cryptop *, int);
static int c7108_newsession(void *, u_int32_t *, struct cryptoini *);
static int c7108_freesession(void *, u_int64_t);
/* Globals */
static int debug = 0;
static spinlock_t csr_mutex;
/* Generic controller-based lock */
#define AES_LOCK()\
spin_lock(&csr_mutex)
#define AES_UNLOCK()\
spin_unlock(&csr_mutex)
/* 7108 AES register access */
#define c7108_reg_wr8(a,d) iowrite8(d, (void*)(iobar+(a)))
#define c7108_reg_wr16(a,d) iowrite16(d, (void*)(iobar+(a)))
#define c7108_reg_wr32(a,d) iowrite32(d, (void*)(iobar+(a)))
#define c7108_reg_rd8(a) ioread8((void*)(iobar+(a)))
#define c7108_reg_rd16(a) ioread16((void*)(iobar+(a)))
#define c7108_reg_rd32(a) ioread32((void*)(iobar+(a)))
static int
c7108_xlate_key(int klen, u8* k8ptr, u32* k32ptr)
{
int i, nw=0;
nw = ((klen >= 256) ? 8 : (klen >= 192) ? 6 : 4);
for ( i = 0; i < nw; i++) {
k32ptr[i] = (k8ptr[i+3] << 24) | (k8ptr[i+2] << 16) |
(k8ptr[i+1] << 8) | k8ptr[i];
}
return 0;
}
static int
c7108_cache_key(int klen, u32* k32ptr, u8* k8ptr)
{
int i, nb=0;
u8* ptr = (u8*)k32ptr;
nb = ((klen >= 256) ? 32 : (klen >= 192) ? 24 : 16);
for ( i = 0; i < nb; i++)
k8ptr[i] = ptr[i];
return 0;
}
static int
c7108_aes_setup_dma(u32 src, u32 dst, u32 len)
{
if (len < 16) {
printk("len < 16\n");
return -10;
}
if (len % 16) {
printk("len not multiple of 16\n");
return -11;
}
c7108_reg_wr16(C7108_AES_DMA_SRC0_LO, (u16) src);
c7108_reg_wr16(C7108_AES_DMA_SRC0_HI, (u16)((src & 0xffff0000) >> 16));
c7108_reg_wr16(C7108_AES_DMA_DST0_LO, (u16) dst);
c7108_reg_wr16(C7108_AES_DMA_DST0_HI, (u16)((dst & 0xffff0000) >> 16));
c7108_reg_wr16(C7108_AES_DMA_LEN, (u16) ((len / 16) - 1));
return 0;
}
static int
c7108_aes_set_hw_iv(u8 iv[16])
{
c7108_reg_wr16(C7108_AES_IV0_LO, (u16) ((iv[1] << 8) | iv[0]));
c7108_reg_wr16(C7108_AES_IV0_HI, (u16) ((iv[3] << 8) | iv[2]));
c7108_reg_wr16(C7108_AES_IV1_LO, (u16) ((iv[5] << 8) | iv[4]));
c7108_reg_wr16(C7108_AES_IV1_HI, (u16) ((iv[7] << 8) | iv[6]));
c7108_reg_wr16(C7108_AES_IV2_LO, (u16) ((iv[9] << 8) | iv[8]));
c7108_reg_wr16(C7108_AES_IV2_HI, (u16) ((iv[11] << 8) | iv[10]));
c7108_reg_wr16(C7108_AES_IV3_LO, (u16) ((iv[13] << 8) | iv[12]));
c7108_reg_wr16(C7108_AES_IV3_HI, (u16) ((iv[15] << 8) | iv[14]));
return 0;
}
static void
c7108_aes_read_dkey(u32 * dkey)
{
dkey[0] = (c7108_reg_rd16(C7108_AES_EKEY0_HI) << 16) |
c7108_reg_rd16(C7108_AES_EKEY0_LO);
dkey[1] = (c7108_reg_rd16(C7108_AES_EKEY1_HI) << 16) |
c7108_reg_rd16(C7108_AES_EKEY1_LO);
dkey[2] = (c7108_reg_rd16(C7108_AES_EKEY2_HI) << 16) |
c7108_reg_rd16(C7108_AES_EKEY2_LO);
dkey[3] = (c7108_reg_rd16(C7108_AES_EKEY3_HI) << 16) |
c7108_reg_rd16(C7108_AES_EKEY3_LO);
dkey[4] = (c7108_reg_rd16(C7108_AES_EKEY4_HI) << 16) |
c7108_reg_rd16(C7108_AES_EKEY4_LO);
dkey[5] = (c7108_reg_rd16(C7108_AES_EKEY5_HI) << 16) |
c7108_reg_rd16(C7108_AES_EKEY5_LO);
dkey[6] = (c7108_reg_rd16(C7108_AES_EKEY6_HI) << 16) |
c7108_reg_rd16(C7108_AES_EKEY6_LO);
dkey[7] = (c7108_reg_rd16(C7108_AES_EKEY7_HI) << 16) |
c7108_reg_rd16(C7108_AES_EKEY7_LO);
}
static int
c7108_aes_cipher(int op,
u32 dst,
u32 src,
u32 len,
int klen,
u16 mode,
u32 key[8],
u8 iv[16])
{
int rv = 0, cnt=0;
u16 ctrl = 0, stat = 0;
AES_LOCK();
/* Setup key length */
if (klen == 128) {
ctrl |= C7108_AES_KEY_LEN_128;
} else if (klen == 192) {
ctrl |= C7108_AES_KEY_LEN_192;
} else if (klen == 256) {
ctrl |= C7108_AES_KEY_LEN_256;
} else {
AES_UNLOCK();
return -3;
}
/* Check opcode */
if (C7108_AES_ENCRYPT == op) {
ctrl |= C7108_AES_ENCRYPT;
} else if (C7108_AES_DECRYPT == op) {
ctrl |= C7108_AES_DECRYPT;
} else {
AES_UNLOCK();
return -4;
}
/* check mode */
if ( (mode != C7108_AES_CTRL_MODE_CBC) &&
(mode != C7108_AES_CTRL_MODE_CFB) &&
(mode != C7108_AES_CTRL_MODE_OFB) &&
(mode != C7108_AES_CTRL_MODE_CTR) &&
(mode != C7108_AES_CTRL_MODE_ECB) ) {
AES_UNLOCK();
return -5;
}
/* Now set mode */
ctrl |= mode;
/* For CFB, OFB, and CTR, neither backward key
* expansion nor key inversion is required.
*/
if ( (C7108_AES_DECRYPT == op) &&
(C7108_AES_CTRL_MODE_CBC == mode ||
C7108_AES_CTRL_MODE_ECB == mode ) ){
/* Program Key */
c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[4]);
c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[4] >> 16));
c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[5]);
c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[5] >> 16));
c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[6]);
c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[6] >> 16));
c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[7]);
c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[7] >> 16));
c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[2]);
c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[2] >> 16));
c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[3]);
c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[3] >> 16));
if (192 == klen) {
c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[7]);
c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[7] >> 16));
c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[7]);
c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[7] >> 16));
} else if (256 == klen) {
/* 256 */
c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[0]);
c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[0] >> 16));
c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[1]);
c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[1] >> 16));
}
} else {
/* Program Key */
c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[0]);
c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[0] >> 16));
c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[1]);
c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[1] >> 16));
c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[2]);
c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[2] >> 16));
c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[3]);
c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[3] >> 16));
c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[4]);
c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[4] >> 16));
c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[5]);
c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[5] >> 16));
c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[6]);
c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[6] >> 16));
c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[7]);
c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[7] >> 16));
}
/* Set IV always */
c7108_aes_set_hw_iv(iv);
/* Program DMA addresses */
if ((rv = c7108_aes_setup_dma(src, dst, len)) < 0) {
AES_UNLOCK();
return rv;
}
/* Start AES cipher */
c7108_reg_wr16(C7108_AES_CTRL, ctrl | C7108_AES_GO);
//printk("Ctrl: 0x%x\n", ctrl | C7108_AES_GO);
do {
/* TODO: interrupt mode */
// printk("aes_stat=0x%x\n", stat);
//udelay(100);
} while ((cnt++ < 1000000) &&
!((stat=c7108_reg_rd16(C7108_AES_CTRL))&C7108_AES_OP_DONE));
if ((mode == C7108_AES_CTRL_MODE_ECB)||
(mode == C7108_AES_CTRL_MODE_CBC)) {
/* Save out key when the lock is held ... */
c7108_aes_read_dkey(key);
}
AES_UNLOCK();
return 0;
}
/*
* Generate a new crypto device session.
*/
static int
c7108_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri)
{
struct cipher_7108 **swd;
u_int32_t i;
char *algo;
int mode, xfm_type;
dprintk("%s()\n", __FUNCTION__);
if (sid == NULL || cri == NULL) {
dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__);
return EINVAL;
}
if (c7108_sessions) {
for (i = 1; i < c7108_sesnum; i++)
if (c7108_sessions[i] == NULL)
break;
} else
i = 1; /* NB: to silence compiler warning */
if (c7108_sessions == NULL || i == c7108_sesnum) {
if (c7108_sessions == NULL) {
i = 1; /* We leave c7108_sessions[0] empty */
c7108_sesnum = CRYPTO_SW_SESSIONS;
} else
c7108_sesnum *= 2;
swd = kmalloc(c7108_sesnum * sizeof(struct cipher_7108 *),
GFP_ATOMIC);
if (swd == NULL) {
/* Reset session number */
if (c7108_sesnum == CRYPTO_SW_SESSIONS)
c7108_sesnum = 0;
else
c7108_sesnum /= 2;
dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__);
return ENOBUFS;
}
memset(swd, 0, c7108_sesnum * sizeof(struct cipher_7108 *));
/* Copy existing sessions */
if (c7108_sessions) {
memcpy(swd, c7108_sessions,
(c7108_sesnum / 2) * sizeof(struct cipher_7108 *));
kfree(c7108_sessions);
}
c7108_sessions = swd;
}
swd = &c7108_sessions[i];
*sid = i;
while (cri) {
*swd = (struct cipher_7108 *)
kmalloc(sizeof(struct cipher_7108), GFP_ATOMIC);
if (*swd == NULL) {
c7108_freesession(NULL, i);
dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__);
return ENOBUFS;
}
memset(*swd, 0, sizeof(struct cipher_7108));
algo = NULL;
mode = 0;
xfm_type = HW_TYPE_CIPHER;
switch (cri->cri_alg) {
case CRYPTO_AES_CBC:
algo = "aes";
mode = CRYPTO_TFM_MODE_CBC;
c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC;
break;
#if 0
case CRYPTO_AES_CTR:
algo = "aes_ctr";
mode = CRYPTO_TFM_MODE_CBC;
c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR;
break;
case CRYPTO_AES_ECB:
algo = "aes_ecb";
mode = CRYPTO_TFM_MODE_CBC;
c7108_crypto_mode = C7108_AES_CTRL_MODE_ECB;
break;
case CRYPTO_AES_OFB:
algo = "aes_ofb";
mode = CRYPTO_TFM_MODE_CBC;
c7108_crypto_mode = C7108_AES_CTRL_MODE_OFB;
break;
case CRYPTO_AES_CFB:
algo = "aes_cfb";
mode = CRYPTO_TFM_MODE_CBC;
c7108_crypto_mode = C7108_AES_CTRL_MODE_CFB;
break;
#endif
default:
printk("unsupported crypto algorithm: %d\n",
cri->cri_alg);
return -EINVAL;
break;
}
if (!algo || !*algo) {
printk("cypher_7108_crypto: Unknown algo 0x%x\n",
cri->cri_alg);
c7108_freesession(NULL, i);
return EINVAL;
}
if (xfm_type == HW_TYPE_CIPHER) {
if (debug) {
dprintk("%s key:", __FUNCTION__);
for (i = 0; i < (cri->cri_klen + 7) / 8; i++)
dprintk("%s0x%02x", (i % 8) ? " " : "\n ",
cri->cri_key[i]);
dprintk("\n");
}
} else if (xfm_type == SW_TYPE_HMAC ||
xfm_type == SW_TYPE_HASH) {
printk("cypher_7108_crypto: HMAC unsupported!\n");
return -EINVAL;
c7108_freesession(NULL, i);
} else {
printk("cypher_7108_crypto: "
"Unhandled xfm_type %d\n", xfm_type);
c7108_freesession(NULL, i);
return EINVAL;
}
(*swd)->cri_alg = cri->cri_alg;
(*swd)->xfm_type = xfm_type;
cri = cri->cri_next;
swd = &((*swd)->next);
}
return 0;
}
/*
* Free a session.
*/
static int
c7108_freesession(void *arg, u_int64_t tid)
{
struct cipher_7108 *swd;
u_int32_t sid = CRYPTO_SESID2LID(tid);
dprintk("%s()\n", __FUNCTION__);
if (sid > c7108_sesnum || c7108_sessions == NULL ||
c7108_sessions[sid] == NULL) {
dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__);
return(EINVAL);
}
/* Silently accept and return */
if (sid == 0)
return(0);
while ((swd = c7108_sessions[sid]) != NULL) {
c7108_sessions[sid] = swd->next;
kfree(swd);
}
return 0;
}
/*
* Process a hardware request.
*/
static int
c7108_process(void *arg, struct cryptop *crp, int hint)
{
struct cryptodesc *crd;
struct cipher_7108 *sw;
u_int32_t lid;
int type;
u32 hwkey[8];
#define SCATTERLIST_MAX 16
struct scatterlist sg[SCATTERLIST_MAX];
int sg_num, sg_len, skip;
struct sk_buff *skb = NULL;
struct uio *uiop = NULL;
dprintk("%s()\n", __FUNCTION__);
/* Sanity check */
if (crp == NULL) {
dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__);
return EINVAL;
}
crp->crp_etype = 0;
if (crp->crp_desc == NULL || crp->crp_buf == NULL) {
dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__);
crp->crp_etype = EINVAL;
goto done;
}
lid = crp->crp_sid & 0xffffffff;
if (lid >= c7108_sesnum || lid == 0 || c7108_sessions == NULL ||
c7108_sessions[lid] == NULL) {
crp->crp_etype = ENOENT;
dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__);
goto done;
}
/*
* do some error checking outside of the loop for SKB and IOV
* processing this leaves us with valid skb or uiop pointers
* for later
*/
if (crp->crp_flags & CRYPTO_F_SKBUF) {
skb = (struct sk_buff *) crp->crp_buf;
if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) {
printk("%s,%d: %d nr_frags > SCATTERLIST_MAX",
__FILE__, __LINE__,
skb_shinfo(skb)->nr_frags);
goto done;
}
} else if (crp->crp_flags & CRYPTO_F_IOV) {
uiop = (struct uio *) crp->crp_buf;
if (uiop->uio_iovcnt > SCATTERLIST_MAX) {
printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX",
__FILE__, __LINE__,
uiop->uio_iovcnt);
goto done;
}
}
/* Go through crypto descriptors, processing as we go */
for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
/*
* Find the crypto context.
*
* XXX Note that the logic here prevents us from having
* XXX the same algorithm multiple times in a session
* XXX (or rather, we can but it won't give us the right
* XXX results). To do that, we'd need some way of differentiating
* XXX between the various instances of an algorithm (so we can
* XXX locate the correct crypto context).
*/
for (sw = c7108_sessions[lid];
sw && sw->cri_alg != crd->crd_alg;
sw = sw->next)
;
/* No such context ? */
if (sw == NULL) {
crp->crp_etype = EINVAL;
dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__);
goto done;
}
skip = crd->crd_skip;
/*
* setup the SG list skip from the start of the buffer
*/
memset(sg, 0, sizeof(sg));
if (crp->crp_flags & CRYPTO_F_SKBUF) {
int i, len;
type = CRYPTO_BUF_SKBUF;
sg_num = 0;
sg_len = 0;
if (skip < skb_headlen(skb)) {
//sg[sg_num].page = virt_to_page(skb->data + skip);
//sg[sg_num].offset = offset_in_page(skb->data + skip);
len = skb_headlen(skb) - skip;
if (len + sg_len > crd->crd_len)
len = crd->crd_len - sg_len;
//sg[sg_num].length = len;
sg_set_page(&sg[sg_num], virt_to_page(skb->data + skip), len, offset_in_page(skb->data + skip));
sg_len += sg[sg_num].length;
sg_num++;
skip = 0;
} else
skip -= skb_headlen(skb);
for (i = 0; sg_len < crd->crd_len &&
i < skb_shinfo(skb)->nr_frags &&
sg_num < SCATTERLIST_MAX; i++) {
if (skip < skb_shinfo(skb)->frags[i].size) {
//sg[sg_num].page = skb_shinfo(skb)->frags[i].page;
//sg[sg_num].offset = skb_shinfo(skb)->frags[i].page_offset + skip;
len = skb_shinfo(skb)->frags[i].size - skip;
if (len + sg_len > crd->crd_len)
len = crd->crd_len - sg_len;
//sg[sg_num].length = len;
sg_set_page(&sg[sg_num], skb_shinfo(skb)->frags[i].page, len, skb_shinfo(skb)->frags[i].page_offset + skip);
sg_len += sg[sg_num].length;
sg_num++;
skip = 0;
} else
skip -= skb_shinfo(skb)->frags[i].size;
}
} else if (crp->crp_flags & CRYPTO_F_IOV) {
int len;
type = CRYPTO_BUF_IOV;
sg_len = 0;
for (sg_num = 0; sg_len < crd->crd_len &&
sg_num < uiop->uio_iovcnt &&
sg_num < SCATTERLIST_MAX; sg_num++) {
if (skip < uiop->uio_iov[sg_num].iov_len) {
//sg[sg_num].page = virt_to_page(uiop->uio_iov[sg_num].iov_base+skip);
//sg[sg_num].offset = offset_in_page(uiop->uio_iov[sg_num].iov_base+skip);
len = uiop->uio_iov[sg_num].iov_len - skip;
if (len + sg_len > crd->crd_len)
len = crd->crd_len - sg_len;
//sg[sg_num].length = len;
sg_set_page(&sg[sg_num], virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), len, offset_in_page(uiop->uio_iov[sg_num].iov_base+skip));
sg_len += sg[sg_num].length;
skip = 0;
} else
skip -= uiop->uio_iov[sg_num].iov_len;
}
} else {
type = CRYPTO_BUF_CONTIG;
//sg[0].page = virt_to_page(crp->crp_buf + skip);
//sg[0].offset = offset_in_page(crp->crp_buf + skip);
sg_len = (crp->crp_ilen - skip);
if (sg_len > crd->crd_len)
sg_len = crd->crd_len;
//sg[0].length = sg_len;
sg_set_page(&sg[0], virt_to_page(crp->crp_buf + skip), sg_len, offset_in_page(crp->crp_buf + skip));
sg_num = 1;
}
switch (sw->xfm_type) {
case HW_TYPE_CIPHER: {
unsigned char iv[64];
unsigned char *ivp = iv;
int i;
int ivsize = 16; /* fixed for AES */
int blocksize = 16; /* fixed for AES */
if (sg_len < blocksize) {
crp->crp_etype = EINVAL;
dprintk("%s,%d: EINVAL len %d < %d\n",
__FILE__, __LINE__,
sg_len,
blocksize);
goto done;
}
if (ivsize > sizeof(iv)) {
crp->crp_etype = EINVAL;
dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__);
goto done;
}
if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */
if (crd->crd_flags & CRD_F_IV_EXPLICIT) {
ivp = crd->crd_iv;
} else {
get_random_bytes(ivp, ivsize);
}
/*
* do we have to copy the IV back to the buffer ?
*/
if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) {
crypto_copyback(crp->crp_buf,
crd->crd_inject,
ivsize,
(caddr_t)ivp);
}
c7108_xlate_key(crd->crd_klen,
(u8*)crd->crd_key, (u32*)hwkey);
/* Encrypt SG list */
for (i = 0; i < sg_num; i++) {
sg[i].dma_address =
dma_map_single(NULL,
kmap(sg_page(&sg[i])) + sg[i].offset, sg_len, DMA_BIDIRECTIONAL);
#if 0
printk("sg[%d]:0x%08x, off 0x%08x "
"kmap 0x%08x phys 0x%08x\n",
i, sg[i].page, sg[i].offset,
kmap(sg[i].page) + sg[i].offset,
sg[i].dma_address);
#endif
c7108_aes_cipher(C7108_AES_ENCRYPT,
sg[i].dma_address,
sg[i].dma_address,
sg_len,
crd->crd_klen,
c7108_crypto_mode,
hwkey,
ivp);
if ((c7108_crypto_mode == C7108_AES_CTRL_MODE_CBC)||
(c7108_crypto_mode == C7108_AES_CTRL_MODE_ECB)) {
/* Read back expanded key and cache it in key
* context.
* NOTE: for ECB/CBC modes only (not CTR, CFB, OFB)
* where you set the key once.
*/
c7108_cache_key(crd->crd_klen,
(u32*)hwkey, (u8*)crd->crd_key);
#if 0
printk("%s expanded key:", __FUNCTION__);
for (i = 0; i < (crd->crd_klen + 7) / 8; i++)
printk("%s0x%02x", (i % 8) ? " " : "\n ",
crd->crd_key[i]);
printk("\n");
#endif
}
}
}
else { /*decrypt */
if (crd->crd_flags & CRD_F_IV_EXPLICIT) {
ivp = crd->crd_iv;
} else {
crypto_copydata(crp->crp_buf, crd->crd_inject,
ivsize, (caddr_t)ivp);
}
c7108_xlate_key(crd->crd_klen,
(u8*)crd->crd_key, (u32*)hwkey);
/* Decrypt SG list */
for (i = 0; i < sg_num; i++) {
sg[i].dma_address =
dma_map_single(NULL,
kmap(sg_page(&sg[i])) + sg[i].offset,
sg_len, DMA_BIDIRECTIONAL);
#if 0
printk("sg[%d]:0x%08x, off 0x%08x "
"kmap 0x%08x phys 0x%08x\n",
i, sg[i].page, sg[i].offset,
kmap(sg[i].page) + sg[i].offset,
sg[i].dma_address);
#endif
c7108_aes_cipher(C7108_AES_DECRYPT,
sg[i].dma_address,
sg[i].dma_address,
sg_len,
crd->crd_klen,
c7108_crypto_mode,
hwkey,
ivp);
}
}
} break;
case SW_TYPE_HMAC:
case SW_TYPE_HASH:
crp->crp_etype = EINVAL;
goto done;
break;
case SW_TYPE_COMP:
crp->crp_etype = EINVAL;
goto done;
break;
default:
/* Unknown/unsupported algorithm */
dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__);
crp->crp_etype = EINVAL;
goto done;
}
}
done:
crypto_done(crp);
return 0;
}
static struct {
softc_device_decl sc_dev;
} a7108dev;
static device_method_t a7108_methods = {
/* crypto device methods */
DEVMETHOD(cryptodev_newsession, c7108_newsession),
DEVMETHOD(cryptodev_freesession, c7108_freesession),
DEVMETHOD(cryptodev_process, c7108_process),
DEVMETHOD(cryptodev_kprocess, NULL)
};
static int
cypher_7108_crypto_init(void)
{
dprintk("%s(%p)\n", __FUNCTION__, cypher_7108_crypto_init);
iobar = (unsigned long)ioremap(CCU_AES_REG_BASE, 0x4000);
printk("7108: AES @ 0x%08x (0x%08x phys) %s mode\n",
iobar, CCU_AES_REG_BASE,
c7108_crypto_mode & C7108_AES_CTRL_MODE_CBC ? "CBC" :
c7108_crypto_mode & C7108_AES_CTRL_MODE_ECB ? "ECB" :
c7108_crypto_mode & C7108_AES_CTRL_MODE_CTR ? "CTR" :
c7108_crypto_mode & C7108_AES_CTRL_MODE_CFB ? "CFB" :
c7108_crypto_mode & C7108_AES_CTRL_MODE_OFB ? "OFB" : "???");
csr_mutex = SPIN_LOCK_UNLOCKED;
memset(&a7108dev, 0, sizeof(a7108dev));
softc_device_init(&a7108dev, "aes7108", 0, a7108_methods);
c7108_id = crypto_get_driverid(softc_get_device(&a7108dev), CRYPTOCAP_F_HARDWARE);
if (c7108_id < 0)
panic("7108: crypto device cannot initialize!");
// crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0, c7108_newsession, c7108_freesession, c7108_process, NULL);
crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0);
return(0);
}
static void
cypher_7108_crypto_exit(void)
{
dprintk("%s()\n", __FUNCTION__);
crypto_unregister_all(c7108_id);
c7108_id = -1;
}
module_init(cypher_7108_crypto_init);
module_exit(cypher_7108_crypto_exit);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_DESCRIPTION("Cypher 7108 Crypto (OCF module for kernel crypto)");

134
target/linux/generic-2.6/files/crypto/ocf/c7108/aes-7108.h Normal file
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@ -0,0 +1,134 @@
/*
* Copyright (C) 2006 Micronas USA
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Effort sponsored in part by the Defense Advanced Research Projects
* Agency (DARPA) and Air Force Research Laboratory, Air Force
* Materiel Command, USAF, under agreement number F30602-01-2-0537.
*
*/
#ifndef __AES_7108_H__
#define __AES_7108_H__
/* Cypher 7108 AES Controller Hardware */
#define CCU_REG_BASE 0x1b500000
#define CCU_AES_REG_BASE (CCU_REG_BASE + 0x100)
#define C7108_AES_KEY0_LO (0x0000)
#define C7108_AES_KEY0_HI (0x0004)
#define C7108_AES_KEY1_LO (0x0008)
#define C7108_AES_KEY1_HI (0x000c)
#define C7108_AES_KEY2_LO (0x0010)
#define C7108_AES_KEY2_HI (0x0014)
#define C7108_AES_KEY3_LO (0x0018)
#define C7108_AES_KEY3_HI (0x001c)
#define C7108_AES_KEY4_LO (0x0020)
#define C7108_AES_KEY4_HI (0x0024)
#define C7108_AES_KEY5_LO (0x0028)
#define C7108_AES_KEY5_HI (0x002c)
#define C7108_AES_KEY6_LO (0x0030)
#define C7108_AES_KEY6_HI (0x0034)
#define C7108_AES_KEY7_LO (0x0038)
#define C7108_AES_KEY7_HI (0x003c)
#define C7108_AES_IV0_LO (0x0040)
#define C7108_AES_IV0_HI (0x0044)
#define C7108_AES_IV1_LO (0x0048)
#define C7108_AES_IV1_HI (0x004c)
#define C7108_AES_IV2_LO (0x0050)
#define C7108_AES_IV2_HI (0x0054)
#define C7108_AES_IV3_LO (0x0058)
#define C7108_AES_IV3_HI (0x005c)
#define C7108_AES_DMA_SRC0_LO (0x0068) /* Bits 0:15 */
#define C7108_AES_DMA_SRC0_HI (0x006c) /* Bits 27:16 */
#define C7108_AES_DMA_DST0_LO (0x0070) /* Bits 0:15 */
#define C7108_AES_DMA_DST0_HI (0x0074) /* Bits 27:16 */
#define C7108_AES_DMA_LEN (0x0078) /*Bytes:(Count+1)x16 */
/* AES/Copy engine control register */
#define C7108_AES_CTRL (0x007c) /* AES control */
#define C7108_AES_CTRL_RS (1<<0) /* Which set of src/dst to use */
/* AES Cipher mode, controlled by setting Bits 2:0 */
#define C7108_AES_CTRL_MODE_CBC 0
#define C7108_AES_CTRL_MODE_CFB (1<<0)
#define C7108_AES_CTRL_MODE_OFB (1<<1)
#define C7108_AES_CTRL_MODE_CTR ((1<<0)|(1<<1))
#define C7108_AES_CTRL_MODE_ECB (1<<2)
/* AES Key length , Bits 5:4 */
#define C7108_AES_KEY_LEN_128 0 /* 00 */
#define C7108_AES_KEY_LEN_192 (1<<4) /* 01 */
#define C7108_AES_KEY_LEN_256 (1<<5) /* 10 */
/* AES Operation (crypt/decrypt), Bit 3 */
#define C7108_AES_DECRYPT (1<<3) /* Clear for encrypt */
#define C7108_AES_ENCRYPT 0
#define C7108_AES_INTR (1<<13) /* Set on done trans from 0->1*/
#define C7108_AES_GO (1<<14) /* Run */
#define C7108_AES_OP_DONE (1<<15) /* Set when complete */
/* Expanded key registers */
#define C7108_AES_EKEY0_LO (0x0080)
#define C7108_AES_EKEY0_HI (0x0084)
#define C7108_AES_EKEY1_LO (0x0088)
#define C7108_AES_EKEY1_HI (0x008c)
#define C7108_AES_EKEY2_LO (0x0090)
#define C7108_AES_EKEY2_HI (0x0094)
#define C7108_AES_EKEY3_LO (0x0098)
#define C7108_AES_EKEY3_HI (0x009c)
#define C7108_AES_EKEY4_LO (0x00a0)
#define C7108_AES_EKEY4_HI (0x00a4)
#define C7108_AES_EKEY5_LO (0x00a8)
#define C7108_AES_EKEY5_HI (0x00ac)
#define C7108_AES_EKEY6_LO (0x00b0)
#define C7108_AES_EKEY6_HI (0x00b4)
#define C7108_AES_EKEY7_LO (0x00b8)
#define C7108_AES_EKEY7_HI (0x00bc)
#define C7108_AES_OK (0x00fc) /* Reset: "OK" */
#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK)
/* Software session entry */
#define HW_TYPE_CIPHER 0
#define SW_TYPE_HMAC 1
#define SW_TYPE_AUTH2 2
#define SW_TYPE_HASH 3
#define SW_TYPE_COMP 4
struct cipher_7108 {
int xfm_type;
int cri_alg;
union {
struct {
char sw_key[HMAC_BLOCK_LEN];
int sw_klen;
int sw_authlen;
} hmac;
} u;
struct cipher_7108 *next;
};
#endif /* __C7108_AES_7108_H__ */

4
target/linux/generic-2.6/files/crypto/ocf/criov.c
View file

@ -1,8 +1,8 @@
/* $OpenBSD: criov.c,v 1.9 2002/01/29 15:48:29 jason Exp $ */
/*
* Linux port done by David McCullough <david_mccullough@securecomputing.com>
* Copyright (C) 2006-2007 David McCullough
* Linux port done by David McCullough <david_mccullough@mcafee.com>
* Copyright (C) 2006-2010 David McCullough
* Copyright (C) 2004-2005 Intel Corporation.
* The license and original author are listed below.
*

65
target/linux/generic-2.6/files/crypto/ocf/crypto.c
View file

@ -1,6 +1,6 @@
/*-
* Linux port done by David McCullough <david_mccullough@securecomputing.com>
* Copyright (C) 2006-2007 David McCullough
* Linux port done by David McCullough <david_mccullough@mcafee.com>
* Copyright (C) 2006-2010 David McCullough
* Copyright (C) 2004-2005 Intel Corporation.
* The license and original author are listed below.
*
@ -139,6 +139,9 @@ struct cryptocap {
#define CRYPTOCAP_F_CLEANUP 0x80000000 /* needs resource cleanup */
int cc_qblocked; /* (q) symmetric q blocked */
int cc_kqblocked; /* (q) asymmetric q blocked */
int cc_unqblocked; /* (q) symmetric q blocked */
int cc_unkqblocked; /* (q) asymmetric q blocked */
};
static struct cryptocap *crypto_drivers = NULL;
static int crypto_drivers_num = 0;
@ -207,6 +210,11 @@ static struct kmem_cache *cryptop_zone;
static struct kmem_cache *cryptodesc_zone;
#endif
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
#include <linux/sched.h>
#define kill_proc(p,s,v) send_sig(s,find_task_by_vpid(p),0)
#endif
#define debug crypto_debug
int crypto_debug = 0;
module_param(crypto_debug, int, 0644);
@ -255,6 +263,18 @@ module_param(crypto_devallowsoft, int, 0644);
MODULE_PARM_DESC(crypto_devallowsoft,
"Enable/disable use of software crypto support");
/*
* This parameter controls the maximum number of crypto operations to
* do consecutively in the crypto kernel thread before scheduling to allow
* other processes to run. Without it, it is possible to get into a
* situation where the crypto thread never allows any other processes to run.
* Default to 1000 which should be less than one second.
*/
static int crypto_max_loopcount = 1000;
module_param(crypto_max_loopcount, int, 0644);
MODULE_PARM_DESC(crypto_max_loopcount,
"Maximum number of crypto ops to do before yielding to other processes");
static pid_t cryptoproc = (pid_t) -1;
static struct completion cryptoproc_exited;
static DECLARE_WAIT_QUEUE_HEAD(cryptoproc_wait);
@ -760,10 +780,12 @@ crypto_unblock(u_int32_t driverid, int what)
if (cap != NULL) {
if (what & CRYPTO_SYMQ) {
cap->cc_qblocked = 0;
cap->cc_unqblocked = 0;
crypto_all_qblocked = 0;
}
if (what & CRYPTO_ASYMQ) {
cap->cc_kqblocked = 0;
cap->cc_unkqblocked = 0;
crypto_all_kqblocked = 0;
}
if (crp_sleep)
@ -798,6 +820,10 @@ crypto_dispatch(struct cryptop *crp)
}
crypto_q_cnt++;
/* make sure we are starting a fresh run on this crp. */
crp->crp_flags &= ~CRYPTO_F_DONE;
crp->crp_etype = 0;
/*
* Caller marked the request to be processed immediately; dispatch
* it directly to the driver unless the driver is currently blocked.
@ -809,12 +835,14 @@ crypto_dispatch(struct cryptop *crp)
KASSERT(cap != NULL, ("%s: Driver disappeared.", __func__));
if (!cap->cc_qblocked) {
crypto_all_qblocked = 0;
crypto_drivers[hid].cc_qblocked = 1;
crypto_drivers[hid].cc_unqblocked = 1;
CRYPTO_Q_UNLOCK();
result = crypto_invoke(cap, crp, 0);
CRYPTO_Q_LOCK();
if (result != ERESTART)
crypto_drivers[hid].cc_qblocked = 0;
if (result == ERESTART)
if (crypto_drivers[hid].cc_unqblocked)
crypto_drivers[hid].cc_qblocked = 1;
crypto_drivers[hid].cc_unqblocked = 0;
}
}
if (result == ERESTART) {
@ -829,13 +857,15 @@ crypto_dispatch(struct cryptop *crp)
*/
list_add(&crp->crp_next, &crp_q);
cryptostats.cs_blocks++;
result = 0;
} else if (result == -1) {
TAILQ_INSERT_TAIL(&crp_q, crp, crp_next);
result = 0;
}
if (crp_sleep)
wake_up_interruptible(&cryptoproc_wait);
CRYPTO_Q_UNLOCK();
return 0;
return result;
}
/*
@ -1246,6 +1276,7 @@ crypto_proc(void *arg)
u_int32_t hid;
int result, hint;
unsigned long q_flags;
int loopcount = 0;
ocf_daemonize("crypto");
@ -1306,7 +1337,7 @@ crypto_proc(void *arg)
hid = CRYPTO_SESID2HID(submit->crp_sid);
crypto_all_qblocked = 0;
list_del(&submit->crp_next);
crypto_drivers[hid].cc_qblocked = 1;
crypto_drivers[hid].cc_unqblocked = 1;
cap = crypto_checkdriver(hid);
CRYPTO_Q_UNLOCK();
KASSERT(cap != NULL, ("%s:%u Driver disappeared.",
@ -1326,8 +1357,11 @@ crypto_proc(void *arg)
/* XXX validate sid again? */
list_add(&submit->crp_next, &crp_q);
cryptostats.cs_blocks++;
} else
crypto_drivers[hid].cc_qblocked=0;
if (crypto_drivers[hid].cc_unqblocked)
crypto_drivers[hid].cc_qblocked=0;
crypto_drivers[hid].cc_unqblocked=0;
}
crypto_drivers[hid].cc_unqblocked = 0;
}
crypto_all_kqblocked = !list_empty(&crp_kq);
@ -1396,6 +1430,7 @@ crypto_proc(void *arg)
__FUNCTION__,
list_empty(&crp_q), crypto_all_qblocked,
list_empty(&crp_kq), crypto_all_kqblocked);
loopcount = 0;
CRYPTO_Q_UNLOCK();
crp_sleep = 1;
wait_event_interruptible(cryptoproc_wait,
@ -1417,7 +1452,15 @@ crypto_proc(void *arg)
if (cryptoproc == (pid_t) -1)
break;
cryptostats.cs_intrs++;
} else if (loopcount > crypto_max_loopcount) {
/*
* Give other processes a chance to run if we've
* been using the CPU exclusively for a while.
*/
loopcount = 0;
schedule();
}
loopcount++;
}
CRYPTO_Q_UNLOCK();
complete_and_exit(&cryptoproc_exited, 0);
@ -1599,7 +1642,7 @@ crypto_init(void)
{
int error;
dprintk("%s(0x%x)\n", __FUNCTION__, (int) crypto_init);
dprintk("%s(%p)\n", __FUNCTION__, (void *) crypto_init);
if (crypto_initted)
return 0;
@ -1737,5 +1780,5 @@ module_init(crypto_init);
module_exit(crypto_exit);
MODULE_LICENSE("BSD");
MODULE_AUTHOR("David McCullough <david_mccullough@securecomputing.com>");
MODULE_AUTHOR("David McCullough <david_mccullough@mcafee.com>");
MODULE_DESCRIPTION("OCF (OpenBSD Cryptographic Framework)");

17
target/linux/generic-2.6/files/crypto/ocf/cryptocteon/Makefile Normal file
View file

@ -0,0 +1,17 @@
# for SGlinux builds
-include $(ROOTDIR)/modules/.config
obj-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon.o
obj ?= .
EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/
ifdef CONFIG_OCF_CRYPTOCTEON
# you need the cavium crypto component installed
EXTRA_CFLAGS += -I$(ROOTDIR)/prop/include
endif
ifdef TOPDIR
-include $(TOPDIR)/Rules.make
endif

2283
target/linux/generic-2.6/files/crypto/ocf/cryptocteon/cavium_crypto.c Normal file
View file

File diff suppressed because it is too large Load diff

574
target/linux/generic-2.6/files/crypto/ocf/cryptocteon/cryptocteon.c Normal file
View file

@ -0,0 +1,574 @@
/*
* Octeon Crypto for OCF
*
* Written by David McCullough <david_mccullough@mcafee.com>
* Copyright (C) 2009-2010 David McCullough
*
* LICENSE TERMS
*
* The free distribution and use of this software in both source and binary
* form is allowed (with or without changes) provided that:
*
* 1. distributions of this source code include the above copyright
* notice, this list of conditions and the following disclaimer;
*
* 2. distributions in binary form include the above copyright
* notice, this list of conditions and the following disclaimer
* in the documentation and/or other associated materials;
*
* 3. the copyright holder's name is not used to endorse products
* built using this software without specific written permission.
*
* DISCLAIMER
*
* This software is provided 'as is' with no explicit or implied warranties
* in respect of its properties, including, but not limited to, correctness
* and/or fitness for purpose.
* ---------------------------------------------------------------------------
*/
#ifndef AUTOCONF_INCLUDED
#include <linux/config.h>
#endif
#include <linux/module.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/wait.h>
#include <linux/crypto.h>
#include <linux/mm.h>
#include <linux/skbuff.h>
#include <linux/random.h>
#include <linux/scatterlist.h>
#include <cryptodev.h>
#include <uio.h>
struct {
softc_device_decl sc_dev;
} octo_softc;
#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK)
struct octo_sess {
int octo_encalg;
#define MAX_CIPHER_KEYLEN 64
char octo_enckey[MAX_CIPHER_KEYLEN];
int octo_encklen;
int octo_macalg;
#define MAX_HASH_KEYLEN 64
char octo_mackey[MAX_HASH_KEYLEN];
int octo_macklen;
int octo_mackey_set;
int octo_mlen;
int octo_ivsize;
#if 0
int (*octo_decrypt)(struct scatterlist *sg, int sg_len,
uint8_t *key, int key_len, uint8_t * iv,
uint64_t *hminner, uint64_t *hmouter);
int (*octo_encrypt)(struct scatterlist *sg, int sg_len,
uint8_t *key, int key_len, uint8_t * iv,
uint64_t *hminner, uint64_t *hmouter);
#else
int (*octo_encrypt)(struct octo_sess *od,
struct scatterlist *sg, int sg_len,
int auth_off, int auth_len,
int crypt_off, int crypt_len,
int icv_off, uint8_t *ivp);
int (*octo_decrypt)(struct octo_sess *od,
struct scatterlist *sg, int sg_len,
int auth_off, int auth_len,
int crypt_off, int crypt_len,
int icv_off, uint8_t *ivp);
#endif
uint64_t octo_hminner[3];
uint64_t octo_hmouter[3];
};
int32_t octo_id = -1;
module_param(octo_id, int, 0444);
MODULE_PARM_DESC(octo_id, "Read-Only OCF ID for cryptocteon driver");
static struct octo_sess **octo_sessions = NULL;
static u_int32_t octo_sesnum = 0;
static int octo_process(device_t, struct cryptop *, int);
static int octo_newsession(device_t, u_int32_t *, struct cryptoini *);
static int octo_freesession(device_t, u_int64_t);
static device_method_t octo_methods = {
/* crypto device methods */
DEVMETHOD(cryptodev_newsession, octo_newsession),
DEVMETHOD(cryptodev_freesession,octo_freesession),
DEVMETHOD(cryptodev_process, octo_process),
};
#define debug octo_debug
int octo_debug = 0;
module_param(octo_debug, int, 0644);
MODULE_PARM_DESC(octo_debug, "Enable debug");
#include "cavium_crypto.c"
/*
* Generate a new octo session. We artifically limit it to a single
* hash/cipher or hash-cipher combo just to make it easier, most callers
* do not expect more than this anyway.
*/
static int
octo_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri)
{
struct cryptoini *c, *encini = NULL, *macini = NULL;
struct octo_sess **ocd;
int i;
dprintk("%s()\n", __FUNCTION__);
if (sid == NULL || cri == NULL) {
dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__);
return EINVAL;
}
/*
* To keep it simple, we only handle hash, cipher or hash/cipher in a
* session, you cannot currently do multiple ciphers/hashes in one
* session even though it would be possibel to code this driver to
* handle it.
*/
for (i = 0, c = cri; c && i < 2; i++) {
if (c->cri_alg == CRYPTO_MD5_HMAC ||
c->cri_alg == CRYPTO_SHA1_HMAC ||
c->cri_alg == CRYPTO_NULL_HMAC) {
if (macini) {
break;
}
macini = c;
}
if (c->cri_alg == CRYPTO_DES_CBC ||
c->cri_alg == CRYPTO_3DES_CBC ||
c->cri_alg == CRYPTO_AES_CBC ||
c->cri_alg == CRYPTO_NULL_CBC) {
if (encini) {
break;
}
encini = c;
}
c = c->cri_next;
}
if (!macini && !encini) {
dprintk("%s,%d - EINVAL bad cipher/hash or combination\n",
__FILE__, __LINE__);
return EINVAL;
}
if (c) {
dprintk("%s,%d - EINVAL cannot handle chained cipher/hash combos\n",
__FILE__, __LINE__);
return EINVAL;
}
/*
* So we have something we can do, lets setup the session
*/
if (octo_sessions) {
for (i = 1; i < octo_sesnum; i++)
if (octo_sessions[i] == NULL)
break;
} else
i = 1; /* NB: to silence compiler warning */
if (octo_sessions == NULL || i == octo_sesnum) {
if (octo_sessions == NULL) {
i = 1; /* We leave octo_sessions[0] empty */
octo_sesnum = CRYPTO_SW_SESSIONS;
} else
octo_sesnum *= 2;
ocd = kmalloc(octo_sesnum * sizeof(struct octo_sess *), SLAB_ATOMIC);
if (ocd == NULL) {
/* Reset session number */
if (octo_sesnum == CRYPTO_SW_SESSIONS)
octo_sesnum = 0;
else
octo_sesnum /= 2;
dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__);
return ENOBUFS;
}
memset(ocd, 0, octo_sesnum * sizeof(struct octo_sess *));
/* Copy existing sessions */
if (octo_sessions) {
memcpy(ocd, octo_sessions,
(octo_sesnum / 2) * sizeof(struct octo_sess *));
kfree(octo_sessions);
}
octo_sessions = ocd;
}
ocd = &octo_sessions[i];
*sid = i;
*ocd = (struct octo_sess *) kmalloc(sizeof(struct octo_sess), SLAB_ATOMIC);
if (*ocd == NULL) {
octo_freesession(NULL, i);
dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__);
return ENOBUFS;
}
memset(*ocd, 0, sizeof(struct octo_sess));
if (encini && encini->cri_key) {
(*ocd)->octo_encklen = (encini->cri_klen + 7) / 8;
memcpy((*ocd)->octo_enckey, encini->cri_key, (*ocd)->octo_encklen);
}
if (macini && macini->cri_key) {
(*ocd)->octo_macklen = (macini->cri_klen + 7) / 8;
memcpy((*ocd)->octo_mackey, macini->cri_key, (*ocd)->octo_macklen);
}
(*ocd)->octo_mlen = 0;
if (encini && encini->cri_mlen)
(*ocd)->octo_mlen = encini->cri_mlen;
else if (macini && macini->cri_mlen)
(*ocd)->octo_mlen = macini->cri_mlen;
else
(*ocd)->octo_mlen = 12;
/*
* point c at the enc if it exists, otherwise the mac
*/
c = encini ? encini : macini;
switch (c->cri_alg) {
case CRYPTO_DES_CBC:
case CRYPTO_3DES_CBC:
(*ocd)->octo_ivsize = 8;
switch (macini ? macini->cri_alg : -1) {
case CRYPTO_MD5_HMAC:
(*ocd)->octo_encrypt = octo_des_cbc_md5_encrypt;
(*ocd)->octo_decrypt = octo_des_cbc_md5_decrypt;
octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner,
(*ocd)->octo_hmouter);
break;
case CRYPTO_SHA1_HMAC:
(*ocd)->octo_encrypt = octo_des_cbc_sha1_encrypt;
(*ocd)->octo_decrypt = octo_des_cbc_sha1_encrypt;
octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner,
(*ocd)->octo_hmouter);
break;
case -1:
(*ocd)->octo_encrypt = octo_des_cbc_encrypt;
(*ocd)->octo_decrypt = octo_des_cbc_decrypt;
break;
default:
octo_freesession(NULL, i);
dprintk("%s,%d: EINVALn", __FILE__, __LINE__);
return EINVAL;
}
break;
case CRYPTO_AES_CBC:
(*ocd)->octo_ivsize = 16;
switch (macini ? macini->cri_alg : -1) {
case CRYPTO_MD5_HMAC:
(*ocd)->octo_encrypt = octo_aes_cbc_md5_encrypt;
(*ocd)->octo_decrypt = octo_aes_cbc_md5_decrypt;
octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner,
(*ocd)->octo_hmouter);
break;
case CRYPTO_SHA1_HMAC:
(*ocd)->octo_encrypt = octo_aes_cbc_sha1_encrypt;
(*ocd)->octo_decrypt = octo_aes_cbc_sha1_decrypt;
octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner,
(*ocd)->octo_hmouter);
break;
case -1:
(*ocd)->octo_encrypt = octo_aes_cbc_encrypt;
(*ocd)->octo_decrypt = octo_aes_cbc_decrypt;
break;
default:
octo_freesession(NULL, i);
dprintk("%s,%d: EINVALn", __FILE__, __LINE__);
return EINVAL;
}
break;
case CRYPTO_MD5_HMAC:
(*ocd)->octo_encrypt = octo_null_md5_encrypt;
(*ocd)->octo_decrypt = octo_null_md5_encrypt;
octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner,
(*ocd)->octo_hmouter);
break;
case CRYPTO_SHA1_HMAC:
(*ocd)->octo_encrypt = octo_null_sha1_encrypt;
(*ocd)->octo_decrypt = octo_null_sha1_encrypt;
octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner,
(*ocd)->octo_hmouter);
break;
default:
octo_freesession(NULL, i);
dprintk("%s,%d: EINVALn", __FILE__, __LINE__);
return EINVAL;
}
(*ocd)->octo_encalg = encini ? encini->cri_alg : -1;
(*ocd)->octo_macalg = macini ? macini->cri_alg : -1;
return 0;
}
/*
* Free a session.
*/
static int
octo_freesession(device_t dev, u_int64_t tid)
{
u_int32_t sid = CRYPTO_SESID2LID(tid);
dprintk("%s()\n", __FUNCTION__);
if (sid > octo_sesnum || octo_sessions == NULL ||
octo_sessions[sid] == NULL) {
dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__);
return(EINVAL);
}
/* Silently accept and return */
if (sid == 0)
return(0);
if (octo_sessions[sid])
kfree(octo_sessions[sid]);
octo_sessions[sid] = NULL;
return 0;
}
/*
* Process a request.
*/
static int
octo_process(device_t dev, struct cryptop *crp, int hint)
{
struct cryptodesc *crd;
struct octo_sess *od;
u_int32_t lid;
#define SCATTERLIST_MAX 16
struct scatterlist sg[SCATTERLIST_MAX];
int sg_num, sg_len;
struct sk_buff *skb = NULL;
struct uio *uiop = NULL;
struct cryptodesc *enccrd = NULL, *maccrd = NULL;
unsigned char *ivp = NULL;
unsigned char iv_data[HASH_MAX_LEN];
int auth_off = 0, auth_len = 0, crypt_off = 0, crypt_len = 0, icv_off = 0;
dprintk("%s()\n", __FUNCTION__);
/* Sanity check */
if (crp == NULL) {
dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__);
return EINVAL;
}
crp->crp_etype = 0;
if (crp->crp_desc == NULL || crp->crp_buf == NULL) {
dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__);
crp->crp_etype = EINVAL;
goto done;
}
lid = crp->crp_sid & 0xffffffff;
if (lid >= octo_sesnum || lid == 0 || octo_sessions == NULL ||
octo_sessions[lid] == NULL) {
crp->crp_etype = ENOENT;
dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__);
goto done;
}
od = octo_sessions[lid];
/*
* do some error checking outside of the loop for SKB and IOV processing
* this leaves us with valid skb or uiop pointers for later
*/
if (crp->crp_flags & CRYPTO_F_SKBUF) {
skb = (struct sk_buff *) crp->crp_buf;
if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) {
printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__,
skb_shinfo(skb)->nr_frags);
goto done;
}
} else if (crp->crp_flags & CRYPTO_F_IOV) {
uiop = (struct uio *) crp->crp_buf;
if (uiop->uio_iovcnt > SCATTERLIST_MAX) {
printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__,
uiop->uio_iovcnt);
goto done;
}
}
/* point our enccrd and maccrd appropriately */
crd = crp->crp_desc;
if (crd->crd_alg == od->octo_encalg) enccrd = crd;
if (crd->crd_alg == od->octo_macalg) maccrd = crd;
crd = crd->crd_next;
if (crd) {
if (crd->crd_alg == od->octo_encalg) enccrd = crd;
if (crd->crd_alg == od->octo_macalg) maccrd = crd;
crd = crd->crd_next;
}
if (crd) {
crp->crp_etype = EINVAL;
dprintk("%s,%d: ENOENT - descriptors do not match session\n",
__FILE__, __LINE__);
goto done;
}
if (enccrd) {
if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) {
ivp = enccrd->crd_iv;
} else {
ivp = iv_data;
crypto_copydata(crp->crp_flags, crp->crp_buf,
enccrd->crd_inject, od->octo_ivsize, (caddr_t) ivp);
}
if (maccrd) {
auth_off = maccrd->crd_skip;
auth_len = maccrd->crd_len;
icv_off = maccrd->crd_inject;
}
crypt_off = enccrd->crd_skip;
crypt_len = enccrd->crd_len;
} else { /* if (maccrd) */
auth_off = maccrd->crd_skip;
auth_len = maccrd->crd_len;
icv_off = maccrd->crd_inject;
}
/*
* setup the SG list to cover the buffer
*/
memset(sg, 0, sizeof(sg));
if (crp->crp_flags & CRYPTO_F_SKBUF) {
int i, len;
sg_num = 0;
sg_len = 0;
len = skb_headlen(skb);
sg_set_page(&sg[sg_num], virt_to_page(skb->data), len,
offset_in_page(skb->data));
sg_len += len;
sg_num++;
for (i = 0; i < skb_shinfo(skb)->nr_frags && sg_num < SCATTERLIST_MAX;
i++) {
len = skb_shinfo(skb)->frags[i].size;
sg_set_page(&sg[sg_num], skb_shinfo(skb)->frags[i].page,
len, skb_shinfo(skb)->frags[i].page_offset);
sg_len += len;
sg_num++;
}
} else if (crp->crp_flags & CRYPTO_F_IOV) {
int len;
sg_len = 0;
for (sg_num = 0; sg_len < crp->crp_ilen &&
sg_num < uiop->uio_iovcnt &&
sg_num < SCATTERLIST_MAX; sg_num++) {
len = uiop->uio_iov[sg_num].iov_len;
sg_set_page(&sg[sg_num],
virt_to_page(uiop->uio_iov[sg_num].iov_base), len,
offset_in_page(uiop->uio_iov[sg_num].iov_base));
sg_len += len;
}
} else {
sg_len = crp->crp_ilen;
sg_set_page(&sg[0], virt_to_page(crp->crp_buf), sg_len,
offset_in_page(crp->crp_buf));
sg_num = 1;
}
/*
* setup a new explicit key
*/
if (enccrd) {
if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
od->octo_encklen = (enccrd->crd_klen + 7) / 8;
memcpy(od->octo_enckey, enccrd->crd_key, od->octo_encklen);
}
}
if (maccrd) {
if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
od->octo_macklen = (maccrd->crd_klen + 7) / 8;
memcpy(od->octo_mackey, maccrd->crd_key, od->octo_macklen);
od->octo_mackey_set = 0;
}
if (!od->octo_mackey_set) {
octo_calc_hash(maccrd->crd_alg == CRYPTO_MD5_HMAC ? 0 : 1,
maccrd->crd_key, od->octo_hminner, od->octo_hmouter);
od->octo_mackey_set = 1;
}
}
if (!enccrd || (enccrd->crd_flags & CRD_F_ENCRYPT))
(*od->octo_encrypt)(od, sg, sg_len,
auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp);
else
(*od->octo_decrypt)(od, sg, sg_len,
auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp);
done:
crypto_done(crp);
return 0;
}
static int
cryptocteon_init(void)
{
dprintk("%s(%p)\n", __FUNCTION__, cryptocteon_init);
softc_device_init(&octo_softc, "cryptocteon", 0, octo_methods);
octo_id = crypto_get_driverid(softc_get_device(&octo_softc),
CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SYNC);
if (octo_id < 0) {
printk("Cryptocteon device cannot initialize!");
return -ENODEV;
}
crypto_register(octo_id, CRYPTO_MD5_HMAC, 0,0);
crypto_register(octo_id, CRYPTO_SHA1_HMAC, 0,0);
//crypto_register(octo_id, CRYPTO_MD5, 0,0);
//crypto_register(octo_id, CRYPTO_SHA1, 0,0);
crypto_register(octo_id, CRYPTO_DES_CBC, 0,0);
crypto_register(octo_id, CRYPTO_3DES_CBC, 0,0);
crypto_register(octo_id, CRYPTO_AES_CBC, 0,0);
return(0);
}
static void
cryptocteon_exit(void)
{
dprintk("%s()\n", __FUNCTION__);
crypto_unregister_all(octo_id);
octo_id = -1;
}
module_init(cryptocteon_init);
module_exit(cryptocteon_exit);
MODULE_LICENSE("BSD");
MODULE_AUTHOR("David McCullough <david_mccullough@mcafee.com>");
MODULE_DESCRIPTION("Cryptocteon (OCF module for Cavium OCTEON crypto)");

93
target/linux/generic-2.6/files/crypto/ocf/cryptodev.c
View file

@ -1,8 +1,8 @@
/* $OpenBSD: cryptodev.c,v 1.52 2002/06/19 07:22:46 deraadt Exp $ */
/*-
* Linux port done by David McCullough <david_mccullough@securecomputing.com>
* Copyright (C) 2006-2007 David McCullough
* Linux port done by David McCullough <david_mccullough@mcafee.com>
* Copyright (C) 2006-2010 David McCullough
* Copyright (C) 2004-2005 Intel Corporation.
* The license and original author are listed below.
*
@ -77,6 +77,7 @@ struct csession_info {
u_int16_t keysize;
/* u_int16_t hashsize; */
u_int16_t authsize;
u_int16_t authkey;
/* u_int16_t ctxsize; */
};
@ -197,7 +198,7 @@ cryptodev_op(struct csession *cse, struct crypt_op *cop)
if (cse->uio.uio_iov[0].iov_base == NULL) {
dprintk("%s: iov_base kmalloc(%d) failed\n", __FUNCTION__,
cse->uio.uio_iov[0].iov_len);
(int)cse->uio.uio_iov[0].iov_len);
return (ENOMEM);
}
@ -208,18 +209,22 @@ cryptodev_op(struct csession *cse, struct crypt_op *cop)
goto bail;
}
if (cse->info.authsize) {
crda = crp->crp_desc;
if (cse->info.blocksize)
crde = crda->crd_next;
} else {
if (cse->info.blocksize)
if (cse->info.authsize && cse->info.blocksize) {
if (cop->op == COP_ENCRYPT) {
crde = crp->crp_desc;
else {
dprintk("%s: bad request\n", __FUNCTION__);
error = EINVAL;
goto bail;
crda = crde->crd_next;
} else {
crda = crp->crp_desc;
crde = crda->crd_next;
}
} else if (cse->info.authsize) {
crda = crp->crp_desc;
} else if (cse->info.blocksize) {
crde = crp->crp_desc;
} else {
dprintk("%s: bad request\n", __FUNCTION__);
error = EINVAL;
goto bail;
}
if ((error = copy_from_user(cse->uio.uio_iov[0].iov_base, cop->src,
@ -300,29 +305,32 @@ cryptodev_op(struct csession *cse, struct crypt_op *cop)
* entry and the crypto_done callback into us.
*/
error = crypto_dispatch(crp);
if (error == 0) {
dprintk("%s about to WAIT\n", __FUNCTION__);
/*
* we really need to wait for driver to complete to maintain
* state, luckily interrupts will be remembered
*/
do {
error = wait_event_interruptible(crp->crp_waitq,
((crp->crp_flags & CRYPTO_F_DONE) != 0));
/*
* we can't break out of this loop or we will leave behind
* a huge mess, however, staying here means if your driver
* is broken user applications can hang and not be killed.
* The solution, fix your driver :-)
*/
if (error) {
schedule();
error = 0;
}
} while ((crp->crp_flags & CRYPTO_F_DONE) == 0);
dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error);
if (error) {
dprintk("%s error in crypto_dispatch\n", __FUNCTION__);
goto bail;
}
dprintk("%s about to WAIT\n", __FUNCTION__);
/*
* we really need to wait for driver to complete to maintain
* state, luckily interrupts will be remembered
*/
do {
error = wait_event_interruptible(crp->crp_waitq,
((crp->crp_flags & CRYPTO_F_DONE) != 0));
/*
* we can't break out of this loop or we will leave behind
* a huge mess, however, staying here means if your driver
* is broken user applications can hang and not be killed.
* The solution, fix your driver :-)
*/
if (error) {
schedule();
error = 0;
}
} while ((crp->crp_flags & CRYPTO_F_DONE) == 0);
dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error);
if (crp->crp_etype != 0) {
error = crp->crp_etype;
dprintk("%s error in crp processing\n", __FUNCTION__);
@ -625,7 +633,7 @@ cryptodev_ioctl(
struct crypt_kop kop;
struct crypt_find_op fop;
u_int64_t sid;
u_int32_t ses;
u_int32_t ses = 0;
int feat, fd, error = 0, crid;
mm_segment_t fs;
@ -744,21 +752,27 @@ cryptodev_ioctl(
break;
case CRYPTO_MD5_HMAC:
info.authsize = MD5_HASH_LEN;
info.authkey = 16;
break;
case CRYPTO_SHA1_HMAC:
info.authsize = SHA1_HASH_LEN;
info.authkey = 20;
break;
case CRYPTO_SHA2_256_HMAC:
info.authsize = SHA2_256_HASH_LEN;
info.authkey = 32;
break;
case CRYPTO_SHA2_384_HMAC:
info.authsize = SHA2_384_HASH_LEN;
info.authkey = 48;
break;
case CRYPTO_SHA2_512_HMAC:
info.authsize = SHA2_512_HASH_LEN;
info.authkey = 64;
break;
case CRYPTO_RIPEMD160_HMAC:
info.authsize = RIPEMD160_HASH_LEN;
info.authkey = 20;
break;
default:
dprintk("%s(%s) - bad mac\n", __FUNCTION__, CIOCGSESSSTR);
@ -790,10 +804,9 @@ cryptodev_ioctl(
if (info.authsize) {
cria.cri_alg = sop.mac;
cria.cri_klen = sop.mackeylen * 8;
if ((info.maxkey && sop.mackeylen > info.maxkey) ||
sop.keylen < info.minkey) {
dprintk("%s(%s) - mackeylen %d\n", __FUNCTION__, CIOCGSESSSTR,
sop.mackeylen);
if (info.authkey && sop.mackeylen != info.authkey) {
dprintk("%s(%s) - mackeylen %d != %d\n", __FUNCTION__,
CIOCGSESSSTR, sop.mackeylen, info.authkey);
error = EINVAL;
goto bail;
}
@ -1044,5 +1057,5 @@ module_init(cryptodev_init);
module_exit(cryptodev_exit);
MODULE_LICENSE("BSD");
MODULE_AUTHOR("David McCullough <david_mccullough@securecomputing.com>");
MODULE_AUTHOR("David McCullough <david_mccullough@mcafee.com>");
MODULE_DESCRIPTION("Cryptodev (user interface to OCF)");

5
target/linux/generic-2.6/files/crypto/ocf/cryptodev.h
View file

@ -2,8 +2,8 @@
/* $OpenBSD: cryptodev.h,v 1.31 2002/06/11 11:14:29 beck Exp $ */
/*-
* Linux port done by David McCullough <david_mccullough@securecomputing.com>
* Copyright (C) 2006-2007 David McCullough
* Linux port done by David McCullough <david_mccullough@mcafee.com>
* Copyright (C) 2006-2010 David McCullough
* Copyright (C) 2004-2005 Intel Corporation.
* The license and original author are listed below.
*
@ -336,6 +336,7 @@ struct cryptodesc {
#define crd_key CRD_INI.cri_key
#define crd_alg CRD_INI.cri_alg
#define crd_klen CRD_INI.cri_klen
#define crd_mlen CRD_INI.cri_mlen
struct cryptodesc *crd_next;
};

1202
target/linux/generic-2.6/files/crypto/ocf/cryptosoft.c
View file

File diff suppressed because it is too large Load diff

38
target/linux/generic-2.6/files/crypto/ocf/ep80579/Makefile
View file

@ -13,7 +13,7 @@
#
# GPL LICENSE SUMMARY
#
# Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of version 2 of the GNU General Public License as
@ -35,7 +35,7 @@
#
# BSD LICENSE
#
# Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@ -65,43 +65,55 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#
# version: Security.L.1.0.130
# version: Security.L.1.0.2-229
############################################################################
####################Common variables and definitions########################
ifndef ICP_ROOT
$(warning ICP_ROOT is undefined. Please set the path to EP80579 release package directory \
"-> setenv ICP_ROOT <path>")
all fastdep:
:
else
ifndef KERNEL_SOURCE_ROOT
$(error KERNEL_SOURCE_ROOT is undefined. Please set the path to the kernel source directory \
"-> setenv KERNEL_SOURCE_ROOT <path>")
endif
# Ensure The ENV_DIR environmental var is defined.
ifndef ICP_ENV_DIR
$(error ICP_ENV_DIR is undefined. Please set the path to your environment makefile \
$(error ICP_ENV_DIR is undefined. Please set the path to EP80579 driver environment.mk file \
"-> setenv ICP_ENV_DIR <path>")
endif
#Add your project environment Makefile
include $(ICP_ENV_DIR)/environment.mk
include ${ICP_ENV_DIR}/environment.mk
#include the makefile with all the default and common Make variable definitions
include $(ICP_BUILDSYSTEM_PATH)/build_files/common.mk
include ${ICP_BUILDSYSTEM_PATH}/build_files/common.mk
#Add the name for the executable, Library or Module output definitions
OUTPUT_NAME= icp_ocf
# List of Source Files to be compiled
SOURCES= icp_common.c icp_sym.c icp_asym.c
SOURCES= icp_common.c icp_sym.c icp_asym.c icp_ocf_linux.c
#common includes between all supported OSes
INCLUDES= -I $(ICP_API_DIR) -I$(ICP_LAC_API) \
-I$(ICP_OCF_SRC_DIR)
INCLUDES= -I ${ICP_API_DIR} -I${ICP_LAC_API} \
-I${ICP_OCF_SRC_DIR}
# The location of the os level makefile needs to be changed.
include $(ICP_ENV_DIR)/$(ICP_OS)_$(ICP_OS_LEVEL).mk
include ${ICP_ENV_DIR}/${ICP_OS}_${ICP_OS_LEVEL}.mk
# On the line directly below list the outputs you wish to build for,
# e.g "lib_static lib_shared exe module" as show below
# e.g "lib_static lib_shared exe module" as shown below
install: module
###################Include rules makefiles########################
include $(ICP_BUILDSYSTEM_PATH)/build_files/rules.mk
include ${ICP_BUILDSYSTEM_PATH}/build_files/rules.mk
###################End of Rules inclusion#########################
endif

75
target/linux/generic-2.6/files/crypto/ocf/ep80579/environment.mk
View file

@ -1,75 +0,0 @@
###########################################################################
#
# This file is provided under a dual BSD/GPLv2 license. When using or
# redistributing this file, you may do so under either license.
#
# GPL LICENSE SUMMARY
#
# Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of version 2 of the GNU General Public License as
# published by the Free Software Foundation.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
# The full GNU General Public License is included in this distribution
# in the file called LICENSE.GPL.
#
# Contact Information:
# Intel Corporation
#
# BSD LICENSE
#
# Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# * Neither the name of Intel Corporation nor the names of its
# contributors may be used to endorse or promote products derived
# from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#
# version: Security.L.1.0.130
#
###########################################################################
ICP_LAC_API=$(ICP_ROOT)/Acceleration/include/lac
ICP_BTR_API=$(ICP_ROOT)/Acceleration/include/btr
ICP_API_DIR=$(ICP_ROOT)/Acceleration/include
ICP_OCF_SHIM_DIR?=$(KERNEL_SOURCE_ROOT)/crypto/ocf/
ICP_OS_LEVEL?=kernel_space
ICP_OS?=linux_2.6
ICP_CORE?=ia

305
target/linux/generic-2.6/files/crypto/ocf/ep80579/icp_asym.c
View file

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
* Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -27,7 +27,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
* Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -57,7 +57,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
* version: Security.L.1.0.130
* version: Security.L.1.0.2-229
*
***************************************************************************/
@ -70,90 +70,94 @@ calling program uses different input buffer positions, these defines will have
to be changed.*/
/*DIFFIE HELLMAN buffer index values*/
#define ICP_DH_KRP_PARAM_PRIME_INDEX (0)
#define ICP_DH_KRP_PARAM_BASE_INDEX (1)
#define ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX (2)
#define ICP_DH_KRP_PARAM_RESULT_INDEX (3)
#define ICP_DH_KRP_PARAM_PRIME_INDEX (0)
#define ICP_DH_KRP_PARAM_BASE_INDEX (1)
#define ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX (2)
#define ICP_DH_KRP_PARAM_RESULT_INDEX (3)
/*MOD EXP buffer index values*/
#define ICP_MOD_EXP_KRP_PARAM_BASE_INDEX (0)
#define ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX (1)
#define ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX (2)
#define ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX (3)
#define SINGLE_BYTE_VALUE (4)
#define ICP_MOD_EXP_KRP_PARAM_BASE_INDEX (0)
#define ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX (1)
#define ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX (2)
#define ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX (3)
/*MOD EXP CRT buffer index values*/
#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX (0)
#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX (1)
#define ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX (2)
#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX (3)
#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX (4)
#define ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX (5)
#define ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX (6)
#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX (0)
#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX (1)
#define ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX (2)
#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX (3)
#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX (4)
#define ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX (5)
#define ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX (6)
/*DSA sign buffer index values*/
#define ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX (0)
#define ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX (1)
#define ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX (2)
#define ICP_DSA_SIGN_KRP_PARAM_G_INDEX (3)
#define ICP_DSA_SIGN_KRP_PARAM_X_INDEX (4)
#define ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX (5)
#define ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX (6)
#define ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX (0)
#define ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX (1)
#define ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX (2)
#define ICP_DSA_SIGN_KRP_PARAM_G_INDEX (3)
#define ICP_DSA_SIGN_KRP_PARAM_X_INDEX (4)
#define ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX (5)
#define ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX (6)
/*DSA verify buffer index values*/
#define ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX (0)
#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX (1)
#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX (2)
#define ICP_DSA_VERIFY_KRP_PARAM_G_INDEX (3)
#define ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX (4)
#define ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX (5)
#define ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX (6)
#define ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX (0)
#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX (1)
#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX (2)
#define ICP_DSA_VERIFY_KRP_PARAM_G_INDEX (3)
#define ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX (4)
#define ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX (5)
#define ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX (6)
/*DSA sign prime Q vs random number K size check values*/
#define DONT_RUN_LESS_THAN_CHECK (0)
#define FAIL_A_IS_GREATER_THAN_B (1)
#define FAIL_A_IS_EQUAL_TO_B (1)
#define SUCCESS_A_IS_LESS_THAN_B (0)
#define DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS (500)
#define DONT_RUN_LESS_THAN_CHECK (0)
#define FAIL_A_IS_GREATER_THAN_B (1)
#define FAIL_A_IS_EQUAL_TO_B (1)
#define SUCCESS_A_IS_LESS_THAN_B (0)
#define DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS (500)
/* We need to set a cryptokp success value just in case it is set or allocated
and not set to zero outside of this module */
#define CRYPTO_OP_SUCCESS (0)
#define CRYPTO_OP_SUCCESS (0)
/*Function to compute Diffie Hellman (DH) phase 1 or phase 2 key values*/
static int icp_ocfDrvDHComputeKey(struct cryptkop *krp);
/*Function to compute a Modular Exponentiation (Mod Exp)*/
static int icp_ocfDrvModExp(struct cryptkop *krp);
/*Function to compute a Mod Exp using the Chinease Remainder Theorem*/
static int icp_ocfDrvModExpCRT(struct cryptkop *krp);
/*Helper function to compute whether the first big number argument is less than
the second big number argument */
static int
icp_ocfDrvCheckALessThanB(CpaFlatBuffer * pK, CpaFlatBuffer * pQ, int *doCheck);
/*Function to sign an input with DSA R and S keys*/
static int icp_ocfDrvDsaSign(struct cryptkop *krp);
/*Function to Verify a DSA buffer signature*/
static int icp_ocfDrvDsaVerify(struct cryptkop *krp);
/*Callback function for DH operation*/
static void
icp_ocfDrvDhP1CallBack(void *callbackTag,
CpaStatus status,
void *pOpData, CpaFlatBuffer * pLocalOctetStringPV);
/*Callback function for ME operation*/
static void
icp_ocfDrvModExpCallBack(void *callbackTag,
CpaStatus status,
void *pOpData, CpaFlatBuffer * pResult);
/*Callback function for ME CRT operation*/
static void
icp_ocfDrvModExpCRTCallBack(void *callbackTag,
CpaStatus status,
void *pOpData, CpaFlatBuffer * pOutputData);
static void
icp_ocfDrvDsaVerifyCallBack(void *callbackTag,
CpaStatus status,
void *pOpData, CpaBoolean verifyStatus);
/*Callback function for DSA sign operation*/
static void
icp_ocfDrvDsaRSSignCallBack(void *callbackTag,
CpaStatus status,
@ -161,12 +165,18 @@ icp_ocfDrvDsaRSSignCallBack(void *callbackTag,
CpaBoolean protocolStatus,
CpaFlatBuffer * pR, CpaFlatBuffer * pS);
/*Callback function for DSA Verify operation*/
static void
icp_ocfDrvDsaVerifyCallBack(void *callbackTag,
CpaStatus status,
void *pOpData, CpaBoolean verifyStatus);
/* Name : icp_ocfDrvPkeProcess
*
* Description : This function will choose which PKE process to follow
* based on the input arguments
*/
int icp_ocfDrvPkeProcess(device_t dev, struct cryptkop *krp, int hint)
int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint)
{
CpaStatus lacStatus = CPA_STATUS_SUCCESS;
@ -176,7 +186,7 @@ int icp_ocfDrvPkeProcess(device_t dev, struct cryptkop *krp, int hint)
return EINVAL;
}
if (CPA_TRUE == atomic_read(&icp_ocfDrvIsExiting)) {
if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) {
krp->krp_status = ECANCELED;
return ECANCELED;
}
@ -258,8 +268,7 @@ int icp_ocfDrvPkeProcess(device_t dev, struct cryptkop *krp, int hint)
* It has been seen that in general we are passed little endian byte order
* buffers, but LAC only accepts big endian byte order buffers.
*/
static void inline
icp_ocfDrvSwapBytes(u_int8_t * num, u_int32_t buff_len_bytes)
static void inline icp_ocfDrvSwapBytes(u_int8_t * num, u_int32_t buff_len_bytes)
{
int i;
@ -319,7 +328,9 @@ static int icp_ocfDrvDHComputeKey(struct cryptkop *krp)
callbackTag = krp;
pPhase1OpData = kmem_cache_zalloc(drvDH_zone, GFP_KERNEL);
/*All allocations are set to ICP_M_NOWAIT due to the possibility of getting
called in interrupt context*/
pPhase1OpData = icp_kmem_cache_zalloc(drvDH_zone, ICP_M_NOWAIT);
if (NULL == pPhase1OpData) {
APRINTK("%s():Failed to get memory for key gen data\n",
__FUNCTION__);
@ -327,11 +338,12 @@ static int icp_ocfDrvDHComputeKey(struct cryptkop *krp)
return ENOMEM;
}
pLocalOctetStringPV = kmem_cache_zalloc(drvFlatBuffer_zone, GFP_KERNEL);
pLocalOctetStringPV =
icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT);
if (NULL == pLocalOctetStringPV) {
APRINTK("%s():Failed to get memory for pLocalOctetStringPV\n",
__FUNCTION__);
kmem_cache_free(drvDH_zone, pPhase1OpData);
ICP_CACHE_FREE(drvDH_zone, pPhase1OpData);
krp->krp_status = ENOMEM;
return ENOMEM;
}
@ -379,7 +391,7 @@ static int icp_ocfDrvDHComputeKey(struct cryptkop *krp)
EPRINTK("%s(): DH Phase 1 Key Gen failed (%d).\n",
__FUNCTION__, lacStatus);
icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV);
kmem_cache_free(drvDH_zone, pPhase1OpData);
ICP_CACHE_FREE(drvDH_zone, pPhase1OpData);
}
return lacStatus;
@ -418,7 +430,7 @@ static int icp_ocfDrvModExp(struct cryptkop *krp)
callbackTag = krp;
pModExpOpData = kmem_cache_zalloc(drvLnModExp_zone, GFP_KERNEL);
pModExpOpData = icp_kmem_cache_zalloc(drvLnModExp_zone, ICP_M_NOWAIT);
if (NULL == pModExpOpData) {
APRINTK("%s():Failed to get memory for key gen data\n",
__FUNCTION__);
@ -426,11 +438,11 @@ static int icp_ocfDrvModExp(struct cryptkop *krp)
return ENOMEM;
}
pResult = kmem_cache_zalloc(drvFlatBuffer_zone, GFP_KERNEL);
pResult = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT);
if (NULL == pResult) {
APRINTK("%s():Failed to get memory for ModExp result\n",
__FUNCTION__);
kmem_cache_free(drvLnModExp_zone, pModExpOpData);
ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData);
krp->krp_status = ENOMEM;
return ENOMEM;
}
@ -445,35 +457,15 @@ static int icp_ocfDrvModExp(struct cryptkop *krp)
icp_ocfDrvSwapBytes(pModExpOpData->modulus.pData,
pModExpOpData->modulus.dataLenInBytes);
/*OCF patch to Openswan Pluto regularly sends the base value as 2
bits in size. In this case, it has been found it is better to
use the base size memory space as the input buffer (if the number
is in bits is less than a byte, the number of bits is the input
value) */
if (krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_nbits <
NUM_BITS_IN_BYTE) {
DPRINTK("%s : base is small (%d)\n", __FUNCTION__, krp->
krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_nbits);
pModExpOpData->base.dataLenInBytes = SINGLE_BYTE_VALUE;
pModExpOpData->base.pData =
(uint8_t *) & (krp->
krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].
crp_nbits);
*((uint32_t *) pModExpOpData->base.pData) =
htonl(*((uint32_t *) pModExpOpData->base.pData));
} else {
DPRINTK("%s : base is big (%d)\n", __FUNCTION__, krp->
krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_nbits);
pModExpOpData->base.pData =
krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_p;
BITS_TO_BYTES(pModExpOpData->base.dataLenInBytes,
krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].
crp_nbits);
icp_ocfDrvSwapBytes(pModExpOpData->base.pData,
pModExpOpData->base.dataLenInBytes);
}
DPRINTK("%s : base (%d)\n", __FUNCTION__, krp->
krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_nbits);
pModExpOpData->base.pData =
krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_p;
BITS_TO_BYTES(pModExpOpData->base.dataLenInBytes,
krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].
crp_nbits);
icp_ocfDrvSwapBytes(pModExpOpData->base.pData,
pModExpOpData->base.dataLenInBytes);
pModExpOpData->exponent.pData =
krp->krp_param[ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX].crp_p;
@ -499,7 +491,7 @@ static int icp_ocfDrvModExp(struct cryptkop *krp)
__FUNCTION__, lacStatus);
krp->krp_status = ECANCELED;
icp_ocfDrvFreeFlatBuffer(pResult);
kmem_cache_free(drvLnModExp_zone, pModExpOpData);
ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData);
}
return lacStatus;
@ -515,7 +507,6 @@ static int icp_ocfDrvModExp(struct cryptkop *krp)
* numbers. Although basic primality checks are done in LAC, it is up to the
* user to do any correct prime number checking before passing the inputs.
*/
static int icp_ocfDrvModExpCRT(struct cryptkop *krp)
{
CpaStatus lacStatus = CPA_STATUS_SUCCESS;
@ -527,7 +518,8 @@ static int icp_ocfDrvModExpCRT(struct cryptkop *krp)
them here. */
callbackTag = krp;
rsaDecryptOpData = kmem_cache_zalloc(drvRSADecrypt_zone, GFP_KERNEL);
rsaDecryptOpData =
icp_kmem_cache_zalloc(drvRSADecrypt_zone, ICP_M_NOWAIT);
if (NULL == rsaDecryptOpData) {
APRINTK("%s():Failed to get memory"
" for MOD EXP CRT Op data struct\n", __FUNCTION__);
@ -536,11 +528,11 @@ static int icp_ocfDrvModExpCRT(struct cryptkop *krp)
}
rsaDecryptOpData->pRecipientPrivateKey
= kmem_cache_zalloc(drvRSAPrivateKey_zone, GFP_KERNEL);
= icp_kmem_cache_zalloc(drvRSAPrivateKey_zone, ICP_M_NOWAIT);
if (NULL == rsaDecryptOpData->pRecipientPrivateKey) {
APRINTK("%s():Failed to get memory for MOD EXP CRT"
" private key values struct\n", __FUNCTION__);
kmem_cache_free(drvRSADecrypt_zone, rsaDecryptOpData);
ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData);
krp->krp_status = ENOMEM;
return ENOMEM;
}
@ -550,13 +542,13 @@ static int icp_ocfDrvModExpCRT(struct cryptkop *krp)
rsaDecryptOpData->pRecipientPrivateKey->
privateKeyRepType = CPA_CY_RSA_PRIVATE_KEY_REP_TYPE_2;
pOutputData = kmem_cache_zalloc(drvFlatBuffer_zone, GFP_KERNEL);
pOutputData = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT);
if (NULL == pOutputData) {
APRINTK("%s():Failed to get memory"
" for MOD EXP CRT output data\n", __FUNCTION__);
kmem_cache_free(drvRSAPrivateKey_zone,
rsaDecryptOpData->pRecipientPrivateKey);
kmem_cache_free(drvRSADecrypt_zone, rsaDecryptOpData);
ICP_CACHE_FREE(drvRSAPrivateKey_zone,
rsaDecryptOpData->pRecipientPrivateKey);
ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData);
krp->krp_status = ENOMEM;
return ENOMEM;
}
@ -658,9 +650,9 @@ static int icp_ocfDrvModExpCRT(struct cryptkop *krp)
__FUNCTION__, lacStatus);
krp->krp_status = ECANCELED;
icp_ocfDrvFreeFlatBuffer(pOutputData);
kmem_cache_free(drvRSAPrivateKey_zone,
rsaDecryptOpData->pRecipientPrivateKey);
kmem_cache_free(drvRSADecrypt_zone, rsaDecryptOpData);
ICP_CACHE_FREE(drvRSAPrivateKey_zone,
rsaDecryptOpData->pRecipientPrivateKey);
ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData);
}
return lacStatus;
@ -747,7 +739,8 @@ static int icp_ocfDrvDsaSign(struct cryptkop *krp)
return EDOM;
}
dsaRsSignOpData = kmem_cache_zalloc(drvDSARSSign_zone, GFP_KERNEL);
dsaRsSignOpData =
icp_kmem_cache_zalloc(drvDSARSSign_zone, ICP_M_NOWAIT);
if (NULL == dsaRsSignOpData) {
APRINTK("%s():Failed to get memory"
" for DSA RS Sign Op data struct\n", __FUNCTION__);
@ -756,35 +749,35 @@ static int icp_ocfDrvDsaSign(struct cryptkop *krp)
}
dsaRsSignOpData->K.pData =
kmem_cache_alloc(drvDSARSSignKValue_zone, GFP_ATOMIC);
icp_kmem_cache_alloc(drvDSARSSignKValue_zone, ICP_M_NOWAIT);
if (NULL == dsaRsSignOpData->K.pData) {
APRINTK("%s():Failed to get memory"
" for DSA RS Sign Op Random value\n", __FUNCTION__);
kmem_cache_free(drvDSARSSign_zone, dsaRsSignOpData);
ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData);
krp->krp_status = ENOMEM;
return ENOMEM;
}
pR = kmem_cache_zalloc(drvFlatBuffer_zone, GFP_KERNEL);
pR = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT);
if (NULL == pR) {
APRINTK("%s():Failed to get memory"
" for DSA signature R\n", __FUNCTION__);
kmem_cache_free(drvDSARSSignKValue_zone,
dsaRsSignOpData->K.pData);
kmem_cache_free(drvDSARSSign_zone, dsaRsSignOpData);
ICP_CACHE_FREE(drvDSARSSignKValue_zone,
dsaRsSignOpData->K.pData);
ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData);
krp->krp_status = ENOMEM;
return ENOMEM;
}
pS = kmem_cache_zalloc(drvFlatBuffer_zone, GFP_KERNEL);
pS = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT);
if (NULL == pS) {
APRINTK("%s():Failed to get memory"
" for DSA signature S\n", __FUNCTION__);
icp_ocfDrvFreeFlatBuffer(pR);
kmem_cache_free(drvDSARSSignKValue_zone,
dsaRsSignOpData->K.pData);
kmem_cache_free(drvDSARSSign_zone, dsaRsSignOpData);
ICP_CACHE_FREE(drvDSARSSignKValue_zone,
dsaRsSignOpData->K.pData);
ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData);
krp->krp_status = ENOMEM;
return ENOMEM;
}
@ -830,9 +823,9 @@ static int icp_ocfDrvDsaSign(struct cryptkop *krp)
"value\n", __FUNCTION__);
icp_ocfDrvFreeFlatBuffer(pS);
icp_ocfDrvFreeFlatBuffer(pR);
kmem_cache_free(drvDSARSSignKValue_zone,
dsaRsSignOpData->K.pData);
kmem_cache_free(drvDSARSSign_zone, dsaRsSignOpData);
ICP_CACHE_FREE(drvDSARSSignKValue_zone,
dsaRsSignOpData->K.pData);
ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData);
krp->krp_status = EAGAIN;
return EAGAIN;
}
@ -843,9 +836,9 @@ static int icp_ocfDrvDsaSign(struct cryptkop *krp)
"value less than Q value\n", __FUNCTION__);
icp_ocfDrvFreeFlatBuffer(pS);
icp_ocfDrvFreeFlatBuffer(pR);
kmem_cache_free(drvDSARSSignKValue_zone,
dsaRsSignOpData->K.pData);
kmem_cache_free(drvDSARSSign_zone, dsaRsSignOpData);
ICP_CACHE_FREE(drvDSARSSignKValue_zone,
dsaRsSignOpData->K.pData);
ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData);
krp->krp_status = EAGAIN;
return EAGAIN;
}
@ -869,13 +862,13 @@ static int icp_ocfDrvDsaSign(struct cryptkop *krp)
icp_ocfDrvSwapBytes(dsaRsSignOpData->X.pData,
dsaRsSignOpData->X.dataLenInBytes);
/*OpenSSL dgst parameter is left in big endian byte order,
therefore no byte swap is required */
dsaRsSignOpData->M.pData =
krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX].crp_p;
BITS_TO_BYTES(dsaRsSignOpData->M.dataLenInBytes,
krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX].
crp_nbits);
icp_ocfDrvSwapBytes(dsaRsSignOpData->M.pData,
dsaRsSignOpData->M.dataLenInBytes);
/* Output Parameters */
pS->pData = krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX].crp_p;
@ -899,9 +892,9 @@ static int icp_ocfDrvDsaSign(struct cryptkop *krp)
krp->krp_status = ECANCELED;
icp_ocfDrvFreeFlatBuffer(pS);
icp_ocfDrvFreeFlatBuffer(pR);
kmem_cache_free(drvDSARSSignKValue_zone,
dsaRsSignOpData->K.pData);
kmem_cache_free(drvDSARSSign_zone, dsaRsSignOpData);
ICP_CACHE_FREE(drvDSARSSignKValue_zone,
dsaRsSignOpData->K.pData);
ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData);
}
return lacStatus;
@ -921,7 +914,8 @@ static int icp_ocfDrvDsaVerify(struct cryptkop *krp)
callbackTag = krp;
dsaVerifyOpData = kmem_cache_zalloc(drvDSAVerify_zone, GFP_KERNEL);
dsaVerifyOpData =
icp_kmem_cache_zalloc(drvDSAVerify_zone, ICP_M_NOWAIT);
if (NULL == dsaVerifyOpData) {
APRINTK("%s():Failed to get memory"
" for DSA Verify Op data struct\n", __FUNCTION__);
@ -962,13 +956,13 @@ static int icp_ocfDrvDsaVerify(struct cryptkop *krp)
icp_ocfDrvSwapBytes(dsaVerifyOpData->Y.pData,
dsaVerifyOpData->Y.dataLenInBytes);
/*OpenSSL dgst parameter is left in big endian byte order,
therefore no byte swap is required */
dsaVerifyOpData->M.pData =
krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX].crp_p;
BITS_TO_BYTES(dsaVerifyOpData->M.dataLenInBytes,
krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX].
crp_nbits);
icp_ocfDrvSwapBytes(dsaVerifyOpData->M.pData,
dsaVerifyOpData->M.dataLenInBytes);
dsaVerifyOpData->R.pData =
krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX].crp_p;
@ -993,48 +987,13 @@ static int icp_ocfDrvDsaVerify(struct cryptkop *krp)
if (CPA_STATUS_SUCCESS != lacStatus) {
EPRINTK("%s(): DSA Verify Operation failed (%d).\n",
__FUNCTION__, lacStatus);
kmem_cache_free(drvDSAVerify_zone, dsaVerifyOpData);
ICP_CACHE_FREE(drvDSAVerify_zone, dsaVerifyOpData);
krp->krp_status = ECANCELED;
}
return lacStatus;
}
/* Name : icp_ocfDrvReadRandom
*
* Description : This function will map RNG functionality calls from OCF
* to the LAC API.
*/
int icp_ocfDrvReadRandom(void *arg, uint32_t * buf, int maxwords)
{
CpaStatus lacStatus = CPA_STATUS_SUCCESS;
CpaCyRandGenOpData randGenOpData;
CpaFlatBuffer randData;
if (NULL == buf) {
APRINTK("%s(): Invalid input parameters\n", __FUNCTION__);
return EINVAL;
}
/* maxwords here is number of integers to generate data for */
randGenOpData.generateBits = CPA_TRUE;
randGenOpData.lenInBytes = maxwords * sizeof(uint32_t);
icp_ocfDrvPtrAndLenToFlatBuffer((Cpa8U *) buf,
randGenOpData.lenInBytes, &randData);
lacStatus = cpaCyRandGen(CPA_INSTANCE_HANDLE_SINGLE,
NULL, NULL, &randGenOpData, &randData);
if (CPA_STATUS_SUCCESS != lacStatus) {
EPRINTK("%s(): icp_LacSymRandGen failed (%d). \n",
__FUNCTION__, lacStatus);
return RETURN_RAND_NUM_GEN_FAILED;
}
return randGenOpData.lenInBytes / sizeof(uint32_t);
}
/* Name : icp_ocfDrvDhP1Callback
*
* Description : When this function returns it signifies that the LAC
@ -1068,7 +1027,7 @@ icp_ocfDrvDhP1CallBack(void *callbackTag,
DPRINTK("%s(): Invalid input parameters - "
"pLocalOctetStringPV Data is NULL\n", __FUNCTION__);
memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData));
kmem_cache_free(drvDH_zone, pPhase1OpData);
ICP_CACHE_FREE(drvDH_zone, pPhase1OpData);
krp->krp_status = ECANCELED;
crypto_kdone(krp);
return;
@ -1087,7 +1046,7 @@ icp_ocfDrvDhP1CallBack(void *callbackTag,
icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV);
memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData));
kmem_cache_free(drvDH_zone, pPhase1OpData);
ICP_CACHE_FREE(drvDH_zone, pPhase1OpData);
crypto_kdone(krp);
@ -1128,7 +1087,7 @@ icp_ocfDrvModExpCallBack(void *callbackTag,
"pResult data is NULL\n", __FUNCTION__);
krp->krp_status = ECANCELED;
memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData));
kmem_cache_free(drvLnModExp_zone, pLnModExpOpData);
ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData);
crypto_kdone(krp);
return;
}
@ -1153,7 +1112,7 @@ icp_ocfDrvModExpCallBack(void *callbackTag,
}
icp_ocfDrvFreeFlatBuffer(pResult);
memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData));
kmem_cache_free(drvLnModExp_zone, pLnModExpOpData);
ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData);
crypto_kdone(krp);
@ -1196,10 +1155,10 @@ icp_ocfDrvModExpCRTCallBack(void *callbackTag,
"pOutputData is NULL\n", __FUNCTION__);
memset(pDecryptData->pRecipientPrivateKey, 0,
sizeof(CpaCyRsaPrivateKey));
kmem_cache_free(drvRSAPrivateKey_zone,
pDecryptData->pRecipientPrivateKey);
ICP_CACHE_FREE(drvRSAPrivateKey_zone,
pDecryptData->pRecipientPrivateKey);
memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData));
kmem_cache_free(drvRSADecrypt_zone, pDecryptData);
ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData);
krp->krp_status = ECANCELED;
crypto_kdone(krp);
return;
@ -1218,10 +1177,10 @@ icp_ocfDrvModExpCRTCallBack(void *callbackTag,
icp_ocfDrvFreeFlatBuffer(pOutputData);
memset(pDecryptData->pRecipientPrivateKey, 0,
sizeof(CpaCyRsaPrivateKey));
kmem_cache_free(drvRSAPrivateKey_zone,
pDecryptData->pRecipientPrivateKey);
ICP_CACHE_FREE(drvRSAPrivateKey_zone,
pDecryptData->pRecipientPrivateKey);
memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData));
kmem_cache_free(drvRSADecrypt_zone, pDecryptData);
ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData);
crypto_kdone(krp);
@ -1264,7 +1223,7 @@ icp_ocfDrvDsaRSSignCallBack(void *callbackTag,
DPRINTK("%s(): Invalid input parameter - "
"pR sign is NULL\n", __FUNCTION__);
icp_ocfDrvFreeFlatBuffer(pS);
kmem_cache_free(drvDSARSSign_zone, pSignData);
ICP_CACHE_FREE(drvDSARSSign_zone, pSignData);
krp->krp_status = ECANCELED;
crypto_kdone(krp);
return;
@ -1274,7 +1233,7 @@ icp_ocfDrvDsaRSSignCallBack(void *callbackTag,
DPRINTK("%s(): Invalid input parameter - "
"pS sign is NULL\n", __FUNCTION__);
icp_ocfDrvFreeFlatBuffer(pR);
kmem_cache_free(drvDSARSSign_zone, pSignData);
ICP_CACHE_FREE(drvDSARSSign_zone, pSignData);
krp->krp_status = ECANCELED;
crypto_kdone(krp);
return;
@ -1304,9 +1263,9 @@ icp_ocfDrvDsaRSSignCallBack(void *callbackTag,
icp_ocfDrvFreeFlatBuffer(pR);
icp_ocfDrvFreeFlatBuffer(pS);
memset(pSignData->K.pData, 0, pSignData->K.dataLenInBytes);
kmem_cache_free(drvDSARSSignKValue_zone, pSignData->K.pData);
ICP_CACHE_FREE(drvDSARSSignKValue_zone, pSignData->K.pData);
memset(pSignData, 0, sizeof(CpaCyDsaRSSignOpData));
kmem_cache_free(drvDSARSSign_zone, pSignData);
ICP_CACHE_FREE(drvDSARSSign_zone, pSignData);
crypto_kdone(krp);
return;
@ -1368,7 +1327,7 @@ icp_ocfDrvDsaVerifyCallBack(void *callbackTag,
}
memset(pVerData, 0, sizeof(CpaCyDsaVerifyOpData));
kmem_cache_free(drvDSAVerify_zone, pVerData);
ICP_CACHE_FREE(drvDSAVerify_zone, pVerData);
crypto_kdone(krp);
return;

576
target/linux/generic-2.6/files/crypto/ocf/ep80579/icp_common.c
View file

@ -1,11 +1,11 @@
/***************************************************************************
/*************************************************************************
*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
* Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -27,7 +27,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
* Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -57,7 +57,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
* version: Security.L.1.0.130
* version: Security.L.1.0.2-229
*
***************************************************************************/
@ -71,38 +71,57 @@
#include "icp_ocf.h"
#define ICP_OCF_COMP_NAME "ICP_OCF"
#define ICP_OCF_VER_MAIN (2)
#define ICP_OCF_VER_MJR (0)
#define ICP_OCF_VER_MNR (0)
#define ICP_OCF_COMP_NAME "ICP_OCF"
#define ICP_OCF_VER_MAIN (2)
#define ICP_OCF_VER_MJR (1)
#define ICP_OCF_VER_MNR (0)
#define MAX_DEREG_RETRIES (100)
#define MAX_DEREG_RETRIES (100)
#define DEFAULT_DEREG_RETRIES (10)
#define DEFAULT_DEREG_DELAY_IN_JIFFIES (10)
/* This defines the maximum number of sessions possible between OCF
and the OCF Tolapai Driver. If set to zero, there is no limit. */
#define DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT (0)
#define NUM_SUPPORTED_CAPABILITIES (21)
and the OCF EP80579 Driver. If set to zero, there is no limit. */
#define DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT (0)
#define NUM_SUPPORTED_CAPABILITIES (21)
/*Slab zone names*/
#define ICP_SESSION_DATA_NAME "icp_ocf.SesDat"
#define ICP_OP_DATA_NAME "icp_ocf.OpDat"
#define ICP_DH_NAME "icp_ocf.DH"
#define ICP_MODEXP_NAME "icp_ocf.ModExp"
#define ICP_RSA_DECRYPT_NAME "icp_ocf.RSAdec"
#define ICP_RSA_PKEY_NAME "icp_ocf.RSApk"
#define ICP_DSA_SIGN_NAME "icp_ocf.DSAsg"
#define ICP_DSA_VER_NAME "icp_ocf.DSAver"
#define ICP_RAND_VAL_NAME "icp_ocf.DSArnd"
#define ICP_FLAT_BUFF_NAME "icp_ocf.FB"
/*Slabs zones*/
struct kmem_cache *drvSessionData_zone = NULL;
struct kmem_cache *drvOpData_zone = NULL;
struct kmem_cache *drvDH_zone = NULL;
struct kmem_cache *drvLnModExp_zone = NULL;
struct kmem_cache *drvRSADecrypt_zone = NULL;
struct kmem_cache *drvRSAPrivateKey_zone = NULL;
struct kmem_cache *drvDSARSSign_zone = NULL;
struct kmem_cache *drvDSARSSignKValue_zone = NULL;
struct kmem_cache *drvDSAVerify_zone = NULL;
icp_kmem_cache drvSessionData_zone = NULL;
icp_kmem_cache drvOpData_zone = NULL;
icp_kmem_cache drvDH_zone = NULL;
icp_kmem_cache drvLnModExp_zone = NULL;
icp_kmem_cache drvRSADecrypt_zone = NULL;
icp_kmem_cache drvRSAPrivateKey_zone = NULL;
icp_kmem_cache drvDSARSSign_zone = NULL;
icp_kmem_cache drvDSARSSignKValue_zone = NULL;
icp_kmem_cache drvDSAVerify_zone = NULL;
/*Slab zones for flatbuffers and bufferlist*/
struct kmem_cache *drvFlatBuffer_zone = NULL;
icp_kmem_cache drvFlatBuffer_zone = NULL;
static int icp_ocfDrvInit(void);
static void icp_ocfDrvExit(void);
static inline int icp_cache_null_check(void)
{
return (drvSessionData_zone && drvOpData_zone
&& drvDH_zone && drvLnModExp_zone && drvRSADecrypt_zone
&& drvRSAPrivateKey_zone && drvDSARSSign_zone
&& drvDSARSSign_zone && drvDSARSSignKValue_zone
&& drvDSAVerify_zone && drvFlatBuffer_zone);
}
/*Function to free all allocated slab caches before exiting the module*/
static void icp_ocfDrvFreeCaches(void);
static void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg);
int32_t icp_ocfDrvDriverId = INVALID_DRIVER_ID;
@ -115,66 +134,42 @@ int num_dereg_retries = DEFAULT_DEREG_RETRIES;
int dereg_retry_delay_in_jiffies = DEFAULT_DEREG_DELAY_IN_JIFFIES;
/* Module parameter - gives the maximum number of sessions possible between
OCF and the OCF Tolapai Driver. If set to zero, there is no limit.*/
OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/
int max_sessions = DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT;
/* This is set when the module is removed from the system, no further
processing can take place if this is set */
atomic_t icp_ocfDrvIsExiting = ATOMIC_INIT(0);
icp_atomic_t icp_ocfDrvIsExiting = ICP_ATOMIC_INIT(0);
/* This is used to show how many lac sessions were not deregistered*/
atomic_t lac_session_failed_dereg_count = ATOMIC_INIT(0);
icp_atomic_t lac_session_failed_dereg_count = ICP_ATOMIC_INIT(0);
/* This is used to track the number of registered sessions between OCF and
* and the OCF Tolapai driver, when max_session is set to value other than
* and the OCF EP80579 driver, when max_session is set to value other than
* zero. This ensures that the max_session set for the OCF and the driver
* is equal to the LAC registered sessions */
atomic_t num_ocf_to_drv_registered_sessions = ATOMIC_INIT(0);
icp_atomic_t num_ocf_to_drv_registered_sessions = ICP_ATOMIC_INIT(0);
/* Head of linked list used to store session data */
struct list_head icp_ocfDrvGlobalSymListHead;
struct list_head icp_ocfDrvGlobalSymListHead_FreeMemList;
icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead;
icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList;
spinlock_t icp_ocfDrvSymSessInfoListSpinlock = SPIN_LOCK_UNLOCKED;
rwlock_t icp_kmem_cache_destroy_alloc_lock = RW_LOCK_UNLOCKED;
icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock;
struct workqueue_struct *icp_ocfDrvFreeLacSessionWorkQ;
/*Below pointer is only used in linux, FreeBSD uses the name to
create its own variable name*/
icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ = NULL;
ICP_WORKQUEUE_DEFINE_THREAD(icp_ocfDrvFreeLacSessionWorkQ);
struct icp_drvBuffListInfo defBuffListInfo;
static struct {
softc_device_decl sc_dev;
} icpDev;
static device_method_t icp_methods = {
/* crypto device methods */
DEVMETHOD(cryptodev_newsession, icp_ocfDrvNewSession),
DEVMETHOD(cryptodev_freesession, icp_ocfDrvFreeLACSession),
DEVMETHOD(cryptodev_process, icp_ocfDrvSymProcess),
DEVMETHOD(cryptodev_kprocess, icp_ocfDrvPkeProcess),
};
module_param(num_dereg_retries, int, S_IRUGO);
module_param(dereg_retry_delay_in_jiffies, int, S_IRUGO);
module_param(max_sessions, int, S_IRUGO);
MODULE_PARM_DESC(num_dereg_retries,
"Number of times to retry LAC Sym Session Deregistration. "
"Default 10, Max 100");
MODULE_PARM_DESC(dereg_retry_delay_in_jiffies, "Delay in jiffies "
"(added to a schedule() function call) before a LAC Sym "
"Session Dereg is retried. Default 10");
MODULE_PARM_DESC(max_sessions, "This sets the maximum number of sessions "
"between OCF and this driver. If this value is set to zero, "
"max session count checking is disabled. Default is zero(0)");
/* Name : icp_ocfDrvInit
*
* Description : This function will register all the symmetric and asymmetric
* functionality that will be accelerated by the hardware. It will also
* get a unique driver ID from the OCF and initialise all slab caches
*/
static int __init icp_ocfDrvInit(void)
ICP_MODULE_INIT_FUNC(icp_ocfDrvInit)
{
int ocfStatus = 0;
@ -184,7 +179,7 @@ static int __init icp_ocfDrvInit(void)
if (MAX_DEREG_RETRIES < num_dereg_retries) {
EPRINTK("Session deregistration retry count set to greater "
"than %d", MAX_DEREG_RETRIES);
return -1;
icp_module_return_code(EINVAL);
}
/* Initialize and Start the Cryptographic component */
@ -192,130 +187,133 @@ static int __init icp_ocfDrvInit(void)
cpaCyStartInstance(CPA_INSTANCE_HANDLE_SINGLE)) {
EPRINTK("Failed to initialize and start the instance "
"of the Cryptographic component.\n");
return -1;
return icp_module_return_code(EINVAL);
}
icp_spin_lock_init(&icp_ocfDrvSymSessInfoListSpinlock);
/* Set the default size of BufferList to allocate */
memset(&defBuffListInfo, 0, sizeof(struct icp_drvBuffListInfo));
if (ICP_OCF_DRV_STATUS_SUCCESS !=
icp_ocfDrvBufferListMemInfo(ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS,
&defBuffListInfo)) {
EPRINTK("Failed to get bufferlist memory info.\n");
return -1;
return icp_module_return_code(ENOMEM);
}
/*Register OCF Tolapai Driver with OCF */
memset(&icpDev, 0, sizeof(icpDev));
softc_device_init(&icpDev, "icp", 0, icp_methods);
icp_ocfDrvDriverId = crypto_get_driverid(softc_get_device(&icpDev),
CRYPTOCAP_F_HARDWARE);
/*Register OCF EP80579 Driver with OCF */
icp_ocfDrvDriverId = ICP_CRYPTO_GET_DRIVERID();
if (icp_ocfDrvDriverId < 0) {
EPRINTK("%s : ICP driver failed to register with OCF!\n",
__FUNCTION__);
return -ENODEV;
return icp_module_return_code(ENODEV);
}
/*Create all the slab caches used by the OCF Tolapai Driver */
/*Create all the slab caches used by the OCF EP80579 Driver */
drvSessionData_zone =
ICP_CACHE_CREATE("ICP Session Data", struct icp_drvSessionData);
ICP_CACHE_NULL_CHECK(drvSessionData_zone);
ICP_CACHE_CREATE(ICP_SESSION_DATA_NAME, struct icp_drvSessionData);
/*
* Allocation of the OpData includes the allocation space for meta data.
* The memory after the opData structure is reserved for this meta data.
*/
drvOpData_zone =
kmem_cache_create("ICP Op Data", sizeof(struct icp_drvOpData) +
defBuffListInfo.metaSize ,0, SLAB_HWCACHE_ALIGN, NULL, NULL);
icp_kmem_cache_create(ICP_OP_DATA_NAME,
sizeof(struct icp_drvOpData) +
defBuffListInfo.metaSize,
ICP_KERNEL_CACHE_ALIGN,
ICP_KERNEL_CACHE_NOINIT);
ICP_CACHE_NULL_CHECK(drvOpData_zone);
drvDH_zone = ICP_CACHE_CREATE("ICP DH data", CpaCyDhPhase1KeyGenOpData);
ICP_CACHE_NULL_CHECK(drvDH_zone);
drvDH_zone = ICP_CACHE_CREATE(ICP_DH_NAME, CpaCyDhPhase1KeyGenOpData);
drvLnModExp_zone =
ICP_CACHE_CREATE("ICP ModExp data", CpaCyLnModExpOpData);
ICP_CACHE_NULL_CHECK(drvLnModExp_zone);
ICP_CACHE_CREATE(ICP_MODEXP_NAME, CpaCyLnModExpOpData);
drvRSADecrypt_zone =
ICP_CACHE_CREATE("ICP RSA decrypt data", CpaCyRsaDecryptOpData);
ICP_CACHE_NULL_CHECK(drvRSADecrypt_zone);
ICP_CACHE_CREATE(ICP_RSA_DECRYPT_NAME, CpaCyRsaDecryptOpData);
drvRSAPrivateKey_zone =
ICP_CACHE_CREATE("ICP RSA private key data", CpaCyRsaPrivateKey);
ICP_CACHE_NULL_CHECK(drvRSAPrivateKey_zone);
ICP_CACHE_CREATE(ICP_RSA_PKEY_NAME, CpaCyRsaPrivateKey);
drvDSARSSign_zone =
ICP_CACHE_CREATE("ICP DSA Sign", CpaCyDsaRSSignOpData);
ICP_CACHE_NULL_CHECK(drvDSARSSign_zone);
ICP_CACHE_CREATE(ICP_DSA_SIGN_NAME, CpaCyDsaRSSignOpData);
/*too awkward to use a macro here */
drvDSARSSignKValue_zone =
kmem_cache_create("ICP DSA Sign Rand Val",
DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES, 0,
SLAB_HWCACHE_ALIGN, NULL, NULL);
ICP_CACHE_NULL_CHECK(drvDSARSSignKValue_zone);
ICP_CACHE_CREATE(ICP_RAND_VAL_NAME,
DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES);
drvDSAVerify_zone =
ICP_CACHE_CREATE("ICP DSA Verify", CpaCyDsaVerifyOpData);
ICP_CACHE_NULL_CHECK(drvDSAVerify_zone);
ICP_CACHE_CREATE(ICP_DSA_VER_NAME, CpaCyDsaVerifyOpData);
drvFlatBuffer_zone =
ICP_CACHE_CREATE("ICP Flat Buffers", CpaFlatBuffer);
ICP_CACHE_NULL_CHECK(drvFlatBuffer_zone);
ICP_CACHE_CREATE(ICP_FLAT_BUFF_NAME, CpaFlatBuffer);
if (0 == icp_cache_null_check()) {
icp_ocfDrvFreeCaches();
EPRINTK("%s() line %d: Not enough memory!\n",
__FUNCTION__, __LINE__);
return ENOMEM;
}
/* Register the ICP symmetric crypto support. */
ICP_REGISTER_SYM_FUNCTIONALITY_WITH_OCF(CRYPTO_NULL_CBC);
ICP_REGISTER_SYM_FUNCTIONALITY_WITH_OCF(CRYPTO_DES_CBC);
ICP_REGISTER_SYM_FUNCTIONALITY_WITH_OCF(CRYPTO_3DES_CBC);
ICP_REGISTER_SYM_FUNCTIONALITY_WITH_OCF(CRYPTO_AES_CBC);
ICP_REGISTER_SYM_FUNCTIONALITY_WITH_OCF(CRYPTO_ARC4);
ICP_REGISTER_SYM_FUNCTIONALITY_WITH_OCF(CRYPTO_MD5);
ICP_REGISTER_SYM_FUNCTIONALITY_WITH_OCF(CRYPTO_MD5_HMAC);
ICP_REGISTER_SYM_FUNCTIONALITY_WITH_OCF(CRYPTO_SHA1);
ICP_REGISTER_SYM_FUNCTIONALITY_WITH_OCF(CRYPTO_SHA1_HMAC);
ICP_REGISTER_SYM_FUNCTIONALITY_WITH_OCF(CRYPTO_SHA2_256);
ICP_REGISTER_SYM_FUNCTIONALITY_WITH_OCF(CRYPTO_SHA2_256_HMAC);
ICP_REGISTER_SYM_FUNCTIONALITY_WITH_OCF(CRYPTO_SHA2_384);
ICP_REGISTER_SYM_FUNCTIONALITY_WITH_OCF(CRYPTO_SHA2_384_HMAC);
ICP_REGISTER_SYM_FUNCTIONALITY_WITH_OCF(CRYPTO_SHA2_512);
ICP_REGISTER_SYM_FUNCTIONALITY_WITH_OCF(CRYPTO_SHA2_512_HMAC);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_NULL_CBC, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_DES_CBC, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_3DES_CBC, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_AES_CBC, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_ARC4, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5_HMAC, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1_HMAC, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256_HMAC,
ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384_HMAC,
ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512_HMAC,
ocfStatus);
/* Register the ICP asymmetric algorithm support */
ICP_REGISTER_ASYM_FUNCTIONALITY_WITH_OCF(CRK_DH_COMPUTE_KEY);
ICP_REGISTER_ASYM_FUNCTIONALITY_WITH_OCF(CRK_MOD_EXP);
ICP_REGISTER_ASYM_FUNCTIONALITY_WITH_OCF(CRK_MOD_EXP_CRT);
ICP_REGISTER_ASYM_FUNCTIONALITY_WITH_OCF(CRK_DSA_SIGN);
ICP_REGISTER_ASYM_FUNCTIONALITY_WITH_OCF(CRK_DSA_VERIFY);
ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DH_COMPUTE_KEY,
ocfStatus);
ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP, ocfStatus);
ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP_CRT, ocfStatus);
ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_SIGN, ocfStatus);
ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_VERIFY, ocfStatus);
/* Register the ICP random number generator support */
if (OCF_REGISTRATION_STATUS_SUCCESS ==
crypto_rregister(icp_ocfDrvDriverId, icp_ocfDrvReadRandom, NULL)) {
ocfStatus++;
}
ICP_REG_RAND_WITH_OCF(icp_ocfDrvDriverId,
icp_ocfDrvReadRandom, NULL, ocfStatus);
if (OCF_ZERO_FUNCTIONALITY_REGISTERED == ocfStatus) {
DPRINTK("%s: Failed to register any device capabilities\n",
__FUNCTION__);
icp_ocfDrvFreeCaches();
icp_ocfDrvDriverId = INVALID_DRIVER_ID;
return -ECANCELED;
return icp_module_return_code(ECANCELED);
}
DPRINTK("%s: Registered %d of %d device capabilities\n",
__FUNCTION__, ocfStatus, NUM_SUPPORTED_CAPABILITIES);
/*Session data linked list used during module exit*/
INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead);
INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead_FreeMemList);
/*Session data linked list used during module exit */
ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead);
ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead_FreeMemList);
icp_ocfDrvFreeLacSessionWorkQ =
create_singlethread_workqueue("ocfLacDeregWorkQueue");
ICP_WORKQUEUE_CREATE(icp_ocfDrvFreeLacSessionWorkQ, "icpwq");
if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) {
EPRINTK("%s: Failed to create single "
"thread workqueue\n", __FUNCTION__);
icp_ocfDrvFreeCaches();
icp_ocfDrvDriverId = INVALID_DRIVER_ID;
return icp_module_return_code(ENOMEM);
}
return 0;
return icp_module_return_code(0);
}
/* Name : icp_ocfDrvExit
@ -325,31 +323,46 @@ static int __init icp_ocfDrvInit(void)
* and asymmetric functionality that can be accelerated by the hardware via OCF
* and random number generation if it is enabled.
*/
static void icp_ocfDrvExit(void)
ICP_MODULE_EXIT_FUNC(icp_ocfDrvExit)
{
CpaStatus lacStatus = CPA_STATUS_SUCCESS;
struct icp_drvSessionData *sessionData = NULL;
struct icp_drvSessionData *tempSessionData = NULL;
int i, remaining_delay_time_in_jiffies = 0;
/* For FreeBSD the invariant macro below makes function to return */
/* with EBUSY value in the case of any session which has been regi- */
/* stered with LAC not being deregistered. */
/* The Linux implementation is empty since it is purely to compensate */
/* for a limitation of the FreeBSD 7.1 Opencrypto framework. */
ICP_MODULE_EXIT_INV();
/* There is a possibility of a process or new session command being */
/* sent before this variable is incremented. The aim of this variable */
/* is to stop a loop of calls creating a deadlock situation which */
/* would prevent the driver from exiting. */
atomic_inc(&icp_ocfDrvIsExiting);
icp_atomic_set(&icp_ocfDrvIsExiting, 1);
/*Existing sessions will be routed to another driver after these calls */
crypto_unregister_all(icp_ocfDrvDriverId);
crypto_runregister_all(icp_ocfDrvDriverId);
if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) {
DPRINTK("%s: workqueue already "
"destroyed, therefore module exit "
" function already called. Exiting.\n", __FUNCTION__);
return ICP_MODULE_EXIT_FUNC_RETURN_VAL;
}
/*If any sessions are waiting to be deregistered, do that. This also
flushes the work queue */
destroy_workqueue(icp_ocfDrvFreeLacSessionWorkQ);
ICP_WORKQUEUE_DESTROY(icp_ocfDrvFreeLacSessionWorkQ);
/*ENTER CRITICAL SECTION */
spin_lock_bh(&icp_ocfDrvSymSessInfoListSpinlock);
list_for_each_entry_safe(tempSessionData, sessionData,
&icp_ocfDrvGlobalSymListHead, listNode) {
icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock);
ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData,
&icp_ocfDrvGlobalSymListHead, listNode) {
for (i = 0; i < num_dereg_retries; i++) {
/*No harm if bad input - LAC will handle error cases */
if (ICP_SESSION_RUNNING == tempSessionData->inUse) {
@ -361,7 +374,7 @@ static void icp_ocfDrvExit(void)
/* Succesfully deregistered */
break;
} else if (CPA_STATUS_RETRY != lacStatus) {
atomic_inc
icp_atomic_inc
(&lac_session_failed_dereg_count);
break;
}
@ -372,8 +385,9 @@ static void icp_ocfDrvExit(void)
dereg_retry_delay_in_jiffies;
while (0 > remaining_delay_time_in_jiffies) {
remaining_delay_time_in_jiffies =
schedule_timeout
(remaining_delay_time_in_jiffies);
icp_schedule_timeout
(&icp_ocfDrvSymSessInfoListSpinlock,
remaining_delay_time_in_jiffies);
}
DPRINTK
@ -383,44 +397,48 @@ static void icp_ocfDrvExit(void)
}
/*remove from current list */
list_del(&(tempSessionData->listNode));
ICP_LIST_DEL(tempSessionData, listNode);
/*add to free mem linked list */
list_add(&(tempSessionData->listNode),
&icp_ocfDrvGlobalSymListHead_FreeMemList);
ICP_LIST_ADD(tempSessionData,
&icp_ocfDrvGlobalSymListHead_FreeMemList,
listNode);
}
/*EXIT CRITICAL SECTION */
spin_unlock_bh(&icp_ocfDrvSymSessInfoListSpinlock);
icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock);
/*set back to initial values */
sessionData = NULL;
/*still have a reference in our list! */
tempSessionData = NULL;
/*free memory */
list_for_each_entry_safe(tempSessionData, sessionData,
&icp_ocfDrvGlobalSymListHead_FreeMemList,
listNode) {
list_del(&(tempSessionData->listNode));
ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData,
&icp_ocfDrvGlobalSymListHead_FreeMemList,
listNode) {
ICP_LIST_DEL(tempSessionData, listNode);
/* Free allocated CpaCySymSessionCtx */
if (NULL != tempSessionData->sessHandle) {
kfree(tempSessionData->sessHandle);
icp_kfree(tempSessionData->sessHandle);
}
memset(tempSessionData, 0, sizeof(struct icp_drvSessionData));
kmem_cache_free(drvSessionData_zone, tempSessionData);
ICP_CACHE_FREE(drvSessionData_zone, tempSessionData);
}
if (0 != atomic_read(&lac_session_failed_dereg_count)) {
if (0 != icp_atomic_read(&lac_session_failed_dereg_count)) {
DPRINTK("%s(): %d LAC sessions were not deregistered "
"correctly. This is not a clean exit! \n",
__FUNCTION__,
atomic_read(&lac_session_failed_dereg_count));
icp_atomic_read(&lac_session_failed_dereg_count));
}
icp_ocfDrvFreeCaches();
icp_ocfDrvDriverId = INVALID_DRIVER_ID;
icp_spin_lock_destroy(&icp_ocfDrvSymSessInfoListSpinlock);
/* Shutdown the Cryptographic component */
lacStatus = cpaCyStopInstance(CPA_INSTANCE_HANDLE_SINGLE);
if (CPA_STATUS_SUCCESS != lacStatus) {
@ -429,6 +447,7 @@ static void icp_ocfDrvExit(void)
__FUNCTION__, lacStatus);
}
return ICP_MODULE_EXIT_FUNC_RETURN_VAL;
}
/* Name : icp_ocfDrvFreeCaches
@ -437,9 +456,7 @@ static void icp_ocfDrvExit(void)
*/
static void icp_ocfDrvFreeCaches(void)
{
if (atomic_read(&icp_ocfDrvIsExiting) != CPA_TRUE) {
atomic_set(&icp_ocfDrvIsExiting, 1);
}
icp_atomic_set(&icp_ocfDrvIsExiting, 1);
/*Sym Zones */
ICP_CACHE_DESTROY(drvSessionData_zone);
@ -465,7 +482,6 @@ static void icp_ocfDrvFreeCaches(void)
* off to a work queue. If it fails, nothing more can be done and it
* returns an error
*/
int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister)
{
struct icp_ocfDrvFreeLacSession *workstore = NULL;
@ -475,11 +491,11 @@ int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister)
/*make sure the session is not available to be allocated during this
process */
atomic_inc(&lac_session_failed_dereg_count);
icp_atomic_inc(&lac_session_failed_dereg_count);
/*Farm off to work queue */
workstore =
kmalloc(sizeof(struct icp_ocfDrvFreeLacSession), GFP_ATOMIC);
icp_kmalloc(sizeof(struct icp_ocfDrvFreeLacSession), ICP_M_NOWAIT);
if (NULL == workstore) {
DPRINTK("%s(): unable to free session - no memory available "
"for work queue\n", __FUNCTION__);
@ -488,9 +504,11 @@ int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister)
workstore->sessionToDeregister = sessionToDeregister;
INIT_WORK(&(workstore->work), icp_ocfDrvDeferedFreeLacSessionProcess,
workstore);
queue_work(icp_ocfDrvFreeLacSessionWorkQ, &(workstore->work));
icp_init_work(&(workstore->work),
icp_ocfDrvDeferedFreeLacSessionTaskFn, workstore);
ICP_WORKQUEUE_ENQUEUE(icp_ocfDrvFreeLacSessionWorkQ,
&(workstore->work));
return ICP_OCF_DRV_STATUS_SUCCESS;
@ -503,7 +521,7 @@ int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister)
* CPA_STATUS_RETRY message from the LAC component. This function is run in
* Thread context because it is called from a worker thread
*/
static void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg)
void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg)
{
struct icp_ocfDrvFreeLacSession *workstore = NULL;
CpaCySymSessionCtx sessionToDeregister = NULL;
@ -519,10 +537,10 @@ static void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg)
}
sessionToDeregister = workstore->sessionToDeregister;
kfree(workstore);
icp_kfree(workstore);
/*if exiting, give deregistration one more blast only */
if (atomic_read(&icp_ocfDrvIsExiting) == CPA_TRUE) {
if (icp_atomic_read(&icp_ocfDrvIsExiting) == CPA_TRUE) {
lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE,
sessionToDeregister);
@ -533,7 +551,7 @@ static void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg)
return;
}
atomic_dec(&lac_session_failed_dereg_count);
icp_atomic_dec(&lac_session_failed_dereg_count);
return;
}
@ -542,7 +560,7 @@ static void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg)
sessionToDeregister);
if (lacStatus == CPA_STATUS_SUCCESS) {
atomic_dec(&lac_session_failed_dereg_count);
icp_atomic_dec(&lac_session_failed_dereg_count);
return;
}
if (lacStatus != CPA_STATUS_RETRY) {
@ -554,16 +572,17 @@ static void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg)
/*schedule_timout returns the time left for completion if this
task is set to TASK_INTERRUPTIBLE */
remaining_delay_time_in_jiffies = dereg_retry_delay_in_jiffies;
while (0 > remaining_delay_time_in_jiffies) {
while (0 < remaining_delay_time_in_jiffies) {
remaining_delay_time_in_jiffies =
schedule_timeout(remaining_delay_time_in_jiffies);
icp_schedule_timeout(NULL,
remaining_delay_time_in_jiffies);
}
}
DPRINTK("%s(): Unable to deregister session\n", __FUNCTION__);
DPRINTK("%s(): Number of unavailable LAC sessions = %d\n", __FUNCTION__,
atomic_read(&lac_session_failed_dereg_count));
icp_atomic_read(&lac_session_failed_dereg_count));
}
/* Name : icp_ocfDrvPtrAndLenToFlatBuffer
@ -581,131 +600,6 @@ icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len,
pFlatBuffer->dataLenInBytes = len;
}
/* Name : icp_ocfDrvSingleSkBuffToFlatBuffer
*
* Description : This function converts a single socket buffer (sk_buff)
* structure to a Fredericksburg Flat Buffer (CpaFlatBuffer) format.
*
* This function assumes that the data passed in are valid.
*/
static inline void
icp_ocfDrvSingleSkBuffToFlatBuffer(struct sk_buff *pSkb,
CpaFlatBuffer * pFlatBuffer)
{
pFlatBuffer->pData = pSkb->data;
pFlatBuffer->dataLenInBytes = skb_headlen(pSkb);
}
/* Name : icp_ocfDrvSkBuffToBufferList
*
* Description : This function converts a socket buffer (sk_buff) structure to
* Fredericksburg Scatter/Gather (CpaBufferList) buffer format.
*
* This function assumes that the bufferlist has been allocated with the correct
* number of buffer arrays.
*
*/
inline int
icp_ocfDrvSkBuffToBufferList(struct sk_buff *pSkb, CpaBufferList * bufferList)
{
CpaFlatBuffer *curFlatBuffer = NULL;
char *skbuffPageAddr = NULL;
struct sk_buff *pCurFrag = NULL;
struct skb_shared_info *pShInfo = NULL;
uint32_t page_offset = 0, i = 0;
DPRINTK("%s(): Entry Point\n", __FUNCTION__);
/*
* In all cases, the first skb needs to be translated to FlatBuffer.
* Perform a buffer translation for the first skbuff
*/
curFlatBuffer = bufferList->pBuffers;
icp_ocfDrvSingleSkBuffToFlatBuffer(pSkb, curFlatBuffer);
/* Set the userData to point to the original sk_buff */
bufferList->pUserData = (void *)pSkb;
/* We now know we'll have at least one element in the SGL */
bufferList->numBuffers = 1;
if (0 == skb_is_nonlinear(pSkb)) {
/* Is a linear buffer - therefore it's a single skbuff */
DPRINTK("%s(): Exit Point\n", __FUNCTION__);
return ICP_OCF_DRV_STATUS_SUCCESS;
}
curFlatBuffer++;
pShInfo = skb_shinfo(pSkb);
if (pShInfo->frag_list != NULL && pShInfo->nr_frags != 0) {
EPRINTK("%s():"
"Translation for a combination of frag_list "
"and frags[] array not supported!\n", __FUNCTION__);
return ICP_OCF_DRV_STATUS_FAIL;
} else if (pShInfo->frag_list != NULL) {
/*
* Non linear skbuff supported through frag_list
* Perform translation for each fragment (sk_buff)
* in the frag_list of the first sk_buff.
*/
for (pCurFrag = pShInfo->frag_list;
pCurFrag != NULL; pCurFrag = pCurFrag->next) {
icp_ocfDrvSingleSkBuffToFlatBuffer(pCurFrag,
curFlatBuffer);
curFlatBuffer++;
bufferList->numBuffers++;
}
} else if (pShInfo->nr_frags != 0) {
/*
* Perform translation for each fragment in frags array
* and add to the BufferList
*/
for (i = 0; i < pShInfo->nr_frags; i++) {
/* Get the page address and offset of this frag */
skbuffPageAddr = (char *)pShInfo->frags[i].page;
page_offset = pShInfo->frags[i].page_offset;
/* Convert a pointer and length to a flat buffer */
icp_ocfDrvPtrAndLenToFlatBuffer(skbuffPageAddr +
page_offset,
pShInfo->frags[i].size,
curFlatBuffer);
curFlatBuffer++;
bufferList->numBuffers++;
}
} else {
EPRINTK("%s():" "Could not recognize skbuff fragments!\n",
__FUNCTION__);
return ICP_OCF_DRV_STATUS_FAIL;
}
DPRINTK("%s(): Exit Point\n", __FUNCTION__);
return ICP_OCF_DRV_STATUS_SUCCESS;
}
/* Name : icp_ocfDrvBufferListToSkBuff
*
* Description : This function converts a Fredericksburg Scatter/Gather
* (CpaBufferList) buffer format to socket buffer structure.
*/
inline int
icp_ocfDrvBufferListToSkBuff(CpaBufferList * bufferList, struct sk_buff **skb)
{
DPRINTK("%s(): Entry Point\n", __FUNCTION__);
/* Retrieve the orignal skbuff */
*skb = (struct sk_buff *)bufferList->pUserData;
if (NULL == *skb) {
EPRINTK("%s():"
"Error on converting from a BufferList. "
"The BufferList does not contain an sk_buff.\n",
__FUNCTION__);
return ICP_OCF_DRV_STATUS_FAIL;
}
DPRINTK("%s(): Exit Point\n", __FUNCTION__);
return ICP_OCF_DRV_STATUS_SUCCESS;
}
/* Name : icp_ocfDrvPtrAndLenToBufferList
*
* Description : This function converts a "pointer and length" buffer
@ -761,45 +655,6 @@ icp_ocfDrvBufferListMemInfo(uint16_t numBuffers,
return ICP_OCF_DRV_STATUS_SUCCESS;
}
/* Name : icp_ocfDrvGetSkBuffFrags
*
* Description : This function will determine the number of
* fragments in a socket buffer(sk_buff).
*/
inline uint16_t icp_ocfDrvGetSkBuffFrags(struct sk_buff * pSkb)
{
uint16_t numFrags = 0;
struct sk_buff *pCurFrag = NULL;
struct skb_shared_info *pShInfo = NULL;
if (NULL == pSkb)
return 0;
numFrags = 1;
if (0 == skb_is_nonlinear(pSkb)) {
/* Linear buffer - it's a single skbuff */
return numFrags;
}
pShInfo = skb_shinfo(pSkb);
if (NULL != pShInfo->frag_list && 0 != pShInfo->nr_frags) {
EPRINTK("%s(): Combination of frag_list "
"and frags[] array not supported!\n", __FUNCTION__);
return 0;
} else if (0 != pShInfo->nr_frags) {
numFrags += pShInfo->nr_frags;
return numFrags;
} else if (NULL != pShInfo->frag_list) {
for (pCurFrag = pShInfo->frag_list;
pCurFrag != NULL; pCurFrag = pCurFrag->next) {
numFrags++;
}
return numFrags;
} else {
return 0;
}
}
/* Name : icp_ocfDrvFreeFlatBuffer
*
* Description : This function will deallocate flat buffer.
@ -808,7 +663,7 @@ inline void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer)
{
if (pFlatBuffer != NULL) {
memset(pFlatBuffer, 0, sizeof(CpaFlatBuffer));
kmem_cache_free(drvFlatBuffer_zone, pFlatBuffer);
ICP_CACHE_FREE(drvFlatBuffer_zone, pFlatBuffer);
}
}
@ -819,14 +674,14 @@ inline void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer)
*/
inline int
icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList,
const struct icp_drvOpData *pOpData)
struct icp_drvOpData *pOpData)
{
Cpa32U metaSize = 0;
if (pBufferList->numBuffers <= ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS){
void *pOpDataStartAddr = (void *)pOpData;
if (pBufferList->numBuffers <= ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) {
uint8_t *pOpDataStartAddr = (uint8_t *) pOpData;
if (0 == defBuffListInfo.metaSize) {
if (0 == defBuffListInfo.metaSize) {
pBufferList->pPrivateMetaData = NULL;
return ICP_OCF_DRV_STATUS_SUCCESS;
}
@ -835,8 +690,9 @@ icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList,
* op data. It has been pre-allocated in memory just after the
* icp_drvOpData structure.
*/
pBufferList->pPrivateMetaData = pOpDataStartAddr +
sizeof(struct icp_drvOpData);
pBufferList->pPrivateMetaData = (void *)(pOpDataStartAddr +
sizeof(struct
icp_drvOpData));
} else {
if (CPA_STATUS_SUCCESS !=
cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE,
@ -852,7 +708,8 @@ icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList,
return ICP_OCF_DRV_STATUS_SUCCESS;
}
pBufferList->pPrivateMetaData = kmalloc(metaSize, GFP_ATOMIC);
pBufferList->pPrivateMetaData =
icp_kmalloc(metaSize, ICP_M_NOWAIT);
}
if (NULL == pBufferList->pPrivateMetaData) {
EPRINTK("%s() Failed to allocate pPrivateMetaData.\n",
@ -879,13 +736,38 @@ inline void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList)
* Otherwise, the meta data shall be freed when the icp_drvOpData is
* freed.
*/
if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < pBufferList->numBuffers){
kfree(pBufferList->pPrivateMetaData);
if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < pBufferList->numBuffers) {
icp_kfree(pBufferList->pPrivateMetaData);
}
}
module_init(icp_ocfDrvInit);
module_exit(icp_ocfDrvExit);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_AUTHOR("Intel");
MODULE_DESCRIPTION("OCF Driver for Intel Quick Assist crypto acceleration");
/* Module declaration, init and exit functions */
ICP_DECLARE_MODULE(icp_ocf, icp_ocfDrvInit, icp_ocfDrvExit);
ICP_MODULE_DESCRIPTION("OCF Driver for Intel Quick Assist crypto acceleration");
ICP_MODULE_VERSION(icp_ocf, ICP_OCF_VER_MJR);
ICP_MODULE_LICENSE("Dual BSD/GPL");
ICP_MODULE_AUTHOR("Intel");
/* Module parameters */
ICP_MODULE_PARAM_INT(icp_ocf, num_dereg_retries,
"Number of times to retry LAC Sym Session Deregistration. "
"Default 10, Max 100");
ICP_MODULE_PARAM_INT(icp_ocf, dereg_retry_delay_in_jiffies, "Delay in jiffies "
"(added to a schedule() function call) before a LAC Sym "
"Session Dereg is retried. Default 10");
ICP_MODULE_PARAM_INT(icp_ocf, max_sessions,
"This sets the maximum number of sessions "
"between OCF and this driver. If this value is set to zero,"
"max session count checking is disabled. Default is zero(0)");
/* Module dependencies */
#define MODULE_MIN_VER 1
#define CRYPTO_MAX_VER 3
#define LAC_MAX_VER 2
ICP_MODULE_DEPEND(icp_ocf, crypto, MODULE_MIN_VER, MODULE_MIN_VER,
CRYPTO_MAX_VER);
ICP_MODULE_DEPEND(icp_ocf, cryptodev, MODULE_MIN_VER, MODULE_MIN_VER,
CRYPTO_MAX_VER);
ICP_MODULE_DEPEND(icp_ocf, icp_crypto, MODULE_MIN_VER, MODULE_MIN_VER,
LAC_MAX_VER);

337
target/linux/generic-2.6/files/crypto/ocf/ep80579/icp_ocf.h
View file

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
* Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -27,7 +27,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
* Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -57,42 +57,34 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
* version: Security.L.1.0.130
* version: Security.L.1.0.2-229
*
***************************************************************************/
/*
* OCF drv driver header file for the Intel ICP processor.
* OCF driver header file for the Intel ICP processor.
*/
#ifndef ICP_OCF_H
#define ICP_OCF_H
#ifndef ICP_OCF_H_
#define ICP_OCF_H_
#include <linux/crypto.h>
#include <linux/delay.h>
#include <linux/skbuff.h>
#include <cpa.h>
#include <cpa_cy_im.h>
#include <cpa_cy_sym.h>
#include <cpa_cy_rand.h>
#include <cpa_cy_dh.h>
#include <cpa_cy_rsa.h>
#include <cpa_cy_ln.h>
#include <cpa_cy_common.h>
#include <cpa_cy_dsa.h>
#include "cryptodev.h"
#include "uio.h"
#include "cpa.h"
#include "cpa_cy_im.h"
#include "cpa_cy_sym.h"
#include "cpa_cy_rand.h"
#include "cpa_cy_dh.h"
#include "cpa_cy_rsa.h"
#include "cpa_cy_ln.h"
#include "cpa_cy_common.h"
#include "cpa_cy_dsa.h"
#include "icp_os.h"
#define NUM_BITS_IN_BYTE (8)
#define NUM_BITS_IN_BYTE_MINUS_ONE (NUM_BITS_IN_BYTE -1)
#define INVALID_DRIVER_ID (-1)
#define RETURN_RAND_NUM_GEN_FAILED (-1)
/*This is define means only one operation can be chained to another
(resulting in one chain of two operations)*/
#define MAX_NUM_OF_CHAINED_OPS (1)
/*This is the max block cipher initialisation vector*/
#define MAX_IV_LEN_IN_BYTES (20)
/*This is used to check whether the OCF to this driver session limit has
@ -118,61 +110,10 @@
#define ICP_OCF_PRINT_KERN_ALERT (1)
#define ICP_OCF_PRINT_KERN_ERRS (1)
/*DSA Prime Q size in bytes (as defined in the standard) */
#define DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES (20)
/*MACRO DEFINITIONS*/
#define BITS_TO_BYTES(bytes, bits) \
bytes = (bits + NUM_BITS_IN_BYTE_MINUS_ONE) / NUM_BITS_IN_BYTE
#define ICP_CACHE_CREATE(cache_ID, cache_name) \
kmem_cache_create(cache_ID, sizeof(cache_name),0, \
SLAB_HWCACHE_ALIGN, NULL, NULL);
#define ICP_CACHE_NULL_CHECK(slab_zone) \
{ \
if(NULL == slab_zone){ \
icp_ocfDrvFreeCaches(); \
EPRINTK("%s() line %d: Not enough memory!\n", \
__FUNCTION__, __LINE__); \
return ENOMEM; \
} \
}
#define ICP_CACHE_DESTROY(slab_zone) \
{ \
if(NULL != slab_zone){ \
kmem_cache_destroy(slab_zone); \
slab_zone = NULL; \
} \
}
#define ICP_REGISTER_SYM_FUNCTIONALITY_WITH_OCF(alg) \
{ \
if(OCF_REGISTRATION_STATUS_SUCCESS == \
crypto_register(icp_ocfDrvDriverId, \
alg, \
0, \
0)) { \
ocfStatus++; \
} \
}
#define ICP_REGISTER_ASYM_FUNCTIONALITY_WITH_OCF(alg) \
{ \
if(OCF_REGISTRATION_STATUS_SUCCESS == \
crypto_kregister(icp_ocfDrvDriverId, \
alg, \
0)){ \
ocfStatus++; \
} \
}
#if ICP_OCF_PRINT_DEBUG_MESSAGES == 1
#define DPRINTK(args...) \
{ \
printk(args); \
ICP_IPRINTK(args); \
}
#else //ICP_OCF_PRINT_DEBUG_MESSAGES == 1
@ -184,7 +125,7 @@
#if ICP_OCF_PRINT_KERN_ALERT == 1
#define APRINTK(args...) \
{ \
printk(KERN_ALERT args); \
ICP_APRINTK(args); \
}
#else //ICP_OCF_PRINT_KERN_ALERT == 1
@ -196,7 +137,7 @@
#if ICP_OCF_PRINT_KERN_ERRS == 1
#define EPRINTK(args...) \
{ \
printk(KERN_ERR args); \
ICP_EPRINTK(args); \
}
#else //ICP_OCF_PRINT_KERN_ERRS == 1
@ -207,47 +148,110 @@
#define IPRINTK(args...) \
{ \
printk(KERN_INFO args); \
ICP_IPRINTK(args); \
}
/*END OF MACRO DEFINITIONS*/
/*DSA Prime Q size in bytes (as defined in the standard) */
#define DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES (20)
#define BITS_TO_BYTES(bytes, bits) \
bytes = (bits + NUM_BITS_IN_BYTE_MINUS_ONE) / NUM_BITS_IN_BYTE
typedef enum {
ICP_OCF_DRV_ALG_CIPHER = 0,
ICP_OCF_DRV_ALG_HASH
} icp_ocf_drv_alg_type_t;
/* These are all defined in icp_common.c */
extern atomic_t lac_session_failed_dereg_count;
extern atomic_t icp_ocfDrvIsExiting;
extern atomic_t num_ocf_to_drv_registered_sessions;
typedef ICP_LIST_HEAD(icp_drvSessionListHead_s,
icp_drvSessionData) icp_drvSessionListHead_t;
/*These are use inputs used in icp_sym.c and icp_common.c
They are instantiated in icp_common.c*/
extern int max_sessions;
/*Values used to derisk chances of performs being called against
deregistered sessions (for which the slab page has been reclaimed)
This is not a fix - since page frames are reclaimed from a slab, one cannot
rely on that memory not being re-used by another app.*/
typedef enum {
ICP_SESSION_INITIALISED = 0x5C5C5C,
ICP_SESSION_RUNNING = 0x005C00,
ICP_SESSION_DEREGISTERED = 0xC5C5C5
} usage_derisk;
/* This struct is required for deferred session
deregistration as a work queue function can
only have one argument*/
struct icp_ocfDrvFreeLacSession {
CpaCySymSessionCtx sessionToDeregister;
icp_workstruct work;
};
/*
This is the OCF<->OCF_DRV session object:
1.listNode
The first member is a listNode. These session objects are added to a linked
list in order to make it easier to remove them all at session exit time.
2.inUse
The second member is used to give the session object state and derisk the
possibility of OCF batch calls executing against a deregistered session (as
described above).
3.sessHandle
The third member is a LAC<->OCF_DRV session handle (initialised with the first
perform request for that session).
4.lacSessCtx
The fourth is the LAC session context. All the parameters for this structure
are only known when the first perform request for this session occurs. That is
why the OCF EP80579 Driver only registers a new LAC session at perform time
*/
struct icp_drvSessionData {
ICP_LIST_ENTRY(icp_drvSessionData) listNode;
usage_derisk inUse;
CpaCySymSessionCtx sessHandle;
CpaCySymSessionSetupData lacSessCtx;
};
/* These are all defined in icp_common.c */
extern icp_atomic_t lac_session_failed_dereg_count;
extern icp_atomic_t icp_ocfDrvIsExiting;
extern icp_atomic_t num_ocf_to_drv_registered_sessions;
extern int32_t icp_ocfDrvDriverId;
extern struct list_head icp_ocfDrvGlobalSymListHead;
extern struct list_head icp_ocfDrvGlobalSymListHead_FreeMemList;
extern struct workqueue_struct *icp_ocfDrvFreeLacSessionWorkQ;
extern spinlock_t icp_ocfDrvSymSessInfoListSpinlock;
extern rwlock_t icp_kmem_cache_destroy_alloc_lock;
extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead;
extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList;
extern icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ;
extern icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock;
/*Slab zones for symettric functionality, instantiated in icp_common.c*/
extern struct kmem_cache *drvSessionData_zone;
extern struct kmem_cache *drvOpData_zone;
extern icp_kmem_cache drvSessionData_zone;
extern icp_kmem_cache drvOpData_zone;
/*Slabs zones for asymettric functionality, instantiated in icp_common.c*/
extern struct kmem_cache *drvDH_zone;
extern struct kmem_cache *drvLnModExp_zone;
extern struct kmem_cache *drvRSADecrypt_zone;
extern struct kmem_cache *drvRSAPrivateKey_zone;
extern struct kmem_cache *drvDSARSSign_zone;
extern struct kmem_cache *drvDSARSSignKValue_zone;
extern struct kmem_cache *drvDSAVerify_zone;
extern icp_kmem_cache drvDH_zone;
extern icp_kmem_cache drvLnModExp_zone;
extern icp_kmem_cache drvRSADecrypt_zone;
extern icp_kmem_cache drvRSAPrivateKey_zone;
extern icp_kmem_cache drvDSARSSign_zone;
extern icp_kmem_cache drvDSARSSignKValue_zone;
extern icp_kmem_cache drvDSAVerify_zone;
/* Module parameters defined in icp_cpmmon.c*/
/* Module parameters - gives the number of times LAC deregistration shall be
re-tried */
extern int num_dereg_retries;
/* Module parameter - gives the delay time in jiffies before a LAC session
shall be attempted to be deregistered again */
extern int dereg_retry_delay_in_jiffies;
/* Module parameter - gives the maximum number of sessions possible between
OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/
extern int max_sessions;
/*Slab zones for flatbuffers and bufferlist*/
extern struct kmem_cache *drvFlatBuffer_zone;
extern icp_kmem_cache drvFlatBuffer_zone;
#define ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS (16)
@ -257,19 +261,13 @@ struct icp_drvBuffListInfo {
Cpa32U metaOffset;
Cpa32U buffListSize;
};
extern struct icp_drvBuffListInfo defBuffListInfo;
/*
* This struct is used to keep a reference to the relevant node in the list
* of sessionData structs, to the buffer type required by OCF and to the OCF
* provided crp struct that needs to be returned. All this info is needed in
* the callback function.
*
* IV can sometimes be stored in non-contiguous memory (e.g. skbuff
* linked/frag list, therefore a contiguous memory space for the IV data must be
* created and passed to LAC
*
*/
/* This struct is used to keep a reference to the relevant node in the list
of sessionData structs, to the buffer type required by OCF and to the OCF
provided crp struct that needs to be returned. All this info is needed in
the callback function.*/
struct icp_drvOpData {
CpaCySymOpData lacOpData;
uint32_t digestSizeInBytes;
@ -281,83 +279,98 @@ struct icp_drvOpData {
CpaFlatBuffer bufferListArray[ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS];
CpaBoolean verifyResult;
};
/*Values used to derisk chances of performs being called against
deregistered sessions (for which the slab page has been reclaimed)
This is not a fix - since page frames are reclaimed from a slab, one cannot
rely on that memory not being re-used by another app.*/
typedef enum {
ICP_SESSION_INITIALISED = 0x5C5C5C,
ICP_SESSION_RUNNING = 0x005C00,
ICP_SESSION_DEREGISTERED = 0xC5C5C5
} usage_derisk;
/*
This is the OCF<->OCF_DRV session object:
/* Create a new session between OCF and this driver*/
int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sild,
struct cryptoini *cri);
1.The first member is a listNode. These session objects are added to a linked
list in order to make it easier to remove them all at session exit time.
2.The second member is used to give the session object state and derisk the
possibility of OCF batch calls executing against a deregistered session (as
described above).
3.The third member is a LAC<->OCF_DRV session handle (initialised with the first
perform request for that session).
4.The fourth is the LAC session context. All the parameters for this structure
are only known when the first perform request for this session occurs. That is
why the OCF Tolapai Driver only registers a new LAC session at perform time
*/
struct icp_drvSessionData {
struct list_head listNode;
usage_derisk inUse;
CpaCySymSessionCtx sessHandle;
CpaCySymSessionSetupData lacSessCtx;
};
/* Free a session between this driver and the Quick Assist Framework*/
int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid);
/* This struct is required for deferred session
deregistration as a work queue function can
only have one argument*/
struct icp_ocfDrvFreeLacSession {
CpaCySymSessionCtx sessionToDeregister;
struct work_struct work;
};
/* Defer freeing a Quick Assist session*/
void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg);
int icp_ocfDrvNewSession(device_t dev, uint32_t * sild, struct cryptoini *cri);
/* Process OCF cryptographic request for a symmetric algorithm*/
int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint);
int icp_ocfDrvFreeLACSession(device_t dev, uint64_t sid);
int icp_ocfDrvSymProcess(device_t dev, struct cryptop *crp, int hint);
int icp_ocfDrvPkeProcess(device_t dev, struct cryptkop *krp, int hint);
/* Process OCF cryptographic request for an asymmetric algorithm*/
int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint);
/* Populate a buffer with random data*/
int icp_ocfDrvReadRandom(void *arg, uint32_t * buf, int maxwords);
/* Retry Quick Assist session deregistration*/
int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister);
int icp_ocfDrvSkBuffToBufferList(struct sk_buff *skb,
CpaBufferList * bufferList);
/* Convert an OS scatter gather list to a CPA buffer list*/
int icp_ocfDrvPacketBuffToBufferList(icp_packet_buffer_t * pPacketBuffer,
CpaBufferList * bufferList);
int icp_ocfDrvBufferListToSkBuff(CpaBufferList * bufferList,
struct sk_buff **skb);
/* Convert a CPA buffer list to an OS scatter gather list*/
int icp_ocfDrvBufferListToPacketBuff(CpaBufferList * bufferList,
icp_packet_buffer_t ** pPacketBuffer);
/* Get the number of buffers in an OS scatter gather list*/
uint16_t icp_ocfDrvGetPacketBuffFrags(icp_packet_buffer_t * pPacketBuffer);
/* Convert a single OS buffer to a CPA Flat Buffer*/
void icp_ocfDrvSinglePacketBuffToFlatBuffer(icp_packet_buffer_t * pPacketBuffer,
CpaFlatBuffer * pFlatBuffer);
/* Add pointer and length to a CPA Flat Buffer structure*/
void icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len,
CpaFlatBuffer * pFlatBuffer);
/* Convert pointer and length values to a CPA buffer list*/
void icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length,
CpaBufferList * pBufferList);
/* Convert a CPA buffer list to pointer and length values*/
void icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList,
void **ppDataOut, uint32_t * pLength);
/* Set the number of flat buffers in bufferlist and the size of memory
to allocate for the pPrivateMetaData member of the CpaBufferList.*/
int icp_ocfDrvBufferListMemInfo(uint16_t numBuffers,
struct icp_drvBuffListInfo *buffListInfo);
uint16_t icp_ocfDrvGetSkBuffFrags(struct sk_buff *pSkb);
/* Find pointer position of the digest within an OS scatter gather list*/
uint8_t *icp_ocfDrvPacketBufferDigestPointerFind(struct icp_drvOpData
*drvOpData,
int offsetInBytes,
uint32_t digestSizeInBytes);
/*This top level function is used to find a pointer to where a digest is
stored/needs to be inserted. */
uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData *drvOpData,
struct cryptodesc *crp_desc);
/* Free a CPA flat buffer*/
void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer);
int icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList,
const struct icp_drvOpData *pOpData);
/* This function will allocate memory for the pPrivateMetaData
member of CpaBufferList. */
int icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList,
struct icp_drvOpData *pOpData);
/* Free data allocated for the pPrivateMetaData
member of CpaBufferList.*/
void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList);
#define ICP_CACHE_CREATE(cache_ID, cache_name) \
icp_kmem_cache_create(cache_ID, sizeof(cache_name),ICP_KERNEL_CACHE_ALIGN,\
ICP_KERNEL_CACHE_NOINIT)
#define ICP_CACHE_FREE(args...) \
icp_kmem_cache_free (args)
#define ICP_CACHE_DESTROY(slab_zone)\
{\
if(NULL != slab_zone){\
icp_kmem_cache_destroy(slab_zone);\
slab_zone = NULL;\
}\
}
#endif
/* ICP_OCF_H */
/* ICP_OCF_H_ */

423
target/linux/generic-2.6/files/crypto/ocf/ep80579/icp_sym.c
View file

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
* Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -27,7 +27,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
* Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -57,7 +57,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
* version: Security.L.1.0.130
* version: Security.L.1.0.2-229
*
***************************************************************************/
/*
@ -96,38 +96,6 @@ static int
icp_ocfDrvAlgorithmSetup(struct cryptoini *cri,
CpaCySymSessionSetupData * lacSessCtx);
/*This top level function is used to find a pointer to where a digest is
stored/needs to be inserted. */
static uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData *drvOpData,
struct cryptodesc *crp_desc);
/*This function is called when a digest pointer has to be found within a
SKBUFF.*/
static inline uint8_t *icp_ocfDrvSkbuffDigestPointerFind(struct icp_drvOpData
*drvOpData,
int offsetInBytes,
uint32_t
digestSizeInBytes);
/*The following two functions are called if the SKBUFF digest pointer is not
positioned in the linear portion of the buffer (i.e. it is in a linked SKBUFF
or page fragment).*/
/*This function takes care of the page fragment case.*/
static inline uint8_t *icp_ocfDrvDigestSkbNRFragsCheck(struct sk_buff *skb,
struct skb_shared_info
*skb_shared,
int offsetInBytes,
uint32_t
digestSizeInBytes);
/*This function takes care of the linked list case.*/
static inline uint8_t *icp_ocfDrvDigestSkbFragListCheck(struct sk_buff *skb,
struct skb_shared_info
*skb_shared,
int offsetInBytes,
uint32_t
digestSizeInBytes);
/*This function is used to free an OCF->OCF_DRV session object*/
static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData);
@ -142,7 +110,7 @@ static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData);
* Notes : The callbackTag is a pointer to an icp_drvOpData. This memory
* object was passed to LAC for the cryptographic processing and contains all
* the relevant information for cleaning up buffer handles etc. so that the
* OCF Tolapai Driver portion of this crypto operation can be fully completed.
* OCF EP80579 Driver portion of this crypto operation can be fully completed.
*/
static void
icp_ocfDrvSymCallBack(void *callbackTag,
@ -188,11 +156,12 @@ icp_ocfDrvSymCallBack(void *callbackTag,
if (CPA_STATUS_SUCCESS == status) {
if (temp_drvOpData->bufferType == CRYPTO_F_SKBUF) {
if (temp_drvOpData->bufferType == ICP_CRYPTO_F_PACKET_BUF) {
if (ICP_OCF_DRV_STATUS_SUCCESS !=
icp_ocfDrvBufferListToSkBuff(pDstBuffer,
(struct sk_buff **)
&(crp->crp_buf))) {
icp_ocfDrvBufferListToPacketBuff(pDstBuffer,
(icp_packet_buffer_t
**)
& (crp->crp_buf))) {
EPRINTK("%s(): BufferList to SkBuff "
"conversion error.\n", __FUNCTION__);
crp->crp_etype = EPERM;
@ -213,10 +182,10 @@ icp_ocfDrvSymCallBack(void *callbackTag,
if (temp_drvOpData->numBufferListArray >
ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) {
kfree(pDstBuffer->pBuffers);
icp_kfree(pDstBuffer->pBuffers);
}
icp_ocfDrvFreeMetaData(pDstBuffer);
kmem_cache_free(drvOpData_zone, temp_drvOpData);
ICP_CACHE_FREE(drvOpData_zone, temp_drvOpData);
/* Invoke the OCF callback function */
crypto_done(crp);
@ -231,7 +200,8 @@ icp_ocfDrvSymCallBack(void *callbackTag,
* Notes : LAC session registration happens during the first perform call.
* That is the first time we know all information about a given session.
*/
int icp_ocfDrvNewSession(device_t dev, uint32_t * sid, struct cryptoini *cri)
int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sid,
struct cryptoini *cri)
{
struct icp_drvSessionData *sessionData = NULL;
uint32_t delete_session = 0;
@ -258,44 +228,44 @@ int icp_ocfDrvNewSession(device_t dev, uint32_t * sid, struct cryptoini *cri)
return EINVAL;
}
sessionData = kmem_cache_zalloc(drvSessionData_zone, GFP_ATOMIC);
sessionData = icp_kmem_cache_zalloc(drvSessionData_zone, ICP_M_NOWAIT);
if (NULL == sessionData) {
DPRINTK("%s():No memory for Session Data\n", __FUNCTION__);
return ENOMEM;
}
/*ENTER CRITICAL SECTION */
spin_lock_bh(&icp_ocfDrvSymSessInfoListSpinlock);
icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock);
/*put this check in the spinlock so no new sessions can be added to the
linked list when we are exiting */
if (CPA_TRUE == atomic_read(&icp_ocfDrvIsExiting)) {
if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) {
delete_session++;
} else if (NO_OCF_TO_DRV_MAX_SESSIONS != max_sessions) {
if (atomic_read(&num_ocf_to_drv_registered_sessions) >=
if (icp_atomic_read(&num_ocf_to_drv_registered_sessions) >=
(max_sessions -
atomic_read(&lac_session_failed_dereg_count))) {
icp_atomic_read(&lac_session_failed_dereg_count))) {
delete_session++;
} else {
atomic_inc(&num_ocf_to_drv_registered_sessions);
icp_atomic_inc(&num_ocf_to_drv_registered_sessions);
/* Add to session data linked list */
list_add(&(sessionData->listNode),
&icp_ocfDrvGlobalSymListHead);
ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead,
listNode);
}
} else if (NO_OCF_TO_DRV_MAX_SESSIONS == max_sessions) {
list_add(&(sessionData->listNode),
&icp_ocfDrvGlobalSymListHead);
ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead,
listNode);
}
sessionData->inUse = ICP_SESSION_INITIALISED;
/*EXIT CRITICAL SECTION */
spin_unlock_bh(&icp_ocfDrvSymSessInfoListSpinlock);
icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock);
if (delete_session) {
DPRINTK("%s():No Session handles available\n", __FUNCTION__);
kmem_cache_free(drvSessionData_zone, sessionData);
ICP_CACHE_FREE(drvSessionData_zone, sessionData);
return EPERM;
}
@ -560,27 +530,27 @@ static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData)
sessionData->inUse = ICP_SESSION_DEREGISTERED;
/*ENTER CRITICAL SECTION */
spin_lock_bh(&icp_ocfDrvSymSessInfoListSpinlock);
icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock);
if (CPA_TRUE == atomic_read(&icp_ocfDrvIsExiting)) {
if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) {
/*If the Driver is exiting, allow that process to
handle any deletions */
/*EXIT CRITICAL SECTION */
spin_unlock_bh(&icp_ocfDrvSymSessInfoListSpinlock);
icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock);
return;
}
atomic_dec(&num_ocf_to_drv_registered_sessions);
icp_atomic_dec(&num_ocf_to_drv_registered_sessions);
list_del(&(sessionData->listNode));
ICP_LIST_DEL(sessionData, listNode);
/*EXIT CRITICAL SECTION */
spin_unlock_bh(&icp_ocfDrvSymSessInfoListSpinlock);
icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock);
if (NULL != sessionData->sessHandle) {
kfree(sessionData->sessHandle);
icp_kfree(sessionData->sessHandle);
}
kmem_cache_free(drvSessionData_zone, sessionData);
ICP_CACHE_FREE(drvSessionData_zone, sessionData);
}
/* Name : icp_ocfDrvFreeLACSession
@ -588,7 +558,7 @@ static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData)
* Description : This attempts to deregister a LAC session. If it fails, the
* deregistation retry function is called.
*/
int icp_ocfDrvFreeLACSession(device_t dev, uint64_t sid)
int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid)
{
CpaCySymSessionCtx sessionToDeregister = NULL;
struct icp_drvSessionData *sessionData = NULL;
@ -604,14 +574,14 @@ int icp_ocfDrvFreeLACSession(device_t dev, uint64_t sid)
sessionToDeregister = sessionData->sessHandle;
if (ICP_SESSION_INITIALISED == sessionData->inUse) {
DPRINTK("%s() Session not registered with LAC\n", __FUNCTION__);
} else if (NULL == sessionData->sessHandle) {
EPRINTK
("%s(): OCF Free session called with Null Session Handle.\n",
__FUNCTION__);
if ((ICP_SESSION_INITIALISED != sessionData->inUse) &&
(ICP_SESSION_RUNNING != sessionData->inUse) &&
(ICP_SESSION_DEREGISTERED != sessionData->inUse)) {
DPRINTK("%s() Session not initialised.\n", __FUNCTION__);
return EINVAL;
} else {
}
if (ICP_SESSION_RUNNING == sessionData->inUse) {
lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE,
sessionToDeregister);
if (CPA_STATUS_RETRY == lacStatus) {
@ -629,9 +599,12 @@ int icp_ocfDrvFreeLACSession(device_t dev, uint64_t sid)
DPRINTK("%s(): LAC failed to deregister the session. "
"localSessionId= %p, lacStatus = %d\n",
__FUNCTION__, sessionToDeregister, lacStatus);
atomic_inc(&lac_session_failed_dereg_count);
icp_atomic_inc(&lac_session_failed_dereg_count);
retval = EPERM;
}
} else {
DPRINTK("%s() Session not registered with LAC.\n",
__FUNCTION__);
}
icp_ocfDrvFreeOCFSession(sessionData);
@ -668,13 +641,12 @@ static int icp_ocfDrvAlgCheck(struct cryptodesc *crp_desc)
* to whether session paramaters have changed (e.g. alg chain order) are
* done.
*/
int icp_ocfDrvSymProcess(device_t dev, struct cryptop *crp, int hint)
int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint)
{
struct icp_drvSessionData *sessionData = NULL;
struct icp_drvOpData *drvOpData = NULL;
CpaStatus lacStatus = CPA_STATUS_SUCCESS;
Cpa32U sessionCtxSizeInBytes = 0;
uint16_t numBufferListArray = 0;
if (NULL == crp) {
DPRINTK("%s(): Invalid input parameters, cryptop is NULL\n",
@ -696,7 +668,7 @@ int icp_ocfDrvSymProcess(device_t dev, struct cryptop *crp, int hint)
return EINVAL;
}
if (CPA_TRUE == atomic_read(&icp_ocfDrvIsExiting)) {
if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) {
crp->crp_etype = EFAULT;
return EFAULT;
}
@ -793,14 +765,16 @@ int icp_ocfDrvSymProcess(device_t dev, struct cryptop *crp, int hint)
if (CPA_STATUS_SUCCESS != lacStatus) {
EPRINTK("%s(): cpaCySymSessionCtxGetSize failed - %d\n",
__FUNCTION__, lacStatus);
crp->crp_etype = EINVAL;
return EINVAL;
}
sessionData->sessHandle =
kmalloc(sessionCtxSizeInBytes, GFP_ATOMIC);
icp_kmalloc(sessionCtxSizeInBytes, ICP_M_NOWAIT);
if (NULL == sessionData->sessHandle) {
EPRINTK
("%s(): Failed to get memory for SymSessionCtx\n",
__FUNCTION__);
crp->crp_etype = ENOMEM;
return ENOMEM;
}
@ -812,13 +786,14 @@ int icp_ocfDrvSymProcess(device_t dev, struct cryptop *crp, int hint)
if (CPA_STATUS_SUCCESS != lacStatus) {
EPRINTK("%s(): cpaCySymInitSession failed -%d \n",
__FUNCTION__, lacStatus);
crp->crp_etype = EFAULT;
return EFAULT;
}
sessionData->inUse = ICP_SESSION_RUNNING;
}
drvOpData = kmem_cache_zalloc(drvOpData_zone, GFP_ATOMIC);
drvOpData = icp_kmem_cache_zalloc(drvOpData_zone, ICP_M_NOWAIT);
if (NULL == drvOpData) {
EPRINTK("%s():Failed to get memory for drvOpData\n",
__FUNCTION__);
@ -835,28 +810,48 @@ int icp_ocfDrvSymProcess(device_t dev, struct cryptop *crp, int hint)
drvOpData->srcBuffer.pBuffers = drvOpData->bufferListArray;
drvOpData->numBufferListArray = ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS;
if (ICP_OCF_DRV_STATUS_SUCCESS !=
icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp->crp_desc)) {
crp->crp_etype = EINVAL;
goto err;
}
if (drvOpData->crp->crp_desc->crd_next != NULL) {
if (icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp->
crp_desc->crd_next)) {
crp->crp_etype = EINVAL;
goto err;
}
}
/*
* Allocate buffer list array memory allocation if the
* data fragment is more than the default allocation
* Allocate buffer list array memory if the data fragment is more than
* the default number (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) and not
* calculated already
*/
if (crp->crp_flags & CRYPTO_F_SKBUF) {
numBufferListArray = icp_ocfDrvGetSkBuffFrags((struct sk_buff *)
crp->crp_buf);
if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < numBufferListArray) {
if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) {
if (NULL == drvOpData->lacOpData.pDigestResult) {
drvOpData->numBufferListArray =
icp_ocfDrvGetPacketBuffFrags((icp_packet_buffer_t *)
crp->crp_buf);
}
if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS <
drvOpData->numBufferListArray) {
DPRINTK("%s() numBufferListArray more than default\n",
__FUNCTION__);
drvOpData->srcBuffer.pBuffers = NULL;
drvOpData->srcBuffer.pBuffers =
kmalloc(numBufferListArray *
sizeof(CpaFlatBuffer), GFP_ATOMIC);
icp_kmalloc(drvOpData->numBufferListArray *
sizeof(CpaFlatBuffer), ICP_M_NOWAIT);
if (NULL == drvOpData->srcBuffer.pBuffers) {
EPRINTK("%s() Failed to get memory for "
"pBuffers\n", __FUNCTION__);
kmem_cache_free(drvOpData_zone, drvOpData);
ICP_CACHE_FREE(drvOpData_zone, drvOpData);
crp->crp_etype = ENOMEM;
return ENOMEM;
}
drvOpData->numBufferListArray = numBufferListArray;
}
}
@ -864,17 +859,18 @@ int icp_ocfDrvSymProcess(device_t dev, struct cryptop *crp, int hint)
* Check the type of buffer structure we got and convert it into
* CpaBufferList format.
*/
if (crp->crp_flags & CRYPTO_F_SKBUF) {
if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) {
if (ICP_OCF_DRV_STATUS_SUCCESS !=
icp_ocfDrvSkBuffToBufferList((struct sk_buff *)crp->crp_buf,
&(drvOpData->srcBuffer))) {
EPRINTK("%s():Failed to translate from SK_BUF "
icp_ocfDrvPacketBuffToBufferList((icp_packet_buffer_t *)
crp->crp_buf,
&(drvOpData->srcBuffer))) {
EPRINTK("%s():Failed to translate from packet buffer "
"to bufferlist\n", __FUNCTION__);
crp->crp_etype = EINVAL;
goto err;
}
drvOpData->bufferType = CRYPTO_F_SKBUF;
drvOpData->bufferType = ICP_CRYPTO_F_PACKET_BUF;
} else if (crp->crp_flags & CRYPTO_F_IOV) {
/* OCF only supports IOV of one entry. */
if (NUM_IOV_SUPPORTED ==
@ -906,21 +902,6 @@ int icp_ocfDrvSymProcess(device_t dev, struct cryptop *crp, int hint)
drvOpData->bufferType = CRYPTO_BUF_CONTIG;
}
if (ICP_OCF_DRV_STATUS_SUCCESS !=
icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp->crp_desc)) {
crp->crp_etype = EINVAL;
goto err;
}
if (drvOpData->crp->crp_desc->crd_next != NULL) {
if (icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp->
crp_desc->crd_next)) {
crp->crp_etype = EINVAL;
goto err;
}
}
/* Allocate srcBuffer's private meta data */
if (ICP_OCF_DRV_STATUS_SUCCESS !=
icp_ocfDrvAllocMetaData(&(drvOpData->srcBuffer), drvOpData)) {
@ -941,7 +922,7 @@ int icp_ocfDrvSymProcess(device_t dev, struct cryptop *crp, int hint)
DPRINTK("%s(): cpaCySymPerformOp retry, lacStatus = %d\n",
__FUNCTION__, lacStatus);
memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData));
crp->crp_etype = EINVAL;
crp->crp_etype = ERESTART;
goto err;
}
if (CPA_STATUS_SUCCESS != lacStatus) {
@ -956,10 +937,10 @@ int icp_ocfDrvSymProcess(device_t dev, struct cryptop *crp, int hint)
err:
if (drvOpData->numBufferListArray > ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) {
kfree(drvOpData->srcBuffer.pBuffers);
icp_kfree(drvOpData->srcBuffer.pBuffers);
}
icp_ocfDrvFreeMetaData(&(drvOpData->srcBuffer));
kmem_cache_free(drvOpData_zone, drvOpData);
ICP_CACHE_FREE(drvOpData_zone, drvOpData);
return crp->crp_etype;
}
@ -1129,32 +1110,20 @@ static int icp_ocfDrvProcessDataSetup(struct icp_drvOpData *drvOpData,
* must be traversed by the data length offset in order to find the digest start
* address. Whether there is enough space for the digest must also be checked.
*/
static uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData *drvOpData,
struct cryptodesc *crp_desc)
uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData * drvOpData,
struct cryptodesc * crp_desc)
{
int offsetInBytes = crp_desc->crd_inject;
uint32_t digestSizeInBytes = drvOpData->digestSizeInBytes;
uint8_t *flat_buffer_base = NULL;
int flat_buffer_length = 0;
struct sk_buff *skb;
if (drvOpData->crp->crp_flags & CRYPTO_F_SKBUF) {
/*check if enough overall space to store hash */
skb = (struct sk_buff *)(drvOpData->crp->crp_buf);
if (drvOpData->crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) {
if (skb->len < (offsetInBytes + digestSizeInBytes)) {
DPRINTK("%s() Not enough space for Digest"
" payload after the offset (%d), "
"digest size (%d) \n", __FUNCTION__,
offsetInBytes, digestSizeInBytes);
return NULL;
}
return icp_ocfDrvSkbuffDigestPointerFind(drvOpData,
offsetInBytes,
digestSizeInBytes);
return icp_ocfDrvPacketBufferDigestPointerFind(drvOpData,
offsetInBytes,
digestSizeInBytes);
} else {
/* IOV or flat buffer */
@ -1182,201 +1151,3 @@ static uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData *drvOpData,
DPRINTK("%s() Should not reach this point\n", __FUNCTION__);
return NULL;
}
/* Name : icp_ocfDrvSkbuffDigestPointerFind
*
* Description : This function is used by icp_ocfDrvDigestPointerFind to process
* the non-linear portion of the skbuff if the fragmentation type is a linked
* list (frag_list is not NULL in the skb_shared_info structure)
*/
static inline uint8_t *icp_ocfDrvSkbuffDigestPointerFind(struct icp_drvOpData
*drvOpData,
int offsetInBytes,
uint32_t
digestSizeInBytes)
{
struct sk_buff *skb = NULL;
struct skb_shared_info *skb_shared = NULL;
uint32_t skbuffisnonlinear = 0;
uint32_t skbheadlen = 0;
skb = (struct sk_buff *)(drvOpData->crp->crp_buf);
skbuffisnonlinear = skb_is_nonlinear(skb);
skbheadlen = skb_headlen(skb);
/*Linear skb checks */
if (skbheadlen > offsetInBytes) {
if (skbheadlen >= (offsetInBytes + digestSizeInBytes)) {
return (uint8_t *) (skb->data + offsetInBytes);
} else {
DPRINTK("%s() Auth payload stretches "
"accross contiguous memory\n", __FUNCTION__);
return NULL;
}
} else {
if (skbuffisnonlinear) {
offsetInBytes -= skbheadlen;
} else {
DPRINTK("%s() Offset outside of buffer boundaries\n",
__FUNCTION__);
return NULL;
}
}
/*Non Linear checks */
skb_shared = (struct skb_shared_info *)(skb->end);
if (unlikely(NULL == skb_shared)) {
DPRINTK("%s() skbuff shared info stucture is NULL! \n",
__FUNCTION__);
return NULL;
} else if ((0 != skb_shared->nr_frags) &&
(skb_shared->frag_list != NULL)) {
DPRINTK("%s() skbuff nr_frags AND "
"frag_list not supported \n", __FUNCTION__);
return NULL;
}
/*TCP segmentation more likely than IP fragmentation */
if (likely(0 != skb_shared->nr_frags)) {
return icp_ocfDrvDigestSkbNRFragsCheck(skb, skb_shared,
offsetInBytes,
digestSizeInBytes);
} else if (skb_shared->frag_list != NULL) {
return icp_ocfDrvDigestSkbFragListCheck(skb, skb_shared,
offsetInBytes,
digestSizeInBytes);
} else {
DPRINTK("%s() skbuff is non-linear but does not show any "
"linked data\n", __FUNCTION__);
return NULL;
}
}
/* Name : icp_ocfDrvDigestSkbNRFragsCheck
*
* Description : This function is used by icp_ocfDrvSkbuffDigestPointerFind to
* process the non-linear portion of the skbuff, if the fragmentation type is
* page fragments
*/
static inline uint8_t *icp_ocfDrvDigestSkbNRFragsCheck(struct sk_buff *skb,
struct skb_shared_info
*skb_shared,
int offsetInBytes,
uint32_t
digestSizeInBytes)
{
int i = 0;
/*nr_frags starts from 1 */
if (MAX_SKB_FRAGS < skb_shared->nr_frags) {
DPRINTK("%s error processing skbuff "
"page frame -- MAX FRAGS exceeded \n", __FUNCTION__);
return NULL;
}
for (i = 0; i < skb_shared->nr_frags; i++) {
if (offsetInBytes >= skb_shared->frags[i].size) {
/*offset still greater than data position */
offsetInBytes -= skb_shared->frags[i].size;
} else {
/* found the page containing start of hash */
if (NULL == skb_shared->frags[i].page) {
DPRINTK("%s() Linked page is NULL!\n",
__FUNCTION__);
return NULL;
}
if (offsetInBytes + digestSizeInBytes >
skb_shared->frags[i].size) {
DPRINTK("%s() Auth payload stretches accross "
"contiguous memory\n", __FUNCTION__);
return NULL;
} else {
return (uint8_t *) (skb_shared->frags[i].page +
skb_shared->frags[i].
page_offset +
offsetInBytes);
}
}
/*only possible if internal page sizes are set wrong */
if (offsetInBytes < 0) {
DPRINTK("%s error processing skbuff page frame "
"-- offset calculation \n", __FUNCTION__);
return NULL;
}
}
/*only possible if internal page sizes are set wrong */
DPRINTK("%s error processing skbuff page frame "
"-- ran out of page fragments, remaining offset = %d \n",
__FUNCTION__, offsetInBytes);
return NULL;
}
/* Name : icp_ocfDrvDigestSkbFragListCheck
*
* Description : This function is used by icp_ocfDrvSkbuffDigestPointerFind to
* process the non-linear portion of the skbuff, if the fragmentation type is
* a linked list
*
*/
static inline uint8_t *icp_ocfDrvDigestSkbFragListCheck(struct sk_buff *skb,
struct skb_shared_info
*skb_shared,
int offsetInBytes,
uint32_t
digestSizeInBytes)
{
struct sk_buff *skb_list = skb_shared->frag_list;
/*check added for readability */
if (NULL == skb_list) {
DPRINTK("%s error processing skbuff "
"-- no more list! \n", __FUNCTION__);
return NULL;
}
for (; skb_list; skb_list = skb_list->next) {
if (NULL == skb_list) {
DPRINTK("%s error processing skbuff "
"-- no more list! \n", __FUNCTION__);
return NULL;
}
if (offsetInBytes >= skb_list->len) {
offsetInBytes -= skb_list->len;
} else {
if (offsetInBytes + digestSizeInBytes > skb_list->len) {
DPRINTK("%s() Auth payload stretches accross "
"contiguous memory\n", __FUNCTION__);
return NULL;
} else {
return (uint8_t *)
(skb_list->data + offsetInBytes);
}
}
/*This check is only needed if internal skb_list length values
are set wrong. */
if (0 > offsetInBytes) {
DPRINTK("%s() error processing skbuff object -- offset "
"calculation \n", __FUNCTION__);
return NULL;
}
}
/*catch all for unusual for-loop exit.
This code should never be reached */
DPRINTK("%s() Catch-All hit! Process error.\n", __FUNCTION__);
return NULL;
}

69
target/linux/generic-2.6/files/crypto/ocf/ep80579/linux_2.6_kernel_space.mk
View file

@ -1,69 +0,0 @@
###################
# @par
# This file is provided under a dual BSD/GPLv2 license. When using or
# redistributing this file, you may do so under either license.
#
# GPL LICENSE SUMMARY
#
# Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of version 2 of the GNU General Public License as
# published by the Free Software Foundation.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
# The full GNU General Public License is included in this distribution
# in the file called LICENSE.GPL.
#
# Contact Information:
# Intel Corporation
#
# BSD LICENSE
#
# Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# * Neither the name of Intel Corporation nor the names of its
# contributors may be used to endorse or promote products derived
# from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#
# version: Security.L.1.0.130
###################
#specific include directories in kernel space
INCLUDES+=#e.g. -I$(OSAL_DIR)/include \
#Extra Flags Specific in kernel space e.g. include path or debug flags etc. e.g to add an include path EXTRA_CFLAGS += -I$(src)/../include
EXTRA_CFLAGS += $(INCLUDES) -O2 -Wall
EXTRA_LDFLAGS +=-whole-archive

8
target/linux/generic-2.6/files/crypto/ocf/hifn/hifn7751.c
View file

@ -98,6 +98,10 @@ int hifn_maxbatch = 1;
module_param(hifn_maxbatch, int, 0644);
MODULE_PARM_DESC(hifn_maxbatch, "max ops to batch w/o interrupt");
int hifn_cache_linesize = 0x10;
module_param(hifn_cache_linesize, int, 0444);
MODULE_PARM_DESC(hifn_cache_linesize, "PCI config cache line size");
#ifdef MODULE_PARM
char *hifn_pllconfig = NULL;
MODULE_PARM(hifn_pllconfig, "s");
@ -865,6 +869,8 @@ hifn_set_retry(struct hifn_softc *sc)
/* NB: RETRY only responds to 8-bit reads/writes */
pci_write_config_byte(sc->sc_pcidev, HIFN_RETRY_TIMEOUT, 0);
pci_write_config_dword(sc->sc_pcidev, HIFN_TRDY_TIMEOUT, 0);
/* piggy back the cache line setting here */
pci_write_config_byte(sc->sc_pcidev, PCI_CACHE_LINE_SIZE, hifn_cache_linesize);
}
/*
@ -2966,5 +2972,5 @@ module_init(hifn_init);
module_exit(hifn_exit);
MODULE_LICENSE("BSD");
MODULE_AUTHOR("David McCullough <david_mccullough@securecomputing.com>");
MODULE_AUTHOR("David McCullough <david_mccullough@mcafee.com>");
MODULE_DESCRIPTION("OCF driver for hifn PCI crypto devices");

10
target/linux/generic-2.6/files/crypto/ocf/ixp4xx/ixp4xx.c
View file

@ -3,8 +3,8 @@
* This driver requires the IXP400 Access Library that is available
* from Intel in order to operate (or compile).
*
* Written by David McCullough <david_mccullough@securecomputing.com>
* Copyright (C) 2006-2007 David McCullough
* Written by David McCullough <david_mccullough@mcafee.com>
* Copyright (C) 2006-2010 David McCullough
* Copyright (C) 2004-2005 Intel Corporation.
*
* LICENSE TERMS
@ -373,9 +373,6 @@ ixp_freesession(device_t dev, u_int64_t tid)
ixCryptoAccCtxUnregister(ixp_sessions[sid]->ixp_ctx_id);
ixp_sessions[sid]->ixp_ctx_id = -1;
}
flush_scheduled_work();
kfree(ixp_sessions[sid]);
}
ixp_sessions[sid] = NULL;
@ -595,8 +592,7 @@ ixp_process_pending(void *arg)
static void
ixp_process_pending_wq(struct work_struct *work)
{
struct ixp_data *ixp = container_of(work, struct ixp_data,
ixp_pending_work);
struct ixp_data *ixp = container_of(work, struct ixp_data, ixp_pending_work);
ixp_process_pending(ixp);
}
#endif

19
target/linux/generic-2.6/files/crypto/ocf/kirkwood/Makefile Normal file
View file

@ -0,0 +1,19 @@
# for SGlinux builds
-include $(ROOTDIR)/modules/.config
obj-$(CONFIG_OCF_KIRKWOOD) += mv_cesa.o
mv_cesa-y := cesa/mvCesa.o cesa/mvLru.o cesa/mvMD5.o cesa/mvSHA1.o cesa/AES/mvAesAlg.o cesa/AES/mvAesApi.o cesa/mvCesaDebug.o cesa_ocf_drv.o
# Extra objects required by the CESA driver
mv_cesa-y += mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.o mvHal/kw_family/boardEnv/mvBoardEnvLib.o mvHal/mv_hal/twsi/mvTwsi.o mvHal/kw_family/ctrlEnv/sys/mvCpuIf.o mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.o mvHal/kw_family/ctrlEnv/sys/mvSysDram.o mvHal/linux_oss/mvOs.o mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.o mvHal/mv_hal/gpp/mvGpp.o mvHal/kw_family/ctrlEnv/sys/mvSysPex.o mvHal/mv_hal/pex/mvPex.o mvHal/kw_family/boardEnv/mvBoardEnvSpec.o mvHal/common/mvCommon.o mvHal/common/mvDebug.o mvHal/kw_family/ctrlEnv/sys/mvSysCesa.o
ifdef src
EXTRA_CFLAGS += -I$(src)/.. -I$(src)/cesa -I$(src)/mvHal -I$(src)/mvHal/common -I$(src)/mvHal/kw_family -I$(src)/mvHal/mv_hal -I$(src)/mvHal/linux_oss -I$(src)
endif
EXTRA_CFLAGS += -DMV_LINUX -DMV_CPU_LE -DMV_ARM -DMV_INCLUDE_CESA -DMV_INCLUDE_PEX -DMV_CACHE_COHERENCY=3
ifdef TOPDIR
-include $(TOPDIR)/Rules.make
endif

62
target/linux/generic-2.6/files/crypto/ocf/kirkwood/cesa/AES/mvAes.h Normal file
View file

@ -0,0 +1,62 @@
/* mvAes.h v2.0 August '99
* Reference ANSI C code
*/
/* AES Cipher header file for ANSI C Submissions
Lawrence E. Bassham III
Computer Security Division
National Institute of Standards and Technology
April 15, 1998
This sample is to assist implementers developing to the Cryptographic
API Profile for AES Candidate Algorithm Submissions. Please consult this
document as a cross-reference.
ANY CHANGES, WHERE APPROPRIATE, TO INFORMATION PROVIDED IN THIS FILE
MUST BE DOCUMENTED. CHANGES ARE ONLY APPROPRIATE WHERE SPECIFIED WITH
THE STRING "CHANGE POSSIBLE". FUNCTION CALLS AND THEIR PARAMETERS CANNOT
BE CHANGED. STRUCTURES CAN BE ALTERED TO ALLOW IMPLEMENTERS TO INCLUDE
IMPLEMENTATION SPECIFIC INFORMATION.
*/
/* Includes:
Standard include files
*/
#include "mvOs.h"
/* Error Codes - CHANGE POSSIBLE: inclusion of additional error codes */
/* Key direction is invalid, e.g., unknown value */
#define AES_BAD_KEY_DIR -1
/* Key material not of correct length */
#define AES_BAD_KEY_MAT -2
/* Key passed is not valid */
#define AES_BAD_KEY_INSTANCE -3
/* Params struct passed to cipherInit invalid */
#define AES_BAD_CIPHER_MODE -4
/* Cipher in wrong state (e.g., not initialized) */
#define AES_BAD_CIPHER_STATE -5
#define AES_BAD_CIPHER_INSTANCE -7
/* Function protoypes */
/* CHANGED: makeKey(): parameter blockLen added
this parameter is absolutely necessary if you want to
setup the round keys in a variable block length setting
cipherInit(): parameter blockLen added (for obvious reasons)
*/
int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen);
int aesBlockEncrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen,
MV_U32 *plain, int numBlocks, MV_U32 *cipher);
int aesBlockDecrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen,
MV_U32 *plain, int numBlocks, MV_U32 *cipher);

317
target/linux/generic-2.6/files/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c Normal file
View file

@ -0,0 +1,317 @@
/* rijndael-alg-ref.c v2.0 August '99
* Reference ANSI C code
* authors: Paulo Barreto
* Vincent Rijmen, K.U.Leuven
*
* This code is placed in the public domain.
*/
#include "mvOs.h"
#include "mvAesAlg.h"
#include "mvAesBoxes.dat"
MV_U8 mul1(MV_U8 aa, MV_U8 bb);
void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC);
void ShiftRow128Enc(MV_U8 a[4][MAXBC]);
void ShiftRow128Dec(MV_U8 a[4][MAXBC]);
void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]);
void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]);
void InvMixColumn(MV_U8 a[4][MAXBC]);
#define mul(aa, bb) (mask[bb] & Alogtable[aa + Logtable[bb]])
MV_U8 mul1(MV_U8 aa, MV_U8 bb)
{
return mask[bb] & Alogtable[aa + Logtable[bb]];
}
void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC)
{
/* Exor corresponding text input and round key input bytes
*/
((MV_U32*)(&(a[0][0])))[0] ^= ((MV_U32*)(&(rk[0][0])))[0];
((MV_U32*)(&(a[1][0])))[0] ^= ((MV_U32*)(&(rk[1][0])))[0];
((MV_U32*)(&(a[2][0])))[0] ^= ((MV_U32*)(&(rk[2][0])))[0];
((MV_U32*)(&(a[3][0])))[0] ^= ((MV_U32*)(&(rk[3][0])))[0];
}
void ShiftRow128Enc(MV_U8 a[4][MAXBC]) {
/* Row 0 remains unchanged
* The other three rows are shifted a variable amount
*/
MV_U8 tmp[MAXBC];
tmp[0] = a[1][1];
tmp[1] = a[1][2];
tmp[2] = a[1][3];
tmp[3] = a[1][0];
((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0];
/*
a[1][0] = tmp[0];
a[1][1] = tmp[1];
a[1][2] = tmp[2];
a[1][3] = tmp[3];
*/
tmp[0] = a[2][2];
tmp[1] = a[2][3];
tmp[2] = a[2][0];
tmp[3] = a[2][1];
((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0];
/*
a[2][0] = tmp[0];
a[2][1] = tmp[1];
a[2][2] = tmp[2];
a[2][3] = tmp[3];
*/
tmp[0] = a[3][3];
tmp[1] = a[3][0];
tmp[2] = a[3][1];
tmp[3] = a[3][2];
((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0];
/*
a[3][0] = tmp[0];
a[3][1] = tmp[1];
a[3][2] = tmp[2];
a[3][3] = tmp[3];
*/
}
void ShiftRow128Dec(MV_U8 a[4][MAXBC]) {
/* Row 0 remains unchanged
* The other three rows are shifted a variable amount
*/
MV_U8 tmp[MAXBC];
tmp[0] = a[1][3];
tmp[1] = a[1][0];
tmp[2] = a[1][1];
tmp[3] = a[1][2];
((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0];
/*
a[1][0] = tmp[0];
a[1][1] = tmp[1];
a[1][2] = tmp[2];
a[1][3] = tmp[3];
*/
tmp[0] = a[2][2];
tmp[1] = a[2][3];
tmp[2] = a[2][0];
tmp[3] = a[2][1];
((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0];
/*
a[2][0] = tmp[0];
a[2][1] = tmp[1];
a[2][2] = tmp[2];
a[2][3] = tmp[3];
*/
tmp[0] = a[3][1];
tmp[1] = a[3][2];
tmp[2] = a[3][3];
tmp[3] = a[3][0];
((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0];
/*
a[3][0] = tmp[0];
a[3][1] = tmp[1];
a[3][2] = tmp[2];
a[3][3] = tmp[3];
*/
}
void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]) {
/* Replace every byte of the input by the byte at that place
* in the nonlinear S-box
*/
int i, j;
for(i = 0; i < 4; i++)
for(j = 0; j < 4; j++) a[i][j] = box[a[i][j]] ;
}
void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]) {
/* Mix the four bytes of every column in a linear way
*/
MV_U8 b[4][MAXBC];
int i, j;
for(j = 0; j < 4; j++){
b[0][j] = mul(25,a[0][j]) ^ mul(1,a[1][j]) ^ a[2][j] ^ a[3][j];
b[1][j] = mul(25,a[1][j]) ^ mul(1,a[2][j]) ^ a[3][j] ^ a[0][j];
b[2][j] = mul(25,a[2][j]) ^ mul(1,a[3][j]) ^ a[0][j] ^ a[1][j];
b[3][j] = mul(25,a[3][j]) ^ mul(1,a[0][j]) ^ a[1][j] ^ a[2][j];
}
for(i = 0; i < 4; i++)
/*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/
((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0] ^ ((MV_U32*)(&(rk[i][0])))[0];;
}
void InvMixColumn(MV_U8 a[4][MAXBC]) {
/* Mix the four bytes of every column in a linear way
* This is the opposite operation of Mixcolumn
*/
MV_U8 b[4][MAXBC];
int i, j;
for(j = 0; j < 4; j++){
b[0][j] = mul(223,a[0][j]) ^ mul(104,a[1][j]) ^ mul(238,a[2][j]) ^ mul(199,a[3][j]);
b[1][j] = mul(223,a[1][j]) ^ mul(104,a[2][j]) ^ mul(238,a[3][j]) ^ mul(199,a[0][j]);
b[2][j] = mul(223,a[2][j]) ^ mul(104,a[3][j]) ^ mul(238,a[0][j]) ^ mul(199,a[1][j]);
b[3][j] = mul(223,a[3][j]) ^ mul(104,a[0][j]) ^ mul(238,a[1][j]) ^ mul(199,a[2][j]);
}
for(i = 0; i < 4; i++)
/*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/
((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0];
}
int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 W[MAXROUNDS+1][4][MAXBC])
{
/* Calculate the necessary round keys
* The number of calculations depends on keyBits and blockBits
*/
int KC, BC, ROUNDS;
int i, j, t, rconpointer = 0;
MV_U8 tk[4][MAXKC];
switch (keyBits) {
case 128: KC = 4; break;
case 192: KC = 6; break;
case 256: KC = 8; break;
default : return (-1);
}
switch (blockBits) {
case 128: BC = 4; break;
case 192: BC = 6; break;
case 256: BC = 8; break;
default : return (-2);
}
switch (keyBits >= blockBits ? keyBits : blockBits) {
case 128: ROUNDS = 10; break;
case 192: ROUNDS = 12; break;
case 256: ROUNDS = 14; break;
default : return (-3); /* this cannot happen */
}
for(j = 0; j < KC; j++)
for(i = 0; i < 4; i++)
tk[i][j] = k[i][j];
t = 0;
/* copy values into round key array */
for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++)
for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j];
while (t < (ROUNDS+1)*BC) { /* while not enough round key material calculated */
/* calculate new values */
for(i = 0; i < 4; i++)
tk[i][0] ^= S[tk[(i+1)%4][KC-1]];
tk[0][0] ^= rcon[rconpointer++];
if (KC != 8)
for(j = 1; j < KC; j++)
for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1];
else {
for(j = 1; j < KC/2; j++)
for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1];
for(i = 0; i < 4; i++) tk[i][KC/2] ^= S[tk[i][KC/2 - 1]];
for(j = KC/2 + 1; j < KC; j++)
for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1];
}
/* copy values into round key array */
for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++)
for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j];
}
return 0;
}
int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds)
{
/* Encryption of one block.
*/
int r, BC, ROUNDS;
BC = 4;
ROUNDS = rounds;
/* begin with a key addition
*/
KeyAddition(a,rk[0],BC);
/* ROUNDS-1 ordinary rounds
*/
for(r = 1; r < ROUNDS; r++) {
Substitution(a,S);
ShiftRow128Enc(a);
MixColumn(a, rk[r]);
/*KeyAddition(a,rk[r],BC);*/
}
/* Last round is special: there is no MixColumn
*/
Substitution(a,S);
ShiftRow128Enc(a);
KeyAddition(a,rk[ROUNDS],BC);
return 0;
}
int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds)
{
int r, BC, ROUNDS;
BC = 4;
ROUNDS = rounds;
/* To decrypt: apply the inverse operations of the encrypt routine,
* in opposite order
*
* (KeyAddition is an involution: it 's equal to its inverse)
* (the inverse of Substitution with table S is Substitution with the inverse table of S)
* (the inverse of Shiftrow is Shiftrow over a suitable distance)
*/
/* First the special round:
* without InvMixColumn
* with extra KeyAddition
*/
KeyAddition(a,rk[ROUNDS],BC);
ShiftRow128Dec(a);
Substitution(a,Si);
/* ROUNDS-1 ordinary rounds
*/
for(r = ROUNDS-1; r > 0; r--) {
KeyAddition(a,rk[r],BC);
InvMixColumn(a);
ShiftRow128Dec(a);
Substitution(a,Si);
}
/* End with the extra key addition
*/
KeyAddition(a,rk[0],BC);
return 0;
}

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/* rijndael-alg-ref.h v2.0 August '99
* Reference ANSI C code
* authors: Paulo Barreto
* Vincent Rijmen, K.U.Leuven
*/
#ifndef __RIJNDAEL_ALG_H
#define __RIJNDAEL_ALG_H
#define MAXBC (128/32)
#define MAXKC (256/32)
#define MAXROUNDS 14
int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 rk[MAXROUNDS+1][4][MAXBC]);
int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds);
int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds);
#endif /* __RIJNDAEL_ALG_H */

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/* rijndael-api-ref.c v2.1 April 2000
* Reference ANSI C code
* authors: v2.0 Paulo Barreto
* Vincent Rijmen, K.U.Leuven
* v2.1 Vincent Rijmen, K.U.Leuven
*
* This code is placed in the public domain.
*/
#include "mvOs.h"
#include "mvAes.h"
#include "mvAesAlg.h"
/* Defines:
Add any additional defines you need
*/
#define MODE_ECB 1 /* Are we ciphering in ECB mode? */
#define MODE_CBC 2 /* Are we ciphering in CBC mode? */
#define MODE_CFB1 3 /* Are we ciphering in 1-bit CFB mode? */
int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen)
{
MV_U8 W[MAXROUNDS+1][4][MAXBC];
MV_U8 k[4][MAXKC];
MV_U8 j;
int i, rounds, KC;
if (expandedKey == NULL)
{
return AES_BAD_KEY_INSTANCE;
}
if (!((keyLen == 128) || (keyLen == 192) || (keyLen == 256)))
{
return AES_BAD_KEY_MAT;
}
if (keyMaterial == NULL)
{
return AES_BAD_KEY_MAT;
}
/* initialize key schedule: */
for(i=0; i<keyLen/8; i++)
{
j = keyMaterial[i];
k[i % 4][i / 4] = j;
}
rijndaelKeySched (k, keyLen, blockLen, W);
#ifdef MV_AES_DEBUG
{
MV_U8* pW = &W[0][0][0];
int x;
mvOsPrintf("Expended Key: size = %d\n", sizeof(W));
for(i=0; i<sizeof(W); i++)
{
mvOsPrintf("%02x ", pW[i]);
}
for(i=0; i<MAXROUNDS+1; i++)
{
mvOsPrintf("\n Round #%02d: ", i);
for(x=0; x<MAXBC; x++)
{
mvOsPrintf("%02x%02x%02x%02x ",
W[i][0][x], W[i][1][x], W[i][2][x], W[i][3][x]);
}
mvOsPrintf("\n");
}
}
#endif /* MV_AES_DEBUG */
switch (keyLen)
{
case 128:
rounds = 10;
KC = 4;
break;
case 192:
rounds = 12;
KC = 6;
break;
case 256:
rounds = 14;
KC = 8;
break;
default :
return (-1);
}
for(i=0; i<MAXBC; i++)
{
for(j=0; j<4; j++)
{
expandedKey[i*4+j] = W[rounds][j][i];
}
}
for(; i<KC; i++)
{
for(j=0; j<4; j++)
{
expandedKey[i*4+j] = W[rounds-1][j][i+MAXBC-KC];
}
}
return 0;
}
int aesBlockEncrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen,
MV_U32 *plain, int numBlocks, MV_U32 *cipher)
{
int i, j, t;
MV_U8 block[4][MAXBC];
int rounds;
char *input, *outBuffer;
input = (char*)plain;
outBuffer = (char*)cipher;
/* check parameter consistency: */
if( (expandedKey == NULL) || ((keyLen != 128) && (keyLen != 192) && (keyLen != 256)))
{
return AES_BAD_KEY_MAT;
}
if ((mode != MODE_ECB && mode != MODE_CBC))
{
return AES_BAD_CIPHER_STATE;
}
switch (keyLen)
{
case 128: rounds = 10; break;
case 192: rounds = 12; break;
case 256: rounds = 14; break;
default : return (-3); /* this cannot happen */
}
switch (mode)
{
case MODE_ECB:
for (i = 0; i < numBlocks; i++)
{
for (j = 0; j < 4; j++)
{
for(t = 0; t < 4; t++)
/* parse input stream into rectangular array */
block[t][j] = input[16*i+4*j+t] & 0xFF;
}
rijndaelEncrypt128(block, (MV_U8 (*)[4][MAXBC])expandedKey, rounds);
for (j = 0; j < 4; j++)
{
/* parse rectangular array into output ciphertext bytes */
for(t = 0; t < 4; t++)
outBuffer[16*i+4*j+t] = (MV_U8) block[t][j];
}
}
break;
case MODE_CBC:
for (j = 0; j < 4; j++)
{
for(t = 0; t < 4; t++)
/* parse initial value into rectangular array */
block[t][j] = IV[t+4*j] & 0xFF;
}
for (i = 0; i < numBlocks; i++)
{
for (j = 0; j < 4; j++)
{
for(t = 0; t < 4; t++)
/* parse input stream into rectangular array and exor with
IV or the previous ciphertext */
block[t][j] ^= input[16*i+4*j+t] & 0xFF;
}
rijndaelEncrypt128(block, (MV_U8 (*)[4][MAXBC])expandedKey, rounds);
for (j = 0; j < 4; j++)
{
/* parse rectangular array into output ciphertext bytes */
for(t = 0; t < 4; t++)
outBuffer[16*i+4*j+t] = (MV_U8) block[t][j];
}
}
break;
default: return AES_BAD_CIPHER_STATE;
}
return 0;
}
int aesBlockDecrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen,
MV_U32 *srcData, int numBlocks, MV_U32 *dstData)
{
int i, j, t;
MV_U8 block[4][MAXBC];
MV_U8 iv[4][MAXBC];
int rounds;
char *input, *outBuffer;
input = (char*)srcData;
outBuffer = (char*)dstData;
if (expandedKey == NULL)
{
return AES_BAD_KEY_MAT;
}
/* check parameter consistency: */
if (keyLen != 128 && keyLen != 192 && keyLen != 256)
{
return AES_BAD_KEY_MAT;
}
if ((mode != MODE_ECB && mode != MODE_CBC))
{
return AES_BAD_CIPHER_STATE;
}
switch (keyLen)
{
case 128: rounds = 10; break;
case 192: rounds = 12; break;
case 256: rounds = 14; break;
default : return (-3); /* this cannot happen */
}
switch (mode)
{
case MODE_ECB:
for (i = 0; i < numBlocks; i++)
{
for (j = 0; j < 4; j++)
{
for(t = 0; t < 4; t++)
{
/* parse input stream into rectangular array */
block[t][j] = input[16*i+4*j+t] & 0xFF;
}
}
rijndaelDecrypt128(block, (MV_U8 (*)[4][MAXBC])expandedKey, rounds);
for (j = 0; j < 4; j++)
{
/* parse rectangular array into output ciphertext bytes */
for(t = 0; t < 4; t++)
outBuffer[16*i+4*j+t] = (MV_U8) block[t][j];
}
}
break;
case MODE_CBC:
/* first block */
for (j = 0; j < 4; j++)
{
for(t = 0; t < 4; t++)
{
/* parse input stream into rectangular array */
block[t][j] = input[4*j+t] & 0xFF;
iv[t][j] = block[t][j];
}
}
rijndaelDecrypt128(block, (MV_U8 (*)[4][MAXBC])expandedKey, rounds);
for (j = 0; j < 4; j++)
{
/* exor the IV and parse rectangular array into output ciphertext bytes */
for(t = 0; t < 4; t++)
{
outBuffer[4*j+t] = (MV_U8) (block[t][j] ^ IV[t+4*j]);
IV[t+4*j] = iv[t][j];
}
}
/* next blocks */
for (i = 1; i < numBlocks; i++)
{
for (j = 0; j < 4; j++)
{
for(t = 0; t < 4; t++)
{
/* parse input stream into rectangular array */
iv[t][j] = input[16*i+4*j+t] & 0xFF;
block[t][j] = iv[t][j];
}
}
rijndaelDecrypt128(block, (MV_U8 (*)[4][MAXBC])expandedKey, rounds);
for (j = 0; j < 4; j++)
{
/* exor previous ciphertext block and parse rectangular array
into output ciphertext bytes */
for(t = 0; t < 4; t++)
{
outBuffer[16*i+4*j+t] = (MV_U8) (block[t][j] ^ IV[t+4*j]);
IV[t+4*j] = iv[t][j];
}
}
}
break;
default: return AES_BAD_CIPHER_STATE;
}
return 0;
}

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target/linux/generic-2.6/files/crypto/ocf/kirkwood/cesa/mvCesa.h Normal file
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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/*******************************************************************************
* mvCesa.h - Header File for Cryptographic Engines and Security Accelerator
*
* DESCRIPTION:
* This header file contains macros typedefs and function declaration for
* the Marvell Cryptographic Engines and Security Accelerator.
*
*******************************************************************************/
#ifndef __mvCesa_h__
#define __mvCesa_h__
#include "mvOs.h"
#include "mvCommon.h"
#include "mvDebug.h"
#include "ctrlEnv/mvCtrlEnvSpec.h"
#include "cesa/mvMD5.h"
#include "cesa/mvSHA1.h"
#include "cesa/mvCesa.h"
#include "cesa/AES/mvAes.h"
#include "mvSysHwConfig.h"
#ifdef MV_INCLUDE_IDMA
#include "idma/mvIdma.h"
#include "idma/mvIdmaRegs.h"
#else
/* Redefine MV_DMA_DESC structure */
typedef struct _mvDmaDesc
{
MV_U32 byteCnt; /* The total number of bytes to transfer */
MV_U32 phySrcAdd; /* The physical source address */
MV_U32 phyDestAdd; /* The physical destination address */
MV_U32 phyNextDescPtr; /* If we are using chain mode DMA transfer, */
/* then this pointer should point to the */
/* physical address of the next descriptor, */
/* otherwise it should be NULL. */
}MV_DMA_DESC;
#endif /* MV_INCLUDE_IDMA */
#include "cesa/mvCesaRegs.h"
#define MV_CESA_AUTH_BLOCK_SIZE 64 /* bytes */
#define MV_CESA_MD5_DIGEST_SIZE 16 /* bytes */
#define MV_CESA_SHA1_DIGEST_SIZE 20 /* bytes */
#define MV_CESA_MAX_DIGEST_SIZE MV_CESA_SHA1_DIGEST_SIZE
#define MV_CESA_DES_KEY_LENGTH 8 /* bytes = 64 bits */
#define MV_CESA_3DES_KEY_LENGTH 24 /* bytes = 192 bits */
#define MV_CESA_AES_128_KEY_LENGTH 16 /* bytes = 128 bits */
#define MV_CESA_AES_192_KEY_LENGTH 24 /* bytes = 192 bits */
#define MV_CESA_AES_256_KEY_LENGTH 32 /* bytes = 256 bits */
#define MV_CESA_MAX_CRYPTO_KEY_LENGTH MV_CESA_AES_256_KEY_LENGTH
#define MV_CESA_DES_BLOCK_SIZE 8 /* bytes = 64 bits */
#define MV_CESA_3DES_BLOCK_SIZE 8 /* bytes = 64 bits */
#define MV_CESA_AES_BLOCK_SIZE 16 /* bytes = 128 bits */
#define MV_CESA_MAX_IV_LENGTH MV_CESA_AES_BLOCK_SIZE
#define MV_CESA_MAX_MAC_KEY_LENGTH 64 /* bytes */
typedef struct
{
MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH];
MV_U8 macKey[MV_CESA_MAX_MAC_KEY_LENGTH];
MV_CESA_OPERATION operation;
MV_CESA_DIRECTION direction;
MV_CESA_CRYPTO_ALG cryptoAlgorithm;
MV_CESA_CRYPTO_MODE cryptoMode;
MV_U8 cryptoKeyLength;
MV_CESA_MAC_MODE macMode;
MV_U8 macKeyLength;
MV_U8 digestSize;
} MV_CESA_OPEN_SESSION;
typedef struct
{
MV_BUF_INFO *pFrags;
MV_U16 numFrags;
MV_U16 mbufSize;
} MV_CESA_MBUF;
typedef struct
{
void* pReqPrv; /* instead of reqId */
MV_U32 retCode;
MV_16 sessionId;
} MV_CESA_RESULT;
typedef void (*MV_CESA_CALLBACK) (MV_CESA_RESULT* pResult);
typedef struct
{
void* pReqPrv; /* instead of reqId */
MV_CESA_MBUF* pSrc;
MV_CESA_MBUF* pDst;
MV_CESA_CALLBACK* pFuncCB;
MV_16 sessionId;
MV_U16 ivFromUser;
MV_U16 ivOffset;
MV_U16 cryptoOffset;
MV_U16 cryptoLength;
MV_U16 digestOffset;
MV_U16 macOffset;
MV_U16 macLength;
MV_BOOL skipFlush;
} MV_CESA_COMMAND;
MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, void *osHandle);
MV_STATUS mvCesaFinish (void);
MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid);
MV_STATUS mvCesaSessionClose(short sid);
MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize);
MV_STATUS mvCesaAction (MV_CESA_COMMAND* pCmd);
MV_U32 mvCesaInProcessGet(void);
MV_STATUS mvCesaReadyDispatch(void);
MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult);
MV_BOOL mvCesaIsReady(void);
int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset);
MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDst, MV_CESA_MBUF* pSrcMbuf,
int offset, int size);
MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrc, MV_CESA_MBUF* pDstMbuf,
int offset, int size);
MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset,
MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size);
/********** Debug functions ********/
void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size);
void mvCesaDebugSA(short sid, int mode);
void mvCesaDebugStats(void);
void mvCesaDebugStatsClear(void);
void mvCesaDebugRegs(void);
void mvCesaDebugStatus(void);
void mvCesaDebugQueue(int mode);
void mvCesaDebugSram(int mode);
void mvCesaDebugSAD(int mode);
/******** CESA Private definitions ********/
#if (MV_CESA_VERSION >= 2)
#if (MV_CACHE_COHERENCY == MV_CACHE_COHER_SW)
#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_128B) \
| MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \
| MV_CESA_TDMA_OUTSTAND_READ_EN_MASK \
| MV_CESA_TDMA_NO_BYTE_SWAP_MASK \
| MV_CESA_TDMA_ENABLE_MASK
#else
#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_32B) \
| MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \
/*| MV_CESA_TDMA_OUTSTAND_READ_EN_MASK */\
| MV_CESA_TDMA_ENABLE_MASK
#endif
#else
#define MV_CESA_IDMA_CTRL_LOW_VALUE ICCLR_DST_BURST_LIM_128BYTE \
| ICCLR_SRC_BURST_LIM_128BYTE \
| ICCLR_INT_MODE_MASK \
| ICCLR_BLOCK_MODE \
| ICCLR_CHAN_ENABLE \
| ICCLR_DESC_MODE_16M
#endif /* MV_CESA_VERSION >= 2 */
#define MV_CESA_MAX_PKT_SIZE (64 * 1024)
#define MV_CESA_MAX_MBUF_FRAGS 20
#define MV_CESA_MAX_REQ_FRAGS ( (MV_CESA_MAX_PKT_SIZE / MV_CESA_MAX_BUF_SIZE) + 1)
#define MV_CESA_MAX_DMA_DESC (MV_CESA_MAX_MBUF_FRAGS*2 + 5)
#define MAX_CESA_CHAIN_LENGTH 20
typedef enum
{
MV_CESA_IDLE = 0,
MV_CESA_PENDING,
MV_CESA_PROCESS,
MV_CESA_READY,
#if (MV_CESA_VERSION >= 3)
MV_CESA_CHAIN,
#endif
} MV_CESA_STATE;
/* Session database */
/* Map of Key materials of the session in SRAM.
* Each field must be 8 byte aligned
* Total size: 32 + 24 + 24 = 80 bytes
*/
typedef struct
{
MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH];
MV_U8 macInnerIV[MV_CESA_MAX_DIGEST_SIZE];
MV_U8 reservedInner[4];
MV_U8 macOuterIV[MV_CESA_MAX_DIGEST_SIZE];
MV_U8 reservedOuter[4];
} MV_CESA_SRAM_SA;
typedef struct
{
MV_CESA_SRAM_SA* pSramSA;
MV_U32 config;
MV_U8 cryptoKeyLength;
MV_U8 cryptoIvSize;
MV_U8 cryptoBlockSize;
MV_U8 digestSize;
MV_U8 macKeyLength;
MV_U8 valid;
MV_U8 ctrMode;
MV_U32 count;
} MV_CESA_SA;
/* DMA list management */
typedef struct
{
MV_DMA_DESC* pDmaFirst;
MV_DMA_DESC* pDmaLast;
} MV_CESA_DMA;
typedef struct
{
MV_U8 numFrag;
MV_U8 nextFrag;
int bufOffset;
int cryptoSize;
int macSize;
int newDigestOffset;
MV_U8 orgDigest[MV_CESA_MAX_DIGEST_SIZE];
} MV_CESA_FRAGS;
/* Request queue */
typedef struct
{
MV_U8 state;
MV_U8 fragMode;
MV_U8 fixOffset;
MV_CESA_COMMAND* pCmd;
MV_CESA_COMMAND* pOrgCmd;
MV_BUF_INFO dmaDescBuf;
MV_CESA_DMA dma[MV_CESA_MAX_REQ_FRAGS];
MV_BUF_INFO cesaDescBuf;
MV_CESA_DESC* pCesaDesc;
MV_CESA_FRAGS frags;
} MV_CESA_REQ;
/* SRAM map */
/* Total SRAM size calculation */
/* SRAM size =
* MV_CESA_MAX_BUF_SIZE +
* sizeof(MV_CESA_DESC) +
* MV_CESA_MAX_IV_LENGTH +
* MV_CESA_MAX_IV_LENGTH +
* MV_CESA_MAX_DIGEST_SIZE +
* sizeof(MV_CESA_SRAM_SA)
* = 1600 + 32 + 16 + 16 + 24 + 80 + 280 (reserved) = 2048 bytes
* = 3200 + 32 + 16 + 16 + 24 + 80 + 728 (reserved) = 4096 bytes
*/
typedef struct
{
MV_U8 buf[MV_CESA_MAX_BUF_SIZE];
MV_CESA_DESC desc;
MV_U8 cryptoIV[MV_CESA_MAX_IV_LENGTH];
MV_U8 tempCryptoIV[MV_CESA_MAX_IV_LENGTH];
MV_U8 tempDigest[MV_CESA_MAX_DIGEST_SIZE+4];
MV_CESA_SRAM_SA sramSA;
} MV_CESA_SRAM_MAP;
typedef struct
{
MV_U32 openedCount;
MV_U32 closedCount;
MV_U32 fragCount;
MV_U32 reqCount;
MV_U32 maxReqCount;
MV_U32 procCount;
MV_U32 readyCount;
MV_U32 notReadyCount;
MV_U32 startCount;
#if (MV_CESA_VERSION >= 3)
MV_U32 maxChainUsage;
#endif
} MV_CESA_STATS;
/* External variables */
extern MV_CESA_STATS cesaStats;
extern MV_CESA_FRAGS cesaFrags;
extern MV_BUF_INFO cesaSramSaBuf;
extern MV_CESA_SA* pCesaSAD;
extern MV_U16 cesaMaxSA;
extern MV_CESA_REQ* pCesaReqFirst;
extern MV_CESA_REQ* pCesaReqLast;
extern MV_CESA_REQ* pCesaReqEmpty;
extern MV_CESA_REQ* pCesaReqProcess;
extern int cesaQueueDepth;
extern int cesaReqResources;
#if (MV_CESA_VERSION>= 3)
extern MV_U32 cesaChainLength;
#endif
extern MV_CESA_SRAM_MAP* cesaSramVirtPtr;
extern MV_U32 cesaSramPhysAddr;
static INLINE MV_ULONG mvCesaVirtToPhys(MV_BUF_INFO* pBufInfo, void* pVirt)
{
return (pBufInfo->bufPhysAddr + ((MV_U8*)pVirt - pBufInfo->bufVirtPtr));
}
/* Additional DEBUG functions */
void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode);
void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode);
void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc);
#endif /* __mvCesa_h__ */

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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "mvOs.h"
#include "mvDebug.h"
#include "cesa/mvMD5.h"
#include "cesa/mvSHA1.h"
#include "cesa/mvCesa.h"
#include "cesa/mvCesaRegs.h"
#include "cesa/AES/mvAes.h"
static const char* mvCesaDebugStateStr(MV_CESA_STATE state)
{
switch(state)
{
case MV_CESA_IDLE:
return "Idle";
case MV_CESA_PENDING:
return "Pend";
case MV_CESA_PROCESS:
return "Proc";
case MV_CESA_READY:
return "Ready";
default:
break;
}
return "Unknown";
}
static const char* mvCesaDebugOperStr(MV_CESA_OPERATION oper)
{
switch(oper)
{
case MV_CESA_MAC_ONLY:
return "MacOnly";
case MV_CESA_CRYPTO_ONLY:
return "CryptoOnly";
case MV_CESA_MAC_THEN_CRYPTO:
return "MacCrypto";
case MV_CESA_CRYPTO_THEN_MAC:
return "CryptoMac";
default:
break;
}
return "Null";
}
static const char* mvCesaDebugCryptoAlgStr(MV_CESA_CRYPTO_ALG cryptoAlg)
{
switch(cryptoAlg)
{
case MV_CESA_CRYPTO_DES:
return "DES";
case MV_CESA_CRYPTO_3DES:
return "3DES";
case MV_CESA_CRYPTO_AES:
return "AES";
default:
break;
}
return "Null";
}
static const char* mvCesaDebugMacModeStr(MV_CESA_MAC_MODE macMode)
{
switch(macMode)
{
case MV_CESA_MAC_MD5:
return "MD5";
case MV_CESA_MAC_SHA1:
return "SHA1";
case MV_CESA_MAC_HMAC_MD5:
return "HMAC-MD5";
case MV_CESA_MAC_HMAC_SHA1:
return "HMAC_SHA1";
default:
break;
}
return "Null";
}
void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode)
{
mvOsPrintf("pCmd=%p, pReqPrv=%p, pSrc=%p, pDst=%p, pCB=%p, sid=%d\n",
pCmd, pCmd->pReqPrv, pCmd->pSrc, pCmd->pDst,
pCmd->pFuncCB, pCmd->sessionId);
mvOsPrintf("isUser=%d, ivOffs=%d, crOffs=%d, crLen=%d, digest=%d, macOffs=%d, macLen=%d\n",
pCmd->ivFromUser, pCmd->ivOffset, pCmd->cryptoOffset, pCmd->cryptoLength,
pCmd->digestOffset, pCmd->macOffset, pCmd->macLength);
}
/* no need to use in tool */
void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size)
{
int frag, len, fragOffset;
if(str != NULL)
mvOsPrintf("%s: pMbuf=%p, numFrags=%d, mbufSize=%d\n",
str, pMbuf, pMbuf->numFrags, pMbuf->mbufSize);
frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset);
if(frag == MV_INVALID)
{
mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset);
return;
}
for(; frag<pMbuf->numFrags; frag++)
{
mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n",
frag, pMbuf->pFrags[frag].bufVirtPtr,
pMbuf->pFrags[frag].bufSize);
if(size > 0)
{
len = MV_MIN(pMbuf->pFrags[frag].bufSize, size);
mvDebugMemDump(pMbuf->pFrags[frag].bufVirtPtr+fragOffset, len, 1);
size -= len;
fragOffset = 0;
}
}
}
void mvCesaDebugRegs(void)
{
mvOsPrintf("\t CESA Registers:\n");
mvOsPrintf("MV_CESA_CMD_REG : 0x%X = 0x%08x\n",
MV_CESA_CMD_REG,
MV_REG_READ( MV_CESA_CMD_REG ) );
mvOsPrintf("MV_CESA_CHAN_DESC_OFFSET_REG : 0x%X = 0x%08x\n",
MV_CESA_CHAN_DESC_OFFSET_REG,
MV_REG_READ(MV_CESA_CHAN_DESC_OFFSET_REG) );
mvOsPrintf("MV_CESA_CFG_REG : 0x%X = 0x%08x\n",
MV_CESA_CFG_REG,
MV_REG_READ( MV_CESA_CFG_REG ) );
mvOsPrintf("MV_CESA_STATUS_REG : 0x%X = 0x%08x\n",
MV_CESA_STATUS_REG,
MV_REG_READ( MV_CESA_STATUS_REG ) );
mvOsPrintf("MV_CESA_ISR_CAUSE_REG : 0x%X = 0x%08x\n",
MV_CESA_ISR_CAUSE_REG,
MV_REG_READ( MV_CESA_ISR_CAUSE_REG ) );
mvOsPrintf("MV_CESA_ISR_MASK_REG : 0x%X = 0x%08x\n",
MV_CESA_ISR_MASK_REG,
MV_REG_READ( MV_CESA_ISR_MASK_REG ) );
#if (MV_CESA_VERSION >= 2)
mvOsPrintf("MV_CESA_TDMA_CTRL_REG : 0x%X = 0x%08x\n",
MV_CESA_TDMA_CTRL_REG,
MV_REG_READ( MV_CESA_TDMA_CTRL_REG ) );
mvOsPrintf("MV_CESA_TDMA_BYTE_COUNT_REG : 0x%X = 0x%08x\n",
MV_CESA_TDMA_BYTE_COUNT_REG,
MV_REG_READ( MV_CESA_TDMA_BYTE_COUNT_REG ) );
mvOsPrintf("MV_CESA_TDMA_SRC_ADDR_REG : 0x%X = 0x%08x\n",
MV_CESA_TDMA_SRC_ADDR_REG,
MV_REG_READ( MV_CESA_TDMA_SRC_ADDR_REG ) );
mvOsPrintf("MV_CESA_TDMA_DST_ADDR_REG : 0x%X = 0x%08x\n",
MV_CESA_TDMA_DST_ADDR_REG,
MV_REG_READ( MV_CESA_TDMA_DST_ADDR_REG ) );
mvOsPrintf("MV_CESA_TDMA_NEXT_DESC_PTR_REG : 0x%X = 0x%08x\n",
MV_CESA_TDMA_NEXT_DESC_PTR_REG,
MV_REG_READ( MV_CESA_TDMA_NEXT_DESC_PTR_REG ) );
mvOsPrintf("MV_CESA_TDMA_CURR_DESC_PTR_REG : 0x%X = 0x%08x\n",
MV_CESA_TDMA_CURR_DESC_PTR_REG,
MV_REG_READ( MV_CESA_TDMA_CURR_DESC_PTR_REG ) );
mvOsPrintf("MV_CESA_TDMA_ERROR_CAUSE_REG : 0x%X = 0x%08x\n",
MV_CESA_TDMA_ERROR_CAUSE_REG,
MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) );
mvOsPrintf("MV_CESA_TDMA_ERROR_MASK_REG : 0x%X = 0x%08x\n",
MV_CESA_TDMA_ERROR_MASK_REG,
MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) );
#endif
}
void mvCesaDebugStatus(void)
{
mvOsPrintf("\n\t CESA Status\n\n");
mvOsPrintf("pReqQ=%p, qDepth=%d, reqSize=%ld bytes, qRes=%d, ",
pCesaReqFirst, cesaQueueDepth, sizeof(MV_CESA_REQ),
cesaReqResources);
#if (MV_CESA_VERSION >= 3)
mvOsPrintf("chainLength=%u\n",cesaChainLength);
#else
mvOsPrintf("\n");
#endif
mvOsPrintf("pSAD=%p, maxSA=%d, sizeSA=%ld bytes\n",
pCesaSAD, cesaMaxSA, sizeof(MV_CESA_SA));
mvOsPrintf("\n");
mvCesaDebugRegs();
mvCesaDebugStats();
mvCesaDebugStatsClear();
}
void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc)
{
mvOsPrintf("config=0x%08x, crSrcOffs=0x%04x, crDstOffs=0x%04x\n",
pDesc->config, pDesc->cryptoSrcOffset, pDesc->cryptoDstOffset);
mvOsPrintf("crLen=0x%04x, crKeyOffs=0x%04x, ivOffs=0x%04x, ivBufOffs=0x%04x\n",
pDesc->cryptoDataLen, pDesc->cryptoKeyOffset,
pDesc->cryptoIvOffset, pDesc->cryptoIvBufOffset);
mvOsPrintf("macSrc=0x%04x, digest=0x%04x, macLen=0x%04x, inIv=0x%04x, outIv=0x%04x\n",
pDesc->macSrcOffset, pDesc->macDigestOffset, pDesc->macDataLen,
pDesc->macInnerIvOffset, pDesc->macOuterIvOffset);
}
void mvCesaDebugQueue(int mode)
{
mvOsPrintf("\n\t CESA Request Queue:\n\n");
mvOsPrintf("pFirstReq=%p, pLastReq=%p, qDepth=%d, reqSize=%ld bytes\n",
pCesaReqFirst, pCesaReqLast, cesaQueueDepth, sizeof(MV_CESA_REQ));
mvOsPrintf("pEmpty=%p, pProcess=%p, qResources=%d\n",
pCesaReqEmpty, pCesaReqProcess,
cesaReqResources);
if(mode != 0)
{
int count = 0;
MV_CESA_REQ* pReq = pCesaReqFirst;
for(count=0; count<cesaQueueDepth; count++)
{
/* Print out requsts */
mvOsPrintf("%02d. pReq=%p, state=%s, frag=0x%x, pCmd=%p, pDma=%p, pDesc=%p\n",
count, pReq, mvCesaDebugStateStr(pReq->state),
pReq->fragMode, pReq->pCmd, pReq->dma[0].pDmaFirst, &pReq->pCesaDesc[0]);
if(pReq->fragMode != MV_CESA_FRAG_NONE)
{
int frag;
mvOsPrintf("pFrags=%p, num=%d, next=%d, bufOffset=%d, cryptoSize=%d, macSize=%d\n",
&pReq->frags, pReq->frags.numFrag, pReq->frags.nextFrag,
pReq->frags.bufOffset, pReq->frags.cryptoSize, pReq->frags.macSize);
for(frag=0; frag<pReq->frags.numFrag; frag++)
{
mvOsPrintf("#%d: pDmaFirst=%p, pDesc=%p\n", frag,
pReq->dma[frag].pDmaFirst, &pReq->pCesaDesc[frag]);
}
}
if(mode > 1)
{
/* Print out Command */
mvCesaDebugCmd(pReq->pCmd, mode);
/* Print out Descriptor */
mvCesaDebugDescriptor(&pReq->pCesaDesc[0]);
}
pReq++;
}
}
}
void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode)
{
if(pSramSA == NULL)
{
mvOsPrintf("cesaSramSA: Unexpected pSramSA=%p\n", pSramSA);
return;
}
mvOsPrintf("pSramSA=%p, sizeSramSA=%ld bytes\n",
pSramSA, sizeof(MV_CESA_SRAM_SA));
if(mode != 0)
{
mvOsPrintf("cryptoKey=%p, maxCryptoKey=%d bytes\n",
pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH);
mvDebugMemDump(pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH, 1);
mvOsPrintf("macInnerIV=%p, maxInnerIV=%d bytes\n",
pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE);
mvDebugMemDump(pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE, 1);
mvOsPrintf("macOuterIV=%p, maxOuterIV=%d bytes\n",
pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE);
mvDebugMemDump(pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE, 1);
}
}
void mvCesaDebugSA(short sid, int mode)
{
MV_CESA_OPERATION oper;
MV_CESA_DIRECTION dir;
MV_CESA_CRYPTO_ALG cryptoAlg;
MV_CESA_CRYPTO_MODE cryptoMode;
MV_CESA_MAC_MODE macMode;
MV_CESA_SA* pSA = &pCesaSAD[sid];
if( (pSA->valid) || ((pSA->count != 0) && (mode > 0)) || (mode >= 2) )
{
mvOsPrintf("\n\nCESA SA Entry #%d (%p) - %s (count=%d)\n",
sid, pSA,
pSA->valid ? "Valid" : "Invalid", pSA->count);
oper = (pSA->config & MV_CESA_OPERATION_MASK) >> MV_CESA_OPERATION_OFFSET;
dir = (pSA->config & MV_CESA_DIRECTION_MASK) >> MV_CESA_DIRECTION_BIT;
mvOsPrintf("%s - %s ", mvCesaDebugOperStr(oper),
(dir == MV_CESA_DIR_ENCODE) ? "Encode" : "Decode");
if(oper != MV_CESA_MAC_ONLY)
{
cryptoAlg = (pSA->config & MV_CESA_CRYPTO_ALG_MASK) >> MV_CESA_CRYPTO_ALG_OFFSET;
cryptoMode = (pSA->config & MV_CESA_CRYPTO_MODE_MASK) >> MV_CESA_CRYPTO_MODE_BIT;
mvOsPrintf("- %s - %s ", mvCesaDebugCryptoAlgStr(cryptoAlg),
(cryptoMode == MV_CESA_CRYPTO_ECB) ? "ECB" : "CBC");
}
if(oper != MV_CESA_CRYPTO_ONLY)
{
macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET;
mvOsPrintf("- %s ", mvCesaDebugMacModeStr(macMode));
}
mvOsPrintf("\n");
if(mode > 0)
{
mvOsPrintf("config=0x%08x, cryptoKeySize=%d, digestSize=%d\n",
pCesaSAD[sid].config, pCesaSAD[sid].cryptoKeyLength,
pCesaSAD[sid].digestSize);
mvCesaDebugSramSA(pCesaSAD[sid].pSramSA, mode);
}
}
}
/**/
void mvCesaDebugSram(int mode)
{
mvOsPrintf("\n\t SRAM contents: size=%ld, pVirt=%p\n\n",
sizeof(MV_CESA_SRAM_MAP), cesaSramVirtPtr);
mvOsPrintf("\n\t Sram buffer: size=%d, pVirt=%p\n",
MV_CESA_MAX_BUF_SIZE, cesaSramVirtPtr->buf);
if(mode != 0)
mvDebugMemDump(cesaSramVirtPtr->buf, 64, 1);
mvOsPrintf("\n");
mvOsPrintf("\n\t Sram descriptor: size=%ld, pVirt=%p\n",
sizeof(MV_CESA_DESC), &cesaSramVirtPtr->desc);
if(mode != 0)
{
mvOsPrintf("\n");
mvCesaDebugDescriptor(&cesaSramVirtPtr->desc);
}
mvOsPrintf("\n\t Sram IV: size=%d, pVirt=%p\n",
MV_CESA_MAX_IV_LENGTH, &cesaSramVirtPtr->cryptoIV);
if(mode != 0)
{
mvOsPrintf("\n");
mvDebugMemDump(cesaSramVirtPtr->cryptoIV, MV_CESA_MAX_IV_LENGTH, 1);
}
mvOsPrintf("\n");
mvCesaDebugSramSA(&cesaSramVirtPtr->sramSA, 0);
}
void mvCesaDebugSAD(int mode)
{
int sid;
mvOsPrintf("\n\t Cesa SAD status: pSAD=%p, maxSA=%d\n",
pCesaSAD, cesaMaxSA);
for(sid=0; sid<cesaMaxSA; sid++)
{
mvCesaDebugSA(sid, mode);
}
}
void mvCesaDebugStats(void)
{
mvOsPrintf("\n\t Cesa Statistics\n");
mvOsPrintf("Opened=%u, Closed=%u\n",
cesaStats.openedCount, cesaStats.closedCount);
mvOsPrintf("Req=%u, maxReq=%u, frags=%u, start=%u\n",
cesaStats.reqCount, cesaStats.maxReqCount,
cesaStats.fragCount, cesaStats.startCount);
#if (MV_CESA_VERSION >= 3)
mvOsPrintf("maxChainUsage=%u\n",cesaStats.maxChainUsage);
#endif
mvOsPrintf("\n");
mvOsPrintf("proc=%u, ready=%u, notReady=%u\n",
cesaStats.procCount, cesaStats.readyCount, cesaStats.notReadyCount);
}
void mvCesaDebugStatsClear(void)
{
memset(&cesaStats, 0, sizeof(cesaStats));
}

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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __mvCesaRegs_h__
#define __mvCesaRegs_h__
#include "mvTypes.h"
typedef struct
{
/* word 0 */
MV_U32 config;
/* word 1 */
MV_U16 cryptoSrcOffset;
MV_U16 cryptoDstOffset;
/* word 2 */
MV_U16 cryptoDataLen;
MV_U16 reserved1;
/* word 3 */
MV_U16 cryptoKeyOffset;
MV_U16 reserved2;
/* word 4 */
MV_U16 cryptoIvOffset;
MV_U16 cryptoIvBufOffset;
/* word 5 */
MV_U16 macSrcOffset;
MV_U16 macTotalLen;
/* word 6 */
MV_U16 macDigestOffset;
MV_U16 macDataLen;
/* word 7 */
MV_U16 macInnerIvOffset;
MV_U16 macOuterIvOffset;
} MV_CESA_DESC;
/* operation */
typedef enum
{
MV_CESA_MAC_ONLY = 0,
MV_CESA_CRYPTO_ONLY = 1,
MV_CESA_MAC_THEN_CRYPTO = 2,
MV_CESA_CRYPTO_THEN_MAC = 3,
MV_CESA_MAX_OPERATION
} MV_CESA_OPERATION;
#define MV_CESA_OPERATION_OFFSET 0
#define MV_CESA_OPERATION_MASK (0x3 << MV_CESA_OPERATION_OFFSET)
/* mac algorithm */
typedef enum
{
MV_CESA_MAC_NULL = 0,
MV_CESA_MAC_MD5 = 4,
MV_CESA_MAC_SHA1 = 5,
MV_CESA_MAC_HMAC_MD5 = 6,
MV_CESA_MAC_HMAC_SHA1 = 7,
} MV_CESA_MAC_MODE;
#define MV_CESA_MAC_MODE_OFFSET 4
#define MV_CESA_MAC_MODE_MASK (0x7 << MV_CESA_MAC_MODE_OFFSET)
typedef enum
{
MV_CESA_MAC_DIGEST_FULL = 0,
MV_CESA_MAC_DIGEST_96B = 1,
} MV_CESA_MAC_DIGEST_SIZE;
#define MV_CESA_MAC_DIGEST_SIZE_BIT 7
#define MV_CESA_MAC_DIGEST_SIZE_MASK (1 << MV_CESA_MAC_DIGEST_SIZE_BIT)
typedef enum
{
MV_CESA_CRYPTO_NULL = 0,
MV_CESA_CRYPTO_DES = 1,
MV_CESA_CRYPTO_3DES = 2,
MV_CESA_CRYPTO_AES = 3,
} MV_CESA_CRYPTO_ALG;
#define MV_CESA_CRYPTO_ALG_OFFSET 8
#define MV_CESA_CRYPTO_ALG_MASK (0x3 << MV_CESA_CRYPTO_ALG_OFFSET)
/* direction */
typedef enum
{
MV_CESA_DIR_ENCODE = 0,
MV_CESA_DIR_DECODE = 1,
} MV_CESA_DIRECTION;
#define MV_CESA_DIRECTION_BIT 12
#define MV_CESA_DIRECTION_MASK (1 << MV_CESA_DIRECTION_BIT)
/* crypto IV mode */
typedef enum
{
MV_CESA_CRYPTO_ECB = 0,
MV_CESA_CRYPTO_CBC = 1,
/* NO HW Support */
MV_CESA_CRYPTO_CTR = 10,
} MV_CESA_CRYPTO_MODE;
#define MV_CESA_CRYPTO_MODE_BIT 16
#define MV_CESA_CRYPTO_MODE_MASK (1 << MV_CESA_CRYPTO_MODE_BIT)
/* 3DES mode */
typedef enum
{
MV_CESA_CRYPTO_3DES_EEE = 0,
MV_CESA_CRYPTO_3DES_EDE = 1,
} MV_CESA_CRYPTO_3DES_MODE;
#define MV_CESA_CRYPTO_3DES_MODE_BIT 20
#define MV_CESA_CRYPTO_3DES_MODE_MASK (1 << MV_CESA_CRYPTO_3DES_MODE_BIT)
/* AES Key Length */
typedef enum
{
MV_CESA_CRYPTO_AES_KEY_128 = 0,
MV_CESA_CRYPTO_AES_KEY_192 = 1,
MV_CESA_CRYPTO_AES_KEY_256 = 2,
} MV_CESA_CRYPTO_AES_KEY_LEN;
#define MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET 24
#define MV_CESA_CRYPTO_AES_KEY_LEN_MASK (0x3 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET)
/* Fragmentation mode */
typedef enum
{
MV_CESA_FRAG_NONE = 0,
MV_CESA_FRAG_FIRST = 1,
MV_CESA_FRAG_LAST = 2,
MV_CESA_FRAG_MIDDLE = 3,
} MV_CESA_FRAG_MODE;
#define MV_CESA_FRAG_MODE_OFFSET 30
#define MV_CESA_FRAG_MODE_MASK (0x3 << MV_CESA_FRAG_MODE_OFFSET)
/*---------------------------------------------------------------------------*/
/********** Security Accelerator Command Register **************/
#define MV_CESA_CMD_REG (MV_CESA_REG_BASE + 0xE00)
#define MV_CESA_CMD_CHAN_ENABLE_BIT 0
#define MV_CESA_CMD_CHAN_ENABLE_MASK (1 << MV_CESA_CMD_CHAN_ENABLE_BIT)
#define MV_CESA_CMD_CHAN_DISABLE_BIT 2
#define MV_CESA_CMD_CHAN_DISABLE_MASK (1 << MV_CESA_CMD_CHAN_DISABLE_BIT)
/********** Security Accelerator Descriptor Pointers Register **********/
#define MV_CESA_CHAN_DESC_OFFSET_REG (MV_CESA_REG_BASE + 0xE04)
/********** Security Accelerator Configuration Register **********/
#define MV_CESA_CFG_REG (MV_CESA_REG_BASE + 0xE08)
#define MV_CESA_CFG_STOP_DIGEST_ERR_BIT 0
#define MV_CESA_CFG_STOP_DIGEST_ERR_MASK (1 << MV_CESA_CFG_STOP_DIGEST_ERR_BIT)
#define MV_CESA_CFG_WAIT_DMA_BIT 7
#define MV_CESA_CFG_WAIT_DMA_MASK (1 << MV_CESA_CFG_WAIT_DMA_BIT)
#define MV_CESA_CFG_ACT_DMA_BIT 9
#define MV_CESA_CFG_ACT_DMA_MASK (1 << MV_CESA_CFG_ACT_DMA_BIT)
#define MV_CESA_CFG_CHAIN_MODE_BIT 11
#define MV_CESA_CFG_CHAIN_MODE_MASK (1 << MV_CESA_CFG_CHAIN_MODE_BIT)
/********** Security Accelerator Status Register ***********/
#define MV_CESA_STATUS_REG (MV_CESA_REG_BASE + 0xE0C)
#define MV_CESA_STATUS_ACTIVE_BIT 0
#define MV_CESA_STATUS_ACTIVE_MASK (1 << MV_CESA_STATUS_ACTIVE_BIT)
#define MV_CESA_STATUS_DIGEST_ERR_BIT 8
#define MV_CESA_STATUS_DIGEST_ERR_MASK (1 << MV_CESA_STATUS_DIGEST_ERR_BIT)
/* Cryptographic Engines and Security Accelerator Interrupt Cause Register */
#define MV_CESA_ISR_CAUSE_REG (MV_CESA_REG_BASE + 0xE20)
/* Cryptographic Engines and Security Accelerator Interrupt Mask Register */
#define MV_CESA_ISR_MASK_REG (MV_CESA_REG_BASE + 0xE24)
#define MV_CESA_CAUSE_AUTH_MASK (1 << 0)
#define MV_CESA_CAUSE_DES_MASK (1 << 1)
#define MV_CESA_CAUSE_AES_ENCR_MASK (1 << 2)
#define MV_CESA_CAUSE_AES_DECR_MASK (1 << 3)
#define MV_CESA_CAUSE_DES_ALL_MASK (1 << 4)
#define MV_CESA_CAUSE_ACC_BIT 5
#define MV_CESA_CAUSE_ACC_MASK (1 << MV_CESA_CAUSE_ACC_BIT)
#define MV_CESA_CAUSE_ACC_DMA_BIT 7
#define MV_CESA_CAUSE_ACC_DMA_MASK (1 << MV_CESA_CAUSE_ACC_DMA_BIT)
#define MV_CESA_CAUSE_ACC_DMA_ALL_MASK (3 << MV_CESA_CAUSE_ACC_DMA_BIT)
#define MV_CESA_CAUSE_DMA_COMPL_BIT 9
#define MV_CESA_CAUSE_DMA_COMPL_MASK (1 << MV_CESA_CAUSE_DMA_COMPL_BIT)
#define MV_CESA_CAUSE_DMA_OWN_ERR_BIT 10
#define MV_CESA_CAUSE_DMA_OWN_ERR_MASK (1 < MV_CESA_CAUSE_DMA_OWN_ERR_BIT)
#define MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT 11
#define MV_CESA_CAUSE_DMA_CHAIN_PKT_MASK (1 < MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT)
#define MV_CESA_AUTH_DATA_IN_REG (MV_CESA_REG_BASE + 0xd38)
#define MV_CESA_AUTH_BIT_COUNT_LOW_REG (MV_CESA_REG_BASE + 0xd20)
#define MV_CESA_AUTH_BIT_COUNT_HIGH_REG (MV_CESA_REG_BASE + 0xd24)
#define MV_CESA_AUTH_INIT_VAL_DIGEST_REG(i) (MV_CESA_REG_BASE + 0xd00 + (i<<2))
#define MV_CESA_AUTH_INIT_VAL_DIGEST_A_REG (MV_CESA_REG_BASE + 0xd00)
#define MV_CESA_AUTH_INIT_VAL_DIGEST_B_REG (MV_CESA_REG_BASE + 0xd04)
#define MV_CESA_AUTH_INIT_VAL_DIGEST_C_REG (MV_CESA_REG_BASE + 0xd08)
#define MV_CESA_AUTH_INIT_VAL_DIGEST_D_REG (MV_CESA_REG_BASE + 0xd0c)
#define MV_CESA_AUTH_INIT_VAL_DIGEST_E_REG (MV_CESA_REG_BASE + 0xd10)
#define MV_CESA_AUTH_COMMAND_REG (MV_CESA_REG_BASE + 0xd18)
#define MV_CESA_AUTH_ALGORITHM_BIT 0
#define MV_CESA_AUTH_ALGORITHM_MD5 (0<<AUTH_ALGORITHM_BIT)
#define MV_CESA_AUTH_ALGORITHM_SHA1 (1<<AUTH_ALGORITHM_BIT)
#define MV_CESA_AUTH_IV_MODE_BIT 1
#define MV_CESA_AUTH_IV_MODE_INIT (0<<AUTH_IV_MODE_BIT)
#define MV_CESA_AUTH_IV_MODE_CONTINUE (1<<AUTH_IV_MODE_BIT)
#define MV_CESA_AUTH_DATA_BYTE_SWAP_BIT 2
#define MV_CESA_AUTH_DATA_BYTE_SWAP_MASK (1<<AUTH_DATA_BYTE_SWAP_BIT)
#define MV_CESA_AUTH_IV_BYTE_SWAP_BIT 4
#define MV_CESA_AUTH_IV_BYTE_SWAP_MASK (1<<AUTH_IV_BYTE_SWAP_BIT)
#define MV_CESA_AUTH_TERMINATION_BIT 31
#define MV_CESA_AUTH_TERMINATION_MASK (1<<AUTH_TERMINATION_BIT)
/*************** TDMA Control Register ************************************************/
#define MV_CESA_TDMA_CTRL_REG (MV_CESA_TDMA_REG_BASE + 0x840)
#define MV_CESA_TDMA_BURST_32B 3
#define MV_CESA_TDMA_BURST_128B 4
#define MV_CESA_TDMA_DST_BURST_OFFSET 0
#define MV_CESA_TDMA_DST_BURST_ALL_MASK (0x7<<MV_CESA_TDMA_DST_BURST_OFFSET)
#define MV_CESA_TDMA_DST_BURST_MASK(burst) ((burst)<<MV_CESA_TDMA_DST_BURST_OFFSET)
#define MV_CESA_TDMA_OUTSTAND_READ_EN_BIT 4
#define MV_CESA_TDMA_OUTSTAND_READ_EN_MASK (1<<MV_CESA_TDMA_OUTSTAND_READ_EN_BIT)
#define MV_CESA_TDMA_SRC_BURST_OFFSET 6
#define MV_CESA_TDMA_SRC_BURST_ALL_MASK (0x7<<MV_CESA_TDMA_SRC_BURST_OFFSET)
#define MV_CESA_TDMA_SRC_BURST_MASK(burst) ((burst)<<MV_CESA_TDMA_SRC_BURST_OFFSET)
#define MV_CESA_TDMA_CHAIN_MODE_BIT 9
#define MV_CESA_TDMA_NON_CHAIN_MODE_MASK (1<<MV_CESA_TDMA_CHAIN_MODE_BIT)
#define MV_CESA_TDMA_BYTE_SWAP_BIT 11
#define MV_CESA_TDMA_BYTE_SWAP_MASK (0 << MV_CESA_TDMA_BYTE_SWAP_BIT)
#define MV_CESA_TDMA_NO_BYTE_SWAP_MASK (1 << MV_CESA_TDMA_BYTE_SWAP_BIT)
#define MV_CESA_TDMA_ENABLE_BIT 12
#define MV_CESA_TDMA_ENABLE_MASK (1<<MV_CESA_TDMA_ENABLE_BIT)
#define MV_CESA_TDMA_FETCH_NEXT_DESC_BIT 13
#define MV_CESA_TDMA_FETCH_NEXT_DESC_MASK (1<<MV_CESA_TDMA_FETCH_NEXT_DESC_BIT)
#define MV_CESA_TDMA_CHAN_ACTIVE_BIT 14
#define MV_CESA_TDMA_CHAN_ACTIVE_MASK (1<<MV_CESA_TDMA_CHAN_ACTIVE_BIT)
/*------------------------------------------------------------------------------------*/
#define MV_CESA_TDMA_BYTE_COUNT_REG (MV_CESA_TDMA_REG_BASE + 0x800)
#define MV_CESA_TDMA_SRC_ADDR_REG (MV_CESA_TDMA_REG_BASE + 0x810)
#define MV_CESA_TDMA_DST_ADDR_REG (MV_CESA_TDMA_REG_BASE + 0x820)
#define MV_CESA_TDMA_NEXT_DESC_PTR_REG (MV_CESA_TDMA_REG_BASE + 0x830)
#define MV_CESA_TDMA_CURR_DESC_PTR_REG (MV_CESA_TDMA_REG_BASE + 0x870)
#define MV_CESA_TDMA_ERROR_CAUSE_REG (MV_CESA_TDMA_REG_BASE + 0x8C0)
#define MV_CESA_TDMA_ERROR_MASK_REG (MV_CESA_TDMA_REG_BASE + 0x8C4)
#endif /* __mvCesaRegs_h__ */

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target/linux/generic-2.6/files/crypto/ocf/kirkwood/cesa/mvLru.c Normal file
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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "mvOs.h"
#include "mvLru.h"
/* LRU Cache support */
/* Init LRU cache database */
MV_LRU_CACHE* mvLruCacheInit(int numOfEntries)
{
int i;
MV_LRU_CACHE* pLruCache;
pLruCache = mvOsMalloc(sizeof(MV_LRU_CACHE));
if(pLruCache == NULL)
{
return NULL;
}
memset(pLruCache, 0, sizeof(MV_LRU_CACHE));
pLruCache->table = mvOsMalloc(numOfEntries*sizeof(MV_LRU_ENTRY));
if(pLruCache->table == NULL)
{
mvOsFree(pLruCache);
return NULL;
}
memset(pLruCache->table, 0, numOfEntries*sizeof(MV_LRU_ENTRY));
pLruCache->tableSize = numOfEntries;
for(i=0; i<numOfEntries; i++)
{
pLruCache->table[i].next = i+1;
pLruCache->table[i].prev = i-1;
}
pLruCache->least = 0;
pLruCache->most = numOfEntries-1;
return pLruCache;
}
void mvLruCacheFinish(MV_LRU_CACHE* pLruCache)
{
mvOsFree(pLruCache->table);
mvOsFree(pLruCache);
}
/* Update LRU cache database after using cache Index */
void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx)
{
int prev, next;
if(cacheIdx == pLruHndl->most)
return;
next = pLruHndl->table[cacheIdx].next;
if(cacheIdx == pLruHndl->least)
{
pLruHndl->least = next;
}
else
{
prev = pLruHndl->table[cacheIdx].prev;
pLruHndl->table[next].prev = prev;
pLruHndl->table[prev].next = next;
}
pLruHndl->table[pLruHndl->most].next = cacheIdx;
pLruHndl->table[cacheIdx].prev = pLruHndl->most;
pLruHndl->most = cacheIdx;
}
/* Delete LRU cache entry */
void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx)
{
int prev, next;
if(cacheIdx == pLruHndl->least)
return;
prev = pLruHndl->table[cacheIdx].prev;
if(cacheIdx == pLruHndl->most)
{
pLruHndl->most = prev;
}
else
{
next = pLruHndl->table[cacheIdx].next;
pLruHndl->table[next].prev = prev;
pLruHndl->table[prev].next = next;
}
pLruHndl->table[pLruHndl->least].prev = cacheIdx;
pLruHndl->table[cacheIdx].next = pLruHndl->least;
pLruHndl->least = cacheIdx;
}

112
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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/*******************************************************************************
* mvLru.h - Header File for Least Recently Used Cache algorithm
*
* DESCRIPTION:
* This header file contains macros typedefs and function declaration for
* the Least Recently Used Cache algorithm.
*
*******************************************************************************/
#ifndef __mvLru_h__
#define __mvLru_h__
typedef struct
{
int next;
int prev;
} MV_LRU_ENTRY;
typedef struct
{
int least;
int most;
MV_LRU_ENTRY* table;
int tableSize;
}MV_LRU_CACHE;
/* Find Cache index for replacement LRU */
static INLINE int mvLruCacheIdxFind(MV_LRU_CACHE* pLruHndl)
{
return pLruHndl->least;
}
/* Init LRU cache module */
MV_LRU_CACHE* mvLruCacheInit(int numOfEntries);
/* Finish LRU cache module */
void mvLruCacheFinish(MV_LRU_CACHE* pLruHndl);
/* Update LRU cache database after using cache Index */
void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx);
/* Delete LRU cache entry */
void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx);
#endif /* __mvLru_h__ */

349
target/linux/generic-2.6/files/crypto/ocf/kirkwood/cesa/mvMD5.c Normal file
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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "mvOs.h"
#include "mvMD5.h"
static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]);
#ifdef MV_CPU_LE
#define mvByteReverse(buf, len) /* Nothing */
#else
static void mvByteReverse(unsigned char *buf, unsigned longs);
/*
* Note: this code is harmless on little-endian machines.
*/
static void mvByteReverse(unsigned char *buf, unsigned longs)
{
MV_U32 t;
do
{
t = (MV_U32) ((unsigned) buf[3] << 8 | buf[2]) << 16 |
((unsigned) buf[1] << 8 | buf[0]);
*(MV_U32 *) buf = t;
buf += 4;
} while (--longs);
}
#endif
/*
* Start MD5 accumulation. Set bit count to 0 and buffer to mysterious
* initialization constants.
*/
void mvMD5Init(MV_MD5_CONTEXT *ctx)
{
ctx->buf[0] = 0x67452301;
ctx->buf[1] = 0xefcdab89;
ctx->buf[2] = 0x98badcfe;
ctx->buf[3] = 0x10325476;
ctx->bits[0] = 0;
ctx->bits[1] = 0;
}
/*
* Update context to reflect the concatenation of another buffer full
* of bytes.
*/
void mvMD5Update(MV_MD5_CONTEXT *ctx, unsigned char const *buf, unsigned len)
{
MV_U32 t;
/* Update bitcount */
t = ctx->bits[0];
if ((ctx->bits[0] = t + ((MV_U32) len << 3)) < t)
ctx->bits[1]++; /* Carry from low to high */
ctx->bits[1] += len >> 29;
t = (t >> 3) & 0x3f; /* Bytes already in shsInfo->data */
/* Handle any leading odd-sized chunks */
if (t)
{
unsigned char *p = (unsigned char *) ctx->in + t;
t = 64 - t;
if (len < t)
{
memcpy(p, buf, len);
return;
}
memcpy(p, buf, t);
mvByteReverse(ctx->in, MV_MD5_MAC_LEN);
mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in);
buf += t;
len -= t;
}
/* Process data in 64-byte chunks */
while (len >= 64)
{
memcpy(ctx->in, buf, 64);
mvByteReverse(ctx->in, MV_MD5_MAC_LEN);
mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in);
buf += 64;
len -= 64;
}
/* Handle any remaining bytes of data. */
memcpy(ctx->in, buf, len);
}
/*
* Final wrapup - pad to 64-byte boundary with the bit pattern
* 1 0* (64-bit count of bits processed, MSB-first)
*/
void mvMD5Final(unsigned char digest[MV_MD5_MAC_LEN], MV_MD5_CONTEXT *ctx)
{
unsigned count;
unsigned char *p;
/* Compute number of bytes mod 64 */
count = (ctx->bits[0] >> 3) & 0x3F;
/* Set the first char of padding to 0x80. This is safe since there is
always at least one byte free */
p = ctx->in + count;
*p++ = 0x80;
/* Bytes of padding needed to make 64 bytes */
count = 64 - 1 - count;
/* Pad out to 56 mod 64 */
if (count < 8)
{
/* Two lots of padding: Pad the first block to 64 bytes */
memset(p, 0, count);
mvByteReverse(ctx->in, MV_MD5_MAC_LEN);
mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in);
/* Now fill the next block with 56 bytes */
memset(ctx->in, 0, 56);
}
else
{
/* Pad block to 56 bytes */
memset(p, 0, count - 8);
}
mvByteReverse(ctx->in, 14);
/* Append length in bits and transform */
((MV_U32 *) ctx->in)[14] = ctx->bits[0];
((MV_U32 *) ctx->in)[15] = ctx->bits[1];
mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in);
mvByteReverse((unsigned char *) ctx->buf, 4);
memcpy(digest, ctx->buf, MV_MD5_MAC_LEN);
memset(ctx, 0, sizeof(ctx)); /* In case it's sensitive */
}
/* The four core functions - F1 is optimized somewhat */
/* #define F1(x, y, z) (x & y | ~x & z) */
#define F1(x, y, z) (z ^ (x & (y ^ z)))
#define F2(x, y, z) F1(z, x, y)
#define F3(x, y, z) (x ^ y ^ z)
#define F4(x, y, z) (y ^ (x | ~z))
/* This is the central step in the MD5 algorithm. */
#define MD5STEP(f, w, x, y, z, data, s) \
( w += f(x, y, z) + data, w = w<<s | w>>(32-s), w += x )
/*
* The core of the MD5 algorithm, this alters an existing MD5 hash to
* reflect the addition of 16 longwords of new data. MD5Update blocks
* the data and converts bytes into longwords for this routine.
*/
static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN])
{
register MV_U32 a, b, c, d;
a = buf[0];
b = buf[1];
c = buf[2];
d = buf[3];
MD5STEP(F1, a, b, c, d, in[0] + 0xd76aa478, 7);
MD5STEP(F1, d, a, b, c, in[1] + 0xe8c7b756, 12);
MD5STEP(F1, c, d, a, b, in[2] + 0x242070db, 17);
MD5STEP(F1, b, c, d, a, in[3] + 0xc1bdceee, 22);
MD5STEP(F1, a, b, c, d, in[4] + 0xf57c0faf, 7);
MD5STEP(F1, d, a, b, c, in[5] + 0x4787c62a, 12);
MD5STEP(F1, c, d, a, b, in[6] + 0xa8304613, 17);
MD5STEP(F1, b, c, d, a, in[7] + 0xfd469501, 22);
MD5STEP(F1, a, b, c, d, in[8] + 0x698098d8, 7);
MD5STEP(F1, d, a, b, c, in[9] + 0x8b44f7af, 12);
MD5STEP(F1, c, d, a, b, in[10] + 0xffff5bb1, 17);
MD5STEP(F1, b, c, d, a, in[11] + 0x895cd7be, 22);
MD5STEP(F1, a, b, c, d, in[12] + 0x6b901122, 7);
MD5STEP(F1, d, a, b, c, in[13] + 0xfd987193, 12);
MD5STEP(F1, c, d, a, b, in[14] + 0xa679438e, 17);
MD5STEP(F1, b, c, d, a, in[15] + 0x49b40821, 22);
MD5STEP(F2, a, b, c, d, in[1] + 0xf61e2562, 5);
MD5STEP(F2, d, a, b, c, in[6] + 0xc040b340, 9);
MD5STEP(F2, c, d, a, b, in[11] + 0x265e5a51, 14);
MD5STEP(F2, b, c, d, a, in[0] + 0xe9b6c7aa, 20);
MD5STEP(F2, a, b, c, d, in[5] + 0xd62f105d, 5);
MD5STEP(F2, d, a, b, c, in[10] + 0x02441453, 9);
MD5STEP(F2, c, d, a, b, in[15] + 0xd8a1e681, 14);
MD5STEP(F2, b, c, d, a, in[4] + 0xe7d3fbc8, 20);
MD5STEP(F2, a, b, c, d, in[9] + 0x21e1cde6, 5);
MD5STEP(F2, d, a, b, c, in[14] + 0xc33707d6, 9);
MD5STEP(F2, c, d, a, b, in[3] + 0xf4d50d87, 14);
MD5STEP(F2, b, c, d, a, in[8] + 0x455a14ed, 20);
MD5STEP(F2, a, b, c, d, in[13] + 0xa9e3e905, 5);
MD5STEP(F2, d, a, b, c, in[2] + 0xfcefa3f8, 9);
MD5STEP(F2, c, d, a, b, in[7] + 0x676f02d9, 14);
MD5STEP(F2, b, c, d, a, in[12] + 0x8d2a4c8a, 20);
MD5STEP(F3, a, b, c, d, in[5] + 0xfffa3942, 4);
MD5STEP(F3, d, a, b, c, in[8] + 0x8771f681, 11);
MD5STEP(F3, c, d, a, b, in[11] + 0x6d9d6122, 16);
MD5STEP(F3, b, c, d, a, in[14] + 0xfde5380c, 23);
MD5STEP(F3, a, b, c, d, in[1] + 0xa4beea44, 4);
MD5STEP(F3, d, a, b, c, in[4] + 0x4bdecfa9, 11);
MD5STEP(F3, c, d, a, b, in[7] + 0xf6bb4b60, 16);
MD5STEP(F3, b, c, d, a, in[10] + 0xbebfbc70, 23);
MD5STEP(F3, a, b, c, d, in[13] + 0x289b7ec6, 4);
MD5STEP(F3, d, a, b, c, in[0] + 0xeaa127fa, 11);
MD5STEP(F3, c, d, a, b, in[3] + 0xd4ef3085, 16);
MD5STEP(F3, b, c, d, a, in[6] + 0x04881d05, 23);
MD5STEP(F3, a, b, c, d, in[9] + 0xd9d4d039, 4);
MD5STEP(F3, d, a, b, c, in[12] + 0xe6db99e5, 11);
MD5STEP(F3, c, d, a, b, in[15] + 0x1fa27cf8, 16);
MD5STEP(F3, b, c, d, a, in[2] + 0xc4ac5665, 23);
MD5STEP(F4, a, b, c, d, in[0] + 0xf4292244, 6);
MD5STEP(F4, d, a, b, c, in[7] + 0x432aff97, 10);
MD5STEP(F4, c, d, a, b, in[14] + 0xab9423a7, 15);
MD5STEP(F4, b, c, d, a, in[5] + 0xfc93a039, 21);
MD5STEP(F4, a, b, c, d, in[12] + 0x655b59c3, 6);
MD5STEP(F4, d, a, b, c, in[3] + 0x8f0ccc92, 10);
MD5STEP(F4, c, d, a, b, in[10] + 0xffeff47d, 15);
MD5STEP(F4, b, c, d, a, in[1] + 0x85845dd1, 21);
MD5STEP(F4, a, b, c, d, in[8] + 0x6fa87e4f, 6);
MD5STEP(F4, d, a, b, c, in[15] + 0xfe2ce6e0, 10);
MD5STEP(F4, c, d, a, b, in[6] + 0xa3014314, 15);
MD5STEP(F4, b, c, d, a, in[13] + 0x4e0811a1, 21);
MD5STEP(F4, a, b, c, d, in[4] + 0xf7537e82, 6);
MD5STEP(F4, d, a, b, c, in[11] + 0xbd3af235, 10);
MD5STEP(F4, c, d, a, b, in[2] + 0x2ad7d2bb, 15);
MD5STEP(F4, b, c, d, a, in[9] + 0xeb86d391, 21);
buf[0] += a;
buf[1] += b;
buf[2] += c;
buf[3] += d;
}
void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest)
{
MV_MD5_CONTEXT ctx;
mvMD5Init(&ctx);
mvMD5Update(&ctx, buf, len);
mvMD5Final(digest, &ctx);
}
void mvHmacMd5(unsigned char const* text, int text_len,
unsigned char const* key, int key_len,
unsigned char* digest)
{
int i;
MV_MD5_CONTEXT ctx;
unsigned char k_ipad[64+1]; /* inner padding - key XORd with ipad */
unsigned char k_opad[64+1]; /* outer padding - key XORd with opad */
/* start out by storing key in pads */
memset(k_ipad, 0, 64);
memcpy(k_ipad, key, key_len);
memset(k_opad, 0, 64);
memcpy(k_opad, key, key_len);
/* XOR key with ipad and opad values */
for (i=0; i<64; i++)
{
k_ipad[i] ^= 0x36;
k_opad[i] ^= 0x5c;
}
/* perform inner MD5 */
mvMD5Init(&ctx); /* init ctx for 1st pass */
mvMD5Update(&ctx, k_ipad, 64); /* start with inner pad */
mvMD5Update(&ctx, text, text_len); /* then text of datagram */
mvMD5Final(digest, &ctx); /* finish up 1st pass */
/* perform outer MD5 */
mvMD5Init(&ctx); /* init ctx for 2nd pass */
mvMD5Update(&ctx, k_opad, 64); /* start with outer pad */
mvMD5Update(&ctx, digest, 16); /* then results of 1st hash */
mvMD5Final(digest, &ctx); /* finish up 2nd pass */
}

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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __mvMD5_h__
#define __mvMD5_h__
#include "mvMD5.h"
#define MV_MD5_MAC_LEN 16
typedef struct
{
MV_U32 buf[4];
MV_U32 bits[2];
MV_U8 in[64];
} MV_MD5_CONTEXT;
void mvMD5Init(MV_MD5_CONTEXT *context);
void mvMD5Update(MV_MD5_CONTEXT *context, unsigned char const *buf,
unsigned len);
void mvMD5Final(unsigned char digest[16], MV_MD5_CONTEXT *context);
void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest);
void mvHmacMd5(unsigned char const* text, int text_len,
unsigned char const* key, int key_len,
unsigned char* digest);
#endif /* __mvMD5_h__ */

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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "mvOs.h"
#include "mvSHA1.h"
#define SHA1HANDSOFF
typedef union
{
MV_U8 c[64];
MV_U32 l[16];
} CHAR64LONG16;
static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer);
#define rol(value, bits) (((value) << (bits)) | ((value) >> (32 - (bits))))
#ifdef MV_CPU_LE
#define blk0(i) (block->l[i] = (rol(block->l[i], 24) & 0xFF00FF00) | \
(rol(block->l[i], 8) & 0x00FF00FF))
#else
#define blk0(i) block->l[i]
#endif
#define blk(i) (block->l[i & 15] = rol(block->l[(i + 13) & 15] ^ \
block->l[(i + 8) & 15] ^ block->l[(i + 2) & 15] ^ block->l[i & 15], 1))
/* (R0+R1), R2, R3, R4 are the different operations used in SHA1 */
#define R0(v,w,x,y,z,i) \
z += ((w & (x ^ y)) ^ y) + blk0(i) + 0x5A827999 + rol(v, 5); \
w = rol(w, 30);
#define R1(v,w,x,y,z,i) \
z += ((w & (x ^ y)) ^ y) + blk(i) + 0x5A827999 + rol(v, 5); \
w = rol(w, 30);
#define R2(v,w,x,y,z,i) \
z += (w ^ x ^ y) + blk(i) + 0x6ED9EBA1 + rol(v, 5); w = rol(w, 30);
#define R3(v,w,x,y,z,i) \
z += (((w | x) & y) | (w & x)) + blk(i) + 0x8F1BBCDC + rol(v, 5); \
w = rol(w, 30);
#define R4(v,w,x,y,z,i) \
z += (w ^ x ^ y) + blk(i) + 0xCA62C1D6 + rol(v, 5); \
w=rol(w, 30);
/* Hash a single 512-bit block. This is the core of the algorithm. */
static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer)
{
MV_U32 a, b, c, d, e;
CHAR64LONG16* block;
#ifdef SHA1HANDSOFF
static MV_U32 workspace[16];
block = (CHAR64LONG16 *) workspace;
memcpy(block, buffer, 64);
#else
block = (CHAR64LONG16 *) buffer;
#endif
/* Copy context->state[] to working vars */
a = state[0];
b = state[1];
c = state[2];
d = state[3];
e = state[4];
/* 4 rounds of 20 operations each. Loop unrolled. */
R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3);
R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7);
R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11);
R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15);
R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19);
R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23);
R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27);
R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31);
R2(d,e,a,b,c,32); R2(c,d,e,a,b,33); R2(b,c,d,e,a,34); R2(a,b,c,d,e,35);
R2(e,a,b,c,d,36); R2(d,e,a,b,c,37); R2(c,d,e,a,b,38); R2(b,c,d,e,a,39);
R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43);
R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47);
R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51);
R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55);
R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59);
R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63);
R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67);
R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71);
R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75);
R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79);
/* Add the working vars back into context.state[] */
state[0] += a;
state[1] += b;
state[2] += c;
state[3] += d;
state[4] += e;
/* Wipe variables */
a = b = c = d = e = 0;
}
void mvSHA1Init(MV_SHA1_CTX* context)
{
/* SHA1 initialization constants */
context->state[0] = 0x67452301;
context->state[1] = 0xEFCDAB89;
context->state[2] = 0x98BADCFE;
context->state[3] = 0x10325476;
context->state[4] = 0xC3D2E1F0;
context->count[0] = context->count[1] = 0;
}
/* Run your data through this. */
void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *data,
unsigned int len)
{
MV_U32 i, j;
j = (context->count[0] >> 3) & 63;
if ((context->count[0] += len << 3) < (len << 3))
context->count[1]++;
context->count[1] += (len >> 29);
if ((j + len) > 63)
{
memcpy(&context->buffer[j], data, (i = 64-j));
mvSHA1Transform(context->state, context->buffer);
for ( ; i + 63 < len; i += 64)
{
mvSHA1Transform(context->state, &data[i]);
}
j = 0;
}
else
{
i = 0;
}
memcpy(&context->buffer[j], &data[i], len - i);
}
void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX* context)
{
MV_U32 i;
MV_U8 finalcount[8];
for (i = 0; i < 8; i++)
{
finalcount[i] = (unsigned char)((context->count[(i >= 4 ? 0 : 1)] >>
((3-(i & 3)) * 8) ) & 255); /* Endian independent */
}
mvSHA1Update(context, (const unsigned char *) "\200", 1);
while ((context->count[0] & 504) != 448)
{
mvSHA1Update(context, (const unsigned char *) "\0", 1);
}
mvSHA1Update(context, finalcount, 8); /* Should cause a mvSHA1Transform()
*/
for (i = 0; i < 20; i++)
{
digest[i] = (unsigned char)
((context->state[i >> 2] >> ((3 - (i & 3)) * 8)) & 255);
}
/* Wipe variables */
i = 0;
memset(context->buffer, 0, 64);
memset(context->state, 0, 20);
memset(context->count, 0, 8);
memset(finalcount, 0, 8);
#ifdef SHA1HANDSOFF /* make SHA1Transform overwrite it's own static vars */
mvSHA1Transform(context->state, context->buffer);
#endif
}
void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest)
{
MV_SHA1_CTX ctx;
mvSHA1Init(&ctx);
mvSHA1Update(&ctx, buf, len);
mvSHA1Final(digest, &ctx);
}

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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __mvSHA1_h__
#define __mvSHA1_h__
#include "mvSHA1.h"
#define MV_SHA1_MAC_LEN 20
typedef struct
{
MV_U32 state[5];
MV_U32 count[2];
MV_U8 buffer[64];
} MV_SHA1_CTX;
void mvSHA1Init(MV_SHA1_CTX *context);
void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *buf, unsigned int len);
void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX *context);
void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest);
#endif /* __mvSHA1_h__ */

1296
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213
target/linux/generic-2.6/files/crypto/ocf/kirkwood/mvHal/common/mv802_3.h Normal file
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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmv802_3h
#define __INCmv802_3h
/* includes */
#include "mvTypes.h"
/* Defines */
#define MV_MAX_ETH_DATA 1500
/* 802.3 types */
#define MV_IP_TYPE 0x0800
#define MV_IP_ARP_TYPE 0x0806
#define MV_APPLE_TALK_ARP_TYPE 0x80F3
#define MV_NOVELL_IPX_TYPE 0x8137
#define MV_EAPOL_TYPE 0x888e
/* Encapsulation header for RFC1042 and Ethernet_tunnel */
#define MV_RFC1042_SNAP_HEADER {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00}
#define MV_ETH_SNAP_LSB 0xF8
#define MV_MAC_ADDR_SIZE (6)
#define MV_MAC_STR_SIZE (20)
#define MV_VLAN_HLEN (4)
/* This macro checks for a multicast mac address */
#define MV_IS_MULTICAST_MAC(mac) (((mac)[0] & 0x1) == 1)
/* This macro checks for an broadcast mac address */
#define MV_IS_BROADCAST_MAC(mac) \
(((mac)[0] == 0xFF) && \
((mac)[1] == 0xFF) && \
((mac)[2] == 0xFF) && \
((mac)[3] == 0xFF) && \
((mac)[4] == 0xFF) && \
((mac)[5] == 0xFF))
/* Typedefs */
typedef struct
{
MV_U8 pDA[MV_MAC_ADDR_SIZE];
MV_U8 pSA[MV_MAC_ADDR_SIZE];
MV_U16 typeOrLen;
} MV_802_3_HEADER;
enum {
MV_IP_PROTO_NULL = 0, /* Dummy protocol for TCP */
MV_IP_PROTO_ICMP = 1, /* Internet Control Message Protocol */
MV_IP_PROTO_IGMP = 2, /* Internet Group Management Protocol */
MV_IP_PROTO_IPIP = 4, /* IPIP tunnels (older KA9Q tunnels use 94) */
MV_IP_PROTO_TCP = 6, /* Transmission Control Protocol */
MV_IP_PROTO_EGP = 8, /* Exterior Gateway Protocol */
MV_IP_PROTO_PUP = 12, /* PUP protocol */
MV_IP_PROTO_UDP = 17, /* User Datagram Protocol */
MV_IP_PROTO_IDP = 22, /* XNS IDP protocol */
MV_IP_PROTO_DCCP = 33, /* Datagram Congestion Control Protocol */
MV_IP_PROTO_IPV6 = 41, /* IPv6-in-IPv4 tunnelling */
MV_IP_PROTO_RSVP = 46, /* RSVP protocol */
MV_IP_PROTO_GRE = 47, /* Cisco GRE tunnels (rfc 1701,1702) */
MV_IP_PROTO_ESP = 50, /* Encapsulation Security Payload protocol */
MV_IP_PROTO_AH = 51, /* Authentication Header protocol */
MV_IP_PROTO_BEETPH = 94, /* IP option pseudo header for BEET */
MV_IP_PROTO_PIM = 103,
MV_IP_PROTO_COMP = 108, /* Compression Header protocol */
MV_IP_PROTO_ZERO_HOP = 114, /* Any 0 hop protocol (IANA) */
MV_IP_PROTO_SCTP = 132, /* Stream Control Transport Protocol */
MV_IP_PROTO_UDPLITE = 136, /* UDP-Lite (RFC 3828) */
MV_IP_PROTO_RAW = 255, /* Raw IP packets */
MV_IP_PROTO_MAX
};
typedef struct
{
MV_U8 version;
MV_U8 tos;
MV_U16 totalLength;
MV_U16 identifier;
MV_U16 fragmentCtrl;
MV_U8 ttl;
MV_U8 protocol;
MV_U16 checksum;
MV_U32 srcIP;
MV_U32 dstIP;
} MV_IP_HEADER;
typedef struct
{
MV_U32 spi;
MV_U32 seqNum;
} MV_ESP_HEADER;
#define MV_ICMP_ECHOREPLY 0 /* Echo Reply */
#define MV_ICMP_DEST_UNREACH 3 /* Destination Unreachable */
#define MV_ICMP_SOURCE_QUENCH 4 /* Source Quench */
#define MV_ICMP_REDIRECT 5 /* Redirect (change route) */
#define MV_ICMP_ECHO 8 /* Echo Request */
#define MV_ICMP_TIME_EXCEEDED 11 /* Time Exceeded */
#define MV_ICMP_PARAMETERPROB 12 /* Parameter Problem */
#define MV_ICMP_TIMESTAMP 13 /* Timestamp Request */
#define MV_ICMP_TIMESTAMPREPLY 14 /* Timestamp Reply */
#define MV_ICMP_INFO_REQUEST 15 /* Information Request */
#define MV_ICMP_INFO_REPLY 16 /* Information Reply */
#define MV_ICMP_ADDRESS 17 /* Address Mask Request */
#define MV_ICMP_ADDRESSREPLY 18 /* Address Mask Reply */
typedef struct
{
MV_U8 type;
MV_U8 code;
MV_U16 checksum;
MV_U16 id;
MV_U16 sequence;
} MV_ICMP_ECHO_HEADER;
typedef struct
{
MV_U16 source;
MV_U16 dest;
MV_U32 seq;
MV_U32 ack_seq;
MV_U16 flags;
MV_U16 window;
MV_U16 chksum;
MV_U16 urg_offset;
} MV_TCP_HEADER;
typedef struct
{
MV_U16 source;
MV_U16 dest;
MV_U16 len;
MV_U16 check;
} MV_UDP_HEADER;
#endif /* __INCmv802_3h */

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target/linux/generic-2.6/files/crypto/ocf/kirkwood/mvHal/common/mvCommon.c Normal file
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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "mvOs.h"
#include "mv802_3.h"
#include "mvCommon.h"
/*******************************************************************************
* mvMacStrToHex - Convert MAC format string to hex.
*
* DESCRIPTION:
* This function convert MAC format string to hex.
*
* INPUT:
* macStr - MAC address string. Fornat of address string is
* uu:vv:ww:xx:yy:zz, where ":" can be any delimiter.
*
* OUTPUT:
* macHex - MAC in hex format.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_STATUS mvMacStrToHex(const char* macStr, MV_U8* macHex)
{
int i;
char tmp[3];
for(i = 0; i < MV_MAC_ADDR_SIZE; i++)
{
tmp[0] = macStr[(i * 3) + 0];
tmp[1] = macStr[(i * 3) + 1];
tmp[2] = '\0';
macHex[i] = (MV_U8) (strtol(tmp, NULL, 16));
}
return MV_OK;
}
/*******************************************************************************
* mvMacHexToStr - Convert MAC in hex format to string format.
*
* DESCRIPTION:
* This function convert MAC in hex format to string format.
*
* INPUT:
* macHex - MAC in hex format.
*
* OUTPUT:
* macStr - MAC address string. String format is uu:vv:ww:xx:yy:zz.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_STATUS mvMacHexToStr(MV_U8* macHex, char* macStr)
{
int i;
for(i = 0; i < MV_MAC_ADDR_SIZE; i++)
{
mvOsSPrintf(&macStr[i * 3], "%02x:", macHex[i]);
}
macStr[(i * 3) - 1] = '\0';
return MV_OK;
}
/*******************************************************************************
* mvSizePrint - Print the given size with size unit description.
*
* DESCRIPTION:
* This function print the given size with size unit description.
* FOr example when size paramter is 0x180000, the function prints:
* "size 1MB+500KB"
*
* INPUT:
* size - Size in bytes.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_VOID mvSizePrint(MV_U32 size)
{
mvOsOutput("size ");
if(size >= _1G)
{
mvOsOutput("%3dGB ", size / _1G);
size %= _1G;
if(size)
mvOsOutput("+");
}
if(size >= _1M )
{
mvOsOutput("%3dMB ", size / _1M);
size %= _1M;
if(size)
mvOsOutput("+");
}
if(size >= _1K)
{
mvOsOutput("%3dKB ", size / _1K);
size %= _1K;
if(size)
mvOsOutput("+");
}
if(size > 0)
{
mvOsOutput("%3dB ", size);
}
}
/*******************************************************************************
* mvHexToBin - Convert hex to binary
*
* DESCRIPTION:
* This function Convert hex to binary.
*
* INPUT:
* pHexStr - hex buffer pointer.
* size - Size to convert.
*
* OUTPUT:
* pBin - Binary buffer pointer.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size)
{
int j, i;
char tmp[3];
MV_U8 byte;
for(j=0, i=0; j<size; j++, i+=2)
{
tmp[0] = pHexStr[i];
tmp[1] = pHexStr[i+1];
tmp[2] = '\0';
byte = (MV_U8) (strtol(tmp, NULL, 16) & 0xFF);
pBin[j] = byte;
}
}
void mvAsciiToHex(const char* asciiStr, char* hexStr)
{
int i=0;
while(asciiStr[i] != 0)
{
mvOsSPrintf(&hexStr[i*2], "%02x", asciiStr[i]);
i++;
}
hexStr[i*2] = 0;
}
void mvBinToHex(const MV_U8* bin, char* hexStr, int size)
{
int i;
for(i=0; i<size; i++)
{
mvOsSPrintf(&hexStr[i*2], "%02x", bin[i]);
}
hexStr[i*2] = '\0';
}
void mvBinToAscii(const MV_U8* bin, char* asciiStr, int size)
{
int i;
for(i=0; i<size; i++)
{
mvOsSPrintf(&asciiStr[i*2], "%c", bin[i]);
}
asciiStr[i*2] = '\0';
}
/*******************************************************************************
* mvLog2 -
*
* DESCRIPTION:
* Calculate the Log2 of a given number.
*
* INPUT:
* num - A number to calculate the Log2 for.
*
* OUTPUT:
* None.
*
* RETURN:
* Log 2 of the input number, or 0xFFFFFFFF if input is 0.
*
*******************************************************************************/
MV_U32 mvLog2(MV_U32 num)
{
MV_U32 result = 0;
if(num == 0)
return 0xFFFFFFFF;
while(num != 1)
{
num = num >> 1;
result++;
}
return result;
}

308
target/linux/generic-2.6/files/crypto/ocf/kirkwood/mvHal/common/mvCommon.h Normal file
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@ -0,0 +1,308 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvCommonh
#define __INCmvCommonh
#include "mvTypes.h"
/* Swap tool */
/* 16bit nibble swap. For example 0x1234 -> 0x2143 */
#define MV_NIBBLE_SWAP_16BIT(X) (((X&0xf) << 4) | \
((X&0xf0) >> 4) | \
((X&0xf00) << 4) | \
((X&0xf000) >> 4))
/* 32bit nibble swap. For example 0x12345678 -> 0x21436587 */
#define MV_NIBBLE_SWAP_32BIT(X) (((X&0xf) << 4) | \
((X&0xf0) >> 4) | \
((X&0xf00) << 4) | \
((X&0xf000) >> 4) | \
((X&0xf0000) << 4) | \
((X&0xf00000) >> 4) | \
((X&0xf000000) << 4) | \
((X&0xf0000000) >> 4))
/* 16bit byte swap. For example 0x1122 -> 0x2211 */
#define MV_BYTE_SWAP_16BIT(X) ((((X)&0xff)<<8) | (((X)&0xff00)>>8))
/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */
#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \
(((X)&0xff00)<<8) | \
(((X)&0xff0000)>>8) | \
(((X)&0xff000000)>>24))
/* 64bit byte swap. For example 0x11223344.55667788 -> 0x88776655.44332211 */
#define MV_BYTE_SWAP_64BIT(X) ((l64) ((((X)&0xffULL)<<56) | \
(((X)&0xff00ULL)<<40) | \
(((X)&0xff0000ULL)<<24) | \
(((X)&0xff000000ULL)<<8) | \
(((X)&0xff00000000ULL)>>8) | \
(((X)&0xff0000000000ULL)>>24) | \
(((X)&0xff000000000000ULL)>>40) | \
(((X)&0xff00000000000000ULL)>>56)))
/* Endianess macros. */
#if defined(MV_CPU_LE)
#define MV_16BIT_LE(X) (X)
#define MV_32BIT_LE(X) (X)
#define MV_64BIT_LE(X) (X)
#define MV_16BIT_BE(X) MV_BYTE_SWAP_16BIT(X)
#define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X)
#define MV_64BIT_BE(X) MV_BYTE_SWAP_64BIT(X)
#elif defined(MV_CPU_BE)
#define MV_16BIT_LE(X) MV_BYTE_SWAP_16BIT(X)
#define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X)
#define MV_64BIT_LE(X) MV_BYTE_SWAP_64BIT(X)
#define MV_16BIT_BE(X) (X)
#define MV_32BIT_BE(X) (X)
#define MV_64BIT_BE(X) (X)
#else
#error "CPU endianess isn't defined!\n"
#endif
/* Bit field definitions */
#define NO_BIT 0x00000000
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
/* Handy sizes */
#define _1K 0x00000400
#define _2K 0x00000800
#define _4K 0x00001000
#define _8K 0x00002000
#define _16K 0x00004000
#define _32K 0x00008000
#define _64K 0x00010000
#define _128K 0x00020000
#define _256K 0x00040000
#define _512K 0x00080000
#define _1M 0x00100000
#define _2M 0x00200000
#define _4M 0x00400000
#define _8M 0x00800000
#define _16M 0x01000000
#define _32M 0x02000000
#define _64M 0x04000000
#define _128M 0x08000000
#define _256M 0x10000000
#define _512M 0x20000000
#define _1G 0x40000000
#define _2G 0x80000000
/* Tclock and Sys clock define */
#define _100MHz 100000000
#define _125MHz 125000000
#define _133MHz 133333334
#define _150MHz 150000000
#define _160MHz 160000000
#define _166MHz 166666667
#define _175MHz 175000000
#define _178MHz 178000000
#define _183MHz 183333334
#define _187MHz 187000000
#define _192MHz 192000000
#define _194MHz 194000000
#define _200MHz 200000000
#define _233MHz 233333334
#define _250MHz 250000000
#define _266MHz 266666667
#define _300MHz 300000000
/* For better address window table readability */
#define EN MV_TRUE
#define DIS MV_FALSE
#define N_A -1 /* Not applicable */
/* Cache configuration options for memory (DRAM, SRAM, ... ) */
/* Memory uncached, HW or SW cache coherency is not needed */
#define MV_UNCACHED 0
/* Memory cached, HW cache coherency supported in WriteThrough mode */
#define MV_CACHE_COHER_HW_WT 1
/* Memory cached, HW cache coherency supported in WriteBack mode */
#define MV_CACHE_COHER_HW_WB 2
/* Memory cached, No HW cache coherency, Cache coherency must be in SW */
#define MV_CACHE_COHER_SW 3
/* Macro for testing aligment. Positive if number is NOT aligned */
#define MV_IS_NOT_ALIGN(number, align) ((number) & ((align) - 1))
/* Macro for alignment up. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0340 */
#define MV_ALIGN_UP(number, align) \
(((number) & ((align) - 1)) ? (((number) + (align)) & ~((align)-1)) : (number))
/* Macro for alignment down. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0320 */
#define MV_ALIGN_DOWN(number, align) ((number) & ~((align)-1))
/* This macro returns absolute value */
#define MV_ABS(number) (((int)(number) < 0) ? -(int)(number) : (int)(number))
/* Bit fields manipulation macros */
/* An integer word which its 'x' bit is set */
#define MV_BIT_MASK(bitNum) (1 << (bitNum) )
/* Checks wheter bit 'x' in integer word is set */
#define MV_BIT_CHECK(word, bitNum) ( (word) & MV_BIT_MASK(bitNum) )
/* Clear (reset) bit 'x' in integer word (RMW - Read-Modify-Write) */
#define MV_BIT_CLEAR(word, bitNum) ( (word) &= ~(MV_BIT_MASK(bitNum)) )
/* Set bit 'x' in integer word (RMW) */
#define MV_BIT_SET(word, bitNum) ( (word) |= MV_BIT_MASK(bitNum) )
/* Invert bit 'x' in integer word (RMW) */
#define MV_BIT_INV(word, bitNum) ( (word) ^= MV_BIT_MASK(bitNum) )
/* Get the min between 'a' or 'b' */
#define MV_MIN(a,b) (((a) < (b)) ? (a) : (b))
/* Get the max between 'a' or 'b' */
#define MV_MAX(a,b) (((a) < (b)) ? (b) : (a))
/* Temporary */
#define mvOsDivide(num, div) \
({ \
int i=0, rem=(num); \
\
while(rem >= (div)) \
{ \
rem -= (div); \
i++; \
} \
(i); \
})
/* Temporary */
#define mvOsReminder(num, div) \
({ \
int rem = (num); \
\
while(rem >= (div)) \
rem -= (div); \
(rem); \
})
#define MV_IP_QUAD(ipAddr) ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), \
((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF)
#define MV_IS_POWER_OF_2(num) ((num != 0) && ((num & (num - 1)) == 0))
#ifndef MV_ASMLANGUAGE
/* mvCommon API list */
MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size);
void mvAsciiToHex(const char* asciiStr, char* hexStr);
void mvBinToHex(const MV_U8* bin, char* hexStr, int size);
void mvBinToAscii(const MV_U8* bin, char* asciiStr, int size);
MV_STATUS mvMacStrToHex(const char* macStr, MV_U8* macHex);
MV_STATUS mvMacHexToStr(MV_U8* macHex, char* macStr);
void mvSizePrint(MV_U32);
MV_U32 mvLog2(MV_U32 num);
#endif /* MV_ASMLANGUAGE */
#endif /* __INCmvCommonh */

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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/* includes */
#include "mvOs.h"
#include "mv802_3.h"
#include "mvCommon.h"
#include "mvDebug.h"
/* Global variables effect on behave MV_DEBUG_PRINT and MV_DEBUG_CODE macros
* mvDebug - map of bits (one for each module) bit=1 means enable
* debug code and messages for this module
* mvModuleDebug - array of 32 bits varables one for each module
*/
MV_U32 mvDebug = 0;
MV_U32 mvDebugModules[MV_MODULE_MAX];
/* Init mvModuleDebug array to default values */
void mvDebugInit(void)
{
int bit;
mvDebug = 0;
for(bit=0; bit<MV_MODULE_MAX; bit++)
{
mvDebugModules[bit] = MV_DEBUG_FLAG_ERR | MV_DEBUG_FLAG_STATS;
mvDebug |= MV_BIT_MASK(bit);
}
}
void mvDebugModuleEnable(MV_MODULE_ID module, MV_BOOL isEnable)
{
if (isEnable)
{
MV_BIT_SET(mvDebug, module);
}
else
MV_BIT_CLEAR(mvDebug, module);
}
void mvDebugModuleSetFlags(MV_MODULE_ID module, MV_U32 flags)
{
mvDebugModules[module] |= flags;
}
void mvDebugModuleClearFlags(MV_MODULE_ID module, MV_U32 flags)
{
mvDebugModules[module] &= ~flags;
}
/* Dump memory in specific format:
* address: X1X1X1X1 X2X2X2X2 ... X8X8X8X8
*/
void mvDebugMemDump(void* addr, int size, int access)
{
int i, j;
MV_U32 memAddr = (MV_U32)addr;
if(access == 0)
access = 1;
if( (access != 4) && (access != 2) && (access != 1) )
{
mvOsPrintf("%d wrong access size. Access must be 1 or 2 or 4\n",
access);
return;
}
memAddr = MV_ALIGN_DOWN( (unsigned int)addr, 4);
size = MV_ALIGN_UP(size, 4);
addr = (void*)MV_ALIGN_DOWN( (unsigned int)addr, access);
while(size > 0)
{
mvOsPrintf("%08x: ", memAddr);
i = 0;
/* 32 bytes in the line */
while(i < 32)
{
if(memAddr >= (MV_U32)addr)
{
switch(access)
{
case 1:
if( memAddr == CPU_PHY_MEM(memAddr) )
{
mvOsPrintf("%02x ", MV_MEMIO8_READ(memAddr));
}
else
{
mvOsPrintf("%02x ", *((MV_U8*)memAddr));
}
break;
case 2:
if( memAddr == CPU_PHY_MEM(memAddr) )
{
mvOsPrintf("%04x ", MV_MEMIO16_READ(memAddr));
}
else
{
mvOsPrintf("%04x ", *((MV_U16*)memAddr));
}
break;
case 4:
if( memAddr == CPU_PHY_MEM(memAddr) )
{
mvOsPrintf("%08x ", MV_MEMIO32_READ(memAddr));
}
else
{
mvOsPrintf("%08x ", *((MV_U32*)memAddr));
}
break;
}
}
else
{
for(j=0; j<(access*2+1); j++)
mvOsPrintf(" ");
}
i += access;
memAddr += access;
size -= access;
if(size <= 0)
break;
}
mvOsPrintf("\n");
}
}
void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access)
{
if(pBufInfo == NULL)
{
mvOsPrintf("\n!!! pBufInfo = NULL\n");
return;
}
mvOsPrintf("\n*** pBufInfo=0x%x, cmdSts=0x%08x, pBuf=0x%x, bufSize=%d\n",
(unsigned int)pBufInfo,
(unsigned int)pBufInfo->cmdSts,
(unsigned int)pBufInfo->pBuff,
(unsigned int)pBufInfo->bufSize);
mvOsPrintf("pData=0x%x, byteCnt=%d, pNext=0x%x, uInfo1=0x%x, uInfo2=0x%x\n",
(unsigned int)pBufInfo->pData,
(unsigned int)pBufInfo->byteCnt,
(unsigned int)pBufInfo->pNextBufInfo,
(unsigned int)pBufInfo->userInfo1,
(unsigned int)pBufInfo->userInfo2);
if(pBufInfo->pData != NULL)
{
if(size > pBufInfo->byteCnt)
size = pBufInfo->byteCnt;
mvDebugMemDump(pBufInfo->pData, size, access);
}
}
void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access)
{
int frag, len;
if(pPktInfo == NULL)
{
mvOsPrintf("\n!!! pPktInfo = NULL\n");
return;
}
mvOsPrintf("\npPkt=%p, stat=0x%08x, numFr=%d, size=%d, pFr=%p, osInfo=0x%lx\n",
pPktInfo, pPktInfo->status, pPktInfo->numFrags, pPktInfo->pktSize,
pPktInfo->pFrags, pPktInfo->osInfo);
for(frag=0; frag<pPktInfo->numFrags; frag++)
{
mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n",
frag, pPktInfo->pFrags[frag].bufVirtPtr,
pPktInfo->pFrags[frag].bufSize);
if(size > 0)
{
len = MV_MIN((int)pPktInfo->pFrags[frag].bufSize, size);
mvDebugMemDump(pPktInfo->pFrags[frag].bufVirtPtr, len, access);
size -= len;
}
}
}
void mvDebugPrintIpAddr(MV_U32 ipAddr)
{
mvOsPrintf("%d.%d.%d.%d", ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF),
((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF));
}
void mvDebugPrintMacAddr(const MV_U8* pMacAddr)
{
int i;
mvOsPrintf("%02x", (unsigned int)pMacAddr[0]);
for(i=1; i<MV_MAC_ADDR_SIZE; i++)
{
mvOsPrintf(":%02x", pMacAddr[i]);
}
/* mvOsPrintf("\n");*/
}
/******* There are three functions deals with MV_DEBUG_TIMES structure ********/
/* Reset MV_DEBUG_TIMES entry */
void mvDebugResetTimeEntry(MV_DEBUG_TIMES* pTimeEntry, int count, char* pName)
{
pTimeEntry->begin = 0;
pTimeEntry->count = count;
pTimeEntry->end = 0;
pTimeEntry->left = pTimeEntry->count;
pTimeEntry->total = 0;
pTimeEntry->min = 0xFFFFFFFF;
pTimeEntry->max = 0x0;
strncpy(pTimeEntry->name, pName, sizeof(pTimeEntry->name)-1);
pTimeEntry->name[sizeof(pTimeEntry->name)-1] = '\0';
}
/* Print out MV_DEBUG_TIMES entry */
void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle)
{
int num;
if(isTitle == MV_TRUE)
mvOsPrintf("Event NumOfEvents TotalTime Average Min Max\n");
num = pTimeEntry->count-pTimeEntry->left;
if(num > 0)
{
mvOsPrintf("%-11s %6u 0x%08lx %6lu %6lu %6lu\n",
pTimeEntry->name, num, pTimeEntry->total, pTimeEntry->total/num,
pTimeEntry->min, pTimeEntry->max);
}
}
/* Update MV_DEBUG_TIMES entry */
void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry)
{
MV_U32 delta;
if(pTimeEntry->left > 0)
{
if(pTimeEntry->end <= pTimeEntry->begin)
{
delta = pTimeEntry->begin - pTimeEntry->end;
}
else
{
delta = ((MV_U32)0x10000 - pTimeEntry->end) + pTimeEntry->begin;
}
pTimeEntry->total += delta;
if(delta < pTimeEntry->min)
pTimeEntry->min = delta;
if(delta > pTimeEntry->max)
pTimeEntry->max = delta;
pTimeEntry->left--;
}
}

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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvDebugh
#define __INCmvDebugh
/* includes */
#include "mvTypes.h"
typedef enum
{
MV_MODULE_INVALID = -1,
MV_MODULE_ETH = 0,
MV_MODULE_IDMA,
MV_MODULE_XOR,
MV_MODULE_TWASI,
MV_MODULE_MGI,
MV_MODULE_USB,
MV_MODULE_CESA,
MV_MODULE_MAX
}MV_MODULE_ID;
/* Define generic flags useful for most of modules */
#define MV_DEBUG_FLAG_ALL (0)
#define MV_DEBUG_FLAG_INIT (1 << 0)
#define MV_DEBUG_FLAG_RX (1 << 1)
#define MV_DEBUG_FLAG_TX (1 << 2)
#define MV_DEBUG_FLAG_ERR (1 << 3)
#define MV_DEBUG_FLAG_TRACE (1 << 4)
#define MV_DEBUG_FLAG_DUMP (1 << 5)
#define MV_DEBUG_FLAG_CACHE (1 << 6)
#define MV_DEBUG_FLAG_IOCTL (1 << 7)
#define MV_DEBUG_FLAG_STATS (1 << 8)
extern MV_U32 mvDebug;
extern MV_U32 mvDebugModules[MV_MODULE_MAX];
#ifdef MV_DEBUG
# define MV_DEBUG_PRINT(module, flags, msg) mvOsPrintf msg
# define MV_DEBUG_CODE(module, flags, code) code
#elif defined(MV_RT_DEBUG)
# define MV_DEBUG_PRINT(module, flags, msg) \
if( (mvDebug & (1<<(module))) && \
((mvDebugModules[(module)] & (flags)) == (flags)) ) \
mvOsPrintf msg
# define MV_DEBUG_CODE(module, flags, code) \
if( (mvDebug & (1<<(module))) && \
((mvDebugModules[(module)] & (flags)) == (flags)) ) \
code
#else
# define MV_DEBUG_PRINT(module, flags, msg)
# define MV_DEBUG_CODE(module, flags, code)
#endif
/* typedefs */
/* time measurement structure used to check how much time pass between
* two points
*/
typedef struct {
char name[20]; /* name of the entry */
unsigned long begin; /* time measured on begin point */
unsigned long end; /* time measured on end point */
unsigned long total; /* Accumulated time */
unsigned long left; /* The rest measurement actions */
unsigned long count; /* Maximum measurement actions */
unsigned long min; /* Minimum time from begin to end */
unsigned long max; /* Maximum time from begin to end */
} MV_DEBUG_TIMES;
/* mvDebug.h API list */
/****** Error Recording ******/
/* Dump memory in specific format:
* address: X1X1X1X1 X2X2X2X2 ... X8X8X8X8
*/
void mvDebugMemDump(void* addr, int size, int access);
void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access);
void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access);
void mvDebugPrintIpAddr(MV_U32 ipAddr);
void mvDebugPrintMacAddr(const MV_U8* pMacAddr);
/**** There are three functions deals with MV_DEBUG_TIMES structure ****/
/* Reset MV_DEBUG_TIMES entry */
void mvDebugResetTimeEntry(MV_DEBUG_TIMES* pTimeEntry, int count, char* name);
/* Update MV_DEBUG_TIMES entry */
void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry);
/* Print out MV_DEBUG_TIMES entry */
void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle);
/******** General ***********/
/* Change value of mvDebugPrint global variable */
void mvDebugInit(void);
void mvDebugModuleEnable(MV_MODULE_ID module, MV_BOOL isEnable);
void mvDebugModuleSetFlags(MV_MODULE_ID module, MV_U32 flags);
void mvDebugModuleClearFlags(MV_MODULE_ID module, MV_U32 flags);
#endif /* __INCmvDebug.h */

225
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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvDeviceIdh
#define __INCmvDeviceIdh
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* defines */
#define MARVELL_VEN_ID 0x11ab
/* Disco-3 */
#define MV64460_DEV_ID 0x6480
#define MV64460B_DEV_ID 0x6485
#define MV64430_DEV_ID 0x6420
/* Disco-5 */
#define MV64560_DEV_ID 0x6450
/* Disco-6 */
#define MV64660_DEV_ID 0x6460
/* Orion */
#define MV_1181_DEV_ID 0x1181
#define MV_5181_DEV_ID 0x5181
#define MV_5281_DEV_ID 0x5281
#define MV_5182_DEV_ID 0x5182
#define MV_8660_DEV_ID 0x8660
#define MV_5180_DEV_ID 0x5180
#define MV_5082_DEV_ID 0x5082
#define MV_1281_DEV_ID 0x1281
#define MV_6082_DEV_ID 0x6082
#define MV_6183_DEV_ID 0x6183
#define MV_6183L_DEV_ID 0x6083
#define MV_5281_D0_REV 0x4
#define MV_5281_D0_ID ((MV_5281_DEV_ID << 16) | MV_5281_D0_REV)
#define MV_5281_D0_NAME "88F5281 D0"
#define MV_5281_D1_REV 0x5
#define MV_5281_D1_ID ((MV_5281_DEV_ID << 16) | MV_5281_D1_REV)
#define MV_5281_D1_NAME "88F5281 D1"
#define MV_5281_D2_REV 0x6
#define MV_5281_D2_ID ((MV_5281_DEV_ID << 16) | MV_5281_D2_REV)
#define MV_5281_D2_NAME "88F5281 D2"
#define MV_5181L_A0_REV 0x8 /* need for PCIE Er */
#define MV_5181_A1_REV 0x1 /* for USB Er ..*/
#define MV_5181_B0_REV 0x2
#define MV_5181_B1_REV 0x3
#define MV_5182_A1_REV 0x1
#define MV_5180N_B1_REV 0x3
#define MV_5181L_A0_ID ((MV_5181_DEV_ID << 16) | MV_5181L_A0_REV)
/* kw */
#define MV_6281_DEV_ID 0x6281
#define MV_6192_DEV_ID 0x6192
#define MV_6190_DEV_ID 0x6190
#define MV_6180_DEV_ID 0x6180
#define MV_6281_A0_REV 0x2
#define MV_6281_A0_ID ((MV_6281_DEV_ID << 16) | MV_6281_A0_REV)
#define MV_6281_A0_NAME "88F6281 A0"
#define MV_6192_A0_REV 0x2
#define MV_6192_A0_ID ((MV_6192_DEV_ID << 16) | MV_6192_A0_REV)
#define MV_6192_A0_NAME "88F6192 A0"
#define MV_6190_A0_REV 0x2
#define MV_6190_A0_ID ((MV_6190_DEV_ID << 16) | MV_6190_A0_REV)
#define MV_6190_A0_NAME "88F6190 A0"
#define MV_6180_A0_REV 0x2
#define MV_6180_A0_ID ((MV_6180_DEV_ID << 16) | MV_6180_A0_REV)
#define MV_6180_A0_NAME "88F6180 A0"
#define MV_6281_A1_REV 0x3
#define MV_6281_A1_ID ((MV_6281_DEV_ID << 16) | MV_6281_A1_REV)
#define MV_6281_A1_NAME "88F6281 A1"
#define MV_6192_A1_REV 0x3
#define MV_6192_A1_ID ((MV_6192_DEV_ID << 16) | MV_6192_A1_REV)
#define MV_6192_A1_NAME "88F6192 A1"
#define MV_6190_A1_REV 0x3
#define MV_6190_A1_ID ((MV_6190_DEV_ID << 16) | MV_6190_A1_REV)
#define MV_6190_A1_NAME "88F6190 A1"
#define MV_6180_A1_REV 0x3
#define MV_6180_A1_ID ((MV_6180_DEV_ID << 16) | MV_6180_A1_REV)
#define MV_6180_A1_NAME "88F6180 A1"
#define MV_88F6XXX_A0_REV 0x2
#define MV_88F6XXX_A1_REV 0x3
/* Disco-Duo */
#define MV_78XX0_ZY_DEV_ID 0x6381
#define MV_78XX0_ZY_NAME "MV78X00"
#define MV_78XX0_Z0_REV 0x1
#define MV_78XX0_Z0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Z0_REV)
#define MV_78XX0_Z0_NAME "78X00 Z0"
#define MV_78XX0_Y0_REV 0x2
#define MV_78XX0_Y0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Y0_REV)
#define MV_78XX0_Y0_NAME "78X00 Y0"
#define MV_78XX0_DEV_ID 0x7800
#define MV_78XX0_NAME "MV78X00"
#define MV_76100_DEV_ID 0x7610
#define MV_78200_DEV_ID 0x7820
#define MV_78100_DEV_ID 0x7810
#define MV_78XX0_A0_REV 0x1
#define MV_78XX0_A1_REV 0x2
#define MV_76100_NAME "MV76100"
#define MV_78100_NAME "MV78100"
#define MV_78200_NAME "MV78200"
#define MV_76100_A0_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A0_REV)
#define MV_78100_A0_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A0_REV)
#define MV_78200_A0_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A0_REV)
#define MV_76100_A1_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A1_REV)
#define MV_78100_A1_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A1_REV)
#define MV_78200_A1_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A1_REV)
#define MV_76100_A0_NAME "MV76100 A0"
#define MV_78100_A0_NAME "MV78100 A0"
#define MV_78200_A0_NAME "MV78200 A0"
#define MV_78XX0_A0_NAME "MV78XX0 A0"
#define MV_76100_A1_NAME "MV76100 A1"
#define MV_78100_A1_NAME "MV78100 A1"
#define MV_78200_A1_NAME "MV78200 A1"
#define MV_78XX0_A1_NAME "MV78XX0 A1"
/*MV88F632X family*/
#define MV_6321_DEV_ID 0x6321
#define MV_6322_DEV_ID 0x6322
#define MV_6323_DEV_ID 0x6323
#define MV_6321_NAME "88F6321"
#define MV_6322_NAME "88F6322"
#define MV_6323_NAME "88F6323"
#define MV_632X_A1_REV 0x2
#define MV_6321_A1_ID ((MV_6321_DEV_ID << 16) | MV_632X_A1_REV)
#define MV_6322_A1_ID ((MV_6322_DEV_ID << 16) | MV_632X_A1_REV)
#define MV_6323_A1_ID ((MV_6323_DEV_ID << 16) | MV_632X_A1_REV)
#define MV_6321_A1_NAME "88F6321 A1"
#define MV_6322_A1_NAME "88F6322 A1"
#define MV_6323_A1_NAME "88F6323 A1"
#endif /* __INCmvDeviceIdh */

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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvHalVerh
#define __INCmvHalVerh
/* Defines */
#define MV_HAL_VERSION "FEROCEON_HAL_3_1_7"
#define MV_RELEASE_BASELINE "SoCandControllers_FEROCEON_RELEASE_7_9_2009_KW_4_3_4_DD_2_1_4_6183_1_1_4"
#endif /* __INCmvHalVerh */

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/*******************************************************************************
* Copyright 2003, Marvell Semiconductor Israel LTD. *
* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. *
* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT *
* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE *
* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. *
* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, *
* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. *
* *
* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, *
* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL *
* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. *
* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). *
********************************************************************************
* mvQueue.c
*
* FILENAME: $Workfile: mvStack.c $
* REVISION: $Revision: 1.1 $
* LAST UPDATE: $Modtime: $
*
* DESCRIPTION:
* This file implements simple Stack LIFO functionality.
*******************************************************************************/
/* includes */
#include "mvOs.h"
#include "mvTypes.h"
#include "mvDebug.h"
#include "mvStack.h"
/* defines */
/* Public functions */
/* Purpose: Create new stack
* Inputs:
* - MV_U32 noOfElements - maximum number of elements in the stack.
* Each element 4 bytes size
* Return: void* - pointer to created stack.
*/
void* mvStackCreate(int numOfElements)
{
MV_STACK* pStack;
MV_U32* pStackElements;
pStack = (MV_STACK*)mvOsMalloc(sizeof(MV_STACK));
pStackElements = (MV_U32*)mvOsMalloc(numOfElements*sizeof(MV_U32));
if( (pStack == NULL) || (pStackElements == NULL) )
{
mvOsPrintf("mvStack: Can't create new stack\n");
return NULL;
}
memset(pStackElements, 0, numOfElements*sizeof(MV_U32));
pStack->numOfElements = numOfElements;
pStack->stackIdx = 0;
pStack->stackElements = pStackElements;
return pStack;
}
/* Purpose: Delete existing stack
* Inputs:
* - void* stackHndl - Stack handle as returned by "mvStackCreate()" function
*
* Return: MV_STATUS MV_NOT_FOUND - Failure. StackHandle is not valid.
* MV_OK - Success.
*/
MV_STATUS mvStackDelete(void* stackHndl)
{
MV_STACK* pStack = (MV_STACK*)stackHndl;
if( (pStack == NULL) || (pStack->stackElements == NULL) )
return MV_NOT_FOUND;
mvOsFree(pStack->stackElements);
mvOsFree(pStack);
return MV_OK;
}
/* PrintOut status of the stack */
void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements)
{
int i;
MV_STACK* pStack = (MV_STACK*)stackHndl;
mvOsPrintf("StackHandle=%p, pElements=%p, numElements=%d, stackIdx=%d\n",
stackHndl, pStack->stackElements, pStack->numOfElements,
pStack->stackIdx);
if(isPrintElements == MV_TRUE)
{
for(i=0; i<pStack->stackIdx; i++)
{
mvOsPrintf("%3d. Value=0x%x\n", i, pStack->stackElements[i]);
}
}
}

140
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/*******************************************************************************
* Copyright 2003, Marvell Semiconductor Israel LTD. *
* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. *
* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT *
* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE *
* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. *
* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, *
* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. *
* *
* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, *
* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL *
* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. *
* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). *
********************************************************************************
* mvStack.h - Header File for :
*
* FILENAME: $Workfile: mvStack.h $
* REVISION: $Revision: 1.1 $
* LAST UPDATE: $Modtime: $
*
* DESCRIPTION:
* This file defines simple Stack (LIFO) functionality.
*
*******************************************************************************/
#ifndef __mvStack_h__
#define __mvStack_h__
/* includes */
#include "mvTypes.h"
/* defines */
/* typedefs */
/* Data structure describes general purpose Stack */
typedef struct
{
int stackIdx;
int numOfElements;
MV_U32* stackElements;
} MV_STACK;
static INLINE MV_BOOL mvStackIsFull(void* stackHndl)
{
MV_STACK* pStack = (MV_STACK*)stackHndl;
if(pStack->stackIdx == pStack->numOfElements)
return MV_TRUE;
return MV_FALSE;
}
static INLINE MV_BOOL mvStackIsEmpty(void* stackHndl)
{
MV_STACK* pStack = (MV_STACK*)stackHndl;
if(pStack->stackIdx == 0)
return MV_TRUE;
return MV_FALSE;
}
/* Purpose: Push new element to stack
* Inputs:
* - void* stackHndl - Stack handle as returned by "mvStackCreate()" function.
* - MV_U32 value - New element.
*
* Return: MV_STATUS MV_FULL - Failure. Stack is full.
* MV_OK - Success. Element is put to stack.
*/
static INLINE void mvStackPush(void* stackHndl, MV_U32 value)
{
MV_STACK* pStack = (MV_STACK*)stackHndl;
#ifdef MV_RT_DEBUG
if(pStack->stackIdx == pStack->numOfElements)
{
mvOsPrintf("mvStackPush: Stack is FULL\n");
return;
}
#endif /* MV_RT_DEBUG */
pStack->stackElements[pStack->stackIdx] = value;
pStack->stackIdx++;
}
/* Purpose: Pop element from the top of stack and copy it to "pValue"
* Inputs:
* - void* stackHndl - Stack handle as returned by "mvStackCreate()" function.
* - MV_U32 value - Element in the top of stack.
*
* Return: MV_STATUS MV_EMPTY - Failure. Stack is empty.
* MV_OK - Success. Element is removed from the stack and
* copied to pValue argument
*/
static INLINE MV_U32 mvStackPop(void* stackHndl)
{
MV_STACK* pStack = (MV_STACK*)stackHndl;
#ifdef MV_RT_DEBUG
if(pStack->stackIdx == 0)
{
mvOsPrintf("mvStackPop: Stack is EMPTY\n");
return 0;
}
#endif /* MV_RT_DEBUG */
pStack->stackIdx--;
return pStack->stackElements[pStack->stackIdx];
}
static INLINE int mvStackIndex(void* stackHndl)
{
MV_STACK* pStack = (MV_STACK*)stackHndl;
return pStack->stackIdx;
}
static INLINE int mvStackFreeElements(void* stackHndl)
{
MV_STACK* pStack = (MV_STACK*)stackHndl;
return (pStack->numOfElements - pStack->stackIdx);
}
/* mvStack.h API list */
/* Create new Stack */
void* mvStackCreate(int numOfElements);
/* Delete existing stack */
MV_STATUS mvStackDelete(void* stackHndl);
/* Print status of the stack */
void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements);
#endif /* __mvStack_h__ */

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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvTypesh
#define __INCmvTypesh
/* Defines */
/* The following is a list of Marvell status */
#define MV_ERROR (-1)
#define MV_OK (0x00) /* Operation succeeded */
#define MV_FAIL (0x01) /* Operation failed */
#define MV_BAD_VALUE (0x02) /* Illegal value (general) */
#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */
#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */
#define MV_BAD_PTR (0x05) /* Illegal pointer value */
#define MV_BAD_SIZE (0x06) /* Illegal size */
#define MV_BAD_STATE (0x07) /* Illegal state of state machine */
#define MV_SET_ERROR (0x08) /* Set operation failed */
#define MV_GET_ERROR (0x09) /* Get operation failed */
#define MV_CREATE_ERROR (0x0A) /* Fail while creating an item */
#define MV_NOT_FOUND (0x0B) /* Item not found */
#define MV_NO_MORE (0x0C) /* No more items found */
#define MV_NO_SUCH (0x0D) /* No such item */
#define MV_TIMEOUT (0x0E) /* Time Out */
#define MV_NO_CHANGE (0x0F) /* Parameter(s) is already in this value */
#define MV_NOT_SUPPORTED (0x10) /* This request is not support */
#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented */
#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */
#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */
#define MV_HW_ERROR (0x17) /* Hardware error */
#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
#define MV_NOT_READY (0x1A) /* The other side is not ready yet */
#define MV_ALREADY_EXIST (0x1B) /* Tried to create existing item */
#define MV_OUT_OF_CPU_MEM (0x1C) /* Cpu memory allocation failed. */
#define MV_NOT_STARTED (0x1D) /* Not started yet */
#define MV_BUSY (0x1E) /* Item is busy. */
#define MV_TERMINATE (0x1F) /* Item terminates it's work. */
#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */
#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */
#define MV_WRITE_PROTECT (0x22) /* Write protected */
#define MV_INVALID (int)(-1)
#define MV_FALSE 0
#define MV_TRUE (!(MV_FALSE))
#ifndef NULL
#define NULL ((void*)0)
#endif
#ifndef MV_ASMLANGUAGE
/* typedefs */
typedef char MV_8;
typedef unsigned char MV_U8;
typedef int MV_32;
typedef unsigned int MV_U32;
typedef short MV_16;
typedef unsigned short MV_U16;
#ifdef MV_PPC64
typedef long MV_64;
typedef unsigned long MV_U64;
#else
typedef long long MV_64;
typedef unsigned long long MV_U64;
#endif
typedef long MV_LONG; /* 32/64 */
typedef unsigned long MV_ULONG; /* 32/64 */
typedef int MV_STATUS;
typedef int MV_BOOL;
typedef void MV_VOID;
typedef float MV_FLOAT;
typedef int (*MV_FUNCPTR) (void); /* ptr to function returning int */
typedef void (*MV_VOIDFUNCPTR) (void); /* ptr to function returning void */
typedef double (*MV_DBLFUNCPTR) (void); /* ptr to function returning double*/
typedef float (*MV_FLTFUNCPTR) (void); /* ptr to function returning float */
typedef MV_U32 MV_KHZ;
typedef MV_U32 MV_MHZ;
typedef MV_U32 MV_HZ;
/* This enumerator describes the set of commands that can be applied on */
/* an engine (e.g. IDMA, XOR). Appling a comman depends on the current */
/* status (see MV_STATE enumerator) */
/* Start can be applied only when status is IDLE */
/* Stop can be applied only when status is IDLE, ACTIVE or PAUSED */
/* Pause can be applied only when status is ACTIVE */
/* Restart can be applied only when status is PAUSED */
typedef enum _mvCommand
{
MV_START, /* Start */
MV_STOP, /* Stop */
MV_PAUSE, /* Pause */
MV_RESTART /* Restart */
} MV_COMMAND;
/* This enumerator describes the set of state conditions. */
/* Moving from one state to other is stricted. */
typedef enum _mvState
{
MV_IDLE,
MV_ACTIVE,
MV_PAUSED,
MV_UNDEFINED_STATE
} MV_STATE;
/* This structure describes address space window. Window base can be */
/* 64 bit, window size up to 4GB */
typedef struct _mvAddrWin
{
MV_U32 baseLow; /* 32bit base low */
MV_U32 baseHigh; /* 32bit base high */
MV_U32 size; /* 32bit size */
}MV_ADDR_WIN;
/* This binary enumerator describes protection attribute status */
typedef enum _mvProtRight
{
ALLOWED, /* Protection attribute allowed */
FORBIDDEN /* Protection attribute forbidden */
}MV_PROT_RIGHT;
/* Unified struct for Rx and Tx packet operations. The user is required to */
/* be familier only with Tx/Rx descriptor command status. */
typedef struct _bufInfo
{
MV_U32 cmdSts; /* Tx/Rx command status */
MV_U16 byteCnt; /* Size of valid data in the buffer */
MV_U16 bufSize; /* Total size of the buffer */
MV_U8 *pBuff; /* Pointer to Buffer */
MV_U8 *pData; /* Pointer to data in the Buffer */
MV_U32 userInfo1; /* Tx/Rx attached user information 1 */
MV_U32 userInfo2; /* Tx/Rx attached user information 2 */
struct _bufInfo *pNextBufInfo; /* Next buffer in packet */
} BUF_INFO;
/* This structure contains information describing one of buffers
* (fragments) they are built Ethernet packet.
*/
typedef struct
{
MV_U8* bufVirtPtr;
MV_ULONG bufPhysAddr;
MV_U32 bufSize;
MV_U32 dataSize;
MV_U32 memHandle;
MV_32 bufAddrShift;
} MV_BUF_INFO;
/* This structure contains information describing Ethernet packet.
* The packet can be divided for few buffers (fragments)
*/
typedef struct
{
MV_ULONG osInfo;
MV_BUF_INFO *pFrags;
MV_U32 status;
MV_U16 pktSize;
MV_U16 numFrags;
MV_U32 ownerId;
MV_U32 fragIP;
} MV_PKT_INFO;
#endif /* MV_ASMLANGUAGE */
#endif /* __INCmvTypesh */

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#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/time.h>
#include "dbg-trace.h"
#define TRACE_ARR_LEN 800
#define STR_LEN 128
struct trace {
struct timeval tv;
char str[STR_LEN];
unsigned int callback_val1;
unsigned int callback_val2;
char valid;
};
static unsigned int (*trc_callback1) (unsigned char) = NULL;
static unsigned int (*trc_callback2) (unsigned char) = NULL;
static unsigned char trc_param1 = 0;
static unsigned char trc_param2 = 0;
struct trace *trc_arr;
static int trc_index;
static int trc_active = 0;
void TRC_START()
{
trc_active = 1;
}
void TRC_STOP()
{
trc_active = 0;
}
void TRC_INIT(void *callback1, void *callback2, unsigned char callback1_param, unsigned char callback2_param)
{
printk("Marvell debug tracing is on\n");
trc_arr = (struct trace *)kmalloc(TRACE_ARR_LEN*sizeof(struct trace),GFP_KERNEL);
if(trc_arr == NULL)
{
printk("Can't allocate Debug Trace buffer\n");
return;
}
memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace));
trc_index = 0;
trc_callback1 = callback1;
trc_callback2 = callback2;
trc_param1 = callback1_param;
trc_param2 = callback2_param;
}
void TRC_REC(char *fmt,...)
{
va_list args;
struct trace *trc = &trc_arr[trc_index];
if(trc_active == 0)
return;
do_gettimeofday(&trc->tv);
if(trc_callback1)
trc->callback_val1 = trc_callback1(trc_param1);
if(trc_callback2)
trc->callback_val2 = trc_callback2(trc_param2);
va_start(args, fmt);
vsprintf(trc->str,fmt,args);
va_end(args);
trc->valid = 1;
if((++trc_index) == TRACE_ARR_LEN) {
trc_index = 0;
}
}
void TRC_OUTPUT(void)
{
int i,j;
struct trace *p;
printk("\n\nTrace %d items\n",TRACE_ARR_LEN);
for(i=0,j=trc_index; i<TRACE_ARR_LEN; i++,j++) {
if(j == TRACE_ARR_LEN)
j = 0;
p = &trc_arr[j];
if(p->valid) {
unsigned long uoffs;
struct trace *plast;
if(p == &trc_arr[0])
plast = &trc_arr[TRACE_ARR_LEN-1];
else
plast = p-1;
if(p->tv.tv_sec == ((plast)->tv.tv_sec))
uoffs = (p->tv.tv_usec - ((plast)->tv.tv_usec));
else
uoffs = (1000000 - ((plast)->tv.tv_usec)) +
((p->tv.tv_sec - ((plast)->tv.tv_sec) - 1) * 1000000) +
p->tv.tv_usec;
printk("%03d: [+%ld usec]", j, (unsigned long)uoffs);
if(trc_callback1)
printk("[%u]",p->callback_val1);
if(trc_callback2)
printk("[%u]",p->callback_val2);
printk(": %s",p->str);
}
p->valid = 0;
}
memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace));
trc_index = 0;
}
void TRC_RELEASE(void)
{
kfree(trc_arr);
trc_index = 0;
}

24
target/linux/generic-2.6/files/crypto/ocf/kirkwood/mvHal/dbg-trace.h Normal file
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#ifndef _MV_DBG_TRCE_H_
#define _MV_DBG_TRCE_H_
#ifdef CONFIG_MV_DBG_TRACE
void TRC_INIT(void *callback1, void *callback2,
unsigned char callback1_param, unsigned char callback2_param);
void TRC_REC(char *fmt,...);
void TRC_OUTPUT(void);
void TRC_RELEASE(void);
void TRC_START(void);
void TRC_STOP(void);
#else
#define TRC_INIT(x1,x2,x3,x4)
#define TRC_REC(X...)
#define TRC_OUTPUT()
#define TRC_RELEASE()
#define TRC_START()
#define TRC_STOP()
#endif
#endif

2513
target/linux/generic-2.6/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c Normal file
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376
target/linux/generic-2.6/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h Normal file
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@ -0,0 +1,376 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvBoardEnvLibh
#define __INCmvBoardEnvLibh
/* defines */
/* The below constant macros defines the board I2C EEPROM data offsets */
#include "ctrlEnv/mvCtrlEnvLib.h"
#include "mvSysHwConfig.h"
#include "boardEnv/mvBoardEnvSpec.h"
/* DUART stuff for Tclk detection only */
#define DUART_BAUD_RATE 115200
#define MAX_CLOCK_MARGINE 5000000 /* Maximum detected clock margine */
/* Voice devices assembly modes */
#define DAISY_CHAIN_MODE 1
#define DUAL_CHIP_SELECT_MODE 0
#define INTERRUPT_TO_MPP 1
#define INTERRUPT_TO_TDM 0
#define BOARD_ETH_PORT_NUM MV_ETH_MAX_PORTS
#define BOARD_ETH_SWITCH_PORT_NUM 5
#define MV_BOARD_MAX_USB_IF 1
#define MV_BOARD_MAX_MPP 7
#define MV_BOARD_NAME_LEN 0x20
typedef struct _boardData
{
MV_U32 magic;
MV_U16 boardId;
MV_U8 boardVer;
MV_U8 boardRev;
MV_U32 reserved1;
MV_U32 reserved2;
}BOARD_DATA;
typedef enum _devBoardMppGroupClass
{
MV_BOARD_MPP_GROUP_1,
MV_BOARD_MPP_GROUP_2,
MV_BOARD_MAX_MPP_GROUP
}MV_BOARD_MPP_GROUP_CLASS;
typedef enum _devBoardMppTypeClass
{
MV_BOARD_AUTO,
MV_BOARD_TDM,
MV_BOARD_AUDIO,
MV_BOARD_RGMII,
MV_BOARD_GMII,
MV_BOARD_TS,
MV_BOARD_MII,
MV_BOARD_OTHER
}MV_BOARD_MPP_TYPE_CLASS;
typedef enum _devBoardModuleIdClass
{
MV_BOARD_MODULE_TDM_ID = 1,
MV_BOARD_MODULE_AUDIO_ID,
MV_BOARD_MODULE_RGMII_ID,
MV_BOARD_MODULE_GMII_ID,
MV_BOARD_MODULE_TS_ID,
MV_BOARD_MODULE_MII_ID,
MV_BOARD_MODULE_TDM_5CHAN_ID,
MV_BOARD_MODULE_OTHER_ID
}MV_BOARD_MODULE_ID_CLASS;
typedef struct _boardMppTypeInfo
{
MV_BOARD_MPP_TYPE_CLASS boardMppGroup1;
MV_BOARD_MPP_TYPE_CLASS boardMppGroup2;
}MV_BOARD_MPP_TYPE_INFO;
typedef enum _devBoardClass
{
BOARD_DEV_NOR_FLASH,
BOARD_DEV_NAND_FLASH,
BOARD_DEV_SEVEN_SEG,
BOARD_DEV_FPGA,
BOARD_DEV_SRAM,
BOARD_DEV_SPI_FLASH,
BOARD_DEV_OTHER,
}MV_BOARD_DEV_CLASS;
typedef enum _devTwsiBoardClass
{
BOARD_TWSI_RTC,
BOARD_DEV_TWSI_EXP,
BOARD_DEV_TWSI_SATR,
BOARD_TWSI_AUDIO_DEC,
BOARD_TWSI_OTHER
}MV_BOARD_TWSI_CLASS;
typedef enum _devGppBoardClass
{
BOARD_GPP_RTC,
BOARD_GPP_MV_SWITCH,
BOARD_GPP_USB_VBUS,
BOARD_GPP_USB_VBUS_EN,
BOARD_GPP_USB_OC,
BOARD_GPP_USB_HOST_DEVICE,
BOARD_GPP_REF_CLCK,
BOARD_GPP_VOIP_SLIC,
BOARD_GPP_LIFELINE,
BOARD_GPP_BUTTON,
BOARD_GPP_TS_BUTTON_C,
BOARD_GPP_TS_BUTTON_U,
BOARD_GPP_TS_BUTTON_D,
BOARD_GPP_TS_BUTTON_L,
BOARD_GPP_TS_BUTTON_R,
BOARD_GPP_POWER_BUTTON,
BOARD_GPP_RESTOR_BUTTON,
BOARD_GPP_WPS_BUTTON,
BOARD_GPP_HDD0_POWER,
BOARD_GPP_HDD1_POWER,
BOARD_GPP_FAN_POWER,
BOARD_GPP_RESET,
BOARD_GPP_POWER_ON_LED,
BOARD_GPP_HDD_POWER,
BOARD_GPP_SDIO_POWER,
BOARD_GPP_SDIO_DETECT,
BOARD_GPP_SDIO_WP,
BOARD_GPP_SWITCH_PHY_INT,
BOARD_GPP_TSU_DIRCTION,
BOARD_GPP_OTHER
}MV_BOARD_GPP_CLASS;
typedef struct _devCsInfo
{
MV_U8 deviceCS;
MV_U32 params;
MV_U32 devClass; /* MV_BOARD_DEV_CLASS */
MV_U8 devWidth;
}MV_DEV_CS_INFO;
#define MV_BOARD_PHY_FORCE_10MB 0x0
#define MV_BOARD_PHY_FORCE_100MB 0x1
#define MV_BOARD_PHY_FORCE_1000MB 0x2
#define MV_BOARD_PHY_SPEED_AUTO 0x3
typedef struct _boardSwitchInfo
{
MV_32 linkStatusIrq;
MV_32 qdPort[BOARD_ETH_SWITCH_PORT_NUM];
MV_32 qdCpuPort;
MV_32 smiScanMode; /* 1 for SMI_MANUAL_MODE, 0 otherwise */
MV_32 switchOnPort;
}MV_BOARD_SWITCH_INFO;
typedef struct _boardLedInfo
{
MV_U8 activeLedsNumber;
MV_U8 ledsPolarity; /* '0' or '1' to turn on led */
MV_U8* gppPinNum; /* Pointer to GPP values */
}MV_BOARD_LED_INFO;
typedef struct _boardGppInfo
{
MV_BOARD_GPP_CLASS devClass;
MV_U8 gppPinNum;
}MV_BOARD_GPP_INFO;
typedef struct _boardTwsiInfo
{
MV_BOARD_TWSI_CLASS devClass;
MV_U8 twsiDevAddr;
MV_U8 twsiDevAddrType;
}MV_BOARD_TWSI_INFO;
typedef enum _boardMacSpeed
{
BOARD_MAC_SPEED_10M,
BOARD_MAC_SPEED_100M,
BOARD_MAC_SPEED_1000M,
BOARD_MAC_SPEED_AUTO,
}MV_BOARD_MAC_SPEED;
typedef struct _boardMacInfo
{
MV_BOARD_MAC_SPEED boardMacSpeed;
MV_U8 boardEthSmiAddr;
}MV_BOARD_MAC_INFO;
typedef struct _boardMppInfo
{
MV_U32 mppGroup[MV_BOARD_MAX_MPP];
}MV_BOARD_MPP_INFO;
typedef struct _boardInfo
{
char boardName[MV_BOARD_NAME_LEN];
MV_U8 numBoardMppTypeValue;
MV_BOARD_MPP_TYPE_INFO* pBoardMppTypeValue;
MV_U8 numBoardMppConfigValue;
MV_BOARD_MPP_INFO* pBoardMppConfigValue;
MV_U32 intsGppMaskLow;
MV_U32 intsGppMaskHigh;
MV_U8 numBoardDeviceIf;
MV_DEV_CS_INFO* pDevCsInfo;
MV_U8 numBoardTwsiDev;
MV_BOARD_TWSI_INFO* pBoardTwsiDev;
MV_U8 numBoardMacInfo;
MV_BOARD_MAC_INFO* pBoardMacInfo;
MV_U8 numBoardGppInfo;
MV_BOARD_GPP_INFO* pBoardGppInfo;
MV_U8 activeLedsNumber;
MV_U8* pLedGppPin;
MV_U8 ledsPolarity; /* '0' or '1' to turn on led */
/* GPP values */
MV_U32 gppOutEnValLow;
MV_U32 gppOutEnValHigh;
MV_U32 gppOutValLow;
MV_U32 gppOutValHigh;
MV_U32 gppPolarityValLow;
MV_U32 gppPolarityValHigh;
/* Switch Configuration */
MV_BOARD_SWITCH_INFO* pSwitchInfo;
}MV_BOARD_INFO;
MV_VOID mvBoardEnvInit(MV_VOID);
MV_U32 mvBoardIdGet(MV_VOID);
MV_U16 mvBoardModelGet(MV_VOID);
MV_U16 mvBoardRevGet(MV_VOID);
MV_STATUS mvBoardNameGet(char *pNameBuff);
MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum);
MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum);
MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum);
MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum);
MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum);
MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum);
MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum);
MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum);
MV_BOOL mvBoardIsPortInGmii(MV_VOID);
MV_U32 mvBoardTclkGet(MV_VOID);
MV_U32 mvBoardSysClkGet(MV_VOID);
MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId);
MV_VOID mvBoardDebugLed(MV_U32 hexNum);
MV_32 mvBoardMppGet(MV_U32 mppGroupNum);
MV_U8 mvBoardRtcTwsiAddrTypeGet(MV_VOID);
MV_U8 mvBoardRtcTwsiAddrGet(MV_VOID);
MV_U8 mvBoardA2DTwsiAddrTypeGet(MV_VOID);
MV_U8 mvBoardA2DTwsiAddrGet(MV_VOID);
MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index);
MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index);
MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index);
MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index);
MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass);
MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass);
MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass,
MV_BOARD_MPP_TYPE_CLASS mppGroupType);
MV_VOID mvBoardMppGroupIdUpdate(MV_VOID);
MV_VOID mvBoardMppMuxSet(MV_VOID);
MV_VOID mvBoardTdmMppSet(MV_32 chType);
MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode);
MV_VOID mvBoardMppModuleTypePrint(MV_VOID);
MV_VOID mvBoardReset(MV_VOID);
MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum);
MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal);
MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data);
/* Board devices API managments */
MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass);
MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass);
MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass);
MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass);
MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass);
MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass);
/* Gpio Pin Connections API */
MV_32 mvBoardUSBVbusGpioPinGet(int devId);
MV_32 mvBoardUSBVbusEnGpioPinGet(int devId);
MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin);
MV_32 mvBoardResetGpioPinGet(MV_VOID);
MV_32 mvBoardRTCGpioPinGet(MV_VOID);
MV_32 mvBoardGpioIntMaskLowGet(MV_VOID);
MV_32 mvBoardGpioIntMaskHighGet(MV_VOID);
MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum);
MV_32 mvBoardSDIOGpioPinGet(MV_VOID);
MV_STATUS mvBoardSDioWPControl(MV_BOOL mode);
MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index);
MV_32 mvBoardNandWidthGet(void);
MV_STATUS mvBoardFanPowerControl(MV_BOOL mode);
MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode);
#endif /* __INCmvBoardEnvLibh */

848
target/linux/generic-2.6/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c Normal file
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@ -0,0 +1,848 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "mvCommon.h"
#include "mvBoardEnvLib.h"
#include "mvBoardEnvSpec.h"
#include "twsi/mvTwsi.h"
#define DB_88F6281A_BOARD_PCI_IF_NUM 0x0
#define DB_88F6281A_BOARD_TWSI_DEF_NUM 0x7
#define DB_88F6281A_BOARD_MAC_INFO_NUM 0x2
#define DB_88F6281A_BOARD_GPP_INFO_NUM 0x3
#define DB_88F6281A_BOARD_MPP_CONFIG_NUM 0x1
#define DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1
#if defined(MV_NAND) && defined(MV_NAND_BOOT)
#define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1
#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
#define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2
#else
#define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1
#endif
#define DB_88F6281A_BOARD_DEBUG_LED_NUM 0x0
MV_BOARD_TWSI_INFO db88f6281AInfoBoardTwsiDev[] =
/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
{
{BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT},
{BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT},
{BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT},
{BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT},
{BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT},
{BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT},
{BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT}
};
MV_BOARD_MAC_INFO db88f6281AInfoBoardMacInfo[] =
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
{
{BOARD_MAC_SPEED_AUTO, 0x8},
{BOARD_MAC_SPEED_AUTO, 0x9}
};
MV_BOARD_MPP_TYPE_INFO db88f6281AInfoBoardMppTypeInfo[] =
/* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1,
MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */
{{MV_BOARD_AUTO, MV_BOARD_AUTO}
};
MV_BOARD_GPP_INFO db88f6281AInfoBoardGppInfo[] =
/* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */
{
{BOARD_GPP_TSU_DIRCTION, 33}
/*muxed with TDM/Audio module via IOexpender
{BOARD_GPP_SDIO_DETECT, 38},
{BOARD_GPP_USB_VBUS, 49}*/
};
MV_DEV_CS_INFO db88f6281AInfoBoardDeCsInfo[] =
/*{deviceCS, params, devType, devWidth}*/
#if defined(MV_NAND) && defined(MV_NAND_BOOT)
{{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */
#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
{
{0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */
{1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */
};
#else
{{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */
#endif
MV_BOARD_MPP_INFO db88f6281AInfoBoardMppConfigValue[] =
{{{
DB_88F6281A_MPP0_7,
DB_88F6281A_MPP8_15,
DB_88F6281A_MPP16_23,
DB_88F6281A_MPP24_31,
DB_88F6281A_MPP32_39,
DB_88F6281A_MPP40_47,
DB_88F6281A_MPP48_55
}}};
MV_BOARD_INFO db88f6281AInfo = {
"DB-88F6281A-BP", /* boardName[MAX_BOARD_NAME_LEN] */
DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
db88f6281AInfoBoardMppTypeInfo,
DB_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
db88f6281AInfoBoardMppConfigValue,
0, /* intsGppMaskLow */
0, /* intsGppMaskHigh */
DB_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
db88f6281AInfoBoardDeCsInfo,
DB_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
db88f6281AInfoBoardTwsiDev,
DB_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
db88f6281AInfoBoardMacInfo,
DB_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
db88f6281AInfoBoardGppInfo,
DB_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
NULL,
0, /* ledsPolarity */
DB_88F6281A_OE_LOW, /* gppOutEnLow */
DB_88F6281A_OE_HIGH, /* gppOutEnHigh */
DB_88F6281A_OE_VAL_LOW, /* gppOutValLow */
DB_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */
0, /* gppPolarityValLow */
BIT6, /* gppPolarityValHigh */
NULL /* pSwitchInfo */
};
#define RD_88F6281A_BOARD_PCI_IF_NUM 0x0
#define RD_88F6281A_BOARD_TWSI_DEF_NUM 0x2
#define RD_88F6281A_BOARD_MAC_INFO_NUM 0x2
#define RD_88F6281A_BOARD_GPP_INFO_NUM 0x5
#define RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1
#define RD_88F6281A_BOARD_MPP_CONFIG_NUM 0x1
#if defined(MV_NAND) && defined(MV_NAND_BOOT)
#define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1
#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
#define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2
#else
#define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1
#endif
#define RD_88F6281A_BOARD_DEBUG_LED_NUM 0x0
MV_BOARD_MAC_INFO rd88f6281AInfoBoardMacInfo[] =
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
{{BOARD_MAC_SPEED_1000M, 0xa},
{BOARD_MAC_SPEED_AUTO, 0xb}
};
MV_BOARD_SWITCH_INFO rd88f6281AInfoBoardSwitchInfo[] =
/* MV_32 linkStatusIrq, {MV_32 qdPort0, MV_32 qdPort1, MV_32 qdPort2, MV_32 qdPort3, MV_32 qdPort4},
MV_32 qdCpuPort, MV_32 smiScanMode, MV_32 switchOnPort} */
{{38, {0, 1, 2, 3, -1}, 5, 2, 0},
{-1, {-1}, -1, -1, -1}};
MV_BOARD_TWSI_INFO rd88f6281AInfoBoardTwsiDev[] =
/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
{
{BOARD_DEV_TWSI_EXP, 0xFF, ADDR7_BIT}, /* dummy entry to align with modules indexes */
{BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}
};
MV_BOARD_MPP_TYPE_INFO rd88f6281AInfoBoardMppTypeInfo[] =
{{MV_BOARD_RGMII, MV_BOARD_TDM}
};
MV_DEV_CS_INFO rd88f6281AInfoBoardDeCsInfo[] =
/*{deviceCS, params, devType, devWidth}*/
#if defined(MV_NAND) && defined(MV_NAND_BOOT)
{{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */
#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
{
{0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */
{1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */
};
#else
{{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */
#endif
MV_BOARD_GPP_INFO rd88f6281AInfoBoardGppInfo[] =
/* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */
{{BOARD_GPP_SDIO_DETECT, 28},
{BOARD_GPP_USB_OC, 29},
{BOARD_GPP_WPS_BUTTON, 35},
{BOARD_GPP_MV_SWITCH, 38},
{BOARD_GPP_USB_VBUS, 49}
};
MV_BOARD_MPP_INFO rd88f6281AInfoBoardMppConfigValue[] =
{{{
RD_88F6281A_MPP0_7,
RD_88F6281A_MPP8_15,
RD_88F6281A_MPP16_23,
RD_88F6281A_MPP24_31,
RD_88F6281A_MPP32_39,
RD_88F6281A_MPP40_47,
RD_88F6281A_MPP48_55
}}};
MV_BOARD_INFO rd88f6281AInfo = {
"RD-88F6281A", /* boardName[MAX_BOARD_NAME_LEN] */
RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
rd88f6281AInfoBoardMppTypeInfo,
RD_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
rd88f6281AInfoBoardMppConfigValue,
0, /* intsGppMaskLow */
(1 << 3), /* intsGppMaskHigh */
RD_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
rd88f6281AInfoBoardDeCsInfo,
RD_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
rd88f6281AInfoBoardTwsiDev,
RD_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
rd88f6281AInfoBoardMacInfo,
RD_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
rd88f6281AInfoBoardGppInfo,
RD_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
NULL,
0, /* ledsPolarity */
RD_88F6281A_OE_LOW, /* gppOutEnLow */
RD_88F6281A_OE_HIGH, /* gppOutEnHigh */
RD_88F6281A_OE_VAL_LOW, /* gppOutValLow */
RD_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */
0, /* gppPolarityValLow */
BIT6, /* gppPolarityValHigh */
rd88f6281AInfoBoardSwitchInfo /* pSwitchInfo */
};
#define DB_88F6192A_BOARD_PCI_IF_NUM 0x0
#define DB_88F6192A_BOARD_TWSI_DEF_NUM 0x7
#define DB_88F6192A_BOARD_MAC_INFO_NUM 0x2
#define DB_88F6192A_BOARD_GPP_INFO_NUM 0x3
#define DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1
#define DB_88F6192A_BOARD_MPP_CONFIG_NUM 0x1
#if defined(MV_NAND) && defined(MV_NAND_BOOT)
#define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1
#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
#define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x2
#else
#define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1
#endif
#define DB_88F6192A_BOARD_DEBUG_LED_NUM 0x0
MV_BOARD_TWSI_INFO db88f6192AInfoBoardTwsiDev[] =
/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
{
{BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT},
{BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT},
{BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT},
{BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT},
{BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT},
{BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT},
{BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT}
};
MV_BOARD_MAC_INFO db88f6192AInfoBoardMacInfo[] =
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
{
{BOARD_MAC_SPEED_AUTO, 0x8},
{BOARD_MAC_SPEED_AUTO, 0x9}
};
MV_BOARD_MPP_TYPE_INFO db88f6192AInfoBoardMppTypeInfo[] =
/* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1,
MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */
{{MV_BOARD_AUTO, MV_BOARD_OTHER}
};
MV_DEV_CS_INFO db88f6192AInfoBoardDeCsInfo[] =
/*{deviceCS, params, devType, devWidth}*/
#if defined(MV_NAND) && defined(MV_NAND_BOOT)
{{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */
#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
{
{0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */
{1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */
};
#else
{{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */
#endif
MV_BOARD_GPP_INFO db88f6192AInfoBoardGppInfo[] =
/* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */
{
{BOARD_GPP_SDIO_WP, 20},
{BOARD_GPP_USB_VBUS, 22},
{BOARD_GPP_SDIO_DETECT, 23},
};
MV_BOARD_MPP_INFO db88f6192AInfoBoardMppConfigValue[] =
{{{
DB_88F6192A_MPP0_7,
DB_88F6192A_MPP8_15,
DB_88F6192A_MPP16_23,
DB_88F6192A_MPP24_31,
DB_88F6192A_MPP32_35
}}};
MV_BOARD_INFO db88f6192AInfo = {
"DB-88F6192A-BP", /* boardName[MAX_BOARD_NAME_LEN] */
DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
db88f6192AInfoBoardMppTypeInfo,
DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
db88f6192AInfoBoardMppConfigValue,
0, /* intsGppMaskLow */
(1 << 3), /* intsGppMaskHigh */
DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
db88f6192AInfoBoardDeCsInfo,
DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
db88f6192AInfoBoardTwsiDev,
DB_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
db88f6192AInfoBoardMacInfo,
DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
db88f6192AInfoBoardGppInfo,
DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
NULL,
0, /* ledsPolarity */
DB_88F6192A_OE_LOW, /* gppOutEnLow */
DB_88F6192A_OE_HIGH, /* gppOutEnHigh */
DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */
DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */
0, /* gppPolarityValLow */
0, /* gppPolarityValHigh */
NULL /* pSwitchInfo */
};
#define DB_88F6190A_BOARD_MAC_INFO_NUM 0x1
MV_BOARD_INFO db88f6190AInfo = {
"DB-88F6190A-BP", /* boardName[MAX_BOARD_NAME_LEN] */
DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
db88f6192AInfoBoardMppTypeInfo,
DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
db88f6192AInfoBoardMppConfigValue,
0, /* intsGppMaskLow */
(1 << 3), /* intsGppMaskHigh */
DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
db88f6192AInfoBoardDeCsInfo,
DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
db88f6192AInfoBoardTwsiDev,
DB_88F6190A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
db88f6192AInfoBoardMacInfo,
DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
db88f6192AInfoBoardGppInfo,
DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
NULL,
0, /* ledsPolarity */
DB_88F6192A_OE_LOW, /* gppOutEnLow */
DB_88F6192A_OE_HIGH, /* gppOutEnHigh */
DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */
DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */
0, /* gppPolarityValLow */
0, /* gppPolarityValHigh */
NULL /* pSwitchInfo */
};
#define RD_88F6192A_BOARD_PCI_IF_NUM 0x0
#define RD_88F6192A_BOARD_TWSI_DEF_NUM 0x0
#define RD_88F6192A_BOARD_MAC_INFO_NUM 0x1
#define RD_88F6192A_BOARD_GPP_INFO_NUM 0xE
#define RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1
#define RD_88F6192A_BOARD_MPP_CONFIG_NUM 0x1
#define RD_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1
#define RD_88F6192A_BOARD_DEBUG_LED_NUM 0x3
MV_U8 rd88f6192AInfoBoardDebugLedIf[] =
{17, 28, 29};
MV_BOARD_MAC_INFO rd88f6192AInfoBoardMacInfo[] =
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
{{BOARD_MAC_SPEED_AUTO, 0x8}
};
MV_BOARD_MPP_TYPE_INFO rd88f6192AInfoBoardMppTypeInfo[] =
/* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1,
MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */
{{MV_BOARD_OTHER, MV_BOARD_OTHER}
};
MV_DEV_CS_INFO rd88f6192AInfoBoardDeCsInfo[] =
/*{deviceCS, params, devType, devWidth}*/
{{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */
MV_BOARD_GPP_INFO rd88f6192AInfoBoardGppInfo[] =
/* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */
{
{BOARD_GPP_USB_VBUS_EN, 10},
{BOARD_GPP_USB_HOST_DEVICE, 11},
{BOARD_GPP_RESET, 14},
{BOARD_GPP_POWER_ON_LED, 15},
{BOARD_GPP_HDD_POWER, 16},
{BOARD_GPP_WPS_BUTTON, 24},
{BOARD_GPP_TS_BUTTON_C, 25},
{BOARD_GPP_USB_VBUS, 26},
{BOARD_GPP_USB_OC, 27},
{BOARD_GPP_TS_BUTTON_U, 30},
{BOARD_GPP_TS_BUTTON_R, 31},
{BOARD_GPP_TS_BUTTON_L, 32},
{BOARD_GPP_TS_BUTTON_D, 34},
{BOARD_GPP_FAN_POWER, 35}
};
MV_BOARD_MPP_INFO rd88f6192AInfoBoardMppConfigValue[] =
{{{
RD_88F6192A_MPP0_7,
RD_88F6192A_MPP8_15,
RD_88F6192A_MPP16_23,
RD_88F6192A_MPP24_31,
RD_88F6192A_MPP32_35
}}};
MV_BOARD_INFO rd88f6192AInfo = {
"RD-88F6192A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */
RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
rd88f6192AInfoBoardMppTypeInfo,
RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
rd88f6192AInfoBoardMppConfigValue,
0, /* intsGppMaskLow */
(1 << 3), /* intsGppMaskHigh */
RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
rd88f6192AInfoBoardDeCsInfo,
RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
NULL,
RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
rd88f6192AInfoBoardMacInfo,
RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
rd88f6192AInfoBoardGppInfo,
RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
rd88f6192AInfoBoardDebugLedIf,
0, /* ledsPolarity */
RD_88F6192A_OE_LOW, /* gppOutEnLow */
RD_88F6192A_OE_HIGH, /* gppOutEnHigh */
RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */
RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */
0, /* gppPolarityValLow */
0, /* gppPolarityValHigh */
NULL /* pSwitchInfo */
};
MV_BOARD_INFO rd88f6190AInfo = {
"RD-88F6190A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */
RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
rd88f6192AInfoBoardMppTypeInfo,
RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
rd88f6192AInfoBoardMppConfigValue,
0, /* intsGppMaskLow */
(1 << 3), /* intsGppMaskHigh */
RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
rd88f6192AInfoBoardDeCsInfo,
RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
NULL,
RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
rd88f6192AInfoBoardMacInfo,
RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
rd88f6192AInfoBoardGppInfo,
RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
rd88f6192AInfoBoardDebugLedIf,
0, /* ledsPolarity */
RD_88F6192A_OE_LOW, /* gppOutEnLow */
RD_88F6192A_OE_HIGH, /* gppOutEnHigh */
RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */
RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */
0, /* gppPolarityValLow */
0, /* gppPolarityValHigh */
NULL /* pSwitchInfo */
};
#define DB_88F6180A_BOARD_PCI_IF_NUM 0x0
#define DB_88F6180A_BOARD_TWSI_DEF_NUM 0x5
#define DB_88F6180A_BOARD_MAC_INFO_NUM 0x1
#define DB_88F6180A_BOARD_GPP_INFO_NUM 0x0
#define DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM 0x2
#define DB_88F6180A_BOARD_MPP_CONFIG_NUM 0x1
#define DB_88F6180A_BOARD_DEVICE_CONFIG_NUM 0x1
#define DB_88F6180A_BOARD_DEBUG_LED_NUM 0x0
MV_BOARD_TWSI_INFO db88f6180AInfoBoardTwsiDev[] =
/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
{
{BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT},
{BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT},
{BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT},
{BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT},
{BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT}
};
MV_BOARD_MAC_INFO db88f6180AInfoBoardMacInfo[] =
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
{{BOARD_MAC_SPEED_AUTO, 0x8}
};
MV_BOARD_GPP_INFO db88f6180AInfoBoardGppInfo[] =
/* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */
{
/* Muxed with TDM/Audio module via IOexpender
{BOARD_GPP_USB_VBUS, 6} */
};
MV_BOARD_MPP_TYPE_INFO db88f6180AInfoBoardMppTypeInfo[] =
/* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1,
MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */
{{MV_BOARD_OTHER, MV_BOARD_AUTO}
};
MV_DEV_CS_INFO db88f6180AInfoBoardDeCsInfo[] =
/*{deviceCS, params, devType, devWidth}*/
#if defined(MV_NAND_BOOT)
{{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */
#else
{{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */
#endif
MV_BOARD_MPP_INFO db88f6180AInfoBoardMppConfigValue[] =
{{{
DB_88F6180A_MPP0_7,
DB_88F6180A_MPP8_15,
DB_88F6180A_MPP16_23,
DB_88F6180A_MPP24_31,
DB_88F6180A_MPP32_39,
DB_88F6180A_MPP40_44
}}};
MV_BOARD_INFO db88f6180AInfo = {
"DB-88F6180A-BP", /* boardName[MAX_BOARD_NAME_LEN] */
DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
db88f6180AInfoBoardMppTypeInfo,
DB_88F6180A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
db88f6180AInfoBoardMppConfigValue,
0, /* intsGppMaskLow */
0, /* intsGppMaskHigh */
DB_88F6180A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
db88f6180AInfoBoardDeCsInfo,
DB_88F6180A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
db88f6180AInfoBoardTwsiDev,
DB_88F6180A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
db88f6180AInfoBoardMacInfo,
DB_88F6180A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
NULL,
DB_88F6180A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
NULL,
0, /* ledsPolarity */
DB_88F6180A_OE_LOW, /* gppOutEnLow */
DB_88F6180A_OE_HIGH, /* gppOutEnHigh */
DB_88F6180A_OE_VAL_LOW, /* gppOutValLow */
DB_88F6180A_OE_VAL_HIGH, /* gppOutValHigh */
0, /* gppPolarityValLow */
0, /* gppPolarityValHigh */
NULL /* pSwitchInfo */
};
#define RD_88F6281A_PCAC_BOARD_PCI_IF_NUM 0x0
#define RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM 0x1
#define RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM 0x1
#define RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM 0x0
#define RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM 0x1
#define RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM 0x1
#if defined(MV_NAND) && defined(MV_NAND_BOOT)
#define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1
#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
#define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x2
#else
#define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1
#endif
#define RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM 0x4
MV_U8 rd88f6281APcacInfoBoardDebugLedIf[] =
{38, 39, 40, 41};
MV_BOARD_MAC_INFO rd88f6281APcacInfoBoardMacInfo[] =
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
{{BOARD_MAC_SPEED_AUTO, 0x8}
};
MV_BOARD_TWSI_INFO rd88f6281APcacInfoBoardTwsiDev[] =
/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
{
{BOARD_TWSI_OTHER, 0xa7, ADDR7_BIT}
};
MV_BOARD_MPP_TYPE_INFO rd88f6281APcacInfoBoardMppTypeInfo[] =
{{MV_BOARD_OTHER, MV_BOARD_OTHER}
};
MV_DEV_CS_INFO rd88f6281APcacInfoBoardDeCsInfo[] =
/*{deviceCS, params, devType, devWidth}*/
#if defined(MV_NAND) && defined(MV_NAND_BOOT)
{{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */
#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
{
{0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */
{1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */
};
#else
{{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */
#endif
MV_BOARD_MPP_INFO rd88f6281APcacInfoBoardMppConfigValue[] =
{{{
RD_88F6281A_PCAC_MPP0_7,
RD_88F6281A_PCAC_MPP8_15,
RD_88F6281A_PCAC_MPP16_23,
RD_88F6281A_PCAC_MPP24_31,
RD_88F6281A_PCAC_MPP32_39,
RD_88F6281A_PCAC_MPP40_47,
RD_88F6281A_PCAC_MPP48_55
}}};
MV_BOARD_INFO rd88f6281APcacInfo = {
"RD-88F6281A-PCAC", /* boardName[MAX_BOARD_NAME_LEN] */
RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
rd88f6281APcacInfoBoardMppTypeInfo,
RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
rd88f6281APcacInfoBoardMppConfigValue,
0, /* intsGppMaskLow */
(1 << 3), /* intsGppMaskHigh */
RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
rd88f6281APcacInfoBoardDeCsInfo,
RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
rd88f6281APcacInfoBoardTwsiDev,
RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
rd88f6281APcacInfoBoardMacInfo,
RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
0,
RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
NULL,
0, /* ledsPolarity */
RD_88F6281A_PCAC_OE_LOW, /* gppOutEnLow */
RD_88F6281A_PCAC_OE_HIGH, /* gppOutEnHigh */
RD_88F6281A_PCAC_OE_VAL_LOW, /* gppOutValLow */
RD_88F6281A_PCAC_OE_VAL_HIGH, /* gppOutValHigh */
0, /* gppPolarityValLow */
0, /* gppPolarityValHigh */
NULL /* pSwitchInfo */
};
/* 6281 Sheeva Plug*/
#define SHEEVA_PLUG_BOARD_PCI_IF_NUM 0x0
#define SHEEVA_PLUG_BOARD_TWSI_DEF_NUM 0x0
#define SHEEVA_PLUG_BOARD_MAC_INFO_NUM 0x1
#define SHEEVA_PLUG_BOARD_GPP_INFO_NUM 0x0
#define SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN 0x1
#define SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM 0x1
#define SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM 0x1
#define SHEEVA_PLUG_BOARD_DEBUG_LED_NUM 0x1
MV_U8 sheevaPlugInfoBoardDebugLedIf[] =
{49};
MV_BOARD_MAC_INFO sheevaPlugInfoBoardMacInfo[] =
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
{{BOARD_MAC_SPEED_AUTO, 0x0}};
MV_BOARD_TWSI_INFO sheevaPlugInfoBoardTwsiDev[] =
/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
{{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}};
MV_BOARD_MPP_TYPE_INFO sheevaPlugInfoBoardMppTypeInfo[] =
{{MV_BOARD_OTHER, MV_BOARD_OTHER}
};
MV_DEV_CS_INFO sheevaPlugInfoBoardDeCsInfo[] =
/*{deviceCS, params, devType, devWidth}*/
{{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */
MV_BOARD_MPP_INFO sheevaPlugInfoBoardMppConfigValue[] =
{{{
RD_SHEEVA_PLUG_MPP0_7,
RD_SHEEVA_PLUG_MPP8_15,
RD_SHEEVA_PLUG_MPP16_23,
RD_SHEEVA_PLUG_MPP24_31,
RD_SHEEVA_PLUG_MPP32_39,
RD_SHEEVA_PLUG_MPP40_47,
RD_SHEEVA_PLUG_MPP48_55
}}};
MV_BOARD_INFO sheevaPlugInfo = {
"SHEEVA PLUG", /* boardName[MAX_BOARD_NAME_LEN] */
SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */
sheevaPlugInfoBoardMppTypeInfo,
SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
sheevaPlugInfoBoardMppConfigValue,
0, /* intsGppMaskLow */
0, /* intsGppMaskHigh */
SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
sheevaPlugInfoBoardDeCsInfo,
SHEEVA_PLUG_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
sheevaPlugInfoBoardTwsiDev,
SHEEVA_PLUG_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
sheevaPlugInfoBoardMacInfo,
SHEEVA_PLUG_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
0,
SHEEVA_PLUG_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
sheevaPlugInfoBoardDebugLedIf,
0, /* ledsPolarity */
RD_SHEEVA_PLUG_OE_LOW, /* gppOutEnLow */
RD_SHEEVA_PLUG_OE_HIGH, /* gppOutEnHigh */
RD_SHEEVA_PLUG_OE_VAL_LOW, /* gppOutValLow */
RD_SHEEVA_PLUG_OE_VAL_HIGH, /* gppOutValHigh */
0, /* gppPolarityValLow */
0, /* gppPolarityValHigh */
NULL /* pSwitchInfo */
};
/* Customer specific board place holder*/
#define DB_CUSTOMER_BOARD_PCI_IF_NUM 0x0
#define DB_CUSTOMER_BOARD_TWSI_DEF_NUM 0x0
#define DB_CUSTOMER_BOARD_MAC_INFO_NUM 0x0
#define DB_CUSTOMER_BOARD_GPP_INFO_NUM 0x0
#define DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN 0x0
#define DB_CUSTOMER_BOARD_MPP_CONFIG_NUM 0x0
#if defined(MV_NAND) && defined(MV_NAND_BOOT)
#define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0
#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
#define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0
#else
#define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0
#endif
#define DB_CUSTOMER_BOARD_DEBUG_LED_NUM 0x0
MV_U8 dbCustomerInfoBoardDebugLedIf[] =
{0};
MV_BOARD_MAC_INFO dbCustomerInfoBoardMacInfo[] =
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
{{BOARD_MAC_SPEED_AUTO, 0x0}};
MV_BOARD_TWSI_INFO dbCustomerInfoBoardTwsiDev[] =
/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
{{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}};
MV_BOARD_MPP_TYPE_INFO dbCustomerInfoBoardMppTypeInfo[] =
{{MV_BOARD_OTHER, MV_BOARD_OTHER}
};
MV_DEV_CS_INFO dbCustomerInfoBoardDeCsInfo[] =
/*{deviceCS, params, devType, devWidth}*/
#if defined(MV_NAND) && defined(MV_NAND_BOOT)
{{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */
#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
{
{0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */
{2, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */
};
#else
{{2, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */
#endif
MV_BOARD_MPP_INFO dbCustomerInfoBoardMppConfigValue[] =
{{{
DB_CUSTOMER_MPP0_7,
DB_CUSTOMER_MPP8_15,
DB_CUSTOMER_MPP16_23,
DB_CUSTOMER_MPP24_31,
DB_CUSTOMER_MPP32_39,
DB_CUSTOMER_MPP40_47,
DB_CUSTOMER_MPP48_55
}}};
MV_BOARD_INFO dbCustomerInfo = {
"DB-CUSTOMER", /* boardName[MAX_BOARD_NAME_LEN] */
DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */
dbCustomerInfoBoardMppTypeInfo,
DB_CUSTOMER_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
dbCustomerInfoBoardMppConfigValue,
0, /* intsGppMaskLow */
0, /* intsGppMaskHigh */
DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
dbCustomerInfoBoardDeCsInfo,
DB_CUSTOMER_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
dbCustomerInfoBoardTwsiDev,
DB_CUSTOMER_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
dbCustomerInfoBoardMacInfo,
DB_CUSTOMER_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
0,
DB_CUSTOMER_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
NULL,
0, /* ledsPolarity */
DB_CUSTOMER_OE_LOW, /* gppOutEnLow */
DB_CUSTOMER_OE_HIGH, /* gppOutEnHigh */
DB_CUSTOMER_OE_VAL_LOW, /* gppOutValLow */
DB_CUSTOMER_OE_VAL_HIGH, /* gppOutValHigh */
0, /* gppPolarityValLow */
0, /* gppPolarityValHigh */
NULL /* pSwitchInfo */
};
MV_BOARD_INFO* boardInfoTbl[] = {
&db88f6281AInfo,
&rd88f6281AInfo,
&db88f6192AInfo,
&rd88f6192AInfo,
&db88f6180AInfo,
&db88f6190AInfo,
&rd88f6190AInfo,
&rd88f6281APcacInfo,
&dbCustomerInfo,
&sheevaPlugInfo
};

262
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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvBoardEnvSpech
#define __INCmvBoardEnvSpech
#include "mvSysHwConfig.h"
/* For future use */
#define BD_ID_DATA_START_OFFS 0x0
#define BD_DETECT_SEQ_OFFS 0x0
#define BD_SYS_NUM_OFFS 0x4
#define BD_NAME_OFFS 0x8
/* I2C bus addresses */
#define MV_BOARD_CTRL_I2C_ADDR 0x0 /* Controller slave addr */
#define MV_BOARD_CTRL_I2C_ADDR_TYPE ADDR7_BIT
#define MV_BOARD_DIMM0_I2C_ADDR 0x56
#define MV_BOARD_DIMM0_I2C_ADDR_TYPE ADDR7_BIT
#define MV_BOARD_DIMM1_I2C_ADDR 0x54
#define MV_BOARD_DIMM1_I2C_ADDR_TYPE ADDR7_BIT
#define MV_BOARD_EEPROM_I2C_ADDR 0x51
#define MV_BOARD_EEPROM_I2C_ADDR_TYPE ADDR7_BIT
#define MV_BOARD_MAIN_EEPROM_I2C_ADDR 0x50
#define MV_BOARD_MAIN_EEPROM_I2C_ADDR_TYPE ADDR7_BIT
#define MV_BOARD_MUX_I2C_ADDR_ENTRY 0x2
#define MV_BOARD_DIMM_I2C_CHANNEL 0x0
#define BOOT_FLASH_INDEX 0
#define MAIN_FLASH_INDEX 1
#define BOARD_ETH_START_PORT_NUM 0
/* Supported clocks */
#define MV_BOARD_TCLK_100MHZ 100000000
#define MV_BOARD_TCLK_125MHZ 125000000
#define MV_BOARD_TCLK_133MHZ 133333333
#define MV_BOARD_TCLK_150MHZ 150000000
#define MV_BOARD_TCLK_166MHZ 166666667
#define MV_BOARD_TCLK_200MHZ 200000000
#define MV_BOARD_SYSCLK_100MHZ 100000000
#define MV_BOARD_SYSCLK_125MHZ 125000000
#define MV_BOARD_SYSCLK_133MHZ 133333333
#define MV_BOARD_SYSCLK_150MHZ 150000000
#define MV_BOARD_SYSCLK_166MHZ 166666667
#define MV_BOARD_SYSCLK_200MHZ 200000000
#define MV_BOARD_SYSCLK_233MHZ 233333333
#define MV_BOARD_SYSCLK_250MHZ 250000000
#define MV_BOARD_SYSCLK_267MHZ 266666667
#define MV_BOARD_SYSCLK_300MHZ 300000000
#define MV_BOARD_SYSCLK_333MHZ 333333334
#define MV_BOARD_SYSCLK_400MHZ 400000000
#define MV_BOARD_REFCLK_25MHZ 25000000
/* Board specific */
/* =============================== */
/* boards ID numbers */
#define BOARD_ID_BASE 0x0
/* New board ID numbers */
#define DB_88F6281A_BP_ID (BOARD_ID_BASE)
#define DB_88F6281_BP_MLL_ID 1680
#define RD_88F6281A_ID (BOARD_ID_BASE+0x1)
#define RD_88F6281_MLL_ID 1682
#define DB_88F6192A_BP_ID (BOARD_ID_BASE+0x2)
#define RD_88F6192A_ID (BOARD_ID_BASE+0x3)
#define RD_88F6192_MLL_ID 1681
#define DB_88F6180A_BP_ID (BOARD_ID_BASE+0x4)
#define DB_88F6190A_BP_ID (BOARD_ID_BASE+0x5)
#define RD_88F6190A_ID (BOARD_ID_BASE+0x6)
#define RD_88F6281A_PCAC_ID (BOARD_ID_BASE+0x7)
#define DB_CUSTOMER_ID (BOARD_ID_BASE+0x8)
#define SHEEVA_PLUG_ID (BOARD_ID_BASE+0x9)
#define MV_MAX_BOARD_ID (SHEEVA_PLUG_ID + 1)
/* DB-88F6281A-BP */
#if defined(MV_NAND)
#define DB_88F6281A_MPP0_7 0x21111111
#else
#define DB_88F6281A_MPP0_7 0x21112220
#endif
#define DB_88F6281A_MPP8_15 0x11113311
#define DB_88F6281A_MPP16_23 0x00551111
#define DB_88F6281A_MPP24_31 0x00000000
#define DB_88F6281A_MPP32_39 0x00000000
#define DB_88F6281A_MPP40_47 0x00000000
#define DB_88F6281A_MPP48_55 0x00000000
#define DB_88F6281A_OE_LOW 0x0
#if defined(MV_TDM_5CHANNELS)
#define DB_88F6281A_OE_HIGH (BIT6)
#else
#define DB_88F6281A_OE_HIGH 0x0
#endif
#define DB_88F6281A_OE_VAL_LOW 0x0
#define DB_88F6281A_OE_VAL_HIGH 0x0
/* RD-88F6281A */
#if defined(MV_NAND)
#define RD_88F6281A_MPP0_7 0x21111111
#else
#define RD_88F6281A_MPP0_7 0x21112220
#endif
#define RD_88F6281A_MPP8_15 0x11113311
#define RD_88F6281A_MPP16_23 0x33331111
#define RD_88F6281A_MPP24_31 0x33003333
#define RD_88F6281A_MPP32_39 0x20440533
#define RD_88F6281A_MPP40_47 0x22202222
#define RD_88F6281A_MPP48_55 0x00000002
#define RD_88F6281A_OE_LOW (BIT28 | BIT29)
#define RD_88F6281A_OE_HIGH (BIT3 | BIT6 | BIT17)
#define RD_88F6281A_OE_VAL_LOW 0x0
#define RD_88F6281A_OE_VAL_HIGH 0x0
/* DB-88F6192A-BP */
#if defined(MV_NAND)
#define DB_88F6192A_MPP0_7 0x21111111
#else
#define DB_88F6192A_MPP0_7 0x21112220
#endif
#define DB_88F6192A_MPP8_15 0x11113311
#define DB_88F6192A_MPP16_23 0x00501111
#define DB_88F6192A_MPP24_31 0x00000000
#define DB_88F6192A_MPP32_35 0x00000000
#define DB_88F6192A_OE_LOW (BIT22 | BIT23)
#define DB_88F6192A_OE_HIGH 0x0
#define DB_88F6192A_OE_VAL_LOW 0x0
#define DB_88F6192A_OE_VAL_HIGH 0x0
/* RD-88F6192A */
#define RD_88F6192A_MPP0_7 0x01222222
#define RD_88F6192A_MPP8_15 0x00000011
#define RD_88F6192A_MPP16_23 0x05550000
#define RD_88F6192A_MPP24_31 0x0
#define RD_88F6192A_MPP32_35 0x0
#define RD_88F6192A_OE_LOW (BIT11 | BIT14 | BIT24 | BIT25 | BIT26 | BIT27 | BIT30 | BIT31)
#define RD_88F6192A_OE_HIGH (BIT0 | BIT2)
#define RD_88F6192A_OE_VAL_LOW 0x18400
#define RD_88F6192A_OE_VAL_HIGH 0x8
/* DB-88F6180A-BP */
#if defined(MV_NAND)
#define DB_88F6180A_MPP0_7 0x21111111
#else
#define DB_88F6180A_MPP0_7 0x01112222
#endif
#define DB_88F6180A_MPP8_15 0x11113311
#define DB_88F6180A_MPP16_23 0x00001111
#define DB_88F6180A_MPP24_31 0x0
#define DB_88F6180A_MPP32_39 0x4444c000
#define DB_88F6180A_MPP40_44 0x00044444
#define DB_88F6180A_OE_LOW 0x0
#define DB_88F6180A_OE_HIGH 0x0
#define DB_88F6180A_OE_VAL_LOW 0x0
#define DB_88F6180A_OE_VAL_HIGH 0x0
/* RD-88F6281A_PCAC */
#define RD_88F6281A_PCAC_MPP0_7 0x21111111
#define RD_88F6281A_PCAC_MPP8_15 0x00003311
#define RD_88F6281A_PCAC_MPP16_23 0x00001100
#define RD_88F6281A_PCAC_MPP24_31 0x00000000
#define RD_88F6281A_PCAC_MPP32_39 0x00000000
#define RD_88F6281A_PCAC_MPP40_47 0x00000000
#define RD_88F6281A_PCAC_MPP48_55 0x00000000
#define RD_88F6281A_PCAC_OE_LOW 0x0
#define RD_88F6281A_PCAC_OE_HIGH 0x0
#define RD_88F6281A_PCAC_OE_VAL_LOW 0x0
#define RD_88F6281A_PCAC_OE_VAL_HIGH 0x0
/* SHEEVA PLUG */
#define RD_SHEEVA_PLUG_MPP0_7 0x01111111
#define RD_SHEEVA_PLUG_MPP8_15 0x11113322
#define RD_SHEEVA_PLUG_MPP16_23 0x00001111
#define RD_SHEEVA_PLUG_MPP24_31 0x00100000
#define RD_SHEEVA_PLUG_MPP32_39 0x00000000
#define RD_SHEEVA_PLUG_MPP40_47 0x00000000
#define RD_SHEEVA_PLUG_MPP48_55 0x00000000
#define RD_SHEEVA_PLUG_OE_LOW 0x0
#define RD_SHEEVA_PLUG_OE_HIGH 0x0
#define RD_SHEEVA_PLUG_OE_VAL_LOW (BIT29)
#define RD_SHEEVA_PLUG_OE_VAL_HIGH ((~(BIT17 | BIT16 | BIT15)) | BIT14)
/* DB-CUSTOMER */
#define DB_CUSTOMER_MPP0_7 0x21111111
#define DB_CUSTOMER_MPP8_15 0x00003311
#define DB_CUSTOMER_MPP16_23 0x00001100
#define DB_CUSTOMER_MPP24_31 0x00000000
#define DB_CUSTOMER_MPP32_39 0x00000000
#define DB_CUSTOMER_MPP40_47 0x00000000
#define DB_CUSTOMER_MPP48_55 0x00000000
#define DB_CUSTOMER_OE_LOW 0x0
#define DB_CUSTOMER_OE_HIGH (~((BIT6) | (BIT7) | (BIT8) | (BIT9)))
#define DB_CUSTOMER_OE_VAL_LOW 0x0
#define DB_CUSTOMER_OE_VAL_HIGH 0x0
#endif /* __INCmvBoardEnvSpech */

320
target/linux/generic-2.6/files/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c Normal file
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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "cpu/mvCpu.h"
#include "ctrlEnv/mvCtrlEnvLib.h"
#include "ctrlEnv/mvCtrlEnvRegs.h"
#include "ctrlEnv/sys/mvCpuIfRegs.h"
/* defines */
#ifdef MV_DEBUG
#define DB(x) x
#else
#define DB(x)
#endif
/* locals */
/*******************************************************************************
* mvCpuPclkGet - Get the CPU pClk (pipe clock)
*
* DESCRIPTION:
* This routine extract the CPU core clock.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* 32bit clock cycles in MHertz.
*
*******************************************************************************/
/* 6180 have different clk reset sampling */
static MV_U32 mvCpu6180PclkGet(MV_VOID)
{
MV_U32 tmpPClkRate=0;
MV_CPU_ARM_CLK cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL;
tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET);
tmpPClkRate = tmpPClkRate & MSAR_CPUCLCK_MASK_6180;
tmpPClkRate = tmpPClkRate >> MSAR_CPUCLCK_OFFS_6180;
tmpPClkRate = cpu6180_ddr_l2_CLK[tmpPClkRate].cpuClk;
return tmpPClkRate;
}
MV_U32 mvCpuPclkGet(MV_VOID)
{
#if defined(PCLCK_AUTO_DETECT)
MV_U32 tmpPClkRate=0;
MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL;
if(mvCtrlModelGet() == MV_6180_DEV_ID)
return mvCpu6180PclkGet();
tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET);
tmpPClkRate = MSAR_CPUCLCK_EXTRACT(tmpPClkRate);
tmpPClkRate = cpuCLK[tmpPClkRate];
return tmpPClkRate;
#else
return MV_DEFAULT_PCLK
#endif
}
/*******************************************************************************
* mvCpuL2ClkGet - Get the CPU L2 (CPU bus clock)
*
* DESCRIPTION:
* This routine extract the CPU L2 clock.
*
* RETURN:
* 32bit clock cycles in Hertz.
*
*******************************************************************************/
static MV_U32 mvCpu6180L2ClkGet(MV_VOID)
{
MV_U32 L2ClkRate=0;
MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL;
L2ClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET);
L2ClkRate = L2ClkRate & MSAR_CPUCLCK_MASK_6180;
L2ClkRate = L2ClkRate >> MSAR_CPUCLCK_OFFS_6180;
L2ClkRate = _cpu6180_ddr_l2_CLK[L2ClkRate].l2Clk;
return L2ClkRate;
}
MV_U32 mvCpuL2ClkGet(MV_VOID)
{
#ifdef L2CLK_AUTO_DETECT
MV_U32 L2ClkRate, tmp, pClkRate, indexL2Rtio;
MV_U32 L2Rtio[][2] = MV_L2_CLCK_RTIO_TBL;
if(mvCtrlModelGet() == MV_6180_DEV_ID)
return mvCpu6180L2ClkGet();
pClkRate = mvCpuPclkGet();
tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET);
indexL2Rtio = MSAR_L2CLCK_EXTRACT(tmp);
L2ClkRate = ((pClkRate * L2Rtio[indexL2Rtio][1]) / L2Rtio[indexL2Rtio][0]);
return L2ClkRate;
#else
return MV_BOARD_DEFAULT_L2CLK;
#endif
}
/*******************************************************************************
* mvCpuNameGet - Get CPU name
*
* DESCRIPTION:
* This function returns a string describing the CPU model and revision.
*
* INPUT:
* None.
*
* OUTPUT:
* pNameBuff - Buffer to contain board name string. Minimum size 32 chars.
*
* RETURN:
* None.
*******************************************************************************/
MV_VOID mvCpuNameGet(char *pNameBuff)
{
MV_U32 cpuModel;
cpuModel = mvOsCpuPartGet();
/* The CPU module is indicated in the Processor Version Register (PVR) */
switch(cpuModel)
{
case CPU_PART_MRVL131:
mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell Feroceon",mvOsCpuRevGet());
break;
case CPU_PART_ARM926:
mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM926",mvOsCpuRevGet());
break;
case CPU_PART_ARM946:
mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM946",mvOsCpuRevGet());
break;
default:
mvOsSPrintf(pNameBuff,"??? (0x%04x) (Rev %d)",cpuModel,mvOsCpuRevGet());
break;
} /* switch */
return;
}
#define MV_PROC_STR_SIZE 50
static void mvCpuIfGetL2EccMode(MV_8 *buf)
{
MV_U32 regVal = MV_REG_READ(CPU_L2_CONFIG_REG);
if (regVal & BIT2)
mvOsSPrintf(buf, "L2 ECC Enabled");
else
mvOsSPrintf(buf, "L2 ECC Disabled");
}
static void mvCpuIfGetL2Mode(MV_8 *buf)
{
MV_U32 regVal = 0;
__asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
if (regVal & BIT22)
mvOsSPrintf(buf, "L2 Enabled");
else
mvOsSPrintf(buf, "L2 Disabled");
}
static void mvCpuIfGetL2PrefetchMode(MV_8 *buf)
{
MV_U32 regVal = 0;
__asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
if (regVal & BIT24)
mvOsSPrintf(buf, "L2 Prefetch Disabled");
else
mvOsSPrintf(buf, "L2 Prefetch Enabled");
}
static void mvCpuIfGetWriteAllocMode(MV_8 *buf)
{
MV_U32 regVal = 0;
__asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
if (regVal & BIT28)
mvOsSPrintf(buf, "Write Allocate Enabled");
else
mvOsSPrintf(buf, "Write Allocate Disabled");
}
static void mvCpuIfGetCpuStreamMode(MV_8 *buf)
{
MV_U32 regVal = 0;
__asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
if (regVal & BIT29)
mvOsSPrintf(buf, "CPU Streaming Enabled");
else
mvOsSPrintf(buf, "CPU Streaming Disabled");
}
static void mvCpuIfPrintCpuRegs(void)
{
MV_U32 regVal = 0;
__asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
mvOsPrintf("Extra Feature Reg = 0x%x\n",regVal);
__asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Control register */
mvOsPrintf("Control Reg = 0x%x\n",regVal);
__asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal)); /* Read ID Code register */
mvOsPrintf("ID Code Reg = 0x%x\n",regVal);
__asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal)); /* Read Cache Type register */
mvOsPrintf("Cache Type Reg = 0x%x\n",regVal);
}
MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index)
{
MV_U32 count = 0;
MV_8 L2_ECC_str[MV_PROC_STR_SIZE];
MV_8 L2_En_str[MV_PROC_STR_SIZE];
MV_8 L2_Prefetch_str[MV_PROC_STR_SIZE];
MV_8 Write_Alloc_str[MV_PROC_STR_SIZE];
MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE];
mvCpuIfGetL2Mode(L2_En_str);
mvCpuIfGetL2EccMode(L2_ECC_str);
mvCpuIfGetL2PrefetchMode(L2_Prefetch_str);
mvCpuIfGetWriteAllocMode(Write_Alloc_str);
mvCpuIfGetCpuStreamMode(Cpu_Stream_str);
mvCpuIfPrintCpuRegs();
count += mvOsSPrintf(buffer + count + index, "%s\n", L2_En_str);
count += mvOsSPrintf(buffer + count + index, "%s\n", L2_ECC_str);
count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Prefetch_str);
count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str);
count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str);
return count;
}
MV_U32 whoAmI(MV_VOID)
{
return 0;
}

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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvCpuh
#define __INCmvCpuh
#include "mvCommon.h"
#include "mvOs.h"
#include "ctrlEnv/mvCtrlEnvSpec.h"
/* defines */
#define CPU_PART_MRVL131 0x131
#define CPU_PART_ARM926 0x926
#define CPU_PART_ARM946 0x946
#define MV_CPU_ARM_CLK_ELM_SIZE 12
#define MV_CPU_ARM_CLK_RATIO_OFF 8
#define MV_CPU_ARM_CLK_DDR_OFF 4
#ifndef MV_ASMLANGUAGE
typedef struct _mvCpuArmClk
{
MV_U32 cpuClk; /* CPU clock in MHz */
MV_U32 ddrClk; /* DDR clock in MHz */
MV_U32 l2Clk; /* CPU DDR clock ratio */
}MV_CPU_ARM_CLK;
MV_U32 mvCpuPclkGet(MV_VOID);
MV_VOID mvCpuNameGet(char *pNameBuff);
MV_U32 mvCpuL2ClkGet(MV_VOID);
MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index);
MV_U32 whoAmI(MV_VOID);
#endif /* MV_ASMLANGUAGE */
#endif /* __INCmvCpuh */

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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/*******************************************************************************
* mvCtrlEnvAddrDec.h - Marvell controller address decode library
*
* DESCRIPTION:
*
* DEPENDENCIES:
* None.
*
*******************************************************************************/
/* includes */
#include "ctrlEnv/mvCtrlEnvAddrDec.h"
#include "ctrlEnv/sys/mvAhbToMbusRegs.h"
#include "ddr2/mvDramIfRegs.h"
#include "pex/mvPexRegs.h"
#define MV_DEBUG
/* defines */
#ifdef MV_DEBUG
#define DB(x) x
#else
#define DB(x)
#endif
/* Default Attributes array */
MV_TARGET_ATTRIB mvTargetDefaultsArray[] = TARGETS_DEF_ARRAY;
extern MV_TARGET *sampleAtResetTargetArray;
/* Dram\AHBToMbus\PEX share regsiter */
#define CTRL_DEC_BASE_OFFS 16
#define CTRL_DEC_BASE_MASK (0xffff << CTRL_DEC_BASE_OFFS)
#define CTRL_DEC_BASE_ALIGNMENT 0x10000
#define CTRL_DEC_SIZE_OFFS 16
#define CTRL_DEC_SIZE_MASK (0xffff << CTRL_DEC_SIZE_OFFS)
#define CTRL_DEC_SIZE_ALIGNMENT 0x10000
#define CTRL_DEC_WIN_EN BIT0
/*******************************************************************************
* mvCtrlAddrDecToReg - Get address decode register format values
*
* DESCRIPTION:
*
* INPUT:
*
* OUTPUT:
*
* RETURN:
*
*******************************************************************************/
MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, MV_DEC_REGS *pAddrDecRegs)
{
MV_U32 baseToReg=0 , sizeToReg=0;
/* BaseLow[31:16] => base register [31:16] */
baseToReg = pAddrDecWin->baseLow & CTRL_DEC_BASE_MASK;
/* Write to address decode Base Address Register */
pAddrDecRegs->baseReg &= ~CTRL_DEC_BASE_MASK;
pAddrDecRegs->baseReg |= baseToReg;
/* Get size register value according to window size */
sizeToReg = ctrlSizeToReg(pAddrDecWin->size, CTRL_DEC_SIZE_ALIGNMENT);
/* Size parameter validity check. */
if (-1 == sizeToReg)
{
return MV_BAD_PARAM;
}
/* set size */
pAddrDecRegs->sizeReg &= ~CTRL_DEC_SIZE_MASK;
pAddrDecRegs->sizeReg |= (sizeToReg << CTRL_DEC_SIZE_OFFS);
return MV_OK;
}
/*******************************************************************************
* mvCtrlRegToAddrDec - Extract address decode struct from registers.
*
* DESCRIPTION:
* This function extract address decode struct from address decode
* registers given as parameters.
*
* INPUT:
* pAddrDecRegs - Address decode register struct.
*
* OUTPUT:
* pAddrDecWin - Target window data structure.
*
* RETURN:
* MV_BAD_PARAM if address decode registers data is invalid.
*
*******************************************************************************/
MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, MV_ADDR_WIN *pAddrDecWin)
{
MV_U32 sizeRegVal;
sizeRegVal = (pAddrDecRegs->sizeReg & CTRL_DEC_SIZE_MASK) >>
CTRL_DEC_SIZE_OFFS;
pAddrDecWin->size = ctrlRegToSize(sizeRegVal, CTRL_DEC_SIZE_ALIGNMENT);
/* Extract base address */
/* Base register [31:16] ==> baseLow[31:16] */
pAddrDecWin->baseLow = pAddrDecRegs->baseReg & CTRL_DEC_BASE_MASK;
pAddrDecWin->baseHigh = 0;
return MV_OK;
}
/*******************************************************************************
* mvCtrlAttribGet -
*
* DESCRIPTION:
*
* INPUT:
*
* OUTPUT:
*
* RETURN:
*
*******************************************************************************/
MV_STATUS mvCtrlAttribGet(MV_TARGET target,
MV_TARGET_ATTRIB *targetAttrib)
{
targetAttrib->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib;
targetAttrib->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId;
return MV_OK;
}
/*******************************************************************************
* mvCtrlGetAttrib -
*
* DESCRIPTION:
*
* INPUT:
*
* OUTPUT:
*
* RETURN:
*
*******************************************************************************/
MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib)
{
MV_TARGET target;
MV_TARGET x;
for (target = SDRAM_CS0; target < MAX_TARGETS ; target ++)
{
x = MV_CHANGE_BOOT_CS(target);
if ((mvTargetDefaultsArray[x].attrib == targetAttrib->attrib) &&
(mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == targetAttrib->targetId))
{
/* found it */
break;
}
}
return target;
}
MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin,
MV_DEC_WIN_PARAMS *pWinParam)
{
MV_U32 baseToReg=0, sizeToReg=0;
/* BaseLow[31:16] => base register [31:16] */
baseToReg = pAddrDecWin->addrWin.baseLow & CTRL_DEC_BASE_MASK;
/* Write to address decode Base Address Register */
pWinParam->baseAddr &= ~CTRL_DEC_BASE_MASK;
pWinParam->baseAddr |= baseToReg;
/* Get size register value according to window size */
sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, CTRL_DEC_SIZE_ALIGNMENT);
/* Size parameter validity check. */
if (-1 == sizeToReg)
{
mvOsPrintf("mvCtrlAddrDecToParams: ERR. ctrlSizeToReg failed.\n");
return MV_BAD_PARAM;
}
pWinParam->size = sizeToReg;
pWinParam->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].attrib;
pWinParam->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].targetId;
return MV_OK;
}
MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam,
MV_DEC_WIN *pAddrDecWin)
{
MV_TARGET_ATTRIB targetAttrib;
pAddrDecWin->addrWin.baseLow = pWinParam->baseAddr;
/* Upper 32bit address base is supported under PCI High Address remap */
pAddrDecWin->addrWin.baseHigh = 0;
/* Prepare sizeReg to ctrlRegToSize function */
pAddrDecWin->addrWin.size = ctrlRegToSize(pWinParam->size, CTRL_DEC_SIZE_ALIGNMENT);
if (-1 == pAddrDecWin->addrWin.size)
{
DB(mvOsPrintf("mvCtrlParamsToAddrDec: ERR. ctrlRegToSize failed.\n"));
return MV_BAD_PARAM;
}
targetAttrib.targetId = pWinParam->targetId;
targetAttrib.attrib = pWinParam->attrib;
pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
return MV_OK;
}

203
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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvCtrlEnvAddrDech
#define __INCmvCtrlEnvAddrDech
/* includes */
#include "ctrlEnv/mvCtrlEnvLib.h"
#include "ctrlEnv/mvCtrlEnvRegs.h"
/* defines */
/* DUnit attributes */
#define ATMWCR_WIN_DUNIT_CS0_OFFS 0
#define ATMWCR_WIN_DUNIT_CS0_MASK BIT0
#define ATMWCR_WIN_DUNIT_CS0_REQ (0 << ATMWCR_WIN_DUNIT_CS0_OFFS)
#define ATMWCR_WIN_DUNIT_CS1_OFFS 1
#define ATMWCR_WIN_DUNIT_CS1_MASK BIT1
#define ATMWCR_WIN_DUNIT_CS1_REQ (0 << ATMWCR_WIN_DUNIT_CS1_OFFS)
#define ATMWCR_WIN_DUNIT_CS2_OFFS 2
#define ATMWCR_WIN_DUNIT_CS2_MASK BIT2
#define ATMWCR_WIN_DUNIT_CS2_REQ (0 << ATMWCR_WIN_DUNIT_CS2_OFFS)
#define ATMWCR_WIN_DUNIT_CS3_OFFS 3
#define ATMWCR_WIN_DUNIT_CS3_MASK BIT3
#define ATMWCR_WIN_DUNIT_CS3_REQ (0 << ATMWCR_WIN_DUNIT_CS3_OFFS)
/* RUnit (Device) attributes */
#define ATMWCR_WIN_RUNIT_DEVCS0_OFFS 0
#define ATMWCR_WIN_RUNIT_DEVCS0_MASK BIT0
#define ATMWCR_WIN_RUNIT_DEVCS0_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS0_OFFS)
#define ATMWCR_WIN_RUNIT_DEVCS1_OFFS 1
#define ATMWCR_WIN_RUNIT_DEVCS1_MASK BIT1
#define ATMWCR_WIN_RUNIT_DEVCS1_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS1_OFFS)
#define ATMWCR_WIN_RUNIT_DEVCS2_OFFS 2
#define ATMWCR_WIN_RUNIT_DEVCS2_MASK BIT2
#define ATMWCR_WIN_RUNIT_DEVCS2_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS2_OFFS)
#define ATMWCR_WIN_RUNIT_BOOTCS_OFFS 4
#define ATMWCR_WIN_RUNIT_BOOTCS_MASK BIT4
#define ATMWCR_WIN_RUNIT_BOOTCS_REQ (0 << ATMWCR_WIN_RUNIT_BOOTCS_OFFS)
/* LMaster (PCI) attributes */
#define ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS 0
#define ATMWCR_WIN_LUNIT_BYTE_SWP_MASK BIT0
#define ATMWCR_WIN_LUNIT_BYTE_SWP (0 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS)
#define ATMWCR_WIN_LUNIT_BYTE_NO_SWP (1 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS)
#define ATMWCR_WIN_LUNIT_WORD_SWP_OFFS 1
#define ATMWCR_WIN_LUNIT_WORD_SWP_MASK BIT1
#define ATMWCR_WIN_LUNIT_WORD_SWP (0 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS)
#define ATMWCR_WIN_LUNIT_WORD_NO_SWP (1 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS)
#define ATMWCR_WIN_LUNIT_NO_SNOOP BIT2
#define ATMWCR_WIN_LUNIT_TYPE_OFFS 3
#define ATMWCR_WIN_LUNIT_TYPE_MASK BIT3
#define ATMWCR_WIN_LUNIT_TYPE_IO (0 << ATMWCR_WIN_LUNIT_TYPE_OFFS)
#define ATMWCR_WIN_LUNIT_TYPE_MEM (1 << ATMWCR_WIN_LUNIT_TYPE_OFFS)
#define ATMWCR_WIN_LUNIT_FORCE64_OFFS 4
#define ATMWCR_WIN_LUNIT_FORCE64_MASK BIT4
#define ATMWCR_WIN_LUNIT_FORCE64 (0 << ATMWCR_WIN_LUNIT_FORCE64_OFFS)
#define ATMWCR_WIN_LUNIT_ORDERING_OFFS 6
#define ATMWCR_WIN_LUNIT_ORDERING_MASK BIT6
#define ATMWCR_WIN_LUNIT_ORDERING (1 << ATMWCR_WIN_LUNIT_FORCE64_OFFS)
/* PEX Attributes */
#define ATMWCR_WIN_PEX_TYPE_OFFS 3
#define ATMWCR_WIN_PEX_TYPE_MASK BIT3
#define ATMWCR_WIN_PEX_TYPE_IO (0 << ATMWCR_WIN_PEX_TYPE_OFFS)
#define ATMWCR_WIN_PEX_TYPE_MEM (1 << ATMWCR_WIN_PEX_TYPE_OFFS)
/* typedefs */
/* Unsupported attributes for address decode: */
/* 2) PCI0/1_REQ64n control */
typedef struct _mvDecRegs
{
MV_U32 baseReg;
MV_U32 baseRegHigh;
MV_U32 sizeReg;
}MV_DEC_REGS;
typedef struct _mvTargetAttrib
{
MV_U8 attrib; /* chip select attributes */
MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */
}MV_TARGET_ATTRIB;
/* This structure describes address decode window */
typedef struct _mvDecWin
{
MV_TARGET target; /* Target for addr decode window */
MV_ADDR_WIN addrWin; /* Address window of target */
MV_BOOL enable; /* Window enable/disable */
}MV_DEC_WIN;
typedef struct _mvDecWinParams
{
MV_TARGET_ID targetId; /* Target ID field */
MV_U8 attrib; /* Attribute field */
MV_U32 baseAddr; /* Base address in register format */
MV_U32 size; /* Size in register format */
}MV_DEC_WIN_PARAMS;
/* mvCtrlEnvAddrDec API list */
MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin,
MV_DEC_REGS *pAddrDecRegs);
MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs,
MV_ADDR_WIN *pAddrDecWin);
MV_STATUS mvCtrlAttribGet(MV_TARGET target,
MV_TARGET_ATTRIB *targetAttrib);
MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib);
MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin,
MV_DEC_WIN_PARAMS *pWinParam);
MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam,
MV_DEC_WIN *pAddrDecWin);
#endif /* __INCmvCtrlEnvAddrDech */

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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvCtrlEnvAsmh
#define __INCmvCtrlEnvAsmh
#include "pex/mvPexRegs.h"
#define CHIP_BOND_REG 0x10034
#define PCKG_OPT_MASK_AS #3
#define PXCCARI_REVID_MASK_AS #PXCCARI_REVID_MASK
/* Read device ID into toReg bits 15:0 from 0xd0000000 */
/* defines */
#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \
MV_DV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\
and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */
/* Read device ID into toReg bits 15:0 from 0xf1000000*/
#define MV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \
MV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\
and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */
/* Read Revision into toReg bits 7:0 0xd0000000*/
#define MV_DV_CTRL_REV_GET_ASM(toReg, tmpReg) \
/* Read device revision */ \
MV_DV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\
and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */
/* Read Revision into toReg bits 7:0 0xf1000000*/
#define MV_CTRL_REV_GET_ASM(toReg, tmpReg) \
/* Read device revision */ \
MV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\
and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */
#endif /* __INCmvCtrlEnvAsmh */

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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvCtrlEnvLibh
#define __INCmvCtrlEnvLibh
/* includes */
#include "mvSysHwConfig.h"
#include "mvCommon.h"
#include "mvTypes.h"
#include "mvOs.h"
#include "boardEnv/mvBoardEnvLib.h"
#include "ctrlEnv/mvCtrlEnvSpec.h"
#include "ctrlEnv/mvCtrlEnvRegs.h"
#include "ctrlEnv/mvCtrlEnvAddrDec.h"
/* typedefs */
/* This enumerator describes the possible HW cache coherency policies the */
/* controllers supports. */
typedef enum _mvCachePolicy
{
NO_COHERENCY, /* No HW cache coherency support */
WT_COHERENCY, /* HW cache coherency supported in Write Through policy */
WB_COHERENCY /* HW cache coherency supported in Write Back policy */
}MV_CACHE_POLICY;
/* The swapping is referred to a 64-bit words (as this is the controller */
/* internal data path width). This enumerator describes the possible */
/* data swap types. Below is an example of the data 0x0011223344556677 */
typedef enum _mvSwapType
{
MV_BYTE_SWAP, /* Byte Swap 77 66 55 44 33 22 11 00 */
MV_NO_SWAP, /* No swapping 00 11 22 33 44 55 66 77 */
MV_BYTE_WORD_SWAP, /* Both byte and word swap 33 22 11 00 77 66 55 44 */
MV_WORD_SWAP, /* Word swap 44 55 66 77 00 11 22 33 */
SWAP_TYPE_MAX /* Delimiter for this enumerator */
}MV_SWAP_TYPE;
/* This structure describes access rights for Access protection windows */
/* that can be found in IDMA, XOR, Ethernet and MPSC units. */
/* Note that the permission enumerator coresponds to its register format. */
/* For example, Read only premission is presented as "1" in register field. */
typedef enum _mvAccessRights
{
NO_ACCESS_ALLOWED = 0, /* No access allowed */
READ_ONLY = 1, /* Read only permission */
ACC_RESERVED = 2, /* Reserved access right */
FULL_ACCESS = 3, /* Read and Write permission */
MAX_ACC_RIGHTS
}MV_ACCESS_RIGHTS;
/* mcspLib.h API list */
MV_STATUS mvCtrlEnvInit(MV_VOID);
MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup);
#if defined(MV_INCLUDE_PEX)
MV_U32 mvCtrlPexMaxIfGet(MV_VOID);
#else
#define mvCtrlPexMaxIfGet() (0)
#endif
#define mvCtrlPciIfMaxIfGet() (0)
#if defined(MV_INCLUDE_GIG_ETH)
MV_U32 mvCtrlEthMaxPortGet(MV_VOID);
#endif
#if defined(MV_INCLUDE_XOR)
MV_U32 mvCtrlXorMaxChanGet(MV_VOID);
#endif
#if defined(MV_INCLUDE_USB)
MV_U32 mvCtrlUsbMaxGet(MV_VOID);
#endif
#if defined(MV_INCLUDE_NAND)
MV_U32 mvCtrlNandSupport(MV_VOID);
#endif
#if defined(MV_INCLUDE_SDIO)
MV_U32 mvCtrlSdioSupport(MV_VOID);
#endif
#if defined(MV_INCLUDE_TS)
MV_U32 mvCtrlTsSupport(MV_VOID);
#endif
#if defined(MV_INCLUDE_AUDIO)
MV_U32 mvCtrlAudioSupport(MV_VOID);
#endif
#if defined(MV_INCLUDE_TDM)
MV_U32 mvCtrlTdmSupport(MV_VOID);
#endif
MV_U16 mvCtrlModelGet(MV_VOID);
MV_U8 mvCtrlRevGet(MV_VOID);
MV_STATUS mvCtrlNameGet(char *pNameBuff);
MV_U32 mvCtrlModelRevGet(MV_VOID);
MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff);
MV_VOID mvCtrlAddrDecShow(MV_VOID);
const MV_8* mvCtrlTargetNameGet(MV_TARGET target);
MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment);
MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment);
MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment);
MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID);
MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2);
MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2);
MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable);
MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index);
MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable);
MV_BOOL mvCtrlIsBootFromSPI(MV_VOID);
MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID);
MV_BOOL mvCtrlIsBootFromNAND(MV_VOID);
#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
MV_VOID mvCtrlPwrSaveOn(MV_VOID);
MV_VOID mvCtrlPwrSaveOff(MV_VOID);
#endif
MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index);
MV_VOID mvMPPConfigToSPI(MV_VOID);
MV_VOID mvMPPConfigToDefault(MV_VOID);
#endif /* __INCmvCtrlEnvLibh */

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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvCtrlEnvRegsh
#define __INCmvCtrlEnvRegsh
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* CV Support */
#define PEX0_MEM0 PEX0_MEM
#define PCI0_MEM0 PEX0_MEM
/* Controller revision info */
#define PCI_CLASS_CODE_AND_REVISION_ID 0x008
#define PCCRIR_REVID_OFFS 0 /* Revision ID */
#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS)
/* Controler environment registers offsets */
/* Power Managment Control */
#define POWER_MNG_MEM_CTRL_REG 0x20118
#define PMC_GESTOPMEM_OFFS(port) ((port)? 13 : 0)
#define PMC_GESTOPMEM_MASK(port) (1 << PMC_GESTOPMEM_OFFS(port))
#define PMC_GESTOPMEM_EN(port) (0 << PMC_GESTOPMEM_OFFS(port))
#define PMC_GESTOPMEM_STOP(port) (1 << PMC_GESTOPMEM_OFFS(port))
#define PMC_PEXSTOPMEM_OFFS 1
#define PMC_PEXSTOPMEM_MASK (1 << PMC_PEXSTOPMEM_OFFS)
#define PMC_PEXSTOPMEM_EN (0 << PMC_PEXSTOPMEM_OFFS)
#define PMC_PEXSTOPMEM_STOP (1 << PMC_PEXSTOPMEM_OFFS)
#define PMC_USBSTOPMEM_OFFS 2
#define PMC_USBSTOPMEM_MASK (1 << PMC_USBSTOPMEM_OFFS)
#define PMC_USBSTOPMEM_EN (0 << PMC_USBSTOPMEM_OFFS)
#define PMC_USBSTOPMEM_STOP (1 << PMC_USBSTOPMEM_OFFS)
#define PMC_DUNITSTOPMEM_OFFS 3
#define PMC_DUNITSTOPMEM_MASK (1 << PMC_DUNITSTOPMEM_OFFS)
#define PMC_DUNITSTOPMEM_EN (0 << PMC_DUNITSTOPMEM_OFFS)
#define PMC_DUNITSTOPMEM_STOP (1 << PMC_DUNITSTOPMEM_OFFS)
#define PMC_RUNITSTOPMEM_OFFS 4
#define PMC_RUNITSTOPMEM_MASK (1 << PMC_RUNITSTOPMEM_OFFS)
#define PMC_RUNITSTOPMEM_EN (0 << PMC_RUNITSTOPMEM_OFFS)
#define PMC_RUNITSTOPMEM_STOP (1 << PMC_RUNITSTOPMEM_OFFS)
#define PMC_XORSTOPMEM_OFFS(port) (5+(port*2))
#define PMC_XORSTOPMEM_MASK(port) (1 << PMC_XORSTOPMEM_OFFS(port))
#define PMC_XORSTOPMEM_EN(port) (0 << PMC_XORSTOPMEM_OFFS(port))
#define PMC_XORSTOPMEM_STOP(port) (1 << PMC_XORSTOPMEM_OFFS(port))
#define PMC_SATASTOPMEM_OFFS(port) (6+(port*5))
#define PMC_SATASTOPMEM_MASK(port) (1 << PMC_SATASTOPMEM_OFFS(port))
#define PMC_SATASTOPMEM_EN(port) (0 << PMC_SATASTOPMEM_OFFS(port))
#define PMC_SATASTOPMEM_STOP(port) (1 << PMC_SATASTOPMEM_OFFS(port))
#define PMC_SESTOPMEM_OFFS 8
#define PMC_SESTOPMEM_MASK (1 << PMC_SESTOPMEM_OFFS)
#define PMC_SESTOPMEM_EN (0 << PMC_SESTOPMEM_OFFS)
#define PMC_SESTOPMEM_STOP (1 << PMC_SESTOPMEM_OFFS)
#define PMC_AUDIOSTOPMEM_OFFS 9
#define PMC_AUDIOSTOPMEM_MASK (1 << PMC_AUDIOSTOPMEM_OFFS)
#define PMC_AUDIOSTOPMEM_EN (0 << PMC_AUDIOSTOPMEM_OFFS)
#define PMC_AUDIOSTOPMEM_STOP (1 << PMC_AUDIOSTOPMEM_OFFS)
#define POWER_MNG_CTRL_REG 0x2011C
#define PMC_GESTOPCLOCK_OFFS(port) ((port)? 19 : 0)
#define PMC_GESTOPCLOCK_MASK(port) (1 << PMC_GESTOPCLOCK_OFFS(port))
#define PMC_GESTOPCLOCK_EN(port) (1 << PMC_GESTOPCLOCK_OFFS(port))
#define PMC_GESTOPCLOCK_STOP(port) (0 << PMC_GESTOPCLOCK_OFFS(port))
#define PMC_PEXPHYSTOPCLOCK_OFFS 1
#define PMC_PEXPHYSTOPCLOCK_MASK (1 << PMC_PEXPHYSTOPCLOCK_OFFS)
#define PMC_PEXPHYSTOPCLOCK_EN (1 << PMC_PEXPHYSTOPCLOCK_OFFS)
#define PMC_PEXPHYSTOPCLOCK_STOP (0 << PMC_PEXPHYSTOPCLOCK_OFFS)
#define PMC_PEXSTOPCLOCK_OFFS 2
#define PMC_PEXSTOPCLOCK_MASK (1 << PMC_PEXSTOPCLOCK_OFFS)
#define PMC_PEXSTOPCLOCK_EN (1 << PMC_PEXSTOPCLOCK_OFFS)
#define PMC_PEXSTOPCLOCK_STOP (0 << PMC_PEXSTOPCLOCK_OFFS)
#define PMC_USBSTOPCLOCK_OFFS 3
#define PMC_USBSTOPCLOCK_MASK (1 << PMC_USBSTOPCLOCK_OFFS)
#define PMC_USBSTOPCLOCK_EN (1 << PMC_USBSTOPCLOCK_OFFS)
#define PMC_USBSTOPCLOCK_STOP (0 << PMC_USBSTOPCLOCK_OFFS)
#define PMC_SDIOSTOPCLOCK_OFFS 4
#define PMC_SDIOSTOPCLOCK_MASK (1 << PMC_SDIOSTOPCLOCK_OFFS)
#define PMC_SDIOSTOPCLOCK_EN (1 << PMC_SDIOSTOPCLOCK_OFFS)
#define PMC_SDIOSTOPCLOCK_STOP (0 << PMC_SDIOSTOPCLOCK_OFFS)
#define PMC_TSSTOPCLOCK_OFFS 5
#define PMC_TSSTOPCLOCK_MASK (1 << PMC_TSSTOPCLOCK_OFFS)
#define PMC_TSSTOPCLOCK_EN (1 << PMC_TSSTOPCLOCK_OFFS)
#define PMC_TSSTOPCLOCK_STOP (0 << PMC_TSSTOPCLOCK_OFFS)
#define PMC_AUDIOSTOPCLOCK_OFFS 9
#define PMC_AUDIOSTOPCLOCK_MASK (1 << PMC_AUDIOSTOPCLOCK_OFFS)
#define PMC_AUDIOSTOPCLOCK_EN (1 << PMC_AUDIOSTOPCLOCK_OFFS)
#define PMC_AUDIOSTOPCLOCK_STOP (0 << PMC_AUDIOSTOPCLOCK_OFFS)
#define PMC_POWERSAVE_OFFS 11
#define PMC_POWERSAVE_MASK (1 << PMC_POWERSAVE_OFFS)
#define PMC_POWERSAVE_EN (1 << PMC_POWERSAVE_OFFS)
#define PMC_POWERSAVE_STOP (0 << PMC_POWERSAVE_OFFS)
#define PMC_SATASTOPCLOCK_OFFS(port) (14+(port))
#define PMC_SATASTOPCLOCK_MASK(port) (1 << PMC_SATASTOPCLOCK_OFFS(port))
#define PMC_SATASTOPCLOCK_EN(port) (1 << PMC_SATASTOPCLOCK_OFFS(port))
#define PMC_SATASTOPCLOCK_STOP(port) (0 << PMC_SATASTOPCLOCK_OFFS(port))
#define PMC_SESTOPCLOCK_OFFS 17
#define PMC_SESTOPCLOCK_MASK (1 << PMC_SESTOPCLOCK_OFFS)
#define PMC_SESTOPCLOCK_EN (1 << PMC_SESTOPCLOCK_OFFS)
#define PMC_SESTOPCLOCK_STOP (0 << PMC_SESTOPCLOCK_OFFS)
#define PMC_TDMSTOPCLOCK_OFFS 20
#define PMC_TDMSTOPCLOCK_MASK (1 << PMC_TDMSTOPCLOCK_OFFS)
#define PMC_TDMSTOPCLOCK_EN (1 << PMC_TDMSTOPCLOCK_OFFS)
#define PMC_TDMSTOPCLOCK_STOP (0 << PMC_TDMSTOPCLOCK_OFFS)
/* Controler environment registers offsets */
#define MPP_CONTROL_REG0 0x10000
#define MPP_CONTROL_REG1 0x10004
#define MPP_CONTROL_REG2 0x10008
#define MPP_CONTROL_REG3 0x1000C
#define MPP_CONTROL_REG4 0x10010
#define MPP_CONTROL_REG5 0x10014
#define MPP_CONTROL_REG6 0x10018
#define MPP_SAMPLE_AT_RESET 0x10030
#define CHIP_BOND_REG 0x10034
#define SYSRST_LENGTH_COUNTER_REG 0x10050
#define SLCR_COUNT_OFFS 0
#define SLCR_COUNT_MASK (0x1FFFFFFF << SLCR_COUNT_OFFS)
#define SLCR_CLR_OFFS 31
#define SLCR_CLR_MASK (1 << SLCR_CLR_OFFS)
#define PCKG_OPT_MASK 0x3
#define MPP_OUTPUT_DRIVE_REG 0x100E0
#define MPP_RGMII0_OUTPUT_DRIVE_OFFS 7
#define MPP_3_3_RGMII0_OUTPUT_DRIVE (0x0 << MPP_RGMII0_OUTPUT_DRIVE_OFFS)
#define MPP_1_8_RGMII0_OUTPUT_DRIVE (0x1 << MPP_RGMII0_OUTPUT_DRIVE_OFFS)
#define MPP_RGMII1_OUTPUT_DRIVE_OFFS 15
#define MPP_3_3_RGMII1_OUTPUT_DRIVE (0x0 << MPP_RGMII1_OUTPUT_DRIVE_OFFS)
#define MPP_1_8_RGMII1_OUTPUT_DRIVE (0x1 << MPP_RGMII1_OUTPUT_DRIVE_OFFS)
#define MSAR_BOOT_MODE_OFFS 12
#define MSAR_BOOT_MODE_MASK (0x7 << MSAR_BOOT_MODE_OFFS)
#define MSAR_BOOT_NAND_WITH_BOOTROM (0x5 << MSAR_BOOT_MODE_OFFS)
#define MSAR_BOOT_SPI_WITH_BOOTROM (0x4 << MSAR_BOOT_MODE_OFFS)
#define MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM (0x2 << MSAR_BOOT_MODE_OFFS)
#define MSAR_BOOT_MODE_6180(X) (((X & 0x3000) >> 12) | \
((X & 0x2) << 1))
#define MSAR_BOOT_SPI_WITH_BOOTROM_6180 0x1
#define MSAR_BOOT_NAND_WITH_BOOTROM_6180 0x5
#define MSAR_TCLCK_OFFS 21
#define MSAR_TCLCK_MASK (0x1 << MSAR_TCLCK_OFFS)
#define MSAR_TCLCK_166 (0x1 << MSAR_TCLCK_OFFS)
#define MSAR_TCLCK_200 (0x0 << MSAR_TCLCK_OFFS)
#define MSAR_CPUCLCK_EXTRACT(X) (((X & 0x2) >> 1) | ((X & 0x400000) >> 21) | \
((X & 0x18) >> 1))
#define MSAR_CPUCLCK_OFFS_6180 2
#define MSAR_CPUCLCK_MASK_6180 (0x7 << MSAR_CPUCLCK_OFFS_6180)
#define MSAR_DDRCLCK_RTIO_OFFS 5
#define MSAR_DDRCLCK_RTIO_MASK (0xF << MSAR_DDRCLCK_RTIO_OFFS)
#define MSAR_L2CLCK_EXTRACT(X) (((X & 0x600) >> 9) | ((X & 0x80000) >> 17))
#ifndef MV_ASMLANGUAGE
/* CPU clock for 6281,6192 0->Resereved */
#define MV_CPU_CLCK_TBL { 0, 0, 0, 0, \
600000000, 0, 800000000, 1000000000, \
0, 1200000000, 0, 0, \
1500000000, 0, 0, 0}
/* DDR clock RATIO for 6281,6192 {0,0}->Reserved */
#define MV_DDR_CLCK_RTIO_TBL {\
{0, 0}, {0, 0}, {2, 1}, {0, 0}, \
{3, 1}, {0, 0}, {4, 1}, {9, 2}, \
{5, 1}, {6, 1}, {0, 0}, {0, 0}, \
{0, 0}, {0, 0}, {0, 0}, {0, 0} \
}
/* L2 clock RATIO for 6281,6192 {1,1}->Reserved */
#define MV_L2_CLCK_RTIO_TBL {\
{0, 0}, {2, 1}, {0, 0}, {3, 1}, \
{0, 0}, {0, 0}, {0, 0}, {0, 0} \
}
/* 6180 have different clk reset sampling */
/* ARM CPU, DDR, L2 clock for 6180 {0,0,0}->Reserved */
#define MV_CPU6180_DDR_L2_CLCK_TBL { \
{0, 0, 0 },\
{0, 0, 0 },\
{0, 0, 0 },\
{0, 0, 0 },\
{0, 0, 0 },\
{600000000, 200000000, 300000000 },\
{800000000, 200000000, 400000000 },\
{0, 0, 0 }\
}
/* These macros help units to identify a target Mbus Arbiter group */
#define MV_TARGET_IS_DRAM(target) \
((target >= SDRAM_CS0) && (target <= SDRAM_CS3))
#define MV_TARGET_IS_PEX0(target) \
((target >= PEX0_MEM) && (target <= PEX0_IO))
#define MV_TARGET_IS_PEX1(target) 0
#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target))
#define MV_TARGET_IS_DEVICE(target) \
((target >= DEVICE_CS0) && (target <= DEVICE_CS3))
#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0
#define MV_TARGET_IS_AS_BOOT(target) ((target) == (sampleAtResetTargetArray[ \
(mvCtrlModelGet() == MV_6180_DEV_ID)? MSAR_BOOT_MODE_6180 \
(MV_REG_READ(MPP_SAMPLE_AT_RESET)):((MV_REG_READ(MPP_SAMPLE_AT_RESET)\
& MSAR_BOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS)]))
#define MV_CHANGE_BOOT_CS(target) (((target) == DEV_BOOCS)?\
sampleAtResetTargetArray[(mvCtrlModelGet() == MV_6180_DEV_ID)? \
MSAR_BOOT_MODE_6180(MV_REG_READ(MPP_SAMPLE_AT_RESET)): \
((MV_REG_READ(MPP_SAMPLE_AT_RESET) & MSAR_BOOT_MODE_MASK)\
>> MSAR_BOOT_MODE_OFFS)]:(target))
#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */
#define BOOT_TARGETS_NAME_ARRAY { \
TBL_TERM, \
TBL_TERM, \
BOOT_ROM_CS, \
TBL_TERM, \
BOOT_ROM_CS, \
BOOT_ROM_CS, \
TBL_TERM, \
TBL_TERM \
}
#define BOOT_TARGETS_NAME_ARRAY_6180 { \
TBL_TERM, \
BOOT_ROM_CS, \
TBL_TERM, \
TBL_TERM, \
TBL_TERM, \
BOOT_ROM_CS, \
TBL_TERM, \
TBL_TERM \
}
/* For old competability */
#define DEVICE_CS0 NFLASH_CS
#define DEVICE_CS1 SPI_CS
#define DEVICE_CS2 BOOT_ROM_CS
#define DEVICE_CS3 DEV_BOOCS
#define MV_BOOTDEVICE_INDEX 0
#define START_DEV_CS DEV_CS0
#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0)
#define PCI_IF0_MEM0 PEX0_MEM
#define PCI_IF0_IO PEX0_IO
/* This enumerator defines the Marvell controller target ID */
typedef enum _mvTargetId
{
DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */
DEV_TARGET_ID = 1, /* Port 1 -> Nand/SPI */
PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */
CRYPT_TARGET_ID = 3 , /* Port 3 --> Crypto Engine */
SAGE_TARGET_ID = 12 , /* Port 12 -> SAGE Unit */
MAX_TARGETS_ID
}MV_TARGET_ID;
/* This enumerator described the possible Controller paripheral targets. */
/* Controller peripherals are designated memory/IO address spaces that the */
/* controller can access. They are also refered as "targets" */
typedef enum _mvTarget
{
TBL_TERM = -1, /* none valid target, used as targets list terminator*/
SDRAM_CS0, /* SDRAM chip select 0 */
SDRAM_CS1, /* SDRAM chip select 1 */
SDRAM_CS2, /* SDRAM chip select 2 */
SDRAM_CS3, /* SDRAM chip select 3 */
PEX0_MEM, /* PCI Express 0 Memory */
PEX0_IO, /* PCI Express 0 IO */
INTER_REGS, /* Internal registers */
NFLASH_CS, /* NFLASH_CS */
SPI_CS, /* SPI_CS */
BOOT_ROM_CS, /* BOOT_ROM_CS */
DEV_BOOCS, /* DEV_BOOCS */
CRYPT_ENG, /* Crypto Engine */
#ifdef MV_INCLUDE_SAGE
SAGE_UNIT, /* SAGE Unit */
#endif
MAX_TARGETS
}MV_TARGET;
#define TARGETS_DEF_ARRAY { \
{0x0E, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \
{0x0D, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \
{0x0B, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \
{0x07, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \
{0xE8, PEX0_TARGET_ID }, /* PEX0_MEM */ \
{0xE0, PEX0_TARGET_ID }, /* PEX0_IO */ \
{0xFF, 0xFF }, /* INTER_REGS */ \
{0x2F, DEV_TARGET_ID }, /* NFLASH_CS */ \
{0x1E, DEV_TARGET_ID }, /* SPI_CS */ \
{0x1D, DEV_TARGET_ID }, /* BOOT_ROM_CS */ \
{0x1E, DEV_TARGET_ID }, /* DEV_BOOCS */ \
{0x01, CRYPT_TARGET_ID}, /* CRYPT_ENG */ \
{0x00, SAGE_TARGET_ID } \
}
#define TARGETS_NAME_ARRAY { \
"SDRAM_CS0", /* SDRAM_CS0 */ \
"SDRAM_CS1", /* SDRAM_CS1 */ \
"SDRAM_CS2", /* SDRAM_CS2 */ \
"SDRAM_CS3", /* SDRAM_CS3 */ \
"PEX0_MEM", /* PEX0_MEM */ \
"PEX0_IO", /* PEX0_IO */ \
"INTER_REGS", /* INTER_REGS */ \
"NFLASH_CS", /* NFLASH_CS */ \
"SPI_CS", /* SPI_CS */ \
"BOOT_ROM_CS", /* BOOT_ROM_CS */ \
"DEV_BOOTCS", /* DEV_BOOCS */ \
"CRYPT_ENG", /* CRYPT_ENG */ \
"SAGE_UNIT" /* SAGE_UNIT */ \
}
#endif /* MV_ASMLANGUAGE */
#endif

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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvCtrlEnvSpech
#define __INCmvCtrlEnvSpech
#include "mvDeviceId.h"
#include "mvSysHwConfig.h"
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#define MV_ARM_SOC
#define SOC_NAME_PREFIX "MV88F"
/* units base and port numbers */
#ifdef MV_ASMLANGUAGE
#define XOR_UNIT_BASE(unit) 0x60800
#else
#define MV_XOR_REG_BASE 0x60000
#define XOR_UNIT_BASE(unit) ((unit)? 0x60900:0x60800)
#endif
#define TDM_REG_BASE 0xD0000
#define USB_REG_BASE(dev) 0x50000
#define AUDIO_REG_BASE 0xA0000
#define SATA_REG_BASE 0x80000
#define MV_CESA_REG_BASE 0x3D000
#define MV_CESA_TDMA_REG_BASE 0x30000
#define MV_SDIO_REG_BASE 0x90000
#define MV_ETH_REG_BASE(port) (((port) == 0) ? 0x72000 : 0x76000)
#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100))
#define DRAM_BASE 0x0
#define CNTMR_BASE 0x20300
#define TWSI_SLAVE_BASE(chanNum) 0x11000
#define PEX_IF_BASE(pexIf) 0x40000
#define MPP_REG_BASE 0x10000
#define TSU_GLOBAL_REG_BASE 0xB4000
#define MAX_AHB_TO_MBUS_REG_BASE 0x20000
#define INTER_REGS_SIZE _1M
/* This define describes the TWSI interrupt bit and location */
#define TWSI_CPU_MAIN_INT_CAUSE_REG 0x20200
#define TWSI0_CPU_MAIN_INT_BIT (1<<29)
#define TWSI_SPEED 100000
#define MV_GPP_MAX_GROUP 2
#define MV_CNTMR_MAX_COUNTER 2
#define MV_UART_MAX_CHAN 2
#define MV_XOR_MAX_UNIT 2
#define MV_XOR_MAX_CHAN 4 /* total channels for all units together*/
#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */
#define MV_SATA_MAX_CHAN 2
#define MV_6281_MPP_MAX_MODULE 2
#define MV_6192_MPP_MAX_MODULE 1
#define MV_6190_MPP_MAX_MODULE 1
#define MV_6180_MPP_MAX_MODULE 2
#define MV_6281_MPP_MAX_GROUP 7
#define MV_6192_MPP_MAX_GROUP 4
#define MV_6190_MPP_MAX_GROUP 4
#define MV_6180_MPP_MAX_GROUP 3
#define MV_DRAM_MAX_CS 4
/* This define describes the maximum number of supported PCI\PCIX Interfaces*/
#define MV_PCI_MAX_IF 0
#define MV_PCI_START_IF 0
/* This define describes the maximum number of supported PEX Interfaces */
#define MV_INCLUDE_PEX0
#define MV_DISABLE_PEX_DEVICE_BAR
#define MV_PEX_MAX_IF 1
#define MV_PEX_START_IF MV_PCI_MAX_IF
/* This define describes the maximum number of supported PCI Interfaces */
#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF)
#define MV_ETH_MAX_PORTS 2
#define MV_6281_ETH_MAX_PORTS 2
#define MV_6192_ETH_MAX_PORTS 2
#define MV_6190_ETH_MAX_PORTS 1
#define MV_6180_ETH_MAX_PORTS 1
#define MV_IDMA_MAX_CHAN 0
#define MV_USB_MAX_PORTS 1
#define MV_USB_VERSION 1
#define MV_6281_NAND 1
#define MV_6192_NAND 1
#define MV_6190_NAND 1
#define MV_6180_NAND 0
#define MV_6281_SDIO 1
#define MV_6192_SDIO 1
#define MV_6190_SDIO 1
#define MV_6180_SDIO 1
#define MV_6281_TS 1
#define MV_6192_TS 1
#define MV_6190_TS 0
#define MV_6180_TS 0
#define MV_6281_AUDIO 1
#define MV_6192_AUDIO 1
#define MV_6190_AUDIO 0
#define MV_6180_AUDIO 1
#define MV_6281_TDM 1
#define MV_6192_TDM 1
#define MV_6190_TDM 0
#define MV_6180_TDM 0
#define MV_DEVICE_MAX_CS 4
/* Others */
#define PEX_HOST_BUS_NUM(pciIf) (pciIf)
#define PEX_HOST_DEV_NUM(pciIf) 0
#define PCI_IO(pciIf) (PEX0_IO)
#define PCI_MEM(pciIf, memNum) (PEX0_MEM0)
/* CESA version #2: One channel, 2KB SRAM, TDMA */
#if defined(MV_CESA_CHAIN_MODE_SUPPORT)
#define MV_CESA_VERSION 3
#else
#define MV_CESA_VERSION 2
#endif
#define MV_CESA_SRAM_SIZE 2*1024
/* This define describes the maximum number of supported Ethernet ports */
#define MV_ETH_VERSION 4
#define MV_ETH_MAX_RXQ 8
#define MV_ETH_MAX_TXQ 8
#define MV_ETH_PORT_SGMII { MV_FALSE, MV_FALSE }
/* This define describes the the support of USB */
#define MV_USB_VERSION 1
#define MV_INCLUDE_SDRAM_CS0
#define MV_INCLUDE_SDRAM_CS1
#define MV_INCLUDE_SDRAM_CS2
#define MV_INCLUDE_SDRAM_CS3
#define MV_INCLUDE_DEVICE_CS0
#define MV_INCLUDE_DEVICE_CS1
#define MV_INCLUDE_DEVICE_CS2
#define MV_INCLUDE_DEVICE_CS3
#define MPP_GROUP_1_TYPE {\
{0, 0, 0}, /* Reserved for AUTO */ \
{0x22220000, 0x22222222, 0x2222}, /* TDM */ \
{0x44440000, 0x00044444, 0x0000}, /* AUDIO */ \
{0x33330000, 0x33003333, 0x0033}, /* RGMII */ \
{0x33330000, 0x03333333, 0x0033}, /* GMII */ \
{0x11110000, 0x11111111, 0x0001}, /* TS */ \
{0x33330000, 0x33333333, 0x3333} /* MII */ \
}
#define MPP_GROUP_2_TYPE {\
{0, 0, 0}, /* Reserved for AUTO */ \
{0x22220000, 0x22222222, 0x22}, /* TDM */ \
{0x44440000, 0x00044444, 0x0}, /* AUDIO */ \
{0, 0, 0}, /* N_A */ \
{0, 0, 0}, /* N_A */ \
{0x11110000, 0x11111111, 0x01} /* TS */ \
}
#ifndef MV_ASMLANGUAGE
/* This enumerator defines the Marvell Units ID */
typedef enum _mvUnitId
{
DRAM_UNIT_ID,
PEX_UNIT_ID,
ETH_GIG_UNIT_ID,
USB_UNIT_ID,
IDMA_UNIT_ID,
XOR_UNIT_ID,
SATA_UNIT_ID,
TDM_UNIT_ID,
UART_UNIT_ID,
CESA_UNIT_ID,
SPI_UNIT_ID,
AUDIO_UNIT_ID,
SDIO_UNIT_ID,
TS_UNIT_ID,
MAX_UNITS_ID
}MV_UNIT_ID;
#endif
#endif /* __INCmvCtrlEnvSpech */

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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvAhbToMbush
#define __INCmvAhbToMbush
/* includes */
#include "ctrlEnv/mvCtrlEnvLib.h"
#include "ctrlEnv/sys/mvAhbToMbusRegs.h"
#include "ctrlEnv/mvCtrlEnvAddrDec.h"
/* defines */
#if defined(MV_88F1181)
/* This enumerator defines the Marvell controller possible MBUS arbiter */
/* target ports. It is used to define crossbar priority scheame (pizza) */
typedef enum _mvMBusArbTargetId
{
DRAM_MBUS_ARB_TARGET = 0, /* Port 0 -> DRAM interface */
TWSI_MBUS_ARB_TARGET = 1, /* Port 1 -> TWSI */
ARM_MBUS_ARB_TARGET = 2, /* Port 2 -> ARM */
PEX1_MBUS_ARB_TARGET = 3, /* Port 3 -> PCI Express 1 */
PEX0_MBUS_ARB_TARGET = 4, /* Port 4 -> PCI Express0 */
MAX_MBUS_ARB_TARGETS
}MV_MBUS_ARB_TARGET;
typedef struct _mvMBusArbCtrl
{
MV_BOOL starvEn;
MV_BOOL highPrio;
MV_BOOL fixedRoundRobin;
}MV_MBUS_ARB_CTRL;
#endif /* #if defined(MV_88F1181) */
typedef struct _mvAhbtoMbusDecWin
{
MV_TARGET target;
MV_ADDR_WIN addrWin; /* An address window*/
MV_BOOL enable; /* Address decode window is enabled/disabled */
}MV_AHB_TO_MBUS_DEC_WIN;
/* mvAhbToMbus.h API list */
MV_STATUS mvAhbToMbusInit(MV_VOID);
MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin);
MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin);
MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum,MV_BOOL enable);
MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrDecWin);
MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target);
MV_U32 mvAhbToMbusWinAvailGet(MV_VOID);
MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2);
#if defined(MV_88F1181)
MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray);
MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl);
MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl);
#endif /* #if defined(MV_88F1181) */
MV_VOID mvAhbToMbusAddDecShow(MV_VOID);
#endif /* __INCmvAhbToMbush */

143
target/linux/generic-2.6/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h Normal file
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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvAhbToMbusRegsh
#define __INCmvAhbToMbusRegsh
/******************************/
/* ARM Address Map Registers */
/******************************/
#define MAX_AHB_TO_MBUS_WINS 9
#define MV_AHB_TO_MBUS_INTREG_WIN 8
#define AHB_TO_MBUS_WIN_CTRL_REG(winNum) (0x20000 + (winNum)*0x10)
#define AHB_TO_MBUS_WIN_BASE_REG(winNum) (0x20004 + (winNum)*0x10)
#define AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum) (0x20008 + (winNum)*0x10)
#define AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum) (0x2000C + (winNum)*0x10)
#define AHB_TO_MBUS_WIN_INTEREG_REG 0x20080
/* Window Control Register */
/* AHB_TO_MBUS_WIN_CTRL_REG (ATMWCR)*/
#define ATMWCR_WIN_ENABLE BIT0 /* Window Enable */
#define ATMWCR_WIN_TARGET_OFFS 4 /* The target interface associated
with this window*/
#define ATMWCR_WIN_TARGET_MASK (0xf << ATMWCR_WIN_TARGET_OFFS)
#define ATMWCR_WIN_ATTR_OFFS 8 /* The target interface attributes
Associated with this window */
#define ATMWCR_WIN_ATTR_MASK (0xff << ATMWCR_WIN_ATTR_OFFS)
/*
Used with the Base register to set the address window size and location
Must be programed from LSB to MSB as sequence of 1’s followed
by sequence of 0’s. The number of 1’s specifies the size of the window
in 64 KB granularity (e.g. a value of 0x00FF specifies 256 = 16 MB).
NOTE: A value of 0x0 specifies 64KB size.
*/
#define ATMWCR_WIN_SIZE_OFFS 16 /* Window Size */
#define ATMWCR_WIN_SIZE_MASK (0xffff << ATMWCR_WIN_SIZE_OFFS)
#define ATMWCR_WIN_SIZE_ALIGNMENT 0x10000
/* Window Base Register */
/* AHB_TO_MBUS_WIN_BASE_REG (ATMWBR) */
/*
Used with the size field to set the address window size and location.
Corresponds to transaction address[31:16]
*/
#define ATMWBR_BASE_OFFS 16 /* Base Address */
#define ATMWBR_BASE_MASK (0xffff << ATMWBR_BASE_OFFS)
#define ATMWBR_BASE_ALIGNMENT 0x10000
/* Window Remap Low Register */
/* AHB_TO_MBUS_WIN_REMAP_LOW_REG (ATMWRLR) */
/*
Used with the size field to specifies address bits[31:0] to be driven to
the target interface.:
target_addr[31:16] = (addr[31:16] & size[15:0]) | (remap[31:16] & ~size[15:0])
*/
#define ATMWRLR_REMAP_LOW_OFFS 16 /* Remap Address */
#define ATMWRLR_REMAP_LOW_MASK (0xffff << ATMWRLR_REMAP_LOW_OFFS)
#define ATMWRLR_REMAP_LOW_ALIGNMENT 0x10000
/* Window Remap High Register */
/* AHB_TO_MBUS_WIN_REMAP_HIGH_REG (ATMWRHR) */
/*
Specifies address bits[63:32] to be driven to the target interface.
target_addr[63:32] = (RemapHigh[31:0]
*/
#define ATMWRHR_REMAP_HIGH_OFFS 0 /* Remap Address */
#define ATMWRHR_REMAP_HIGH_MASK (0xffffffff << ATMWRHR_REMAP_HIGH_OFFS)
#endif /* __INCmvAhbToMbusRegsh */

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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvCpuIfh
#define __INCmvCpuIfh
/* includes */
#include "ctrlEnv/mvCtrlEnvLib.h"
#include "ctrlEnv/sys/mvCpuIfRegs.h"
#include "ctrlEnv/sys/mvAhbToMbus.h"
#include "ddr2/mvDramIf.h"
#include "ctrlEnv/sys/mvSysDram.h"
#if defined(MV_INCLUDE_PEX)
#include "pex/mvPex.h"
#endif
/* defines */
/* typedefs */
/* This structure describes CPU interface address decode window */
typedef struct _mvCpuIfDecWin
{
MV_ADDR_WIN addrWin; /* An address window*/
MV_U32 winNum; /* Window Number in the AHB To Mbus bridge */
MV_BOOL enable; /* Address decode window is enabled/disabled */
}MV_CPU_DEC_WIN;
/* mvCpuIfLib.h API list */
/* mvCpuIfLib.h API list */
MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap);
MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin);
MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin);
MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable);
MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target);
MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target);
MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target);
MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress);
#if defined(MV_INCLUDE_PEX)
MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin);
MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType);
#endif
#if defined(MV_INCLUDE_PCI)
MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin);
#endif
MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin);
MV_VOID mvCpuIfAddDecShow(MV_VOID);
#if defined(MV88F6281)
MV_STATUS mvCpuIfBridgeReorderWAInit(void);
#endif
#endif /* __INCmvCpuIfh */

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@ -0,0 +1,304 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvCpuIfRegsh
#define __INCmvCpuIfRegsh
/****************************************/
/* ARM Control and Status Registers Map */
/****************************************/
#define CPU_CONFIG_REG 0x20100
#define CPU_CTRL_STAT_REG 0x20104
#define CPU_RSTOUTN_MASK_REG 0x20108
#define CPU_SYS_SOFT_RST_REG 0x2010C
#define CPU_AHB_MBUS_CAUSE_INT_REG 0x20110
#define CPU_AHB_MBUS_MASK_INT_REG 0x20114
#define CPU_FTDLL_CONFIG_REG 0x20120
#define CPU_L2_CONFIG_REG 0x20128
/* ARM Configuration register */
/* CPU_CONFIG_REG (CCR) */
/* Reset vector location */
#define CCR_VEC_INIT_LOC_OFFS 1
#define CCR_VEC_INIT_LOC_MASK BIT1
/* reset at 0x00000000 */
#define CCR_VEC_INIT_LOC_0000 (0 << CCR_VEC_INIT_LOC_OFFS)
/* reset at 0xFFFF0000 */
#define CCR_VEC_INIT_LOC_FF00 (1 << CCR_VEC_INIT_LOC_OFFS)
#define CCR_AHB_ERROR_PROP_OFFS 2
#define CCR_AHB_ERROR_PROP_MASK BIT2
/* Erros are not propogated to AHB */
#define CCR_AHB_ERROR_PROP_NO_INDICATE (0 << CCR_AHB_ERROR_PROP_OFFS)
/* Erros are propogated to AHB */
#define CCR_AHB_ERROR_PROP_INDICATE (1 << CCR_AHB_ERROR_PROP_OFFS)
#define CCR_ENDIAN_INIT_OFFS 3
#define CCR_ENDIAN_INIT_MASK BIT3
#define CCR_ENDIAN_INIT_LITTLE (0 << CCR_ENDIAN_INIT_OFFS)
#define CCR_ENDIAN_INIT_BIG (1 << CCR_ENDIAN_INIT_OFFS)
#define CCR_INCR_EN_OFFS 4
#define CCR_INCR_EN_MASK BIT4
#define CCR_INCR_EN BIT4
#define CCR_NCB_BLOCKING_OFFS 5
#define CCR_NCB_BLOCKING_MASK (1 << CCR_NCB_BLOCKING_OFFS)
#define CCR_NCB_BLOCKING_NON (0 << CCR_NCB_BLOCKING_OFFS)
#define CCR_NCB_BLOCKING_EN (1 << CCR_NCB_BLOCKING_OFFS)
#define CCR_CPU_2_MBUSL_TICK_DRV_OFFS 8
#define CCR_CPU_2_MBUSL_TICK_DRV_MASK (0xF << CCR_CPU_2_MBUSL_TICK_DRV_OFFS)
#define CCR_CPU_2_MBUSL_TICK_SMPL_OFFS 12
#define CCR_CPU_2_MBUSL_TICK_SMPL_MASK (0xF << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)
#define CCR_ICACH_PREF_BUF_ENABLE BIT16
#define CCR_DCACH_PREF_BUF_ENABLE BIT17
/* Ratio options for CPU to DDR for 6281/6192/6190 */
#define CPU_2_DDR_CLK_1x3 4
#define CPU_2_DDR_CLK_1x4 6
/* Ratio options for CPU to DDR for 6281 only */
#define CPU_2_DDR_CLK_2x9 7
#define CPU_2_DDR_CLK_1x5 8
#define CPU_2_DDR_CLK_1x6 9
/* Ratio options for CPU to DDR for 6180 only */
#define CPU_2_DDR_CLK_1x3_1 0x5
#define CPU_2_DDR_CLK_1x4_1 0x6
/* Default values for CPU to Mbus-L DDR Interface Tick Driver and */
/* CPU to Mbus-L Tick Sample fields in CPU config register */
#define TICK_DRV_1x1 0
#define TICK_DRV_1x2 0
#define TICK_DRV_1x3 1
#define TICK_DRV_1x4 2
#define TICK_SMPL_1x1 0
#define TICK_SMPL_1x2 1
#define TICK_SMPL_1x3 0
#define TICK_SMPL_1x4 0
#define CPU_2_MBUSL_DDR_CLK_1x2 \
((TICK_DRV_1x2 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \
(TICK_SMPL_1x2 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS))
#define CPU_2_MBUSL_DDR_CLK_1x3 \
((TICK_DRV_1x3 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \
(TICK_SMPL_1x3 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS))
#define CPU_2_MBUSL_DDR_CLK_1x4 \
((TICK_DRV_1x4 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \
(TICK_SMPL_1x4 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS))
/* ARM Control and Status register */
/* CPU_CTRL_STAT_REG (CCSR) */
/*
This is used to block PCI express\PCI from access Socrates/Feroceon GP
while ARM boot is still in progress
*/
#define CCSR_PCI_ACCESS_OFFS 0
#define CCSR_PCI_ACCESS_MASK BIT0
#define CCSR_PCI_ACCESS_ENABLE (0 << CCSR_PCI_ACCESS_OFFS)
#define CCSR_PCI_ACCESS_DISBALE (1 << CCSR_PCI_ACCESS_OFFS)
#define CCSR_ARM_RESET BIT1
#define CCSR_SELF_INT BIT2
#define CCSR_BIG_ENDIAN BIT15
/* RSTOUTn Mask Register */
/* CPU_RSTOUTN_MASK_REG (CRMR) */
#define CRMR_PEX_RST_OUT_OFFS 0
#define CRMR_PEX_RST_OUT_MASK BIT0
#define CRMR_PEX_RST_OUT_ENABLE (1 << CRMR_PEX_RST_OUT_OFFS)
#define CRMR_PEX_RST_OUT_DISABLE (0 << CRMR_PEX_RST_OUT_OFFS)
#define CRMR_WD_RST_OUT_OFFS 1
#define CRMR_WD_RST_OUT_MASK BIT1
#define CRMR_WD_RST_OUT_ENABLE (1 << CRMR_WD_RST_OUT_OFFS)
#define CRMR_WD_RST_OUT_DISBALE (0 << CRMR_WD_RST_OUT_OFFS)
#define CRMR_SOFT_RST_OUT_OFFS 2
#define CRMR_SOFT_RST_OUT_MASK BIT2
#define CRMR_SOFT_RST_OUT_ENABLE (1 << CRMR_SOFT_RST_OUT_OFFS)
#define CRMR_SOFT_RST_OUT_DISBALE (0 << CRMR_SOFT_RST_OUT_OFFS)
/* System Software Reset Register */
/* CPU_SYS_SOFT_RST_REG (CSSRR) */
#define CSSRR_SYSTEM_SOFT_RST BIT0
/* AHB to Mbus Bridge Interrupt Cause Register*/
/* CPU_AHB_MBUS_CAUSE_INT_REG (CAMCIR) */
#define CAMCIR_ARM_SELF_INT BIT0
#define CAMCIR_ARM_TIMER0_INT_REQ BIT1
#define CAMCIR_ARM_TIMER1_INT_REQ BIT2
#define CAMCIR_ARM_WD_TIMER_INT_REQ BIT3
/* AHB to Mbus Bridge Interrupt Mask Register*/
/* CPU_AHB_MBUS_MASK_INT_REG (CAMMIR) */
#define CAMCIR_ARM_SELF_INT_OFFS 0
#define CAMCIR_ARM_SELF_INT_MASK BIT0
#define CAMCIR_ARM_SELF_INT_EN (1 << CAMCIR_ARM_SELF_INT_OFFS)
#define CAMCIR_ARM_SELF_INT_DIS (0 << CAMCIR_ARM_SELF_INT_OFFS)
#define CAMCIR_ARM_TIMER0_INT_REQ_OFFS 1
#define CAMCIR_ARM_TIMER0_INT_REQ_MASK BIT1
#define CAMCIR_ARM_TIMER0_INT_REQ_EN (1 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS)
#define CAMCIR_ARM_TIMER0_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS)
#define CAMCIR_ARM_TIMER1_INT_REQ_OFFS 2
#define CAMCIR_ARM_TIMER1_INT_REQ_MASK BIT2
#define CAMCIR_ARM_TIMER1_INT_REQ_EN (1 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS)
#define CAMCIR_ARM_TIMER1_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS)
#define CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS 3
#define CAMCIR_ARM_WD_TIMER_INT_REQ_MASK BIT3
#define CAMCIR_ARM_WD_TIMER_INT_REQ_EN (1 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS)
#define CAMCIR_ARM_WD_TIMER_INT_REQ_DIS (0 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS)
/* CPU FTDLL Config register (CFCR) fields */
#define CFCR_FTDLL_ICACHE_TAG_OFFS 0
#define CFCR_FTDLL_ICACHE_TAG_MASK (0x7F << CFCR_FTDLL_ICACHE_TAG_OFFS)
#define CFCR_FTDLL_DCACHE_TAG_OFFS 8
#define CFCR_FTDLL_DCACHE_TAG_MASK (0x7F << CFCR_FTDLL_DCACHE_TAG_OFFS)
#define CFCR_FTDLL_OVERWRITE_ENABLE (1 << 15)
/* For Orion 2 D2 only */
#define CFCR_MRVL_CPU_ID_OFFS 16
#define CFCR_MRVL_CPU_ID_MASK (0x1 << CFCR_MRVL_CPU_ID_OFFS)
#define CFCR_ARM_CPU_ID (0x0 << CFCR_MRVL_CPU_ID_OFFS)
#define CFCR_MRVL_CPU_ID (0x1 << CFCR_MRVL_CPU_ID_OFFS)
#define CFCR_VFP_SUB_ARC_NUM_OFFS 7
#define CFCR_VFP_SUB_ARC_NUM_MASK (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS)
#define CFCR_VFP_SUB_ARC_NUM_1 (0x0 << CFCR_VFP_SUB_ARC_NUM_OFFS)
#define CFCR_VFP_SUB_ARC_NUM_2 (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS)
/* CPU_L2_CONFIG_REG fields */
#ifdef MV_CPU_LE
#define CL2CR_L2_ECC_EN_OFFS 2
#define CL2CR_L2_WT_MODE_OFFS 4
#else
#define CL2CR_L2_ECC_EN_OFFS 26
#define CL2CR_L2_WT_MODE_OFFS 28
#endif
#define CL2CR_L2_ECC_EN_MASK (1 << CL2CR_L2_ECC_EN_OFFS)
#define CL2CR_L2_WT_MODE_MASK (1 << CL2CR_L2_WT_MODE_OFFS)
/*******************************************/
/* Main Interrupt Controller Registers Map */
/*******************************************/
#define CPU_MAIN_INT_CAUSE_REG 0x20200
#define CPU_MAIN_IRQ_MASK_REG 0x20204
#define CPU_MAIN_FIQ_MASK_REG 0x20208
#define CPU_ENPOINT_MASK_REG 0x2020C
#define CPU_MAIN_INT_CAUSE_HIGH_REG 0x20210
#define CPU_MAIN_IRQ_MASK_HIGH_REG 0x20214
#define CPU_MAIN_FIQ_MASK_HIGH_REG 0x20218
#define CPU_ENPOINT_MASK_HIGH_REG 0x2021C
/*******************************************/
/* ARM Doorbell Registers Map */
/*******************************************/
#define CPU_HOST_TO_ARM_DRBL_REG 0x20400
#define CPU_HOST_TO_ARM_MASK_REG 0x20404
#define CPU_ARM_TO_HOST_DRBL_REG 0x20408
#define CPU_ARM_TO_HOST_MASK_REG 0x2040C
/* CPU control register map */
/* Set bits means value is about to change according to new value */
#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK | CCR_AHB_ERROR_PROP_MASK)
#define CPU_CONFIG_DEFAULT (CCR_VEC_INIT_LOC_FF00)
/* CPU Control and status defaults */
#define CPU_CTRL_STAT_DEFAULT_MASK (CCSR_PCI_ACCESS_MASK)
#define CPU_CTRL_STAT_DEFAULT (CCSR_PCI_ACCESS_ENABLE)
#endif /* __INCmvCpuIfRegsh */

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target/linux/generic-2.6/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c Normal file
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@ -0,0 +1,324 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "mvSysAudio.h"
/*******************************************************************************
* mvAudioWinSet - Set AUDIO target address window
*
* DESCRIPTION:
* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)
* address window, also known as address decode window.
* After setting this target window, the AUDIO will be able to access the
* target within the address window.
*
* INPUT:
* winNum - AUDIO target address decode window number.
* pAddrDecWin - AUDIO target window data structure.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_ERROR if address window overlapps with other address decode windows.
* MV_BAD_PARAM if base address is invalid parameter or target is
* unknown.
*
*******************************************************************************/
MV_STATUS mvAudioWinSet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin)
{
MV_TARGET_ATTRIB targetAttribs;
MV_DEC_REGS decRegs;
/* Parameter checking */
if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN)
{
mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum);
return MV_BAD_PARAM;
}
/* check if address is aligned to the size */
if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size))
{
mvOsPrintf("mvAudioWinSet:Error setting AUDIO window %d to "\
"target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n",
winNum,
mvCtrlTargetNameGet(pAddrDecWin->target),
pAddrDecWin->addrWin.baseLow,
pAddrDecWin->addrWin.size);
return MV_ERROR;
}
decRegs.baseReg = 0;
decRegs.sizeReg = 0;
if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs))
{
mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__);
return MV_ERROR;
}
mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs);
/* set attributes */
decRegs.sizeReg &= ~MV_AUDIO_WIN_ATTR_MASK;
decRegs.sizeReg |= (targetAttribs.attrib << MV_AUDIO_WIN_ATTR_OFFSET);
/* set target ID */
decRegs.sizeReg &= ~MV_AUDIO_WIN_TARGET_MASK;
decRegs.sizeReg |= (targetAttribs.targetId << MV_AUDIO_WIN_TARGET_OFFSET);
if (pAddrDecWin->enable == MV_TRUE)
{
decRegs.sizeReg |= MV_AUDIO_WIN_ENABLE_MASK;
}
else
{
decRegs.sizeReg &= ~MV_AUDIO_WIN_ENABLE_MASK;
}
MV_REG_WRITE( MV_AUDIO_WIN_CTRL_REG(winNum), decRegs.sizeReg);
MV_REG_WRITE( MV_AUDIO_WIN_BASE_REG(winNum), decRegs.baseReg);
return MV_OK;
}
/*******************************************************************************
* mvAudioWinGet - Get AUDIO peripheral target address window.
*
* DESCRIPTION:
* Get AUDIO peripheral target address window.
*
* INPUT:
* winNum - AUDIO target address decode window number.
*
* OUTPUT:
* pAddrDecWin - AUDIO target window data structure.
*
* RETURN:
* MV_ERROR if register parameters are invalid.
*
*******************************************************************************/
MV_STATUS mvAudioWinGet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin)
{
MV_DEC_REGS decRegs;
MV_TARGET_ATTRIB targetAttrib;
/* Parameter checking */
if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN)
{
mvOsPrintf("%s : ERR. Invalid winNum %d\n",
__FUNCTION__, winNum);
return MV_NOT_SUPPORTED;
}
decRegs.baseReg = MV_REG_READ( MV_AUDIO_WIN_BASE_REG(winNum) );
decRegs.sizeReg = MV_REG_READ( MV_AUDIO_WIN_CTRL_REG(winNum) );
if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) )
{
mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__);
return MV_ERROR;
}
/* attrib and targetId */
targetAttrib.attrib = (decRegs.sizeReg & MV_AUDIO_WIN_ATTR_MASK) >>
MV_AUDIO_WIN_ATTR_OFFSET;
targetAttrib.targetId = (decRegs.sizeReg & MV_AUDIO_WIN_TARGET_MASK) >>
MV_AUDIO_WIN_TARGET_OFFSET;
pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
/* Check if window is enabled */
if(decRegs.sizeReg & MV_AUDIO_WIN_ENABLE_MASK)
{
pAddrDecWin->enable = MV_TRUE;
}
else
{
pAddrDecWin->enable = MV_FALSE;
}
return MV_OK;
}
/*******************************************************************************
* mvAudioAddrDecShow - Print the AUDIO address decode map.
*
* DESCRIPTION:
* This function print the AUDIO address decode map.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_VOID mvAudioAddrDecShow(MV_VOID)
{
MV_AUDIO_DEC_WIN win;
int i;
if (MV_FALSE == mvCtrlPwrClckGet(AUDIO_UNIT_ID, 0))
return;
mvOsOutput( "\n" );
mvOsOutput( "AUDIO:\n" );
mvOsOutput( "----\n" );
for( i = 0; i < MV_AUDIO_MAX_ADDR_DECODE_WIN; i++ )
{
memset( &win, 0, sizeof(MV_AUDIO_DEC_WIN) );
mvOsOutput( "win%d - ", i );
if( mvAudioWinGet( i, &win ) == MV_OK )
{
if( win.enable )
{
mvOsOutput( "%s base %08x, ",
mvCtrlTargetNameGet(win.target), win.addrWin.baseLow );
mvOsOutput( "...." );
mvSizePrint( win.addrWin.size );
mvOsOutput( "\n" );
}
else
mvOsOutput( "disable\n" );
}
}
}
/*******************************************************************************
* mvAudioWinInit - Initialize the integrated AUDIO target address window.
*
* DESCRIPTION:
* Initialize the AUDIO peripheral target address window.
*
* INPUT:
*
*
* OUTPUT:
*
*
* RETURN:
* MV_ERROR if register parameters are invalid.
*
*******************************************************************************/
MV_STATUS mvAudioInit(MV_VOID)
{
int winNum;
MV_AUDIO_DEC_WIN audioWin;
MV_CPU_DEC_WIN cpuAddrDecWin;
MV_U32 status;
mvAudioHalInit();
/* Initiate Audio address decode */
/* First disable all address decode windows */
for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++)
{
MV_U32 regVal = MV_REG_READ(MV_AUDIO_WIN_CTRL_REG(winNum));
regVal &= ~MV_AUDIO_WIN_ENABLE_MASK;
MV_REG_WRITE(MV_AUDIO_WIN_CTRL_REG(winNum), regVal);
}
for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++)
{
/* We will set the Window to DRAM_CS0 in default */
/* first get attributes from CPU If */
status = mvCpuIfTargetWinGet(SDRAM_CS0,
&cpuAddrDecWin);
if (MV_OK != status)
{
mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__);
return MV_ERROR;
}
if (cpuAddrDecWin.enable == MV_TRUE)
{
audioWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;
audioWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow;
audioWin.addrWin.size = cpuAddrDecWin.addrWin.size;
audioWin.enable = MV_TRUE;
audioWin.target = SDRAM_CS0;
if(MV_OK != mvAudioWinSet(winNum, &audioWin))
{
return MV_ERROR;
}
}
}
return MV_OK;
}

123
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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCMVSysAudioH
#define __INCMVSysAudioH
#include "mvCommon.h"
#include "audio/mvAudio.h"
#include "ctrlEnv/mvCtrlEnvSpec.h"
#include "ctrlEnv/sys/mvCpuIf.h"
/***********************************/
/* Audio Address Decoding registers*/
/***********************************/
#define MV_AUDIO_MAX_ADDR_DECODE_WIN 2
#define MV_AUDIO_RECORD_WIN_NUM 0
#define MV_AUDIO_PLAYBACK_WIN_NUM 1
#define MV_AUDIO_WIN_CTRL_REG(win) (AUDIO_REG_BASE + 0xA04 + ((win)<<3))
#define MV_AUDIO_WIN_BASE_REG(win) (AUDIO_REG_BASE + 0xA00 + ((win)<<3))
#define MV_AUDIO_RECORD_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_RECORD_WIN_NUM)
#define MV_AUDIO_RECORD_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_RECORD_WIN_NUM)
#define MV_AUDIO_PLAYBACK_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_PLAYBACK_WIN_NUM)
#define MV_AUDIO_PLAYBACK_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_PLAYBACK_WIN_NUM)
/* BITs in Windows 0-3 Control and Base Registers */
#define MV_AUDIO_WIN_ENABLE_BIT 0
#define MV_AUDIO_WIN_ENABLE_MASK (1<<MV_AUDIO_WIN_ENABLE_BIT)
#define MV_AUDIO_WIN_TARGET_OFFSET 4
#define MV_AUDIO_WIN_TARGET_MASK (0xF<<MV_AUDIO_WIN_TARGET_OFFSET)
#define MV_AUDIO_WIN_ATTR_OFFSET 8
#define MV_AUDIO_WIN_ATTR_MASK (0xFF<<MV_AUDIO_WIN_ATTR_OFFSET)
#define MV_AUDIO_WIN_SIZE_OFFSET 16
#define MV_AUDIO_WIN_SIZE_MASK (0xFFFF<<MV_AUDIO_WIN_SIZE_OFFSET)
#define MV_AUDIO_WIN_BASE_OFFSET 16
#define MV_AUDIO_WIN_BASE_MASK (0xFFFF<<MV_AUDIO_WIN_BASE_OFFSET)
typedef struct _mvAudioDecWin
{
MV_TARGET target;
MV_ADDR_WIN addrWin; /* An address window*/
MV_BOOL enable; /* Address decode window is enabled/disabled */
} MV_AUDIO_DEC_WIN;
MV_STATUS mvAudioInit(MV_VOID);
MV_STATUS mvAudioWinGet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin);
MV_STATUS mvAudioWinSet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin);
MV_STATUS mvAudioWinInit(MV_VOID);
MV_VOID mvAudioAddrDecShow(MV_VOID);
#endif

382
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@ -0,0 +1,382 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "mvSysCesa.h"
#if (MV_CESA_VERSION >= 2)
MV_TARGET tdmaAddrDecPrioTable[] =
{
#if defined(MV_INCLUDE_SDRAM_CS0)
SDRAM_CS0,
#endif
#if defined(MV_INCLUDE_SDRAM_CS1)
SDRAM_CS1,
#endif
#if defined(MV_INCLUDE_SDRAM_CS2)
SDRAM_CS2,
#endif
#if defined(MV_INCLUDE_SDRAM_CS3)
SDRAM_CS3,
#endif
#if defined(MV_INCLUDE_PEX)
PEX0_MEM,
#endif
TBL_TERM
};
/*******************************************************************************
* mvCesaWinGet - Get TDMA target address window.
*
* DESCRIPTION:
* Get TDMA target address window.
*
* INPUT:
* winNum - TDMA target address decode window number.
*
* OUTPUT:
* pDecWin - TDMA target window data structure.
*
* RETURN:
* MV_ERROR if register parameters are invalid.
*
*******************************************************************************/
static MV_STATUS mvCesaWinGet(MV_U32 winNum, MV_DEC_WIN *pDecWin)
{
MV_DEC_WIN_PARAMS winParam;
MV_U32 sizeReg, baseReg;
/* Parameter checking */
if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN)
{
mvOsPrintf("%s : ERR. Invalid winNum %d\n",
__FUNCTION__, winNum);
return MV_NOT_SUPPORTED;
}
baseReg = MV_REG_READ( MV_CESA_TDMA_BASE_ADDR_REG(winNum) );
sizeReg = MV_REG_READ( MV_CESA_TDMA_WIN_CTRL_REG(winNum) );
/* Check if window is enabled */
if(sizeReg & MV_CESA_TDMA_WIN_ENABLE_MASK)
{
pDecWin->enable = MV_TRUE;
/* Extract window parameters from registers */
winParam.targetId = (sizeReg & MV_CESA_TDMA_WIN_TARGET_MASK) >> MV_CESA_TDMA_WIN_TARGET_OFFSET;
winParam.attrib = (sizeReg & MV_CESA_TDMA_WIN_ATTR_MASK) >> MV_CESA_TDMA_WIN_ATTR_OFFSET;
winParam.size = (sizeReg & MV_CESA_TDMA_WIN_SIZE_MASK) >> MV_CESA_TDMA_WIN_SIZE_OFFSET;
winParam.baseAddr = (baseReg & MV_CESA_TDMA_WIN_BASE_MASK);
/* Translate the decode window parameters to address decode struct */
if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin))
{
mvOsPrintf("Failed to translate register parameters to CESA address" \
" decode window structure\n");
return MV_ERROR;
}
}
else
{
pDecWin->enable = MV_FALSE;
}
return MV_OK;
}
/*******************************************************************************
* cesaWinOverlapDetect - Detect CESA TDMA address windows overlapping
*
* DESCRIPTION:
* An unpredicted behaviur is expected in case TDMA address decode
* windows overlapps.
* This function detects TDMA address decode windows overlapping of a
* specified window. The function does not check the window itself for
* overlapping. The function also skipps disabled address decode windows.
*
* INPUT:
* winNum - address decode window number.
* pAddrDecWin - An address decode window struct.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_TRUE - if the given address window overlap current address
* decode map,
* MV_FALSE - otherwise, MV_ERROR if reading invalid data
* from registers.
*
*******************************************************************************/
static MV_STATUS cesaWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin)
{
MV_U32 winNumIndex;
MV_DEC_WIN addrDecWin;
for(winNumIndex=0; winNumIndex<MV_CESA_TDMA_ADDR_DEC_WIN; winNumIndex++)
{
/* Do not check window itself */
if (winNumIndex == winNum)
{
continue;
}
/* Get window parameters */
if (MV_OK != mvCesaWinGet(winNumIndex, &addrDecWin))
{
mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__);
return MV_ERROR;
}
/* Do not check disabled windows */
if(addrDecWin.enable == MV_FALSE)
{
continue;
}
if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin)))
{
return MV_TRUE;
}
}
return MV_FALSE;
}
/*******************************************************************************
* mvCesaTdmaWinSet - Set CESA TDMA target address window
*
* DESCRIPTION:
* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)
* address window, also known as address decode window.
* After setting this target window, the CESA TDMA will be able to access the
* target within the address window.
*
* INPUT:
* winNum - CESA TDMA target address decode window number.
* pAddrDecWin - CESA TDMA target window data structure.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_ERROR - if address window overlapps with other address decode windows.
* MV_BAD_PARAM - if base address is invalid parameter or target is
* unknown.
*
*******************************************************************************/
static MV_STATUS mvCesaTdmaWinSet(MV_U32 winNum, MV_DEC_WIN *pDecWin)
{
MV_DEC_WIN_PARAMS winParams;
MV_U32 sizeReg, baseReg;
/* Parameter checking */
if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN)
{
mvOsPrintf("mvCesaTdmaWinSet: ERR. Invalid win num %d\n",winNum);
return MV_BAD_PARAM;
}
/* Check if the requested window overlapps with current windows */
if (MV_TRUE == cesaWinOverlapDetect(winNum, &pDecWin->addrWin))
{
mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum);
return MV_ERROR;
}
/* check if address is aligned to the size */
if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size))
{
mvOsPrintf("mvCesaTdmaWinSet: Error setting CESA TDMA window %d to "\
"target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n",
winNum,
mvCtrlTargetNameGet(pDecWin->target),
pDecWin->addrWin.baseLow,
pDecWin->addrWin.size);
return MV_ERROR;
}
if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams))
{
mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__);
return MV_ERROR;
}
/* set Size, Attributes and TargetID */
sizeReg = (((winParams.targetId << MV_CESA_TDMA_WIN_TARGET_OFFSET) & MV_CESA_TDMA_WIN_TARGET_MASK) |
((winParams.attrib << MV_CESA_TDMA_WIN_ATTR_OFFSET) & MV_CESA_TDMA_WIN_ATTR_MASK) |
((winParams.size << MV_CESA_TDMA_WIN_SIZE_OFFSET) & MV_CESA_TDMA_WIN_SIZE_MASK));
if (pDecWin->enable == MV_TRUE)
{
sizeReg |= MV_CESA_TDMA_WIN_ENABLE_MASK;
}
else
{
sizeReg &= ~MV_CESA_TDMA_WIN_ENABLE_MASK;
}
/* Update Base value */
baseReg = (winParams.baseAddr & MV_CESA_TDMA_WIN_BASE_MASK);
MV_REG_WRITE( MV_CESA_TDMA_WIN_CTRL_REG(winNum), sizeReg);
MV_REG_WRITE( MV_CESA_TDMA_BASE_ADDR_REG(winNum), baseReg);
return MV_OK;
}
static MV_STATUS mvCesaTdmaAddrDecInit (void)
{
MV_U32 winNum;
MV_STATUS status;
MV_CPU_DEC_WIN cpuAddrDecWin;
MV_DEC_WIN cesaWin;
MV_U32 winPrioIndex = 0;
/* First disable all address decode windows */
for(winNum=0; winNum<MV_CESA_TDMA_ADDR_DEC_WIN; winNum++)
{
MV_REG_BIT_RESET(MV_CESA_TDMA_WIN_CTRL_REG(winNum), MV_CESA_TDMA_WIN_ENABLE_MASK);
}
/* Go through all windows in user table until table terminator */
winNum = 0;
while( (tdmaAddrDecPrioTable[winPrioIndex] != TBL_TERM) &&
(winNum < MV_CESA_TDMA_ADDR_DEC_WIN) ) {
/* first get attributes from CPU If */
status = mvCpuIfTargetWinGet(tdmaAddrDecPrioTable[winPrioIndex],
&cpuAddrDecWin);
if(MV_NO_SUCH == status){
winPrioIndex++;
continue;
}
if (MV_OK != status)
{
mvOsPrintf("cesaInit: TargetWinGet failed. winNum=%d, winIdx=%d, target=%d, status=0x%x\n",
winNum, winPrioIndex, tdmaAddrDecPrioTable[winPrioIndex], status);
return MV_ERROR;
}
if (cpuAddrDecWin.enable == MV_TRUE)
{
cesaWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;
cesaWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow;
cesaWin.addrWin.size = cpuAddrDecWin.addrWin.size;
cesaWin.enable = MV_TRUE;
cesaWin.target = tdmaAddrDecPrioTable[winPrioIndex];
#if defined(MV646xx)
/* Get the default attributes for that target window */
mvCtrlDefAttribGet(cesaWin.target, &cesaWin.addrWinAttr);
#endif /* MV646xx */
if(MV_OK != mvCesaTdmaWinSet(winNum, &cesaWin))
{
mvOsPrintf("mvCesaTdmaWinSet FAILED: winNum=%d\n",
winNum);
return MV_ERROR;
}
winNum++;
}
winPrioIndex++;
}
return MV_OK;
}
#endif /* MV_CESA_VERSION >= 2 */
MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle)
{
MV_U32 cesaCryptEngBase;
MV_CPU_DEC_WIN addrDecWin;
if(sizeof(MV_CESA_SRAM_MAP) > MV_CESA_SRAM_SIZE)
{
mvOsPrintf("mvCesaInit: Wrong SRAM map - %ld > %d\n",
sizeof(MV_CESA_SRAM_MAP), MV_CESA_SRAM_SIZE);
return MV_FAIL;
}
#if 0
if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK)
cesaCryptEngBase = addrDecWin.addrWin.baseLow;
else
{
mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n");
return MV_ERROR;
}
#else
cesaCryptEngBase = (MV_U32)pSramBase;
#endif
#if 0 /* Already done in the platform init */
#if (MV_CESA_VERSION >= 2)
mvCesaTdmaAddrDecInit();
#endif /* MV_CESA_VERSION >= 2 */
#endif
return mvCesaHalInit(numOfSession, queueDepth, pSramBase, cesaCryptEngBase,
osHandle);
}

100
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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __mvSysCesa_h__
#define __mvSysCesa_h__
#include "mvCommon.h"
#include "cesa/mvCesa.h"
#include "ctrlEnv/mvCtrlEnvSpec.h"
#include "ctrlEnv/sys/mvCpuIf.h"
/***************************** TDMA Registers *************************************/
#define MV_CESA_TDMA_ADDR_DEC_WIN 4
#define MV_CESA_TDMA_BASE_ADDR_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa00 + (win<<3))
#define MV_CESA_TDMA_WIN_CTRL_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa04 + (win<<3))
#define MV_CESA_TDMA_WIN_ENABLE_BIT 0
#define MV_CESA_TDMA_WIN_ENABLE_MASK (1 << MV_CESA_TDMA_WIN_ENABLE_BIT)
#define MV_CESA_TDMA_WIN_TARGET_OFFSET 4
#define MV_CESA_TDMA_WIN_TARGET_MASK (0xf << MV_CESA_TDMA_WIN_TARGET_OFFSET)
#define MV_CESA_TDMA_WIN_ATTR_OFFSET 8
#define MV_CESA_TDMA_WIN_ATTR_MASK (0xff << MV_CESA_TDMA_WIN_ATTR_OFFSET)
#define MV_CESA_TDMA_WIN_SIZE_OFFSET 16
#define MV_CESA_TDMA_WIN_SIZE_MASK (0xFFFF << MV_CESA_TDMA_WIN_SIZE_OFFSET)
#define MV_CESA_TDMA_WIN_BASE_OFFSET 16
#define MV_CESA_TDMA_WIN_BASE_MASK (0xFFFF << MV_CESA_TDMA_WIN_BASE_OFFSET)
MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle);
#endif

348
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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/* includes */
#include "ddr2/mvDramIf.h"
#include "ctrlEnv/sys/mvCpuIf.h"
#include "ctrlEnv/sys/mvSysDram.h"
/* #define MV_DEBUG */
#ifdef MV_DEBUG
#define DB(x) x
#else
#define DB(x)
#endif
static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin);
/*******************************************************************************
* mvDramIfWinSet - Set DRAM interface address decode window
*
* DESCRIPTION:
* This function sets DRAM interface address decode window.
*
* INPUT:
* target - System target. Use only SDRAM targets.
* pAddrDecWin - SDRAM address window structure.
*
* OUTPUT:
* None
*
* RETURN:
* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK
* otherwise.
*******************************************************************************/
MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin)
{
MV_U32 baseReg=0,sizeReg=0;
MV_U32 baseToReg=0 , sizeToReg=0;
/* Check parameters */
if (!MV_TARGET_IS_DRAM(target))
{
mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target);
return MV_BAD_PARAM;
}
/* Check if the requested window overlaps with current enabled windows */
if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin))
{
mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target);
return MV_BAD_PARAM;
}
/* check if address is aligned to the size */
if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size))
{
mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\
"\nAddress 0x%08x is unaligned to size 0x%x.\n",
target,
pAddrDecWin->addrWin.baseLow,
pAddrDecWin->addrWin.size);
return MV_ERROR;
}
/* read base register*/
baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target));
/* read size register */
sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target));
/* BaseLow[31:16] => base register [31:16] */
baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK;
/* Write to address decode Base Address Register */
baseReg &= ~SCBAR_BASE_MASK;
baseReg |= baseToReg;
/* Translate the given window size to register format */
sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT);
/* Size parameter validity check. */
if (-1 == sizeToReg)
{
mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target);
return MV_BAD_PARAM;
}
/* set size */
sizeReg &= ~SCSR_SIZE_MASK;
/* Size is located at upper 16 bits */
sizeReg |= (sizeToReg << SCSR_SIZE_OFFS);
/* enable/Disable */
if (MV_TRUE == pAddrDecWin->enable)
{
sizeReg |= SCSR_WIN_EN;
}
else
{
sizeReg &= ~SCSR_WIN_EN;
}
/* 3) Write to address decode Base Address Register */
MV_REG_WRITE(SDRAM_BASE_ADDR_REG(0,target), baseReg);
/* Write to address decode Size Register */
MV_REG_WRITE(SDRAM_SIZE_REG(0,target), sizeReg);
return MV_OK;
}
/*******************************************************************************
* mvDramIfWinGet - Get DRAM interface address decode window
*
* DESCRIPTION:
* This function gets DRAM interface address decode window.
*
* INPUT:
* target - System target. Use only SDRAM targets.
*
* OUTPUT:
* pAddrDecWin - SDRAM address window structure.
*
* RETURN:
* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK
* otherwise.
*******************************************************************************/
MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin)
{
MV_U32 baseReg,sizeReg;
MV_U32 sizeRegVal;
/* Check parameters */
if (!MV_TARGET_IS_DRAM(target))
{
mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target);
return MV_ERROR;
}
/* Read base and size registers */
sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target));
baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target));
sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS;
pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal,
SCSR_SIZE_ALIGNMENT);
/* Check if ctrlRegToSize returned OK */
if (-1 == pAddrDecWin->addrWin.size)
{
mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target);
return MV_ERROR;
}
/* Extract base address */
/* Base register [31:16] ==> baseLow[31:16] */
pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK;
pAddrDecWin->addrWin.baseHigh = 0;
if (sizeReg & SCSR_WIN_EN)
{
pAddrDecWin->enable = MV_TRUE;
}
else
{
pAddrDecWin->enable = MV_FALSE;
}
return MV_OK;
}
/*******************************************************************************
* mvDramIfWinEnable - Enable/Disable SDRAM address decode window
*
* DESCRIPTION:
* This function enable/Disable SDRAM address decode window.
*
* INPUT:
* target - System target. Use only SDRAM targets.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_ERROR in case function parameter are invalid, MV_OK otherewise.
*
*******************************************************************************/
MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable)
{
MV_DRAM_DEC_WIN addrDecWin;
/* Check parameters */
if (!MV_TARGET_IS_DRAM(target))
{
mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target);
return MV_ERROR;
}
if (enable == MV_TRUE)
{ /* First check for overlap with other enabled windows */
if (MV_OK != mvDramIfWinGet(target, &addrDecWin))
{
mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n",
target);
return MV_ERROR;
}
/* Check for overlapping */
if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin)))
{
/* No Overlap. Enable address decode winNum window */
MV_REG_BIT_SET(SDRAM_SIZE_REG(0,target), SCSR_WIN_EN);
}
else
{ /* Overlap detected */
mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n",
target);
return MV_ERROR;
}
}
else
{ /* Disable address decode winNum window */
MV_REG_BIT_RESET(SDRAM_SIZE_REG(0, target), SCSR_WIN_EN);
}
return MV_OK;
}
/*******************************************************************************
* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window
*
* DESCRIPTION:
* This function scan each SDRAM address decode window to test if it
* overlapps the given address windoow
*
* INPUT:
* target - SDRAM target where the function skips checking.
* pAddrDecWin - The tested address window for overlapping with
* SDRAM windows.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_TRUE if the given address window overlaps any enabled address
* decode map, MV_FALSE otherwise.
*
*******************************************************************************/
static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin)
{
MV_TARGET targetNum;
MV_DRAM_DEC_WIN addrDecWin;
for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++)
{
/* don't check our winNum or illegal targets */
if (targetNum == target)
{
continue;
}
/* Get window parameters */
if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin))
{
mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n");
return MV_ERROR;
}
/* Do not check disabled windows */
if (MV_FALSE == addrDecWin.enable)
{
continue;
}
if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin))
{
mvOsPrintf(
"sdramIfWinOverlap: Required target %d overlap winNum %d\n",
target, targetNum);
return MV_TRUE;
}
}
return MV_FALSE;
}

80
target/linux/generic-2.6/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h Normal file
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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __sysDram
#define __sysDram
/* This structure describes CPU interface address decode window */
typedef struct _mvDramIfDecWin
{
MV_ADDR_WIN addrWin; /* An address window*/
MV_BOOL enable; /* Address decode window is enabled/disabled */
}MV_DRAM_DEC_WIN;
MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin);
MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin);
MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable);
#endif

658
target/linux/generic-2.6/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c Normal file
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@ -0,0 +1,658 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "ctrlEnv/sys/mvSysGbe.h"
typedef struct _mvEthDecWin
{
MV_TARGET target;
MV_ADDR_WIN addrWin; /* An address window*/
MV_BOOL enable; /* Address decode window is enabled/disabled */
}MV_ETH_DEC_WIN;
MV_TARGET ethAddrDecPrioTap[] =
{
#if defined(MV_INCLUDE_SDRAM_CS0)
SDRAM_CS0,
#endif
#if defined(MV_INCLUDE_SDRAM_CS1)
SDRAM_CS1,
#endif
#if defined(MV_INCLUDE_SDRAM_CS2)
SDRAM_CS2,
#endif
#if defined(MV_INCLUDE_SDRAM_CS3)
SDRAM_CS3,
#endif
#if defined(MV_INCLUDE_DEVICE_CS0)
DEVICE_CS0,
#endif
#if defined(MV_INCLUDE_DEVICE_CS1)
DEVICE_CS1,
#endif
#if defined(MV_INCLUDE_DEVICE_CS2)
DEVICE_CS2,
#endif
#if defined(MV_INCLUDE_DEVICE_CS3)
DEVICE_CS3,
#endif
#if defined(MV_INCLUDE_PEX)
PEX0_IO,
#endif
TBL_TERM
};
static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin);
static MV_STATUS mvEthWinSet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin);
static MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin);
/*******************************************************************************
* mvEthWinInit - Initialize ETH address decode windows
*
* DESCRIPTION:
* This function initialize ETH window decode unit. It set the
* default address decode windows of the unit.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_ERROR if setting fail.
*******************************************************************************/
/* Configure EthDrv memory map registes. */
MV_STATUS mvEthWinInit (int port)
{
MV_U32 winNum, status, winPrioIndex=0, i, regVal=0;
MV_ETH_DEC_WIN ethWin;
MV_CPU_DEC_WIN cpuAddrDecWin;
static MV_U32 accessProtReg = 0;
#if (MV_ETH_VERSION <= 1)
static MV_BOOL isFirst = MV_TRUE;
if(isFirst == MV_FALSE)
{
MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(port), accessProtReg);
return MV_OK;
}
isFirst = MV_FALSE;
#endif /* MV_GIGA_ETH_VERSION */
/* Initiate Ethernet address decode */
/* First disable all address decode windows */
for(winNum=0; winNum<ETH_MAX_DECODE_WIN; winNum++)
{
regVal |= MV_BIT_MASK(winNum);
}
MV_REG_WRITE(ETH_BASE_ADDR_ENABLE_REG(port), regVal);
/* Go through all windows in user table until table terminator */
for (winNum=0; ((ethAddrDecPrioTap[winPrioIndex] != TBL_TERM) &&
(winNum < ETH_MAX_DECODE_WIN)); )
{
/* first get attributes from CPU If */
status = mvCpuIfTargetWinGet(ethAddrDecPrioTap[winPrioIndex],
&cpuAddrDecWin);
if(MV_NO_SUCH == status)
{
winPrioIndex++;
continue;
}
if (MV_OK != status)
{
mvOsPrintf("mvEthWinInit: ERR. mvCpuIfTargetWinGet failed\n");
return MV_ERROR;
}
if (cpuAddrDecWin.enable == MV_TRUE)
{
ethWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;
ethWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow;
ethWin.addrWin.size = cpuAddrDecWin.addrWin.size;
ethWin.enable = MV_TRUE;
ethWin.target = ethAddrDecPrioTap[winPrioIndex];
if(MV_OK != mvEthWinSet(port, winNum, &ethWin))
{
mvOsPrintf("mvEthWinInit: ERR. mvEthWinSet failed winNum=%d\n",
winNum);
return MV_ERROR;
}
winNum++;
}
winPrioIndex ++;
}
/* set full access to all windows. */
for(i=0; i<winNum; i++)
{
accessProtReg |= (FULL_ACCESS << (i*2));
}
MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(port), accessProtReg);
return MV_OK;
}
/*******************************************************************************
* mvEthWinSet - Set ETH target address window
*
* DESCRIPTION:
* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)
* address window, also known as address decode window.
* After setting this target window, the ETH will be able to access the
* target within the address window.
*
* INPUT:
* winNum - ETH to target address decode window number.
* pAddrDecWin - ETH target window data structure.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_ERROR if address window overlapps with other address decode windows.
* MV_BAD_PARAM if base address is invalid parameter or target is
* unknown.
*
*******************************************************************************/
MV_STATUS mvEthWinSet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin)
{
MV_TARGET_ATTRIB targetAttribs;
MV_DEC_REGS decRegs;
/* Parameter checking */
if (winNum >= ETH_MAX_DECODE_WIN)
{
mvOsPrintf("mvEthWinSet: ERR. Invalid win num %d\n",winNum);
return MV_BAD_PARAM;
}
/* Check if the requested window overlapps with current windows */
if (MV_TRUE == ethWinOverlapDetect(port, winNum, &pAddrDecWin->addrWin))
{
mvOsPrintf("mvEthWinSet: ERR. Window %d overlap\n", winNum);
return MV_ERROR;
}
/* check if address is aligned to the size */
if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size))
{
mvOsPrintf("mvEthWinSet: Error setting Ethernet window %d to "\
"target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n",
winNum,
mvCtrlTargetNameGet(pAddrDecWin->target),
pAddrDecWin->addrWin.baseLow,
pAddrDecWin->addrWin.size);
return MV_ERROR;
}
decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum));
decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum));
if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs))
{
mvOsPrintf("mvEthWinSet:mvCtrlAddrDecToReg Failed\n");
return MV_ERROR;
}
mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs);
/* set attributes */
decRegs.baseReg &= ~ETH_WIN_ATTR_MASK;
decRegs.baseReg |= targetAttribs.attrib << ETH_WIN_ATTR_OFFS;
/* set target ID */
decRegs.baseReg &= ~ETH_WIN_TARGET_MASK;
decRegs.baseReg |= targetAttribs.targetId << ETH_WIN_TARGET_OFFS;
/* for the safe side we disable the window before writing the new
values */
mvEthWinEnable(port, winNum, MV_FALSE);
MV_REG_WRITE(ETH_WIN_BASE_REG(port, winNum), decRegs.baseReg);
/* Write to address decode Size Register */
MV_REG_WRITE(ETH_WIN_SIZE_REG(port, winNum), decRegs.sizeReg);
/* Enable address decode target window */
if (pAddrDecWin->enable == MV_TRUE)
{
mvEthWinEnable(port, winNum, MV_TRUE);
}
return MV_OK;
}
/*******************************************************************************
* mvETHWinGet - Get dma peripheral target address window.
*
* DESCRIPTION:
* Get ETH peripheral target address window.
*
* INPUT:
* winNum - ETH to target address decode window number.
*
* OUTPUT:
* pAddrDecWin - ETH target window data structure.
*
* RETURN:
* MV_ERROR if register parameters are invalid.
*
*******************************************************************************/
MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin)
{
MV_DEC_REGS decRegs;
MV_TARGET_ATTRIB targetAttrib;
/* Parameter checking */
if (winNum >= ETH_MAX_DECODE_WIN)
{
mvOsPrintf("mvEthWinGet: ERR. Invalid winNum %d\n", winNum);
return MV_NOT_SUPPORTED;
}
decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum));
decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum));
if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin)))
{
mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n");
return MV_ERROR;
}
/* attrib and targetId */
targetAttrib.attrib =
(decRegs.baseReg & ETH_WIN_ATTR_MASK) >> ETH_WIN_ATTR_OFFS;
targetAttrib.targetId =
(decRegs.baseReg & ETH_WIN_TARGET_MASK) >> ETH_WIN_TARGET_OFFS;
pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
/* Check if window is enabled */
if (~(MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port))) & (1 << winNum) )
{
pAddrDecWin->enable = MV_TRUE;
}
else
{
pAddrDecWin->enable = MV_FALSE;
}
return MV_OK;
}
/*******************************************************************************
* mvEthWinEnable - Enable/disable a ETH to target address window
*
* DESCRIPTION:
* This function enable/disable a ETH to target address window.
* According to parameter 'enable' the routine will enable the
* window, thus enabling ETH accesses (before enabling the window it is
* tested for overlapping). Otherwise, the window will be disabled.
*
* INPUT:
* winNum - ETH to target address decode window number.
* enable - Enable/disable parameter.
*
* OUTPUT:
* N/A
*
* RETURN:
* MV_ERROR if decode window number was wrong or enabled window overlapps.
*
*******************************************************************************/
MV_STATUS mvEthWinEnable(int port, MV_U32 winNum,MV_BOOL enable)
{
MV_ETH_DEC_WIN addrDecWin;
/* Parameter checking */
if (winNum >= ETH_MAX_DECODE_WIN)
{
mvOsPrintf("mvEthTargetWinEnable:ERR. Invalid winNum%d\n",winNum);
return MV_ERROR;
}
if (enable == MV_TRUE)
{ /* First check for overlap with other enabled windows */
/* Get current window */
if (MV_OK != mvEthWinGet(port, winNum, &addrDecWin))
{
mvOsPrintf("mvEthTargetWinEnable:ERR. targetWinGet fail\n");
return MV_ERROR;
}
/* Check for overlapping */
if (MV_FALSE == ethWinOverlapDetect(port, winNum, &(addrDecWin.addrWin)))
{
/* No Overlap. Enable address decode target window */
MV_REG_BIT_RESET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum));
}
else
{ /* Overlap detected */
mvOsPrintf("mvEthTargetWinEnable:ERR. Overlap detected\n");
return MV_ERROR;
}
}
else
{ /* Disable address decode target window */
MV_REG_BIT_SET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum));
}
return MV_OK;
}
/*******************************************************************************
* mvEthWinTargetGet - Get Window number associated with target
*
* DESCRIPTION:
*
* INPUT:
*
* OUTPUT:
*
* RETURN:
* window number
*
*******************************************************************************/
MV_U32 mvEthWinTargetGet(int port, MV_TARGET target)
{
MV_ETH_DEC_WIN decWin;
MV_U32 winNum;
/* Check parameters */
if (target >= MAX_TARGETS)
{
mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target);
return 0xffffffff;
}
for (winNum=0; winNum<ETH_MAX_DECODE_WIN; winNum++)
{
if (mvEthWinGet(port, winNum,&decWin) != MV_OK)
{
mvOsPrintf("mvAhbToMbusWinTargetGet: window returned error\n");
return 0xffffffff;
}
if (decWin.enable == MV_TRUE)
{
if (decWin.target == target)
{
return winNum;
}
}
}
return 0xFFFFFFFF;
}
/*******************************************************************************
* mvEthProtWinSet - Set access protection of Ethernet to target window.
*
* DESCRIPTION:
* Each Ethernet port can be configured with access attributes for each
* of the Ethenret to target windows (address decode windows). This
* function sets access attributes to a given window for the given channel.
*
* INPUTS:
* ethPort - ETH channel number. See MV_ETH_CHANNEL enumerator.
* winNum - IETH to target address decode window number.
* access - IETH access rights. See MV_ACCESS_RIGHTS enumerator.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_ERROR in case window number is invalid or access right reserved.
*
*******************************************************************************/
MV_STATUS mvEthProtWinSet(MV_U32 portNo, MV_U32 winNum, MV_ACCESS_RIGHTS access)
{
MV_U32 protReg;
/* Parameter checking */
if(portNo >= mvCtrlEthMaxPortGet())
{
mvOsPrintf("mvEthProtWinSet:ERR. Invalid port number %d\n", portNo);
return MV_ERROR;
}
if (winNum >= ETH_MAX_DECODE_WIN)
{
mvOsPrintf("mvEthProtWinSet:ERR. Invalid winNum%d\n",winNum);
return MV_ERROR;
}
if((access == ACC_RESERVED) || (access >= MAX_ACC_RIGHTS))
{
mvOsPrintf("mvEthProtWinSet:ERR. Inv access param %d\n", access);
return MV_ERROR;
}
/* Read current protection register */
protReg = MV_REG_READ(ETH_ACCESS_PROTECT_REG(portNo));
/* Clear protection window field */
protReg &= ~(ETH_PROT_WIN_MASK(winNum));
/* Set new protection field value */
protReg |= (access << (ETH_PROT_WIN_OFFS(winNum)));
/* Write protection register back */
MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(portNo), protReg);
return MV_OK;
}
/*******************************************************************************
* ethWinOverlapDetect - Detect ETH address windows overlapping
*
* DESCRIPTION:
* An unpredicted behaviur is expected in case ETH address decode
* windows overlapps.
* This function detects ETH address decode windows overlapping of a
* specified window. The function does not check the window itself for
* overlapping. The function also skipps disabled address decode windows.
*
* INPUT:
* winNum - address decode window number.
* pAddrDecWin - An address decode window struct.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_TRUE if the given address window overlap current address
* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data
* from registers.
*
*******************************************************************************/
static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin)
{
MV_U32 baseAddrEnableReg;
MV_U32 winNumIndex;
MV_ETH_DEC_WIN addrDecWin;
/* Read base address enable register. Do not check disabled windows */
baseAddrEnableReg = MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port));
for (winNumIndex=0; winNumIndex<ETH_MAX_DECODE_WIN; winNumIndex++)
{
/* Do not check window itself */
if (winNumIndex == winNum)
{
continue;
}
/* Do not check disabled windows */
if (baseAddrEnableReg & (1 << winNumIndex))
{
continue;
}
/* Get window parameters */
if (MV_OK != mvEthWinGet(port, winNumIndex, &addrDecWin))
{
mvOsPrintf("ethWinOverlapDetect: ERR. TargetWinGet failed\n");
return MV_ERROR;
}
/*
mvOsPrintf("ethWinOverlapDetect:\n
winNumIndex =%d baseHigh =0x%x baseLow=0x%x size=0x%x enable=0x%x\n",
winNumIndex,
addrDecWin.addrWin.baseHigh,
addrDecWin.addrWin.baseLow,
addrDecWin.addrWin.size,
addrDecWin.enable);
*/
if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin)))
{
return MV_TRUE;
}
}
return MV_FALSE;
}
/*******************************************************************************
* mvEthAddrDecShow - Print the Etherent address decode map.
*
* DESCRIPTION:
* This function print the Etherent address decode map.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
void mvEthPortAddrDecShow(int port)
{
MV_ETH_DEC_WIN win;
int i;
mvOsOutput( "\n" );
mvOsOutput( "ETH %d:\n", port );
mvOsOutput( "----\n" );
for( i = 0; i < ETH_MAX_DECODE_WIN; i++ )
{
memset( &win, 0, sizeof(ETH_MAX_DECODE_WIN) );
mvOsOutput( "win%d - ", i );
if( mvEthWinGet(port, i, &win ) == MV_OK )
{
if( win.enable )
{
mvOsOutput( "%s base %08x, ",
mvCtrlTargetNameGet(win.target), win.addrWin.baseLow );
mvOsOutput( "...." );
mvSizePrint( win.addrWin.size );
mvOsOutput( "\n" );
}
else
mvOsOutput( "disable\n" );
}
}
return;
}
void mvEthAddrDecShow(void)
{
int port;
for(port=0; port<mvCtrlEthMaxPortGet(); port++)
{
if (MV_FALSE == mvCtrlPwrClckGet(ETH_GIG_UNIT_ID, port)) continue;
mvEthPortAddrDecShow(port);
}
}
void mvEthInit(void)
{
MV_U32 port;
/* Power down all existing ports */
for(port=0; port<mvCtrlEthMaxPortGet(); port++)
{
if (MV_FALSE == mvCtrlPwrClckGet(ETH_GIG_UNIT_ID, port))
continue;
mvEthPortPowerUp(port);
mvEthWinInit(port);
}
mvEthHalInit();
}

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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvSysGbeh
#define __INCmvSysGbeh
#include "mvCommon.h"
#include "eth/mvEth.h"
#include "ctrlEnv/mvCtrlEnvSpec.h"
#include "ctrlEnv/sys/mvCpuIf.h"
#define ETH_WIN_BASE_REG(port, win) (MV_ETH_REG_BASE(port) + 0x200 + ((win)<<3))
#define ETH_WIN_SIZE_REG(port, win) (MV_ETH_REG_BASE(port) + 0x204 + ((win)<<3))
#define ETH_WIN_REMAP_REG(port, win) (MV_ETH_REG_BASE(port) + 0x280 + ((win)<<2))
#define ETH_BASE_ADDR_ENABLE_REG(port) (MV_ETH_REG_BASE(port) + 0x290)
#define ETH_ACCESS_PROTECT_REG(port) (MV_ETH_REG_BASE(port) + 0x294)
/**** Address decode parameters ****/
/* Ethernet Base Address Register bits */
#define ETH_MAX_DECODE_WIN 6
#define ETH_MAX_HIGH_ADDR_REMAP_WIN 4
/* Ethernet Port Access Protect (EPAP) register */
/* The target associated with this window*/
#define ETH_WIN_TARGET_OFFS 0
#define ETH_WIN_TARGET_MASK (0xf << ETH_WIN_TARGET_OFFS)
/* The target attributes Associated with window */
#define ETH_WIN_ATTR_OFFS 8
#define ETH_WIN_ATTR_MASK (0xff << ETH_WIN_ATTR_OFFS)
/* Ethernet Port Access Protect Register (EPAPR) */
#define ETH_PROT_NO_ACCESS NO_ACCESS_ALLOWED
#define ETH_PROT_READ_ONLY READ_ONLY
#define ETH_PROT_FULL_ACCESS FULL_ACCESS
#define ETH_PROT_WIN_OFFS(winNum) (2 * (winNum))
#define ETH_PROT_WIN_MASK(winNum) (0x3 << ETH_PROT_WIN_OFFS(winNum))
MV_STATUS mvEthWinInit (int port);
MV_STATUS mvEthWinEnable(int port, MV_U32 winNum, MV_BOOL enable);
MV_U32 mvEthWinTargetGet(int port, MV_TARGET target);
MV_STATUS mvEthProtWinSet(MV_U32 portNo, MV_U32 winNum, MV_ACCESS_RIGHTS
access);
void mvEthPortAddrDecShow(int port);
MV_VOID mvEthAddrDecShow(MV_VOID);
void mvEthInit(void);
#endif

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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCSysPEXH
#define __INCSysPEXH
#include "mvCommon.h"
#include "ctrlEnv/sys/mvCpuIf.h"
#include "ctrlEnv/mvCtrlEnvLib.h"
#include "ctrlEnv/mvCtrlEnvAddrDec.h"
/* 4KB granularity */
#define MINIMUM_WINDOW_SIZE 0x1000
#define MINIMUM_BAR_SIZE 0x1000
#define MINIMUM_BAR_SIZE_MASK 0xFFFFF000
#define BAR_SIZE_OFFS 12
#define BAR_SIZE_MASK (0xFFFFF << BAR_SIZE_OFFS)
#define MV_PEX_WIN_DEFAULT 6
#define MV_PEX_WIN_EXP_ROM 7
#define PEX_MAX_TARGET_WIN 8
#define PEX_MAX_BARS 3
#define PEX_INTER_REGS_BAR 0
#define PEX_DRAM_BAR 1
#define PEX_DEVICE_BAR 2
/*************************************/
/* PCI Express BAR Control Registers */
/*************************************/
#define PEX_BAR_CTRL_REG(pexIf,bar) (0x41804 + (bar-1)*4- (pexIf)*0x10000)
#define PEX_EXP_ROM_BAR_CTRL_REG(pexIf) (0x4180C - (pexIf)*0x10000)
/* PCI Express BAR Control Register */
/* PEX_BAR_CTRL_REG (PXBCR) */
#define PXBCR_BAR_EN BIT0
#define PXBCR_BAR_SIZE_OFFS 16
#define PXBCR_BAR_SIZE_MASK (0xffff << PXBCR_BAR_SIZE_OFFS)
#define PXBCR_BAR_SIZE_ALIGNMENT 0x10000
/* PCI Express Expansion ROM BAR Control Register */
/* PEX_EXP_ROM_BAR_CTRL_REG (PXERBCR) */
#define PXERBCR_EXPROM_EN BIT0
#define PXERBCR_EXPROMSZ_OFFS 19
#define PXERBCR_EXPROMSZ_MASK (0xf << PXERBCR_EXPROMSZ_OFFS)
#define PXERBCR_EXPROMSZ_512KB (0x0 << PXERBCR_EXPROMSZ_OFFS)
#define PXERBCR_EXPROMSZ_1024KB (0x1 << PXERBCR_EXPROMSZ_OFFS)
#define PXERBCR_EXPROMSZ_2048KB (0x3 << PXERBCR_EXPROMSZ_OFFS)
#define PXERBCR_EXPROMSZ_4096KB (0x7 << PXERBCR_EXPROMSZ_OFFS)
/************************************************/
/* PCI Express Address Window Control Registers */
/************************************************/
#define PEX_WIN0_3_CTRL_REG(pexIf,winNum) \
(0x41820 + (winNum) * 0x10 - (pexIf) * 0x10000)
#define PEX_WIN0_3_BASE_REG(pexIf,winNum) \
(0x41824 + (winNum) * 0x10 - (pexIf) * 0x10000)
#define PEX_WIN0_3_REMAP_REG(pexIf,winNum) \
(0x4182C + (winNum) * 0x10 - (pexIf) * 0x10000)
#define PEX_WIN4_5_CTRL_REG(pexIf,winNum) \
(0x41860 + (winNum - 4) * 0x20 - (pexIf) * 0x10000)
#define PEX_WIN4_5_BASE_REG(pexIf,winNum) \
(0x41864 + (winNum - 4) * 0x20 - (pexIf) * 0x10000)
#define PEX_WIN4_5_REMAP_REG(pexIf,winNum) \
(0x4186C + (winNum - 4) * 0x20 - (pexIf) * 0x10000)
#define PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum) \
(0x41870 + (winNum - 4) * 0x20 - (pexIf) * 0x10000)
#define PEX_WIN_DEFAULT_CTRL_REG(pexIf) (0x418B0 - (pexIf) * 0x10000)
#define PEX_WIN_EXP_ROM_CTRL_REG(pexIf) (0x418C0 - (pexIf) * 0x10000)
#define PEX_WIN_EXP_ROM_REMAP_REG(pexIf) (0x418C4 - (pexIf) * 0x10000)
/* PCI Express Window Control Register */
/* PEX_WIN_CTRL_REG (PXWCR) */
#define PXWCR_WIN_EN BIT0 /* Window Enable.*/
#define PXWCR_WIN_BAR_MAP_OFFS 1 /* Mapping to BAR.*/
#define PXWCR_WIN_BAR_MAP_MASK BIT1
#define PXWCR_WIN_BAR_MAP_BAR1 (0 << PXWCR_WIN_BAR_MAP_OFFS)
#define PXWCR_WIN_BAR_MAP_BAR2 (1 << PXWCR_WIN_BAR_MAP_OFFS)
#define PXWCR_TARGET_OFFS 4 /*Unit ID */
#define PXWCR_TARGET_MASK (0xf << PXWCR_TARGET_OFFS)
#define PXWCR_ATTRIB_OFFS 8 /* target attributes */
#define PXWCR_ATTRIB_MASK (0xff << PXWCR_ATTRIB_OFFS)
#define PXWCR_SIZE_OFFS 16 /* size */
#define PXWCR_SIZE_MASK (0xffff << PXWCR_SIZE_OFFS)
#define PXWCR_SIZE_ALIGNMENT 0x10000
/* PCI Express Window Base Register */
/* PEX_WIN_BASE_REG (PXWBR)*/
#define PXWBR_BASE_OFFS 16 /* address[31:16] */
#define PXWBR_BASE_MASK (0xffff << PXWBR_BASE_OFFS)
#define PXWBR_BASE_ALIGNMENT 0x10000
/* PCI Express Window Remap Register */
/* PEX_WIN_REMAP_REG (PXWRR)*/
#define PXWRR_REMAP_EN BIT0
#define PXWRR_REMAP_OFFS 16
#define PXWRR_REMAP_MASK (0xffff << PXWRR_REMAP_OFFS)
#define PXWRR_REMAP_ALIGNMENT 0x10000
/* PCI Express Window Remap (High) Register */
/* PEX_WIN_REMAP_HIGH_REG (PXWRHR)*/
#define PXWRHR_REMAP_HIGH_OFFS 0
#define PXWRHR_REMAP_HIGH_MASK (0xffffffff << PXWRHR_REMAP_HIGH_OFFS)
/* PCI Express Default Window Control Register */
/* PEX_WIN_DEFAULT_CTRL_REG (PXWDCR) */
#define PXWDCR_TARGET_OFFS 4 /*Unit ID */
#define PXWDCR_TARGET_MASK (0xf << PXWDCR_TARGET_OFFS)
#define PXWDCR_ATTRIB_OFFS 8 /* target attributes */
#define PXWDCR_ATTRIB_MASK (0xff << PXWDCR_ATTRIB_OFFS)
/* PCI Express Expansion ROM Window Control Register */
/* PEX_WIN_EXP_ROM_CTRL_REG (PXWERCR)*/
#define PXWERCR_TARGET_OFFS 4 /*Unit ID */
#define PXWERCR_TARGET_MASK (0xf << PXWERCR_TARGET_OFFS)
#define PXWERCR_ATTRIB_OFFS 8 /* target attributes */
#define PXWERCR_ATTRIB_MASK (0xff << PXWERCR_ATTRIB_OFFS)
/* PCI Express Expansion ROM Window Remap Register */
/* PEX_WIN_EXP_ROM_REMAP_REG (PXWERRR)*/
#define PXWERRR_REMAP_EN BIT0
#define PXWERRR_REMAP_OFFS 16
#define PXWERRR_REMAP_MASK (0xffff << PXWERRR_REMAP_OFFS)
#define PXWERRR_REMAP_ALIGNMENT 0x10000
/*PEX_MEMORY_BAR_BASE_ADDR(barNum) (PXMBBA)*/
/* PCI Express BAR0 Internal Register*/
/*PEX BAR0_INTER_REG (PXBIR)*/
#define PXBIR_IOSPACE BIT0 /* Memory Space Indicator */
#define PXBIR_TYPE_OFFS 1 /* BAR Type/Init Val. */
#define PXBIR_TYPE_MASK (0x3 << PXBIR_TYPE_OFFS)
#define PXBIR_TYPE_32BIT_ADDR (0x0 << PXBIR_TYPE_OFFS)
#define PXBIR_TYPE_64BIT_ADDR (0x2 << PXBIR_TYPE_OFFS)
#define PXBIR_PREFETCH_EN BIT3 /* Prefetch Enable */
#define PXBIR_BASE_OFFS 20 /* Base address. Address bits [31:20] */
#define PXBIR_BASE_MASK (0xfff << PXBIR_BASE_OFFS)
#define PXBIR_BASE_ALIGNMET (1 << PXBIR_BASE_OFFS)
/* PCI Express BAR0 Internal (High) Register*/
/*PEX BAR0_INTER_REG_HIGH (PXBIRH)*/
#define PXBIRH_BASE_OFFS 0 /* Base address. Bits [63:32] */
#define PXBIRH_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS)
#define PEX_BAR_DEFAULT_ATTRIB 0xc /* Memory - Prefetch - 64 bit address */
#define PEX_BAR0_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB
#define PEX_BAR1_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB
#define PEX_BAR2_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB
/* PCI Express BAR1 Register */
/* PCI Express BAR2 Register*/
/*PEX BAR1_REG (PXBR)*/
/*PEX BAR2_REG (PXBR)*/
#define PXBR_IOSPACE BIT0 /* Memory Space Indicator */
#define PXBR_TYPE_OFFS 1 /* BAR Type/Init Val. */
#define PXBR_TYPE_MASK (0x3 << PXBR_TYPE_OFFS)
#define PXBR_TYPE_32BIT_ADDR (0x0 << PXBR_TYPE_OFFS)
#define PXBR_TYPE_64BIT_ADDR (0x2 << PXBR_TYPE_OFFS)
#define PXBR_PREFETCH_EN BIT3 /* Prefetch Enable */
#define PXBR_BASE_OFFS 16 /* Base address. Address bits [31:16] */
#define PXBR_BASE_MASK (0xffff << PXBR_BASE_OFFS)
#define PXBR_BASE_ALIGNMET (1 << PXBR_BASE_OFFS)
/* PCI Express BAR1 (High) Register*/
/* PCI Express BAR2 (High) Register*/
/*PEX BAR1_REG_HIGH (PXBRH)*/
/*PEX BAR2_REG_HIGH (PXBRH)*/
#define PXBRH_BASE_OFFS 0 /* Base address. Address bits [63:32] */
#define PXBRH_BASE_MASK (0xffffffff << PXBRH_BASE_OFFS)
/* PCI Express Expansion ROM BAR Register*/
/*PEX_EXPANSION_ROM_BASE_ADDR_REG (PXERBAR)*/
#define PXERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */
#define PXERBAR_BASE_512K_OFFS 19 /* Expansion ROM Base Address */
#define PXERBAR_BASE_512K_MASK (0x1fff << PXERBAR_BASE_512K_OFFS)
#define PXERBAR_BASE_1MB_OFFS 20 /* Expansion ROM Base Address */
#define PXERBAR_BASE_1MB_MASK (0xfff << PXERBAR_BASE_1MB_OFFS)
#define PXERBAR_BASE_2MB_OFFS 21 /* Expansion ROM Base Address */
#define PXERBAR_BASE_2MB_MASK (0x7ff << PXERBAR_BASE_2MB_OFFS)
#define PXERBAR_BASE_4MB_OFFS 22 /* Expansion ROM Base Address */
#define PXERBAR_BASE_4MB_MASK (0x3ff << PXERBAR_BASE_4MB_OFFS)
/* PEX Bar attributes */
typedef struct _mvPexBar
{
MV_ADDR_WIN addrWin; /* An address window*/
MV_BOOL enable; /* Address decode window is enabled/disabled */
}MV_PEX_BAR;
/* PEX Remap Window attributes */
typedef struct _mvPexRemapWin
{
MV_ADDR_WIN addrWin; /* An address window*/
MV_BOOL enable; /* Address decode window is enabled/disabled */
}MV_PEX_REMAP_WIN;
/* PEX Remap Window attributes */
typedef struct _mvPexDecWin
{
MV_TARGET target;
MV_ADDR_WIN addrWin; /* An address window*/
MV_U32 targetBar;
MV_U8 attrib; /* chip select attributes */
MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */
MV_BOOL enable; /* Address decode window is enabled/disabled */
}MV_PEX_DEC_WIN;
/* Global Functions prototypes */
/* mvPexHalInit - Initialize PEX interfaces*/
MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType);
/* mvPexTargetWinSet - Set PEX to peripheral target address window BAR*/
MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum,
MV_PEX_DEC_WIN *pAddrDecWin);
/* mvPexTargetWinGet - Get PEX to peripheral target address window*/
MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum,
MV_PEX_DEC_WIN *pAddrDecWin);
/* mvPexTargetWinEnable - Enable/disable a PEX BAR window*/
MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable);
/* mvPexTargetWinRemap - Set PEX to target address window remap.*/
MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum,
MV_PEX_REMAP_WIN *pAddrWin);
/* mvPexTargetWinRemapEnable -enable\disable a PEX Window remap.*/
MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum,
MV_BOOL enable);
/* mvPexBarSet - Set PEX bar address and size */
MV_STATUS mvPexBarSet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin);
/* mvPexBarGet - Get PEX bar address and size */
MV_STATUS mvPexBarGet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin);
/* mvPexBarEnable - enable\disable a PEX bar*/
MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable);
/* mvPexAddrDecShow - Display address decode windows attributes */
MV_VOID mvPexAddrDecShow(MV_VOID);
#endif

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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "mvTypes.h"
#include "mvCommon.h"
#include "mvOs.h"
#include "ctrlEnv/mvCtrlEnvLib.h"
#include "cpu/mvCpu.h"
#include "ctrlEnv/sys/mvCpuIf.h"
#include "sata/CoreDriver/mvRegs.h"
#include "ctrlEnv/sys/mvSysSata.h"
MV_TARGET sataAddrDecPrioTab[] =
{
#if defined(MV_INCLUDE_SDRAM_CS0)
SDRAM_CS0,
#endif
#if defined(MV_INCLUDE_SDRAM_CS1)
SDRAM_CS1,
#endif
#if defined(MV_INCLUDE_SDRAM_CS2)
SDRAM_CS2,
#endif
#if defined(MV_INCLUDE_SDRAM_CS3)
SDRAM_CS3,
#endif
#if defined(MV_INCLUDE_PEX)
PEX0_MEM,
#endif
TBL_TERM
};
/*******************************************************************************
* sataWinOverlapDetect - Detect SATA address windows overlapping
*
* DESCRIPTION:
* An unpredicted behaviur is expected in case SATA address decode
* windows overlapps.
* This function detects SATA address decode windows overlapping of a
* specified window. The function does not check the window itself for
* overlapping. The function also skipps disabled address decode windows.
*
* INPUT:
* winNum - address decode window number.
* pAddrDecWin - An address decode window struct.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_TRUE if the given address window overlap current address
* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data
* from registers.
*
*******************************************************************************/
static MV_STATUS sataWinOverlapDetect(int dev, MV_U32 winNum,
MV_ADDR_WIN *pAddrWin)
{
MV_U32 winNumIndex;
MV_SATA_DEC_WIN addrDecWin;
for(winNumIndex=0; winNumIndex<MV_SATA_MAX_ADDR_DECODE_WIN; winNumIndex++)
{
/* Do not check window itself */
if (winNumIndex == winNum)
{
continue;
}
/* Get window parameters */
if (MV_OK != mvSataWinGet(dev, winNumIndex, &addrDecWin))
{
mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__);
return MV_ERROR;
}
/* Do not check disabled windows */
if(addrDecWin.enable == MV_FALSE)
{
continue;
}
if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin)))
{
return MV_TRUE;
}
}
return MV_FALSE;
}
/*******************************************************************************
* mvSataWinSet - Set SATA target address window
*
* DESCRIPTION:
* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)
* address window, also known as address decode window.
* After setting this target window, the SATA will be able to access the
* target within the address window.
*
* INPUT:
* winNum - SATA target address decode window number.
* pAddrDecWin - SATA target window data structure.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_ERROR if address window overlapps with other address decode windows.
* MV_BAD_PARAM if base address is invalid parameter or target is
* unknown.
*
*******************************************************************************/
MV_STATUS mvSataWinSet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin)
{
MV_TARGET_ATTRIB targetAttribs;
MV_DEC_REGS decRegs;
/* Parameter checking */
if (winNum >= MV_SATA_MAX_ADDR_DECODE_WIN)
{
mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum);
return MV_BAD_PARAM;
}
/* Check if the requested window overlapps with current windows */
if (MV_TRUE == sataWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin))
{
mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum);
return MV_ERROR;
}
/* check if address is aligned to the size */
if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size))
{
mvOsPrintf("mvSataWinSet:Error setting SATA window %d to "\
"target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n",
winNum,
mvCtrlTargetNameGet(pAddrDecWin->target),
pAddrDecWin->addrWin.baseLow,
pAddrDecWin->addrWin.size);
return MV_ERROR;
}
decRegs.baseReg = 0;
decRegs.sizeReg = 0;
if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs))
{
mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__);
return MV_ERROR;
}
mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs);
/* set attributes */
decRegs.sizeReg &= ~MV_SATA_WIN_ATTR_MASK;
decRegs.sizeReg |= (targetAttribs.attrib << MV_SATA_WIN_ATTR_OFFSET);
/* set target ID */
decRegs.sizeReg &= ~MV_SATA_WIN_TARGET_MASK;
decRegs.sizeReg |= (targetAttribs.targetId << MV_SATA_WIN_TARGET_OFFSET);
if (pAddrDecWin->enable == MV_TRUE)
{
decRegs.sizeReg |= MV_SATA_WIN_ENABLE_MASK;
}
else
{
decRegs.sizeReg &= ~MV_SATA_WIN_ENABLE_MASK;
}
MV_REG_WRITE( MV_SATA_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg);
MV_REG_WRITE( MV_SATA_WIN_BASE_REG(dev, winNum), decRegs.baseReg);
return MV_OK;
}
/*******************************************************************************
* mvSataWinGet - Get SATA peripheral target address window.
*
* DESCRIPTION:
* Get SATA peripheral target address window.
*
* INPUT:
* winNum - SATA target address decode window number.
*
* OUTPUT:
* pAddrDecWin - SATA target window data structure.
*
* RETURN:
* MV_ERROR if register parameters are invalid.
*
*******************************************************************************/
MV_STATUS mvSataWinGet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin)
{
MV_DEC_REGS decRegs;
MV_TARGET_ATTRIB targetAttrib;
/* Parameter checking */
if (winNum >= MV_SATA_MAX_ADDR_DECODE_WIN)
{
mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n",
__FUNCTION__, dev, winNum);
return MV_NOT_SUPPORTED;
}
decRegs.baseReg = MV_REG_READ( MV_SATA_WIN_BASE_REG(dev, winNum) );
decRegs.sizeReg = MV_REG_READ( MV_SATA_WIN_CTRL_REG(dev, winNum) );
if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) )
{
mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__);
return MV_ERROR;
}
/* attrib and targetId */
targetAttrib.attrib = (decRegs.sizeReg & MV_SATA_WIN_ATTR_MASK) >>
MV_SATA_WIN_ATTR_OFFSET;
targetAttrib.targetId = (decRegs.sizeReg & MV_SATA_WIN_TARGET_MASK) >>
MV_SATA_WIN_TARGET_OFFSET;
pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
/* Check if window is enabled */
if(decRegs.sizeReg & MV_SATA_WIN_ENABLE_MASK)
{
pAddrDecWin->enable = MV_TRUE;
}
else
{
pAddrDecWin->enable = MV_FALSE;
}
return MV_OK;
}
/*******************************************************************************
* mvSataAddrDecShow - Print the SATA address decode map.
*
* DESCRIPTION:
* This function print the SATA address decode map.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_VOID mvSataAddrDecShow(MV_VOID)
{
MV_SATA_DEC_WIN win;
int i,j;
for( j = 0; j < MV_SATA_MAX_CHAN; j++ )
{
if (MV_FALSE == mvCtrlPwrClckGet(SATA_UNIT_ID, j))
return;
mvOsOutput( "\n" );
mvOsOutput( "SATA %d:\n", j );
mvOsOutput( "----\n" );
for( i = 0; i < MV_SATA_MAX_ADDR_DECODE_WIN; i++ )
{
memset( &win, 0, sizeof(MV_SATA_DEC_WIN) );
mvOsOutput( "win%d - ", i );
if( mvSataWinGet(j, i, &win ) == MV_OK )
{
if( win.enable )
{
mvOsOutput( "%s base %08x, ",
mvCtrlTargetNameGet(win.target), win.addrWin.baseLow );
mvOsOutput( "...." );
mvSizePrint( win.addrWin.size );
mvOsOutput( "\n" );
}
else
mvOsOutput( "disable\n" );
}
}
}
}
/*******************************************************************************
* mvSataWinInit - Initialize the integrated SATA target address window.
*
* DESCRIPTION:
* Initialize the SATA peripheral target address window.
*
* INPUT:
*
*
* OUTPUT:
*
*
* RETURN:
* MV_ERROR if register parameters are invalid.
*
*******************************************************************************/
MV_STATUS mvSataWinInit(MV_VOID)
{
int winNum;
MV_SATA_DEC_WIN sataWin;
MV_CPU_DEC_WIN cpuAddrDecWin;
MV_U32 status, winPrioIndex = 0;
/* Initiate Sata address decode */
/* First disable all address decode windows */
for(winNum = 0; winNum < MV_SATA_MAX_ADDR_DECODE_WIN; winNum++)
{
MV_U32 regVal = MV_REG_READ(MV_SATA_WIN_CTRL_REG(0, winNum));
regVal &= ~MV_SATA_WIN_ENABLE_MASK;
MV_REG_WRITE(MV_SATA_WIN_CTRL_REG(0, winNum), regVal);
}
winNum = 0;
while( (sataAddrDecPrioTab[winPrioIndex] != TBL_TERM) &&
(winNum < MV_SATA_MAX_ADDR_DECODE_WIN) )
{
/* first get attributes from CPU If */
status = mvCpuIfTargetWinGet(sataAddrDecPrioTab[winPrioIndex],
&cpuAddrDecWin);
if(MV_NO_SUCH == status)
{
winPrioIndex++;
continue;
}
if (MV_OK != status)
{
mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__);
return MV_ERROR;
}
if (cpuAddrDecWin.enable == MV_TRUE)
{
sataWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;
sataWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow;
sataWin.addrWin.size = cpuAddrDecWin.addrWin.size;
sataWin.enable = MV_TRUE;
sataWin.target = sataAddrDecPrioTab[winPrioIndex];
if(MV_OK != mvSataWinSet(0/*dev*/, winNum, &sataWin))
{
return MV_ERROR;
}
winNum++;
}
winPrioIndex++;
}
return MV_OK;
}

128
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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCMVSysSataAddrDech
#define __INCMVSysSataAddrDech
#include "mvCommon.h"
#include "ctrlEnv/mvCtrlEnvLib.h"
#include "ctrlEnv/sys/mvCpuIf.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct _mvSataDecWin
{
MV_TARGET target;
MV_ADDR_WIN addrWin; /* An address window*/
MV_BOOL enable; /* Address decode window is enabled/disabled */
} MV_SATA_DEC_WIN;
#define MV_SATA_MAX_ADDR_DECODE_WIN 4
#define MV_SATA_WIN_CTRL_REG(dev, win) (SATA_REG_BASE + 0x30 + ((win)<<4))
#define MV_SATA_WIN_BASE_REG(dev, win) (SATA_REG_BASE + 0x34 + ((win)<<4))
/* BITs in Bridge Interrupt Cause and Mask registers */
#define MV_SATA_ADDR_DECODE_ERROR_BIT 0
#define MV_SATA_ADDR_DECODE_ERROR_MASK (1<<MV_SATA_ADDR_DECODE_ERROR_BIT)
/* BITs in Windows 0-3 Control and Base Registers */
#define MV_SATA_WIN_ENABLE_BIT 0
#define MV_SATA_WIN_ENABLE_MASK (1<<MV_SATA_WIN_ENABLE_BIT)
#define MV_SATA_WIN_TARGET_OFFSET 4
#define MV_SATA_WIN_TARGET_MASK (0xF<<MV_SATA_WIN_TARGET_OFFSET)
#define MV_SATA_WIN_ATTR_OFFSET 8
#define MV_SATA_WIN_ATTR_MASK (0xFF<<MV_SATA_WIN_ATTR_OFFSET)
#define MV_SATA_WIN_SIZE_OFFSET 16
#define MV_SATA_WIN_SIZE_MASK (0xFFFF<<MV_SATA_WIN_SIZE_OFFSET)
#define MV_SATA_WIN_BASE_OFFSET 16
#define MV_SATA_WIN_BASE_MASK (0xFFFF<<MV_SATA_WIN_BASE_OFFSET)
MV_STATUS mvSataWinGet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin);
MV_STATUS mvSataWinSet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin);
MV_STATUS mvSataWinByTargetGet(MV_TARGET target, MV_SATA_DEC_WIN *pAddrDecWin);
MV_STATUS mvSataWinInit(MV_VOID);
MV_VOID mvSataAddrDecShow(MV_VOID);
#ifdef __cplusplus
}
#endif
#endif

427
target/linux/generic-2.6/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.c Normal file
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@ -0,0 +1,427 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "mvTypes.h"
#include "mvCommon.h"
#include "mvOs.h"
#include "ctrlEnv/mvCtrlEnvLib.h"
#include "cpu/mvCpu.h"
#include "ctrlEnv/sys/mvCpuIf.h"
#include "mvRegs.h"
#include "ctrlEnv/sys/mvSysSdmmc.h"
MV_TARGET sdmmcAddrDecPrioTab[] =
{
#if defined(MV_INCLUDE_SDRAM_CS0)
SDRAM_CS0,
#endif
#if defined(MV_INCLUDE_SDRAM_CS1)
SDRAM_CS1,
#endif
#if defined(MV_INCLUDE_SDRAM_CS2)
SDRAM_CS2,
#endif
#if defined(MV_INCLUDE_SDRAM_CS3)
SDRAM_CS3,
#endif
#if defined(MV_INCLUDE_PEX)
PEX0_MEM,
#endif
TBL_TERM
};
/*******************************************************************************
* sdmmcWinOverlapDetect - Detect SDMMC address windows overlapping
*
* DESCRIPTION:
* An unpredicted behaviur is expected in case SDMMC address decode
* windows overlapps.
* This function detects SDMMC address decode windows overlapping of a
* specified window. The function does not check the window itself for
* overlapping. The function also skipps disabled address decode windows.
*
* INPUT:
* winNum - address decode window number.
* pAddrDecWin - An address decode window struct.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_TRUE if the given address window overlap current address
* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data
* from registers.
*
*******************************************************************************/
static MV_STATUS sdmmcWinOverlapDetect(int dev, MV_U32 winNum,
MV_ADDR_WIN *pAddrWin)
{
MV_U32 winNumIndex;
MV_SDMMC_DEC_WIN addrDecWin;
for(winNumIndex=0; winNumIndex<MV_SDMMC_MAX_ADDR_DECODE_WIN; winNumIndex++)
{
/* Do not check window itself */
if (winNumIndex == winNum)
{
continue;
}
/* Get window parameters */
if (MV_OK != mvSdmmcWinGet(dev, winNumIndex, &addrDecWin))
{
mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__);
return MV_ERROR;
}
/* Do not check disabled windows */
if(addrDecWin.enable == MV_FALSE)
{
continue;
}
if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin)))
{
return MV_TRUE;
}
}
return MV_FALSE;
}
/*******************************************************************************
* mvSdmmcWinSet - Set SDMMC target address window
*
* DESCRIPTION:
* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)
* address window, also known as address decode window.
* After setting this target window, the SDMMC will be able to access the
* target within the address window.
*
* INPUT:
* winNum - SDMMC target address decode window number.
* pAddrDecWin - SDMMC target window data structure.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_ERROR if address window overlapps with other address decode windows.
* MV_BAD_PARAM if base address is invalid parameter or target is
* unknown.
*
*******************************************************************************/
MV_STATUS mvSdmmcWinSet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin)
{
MV_TARGET_ATTRIB targetAttribs;
MV_DEC_REGS decRegs;
/* Parameter checking */
if (winNum >= MV_SDMMC_MAX_ADDR_DECODE_WIN)
{
mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum);
return MV_BAD_PARAM;
}
/* Check if the requested window overlapps with current windows */
if (MV_TRUE == sdmmcWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin))
{
mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum);
return MV_ERROR;
}
/* check if address is aligned to the size */
if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size))
{
mvOsPrintf("mvSdmmcWinSet:Error setting SDMMC window %d to "\
"target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n",
winNum,
mvCtrlTargetNameGet(pAddrDecWin->target),
pAddrDecWin->addrWin.baseLow,
pAddrDecWin->addrWin.size);
return MV_ERROR;
}
decRegs.baseReg = 0;
decRegs.sizeReg = 0;
if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs))
{
mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__);
return MV_ERROR;
}
mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs);
/* set attributes */
decRegs.sizeReg &= ~MV_SDMMC_WIN_ATTR_MASK;
decRegs.sizeReg |= (targetAttribs.attrib << MV_SDMMC_WIN_ATTR_OFFSET);
/* set target ID */
decRegs.sizeReg &= ~MV_SDMMC_WIN_TARGET_MASK;
decRegs.sizeReg |= (targetAttribs.targetId << MV_SDMMC_WIN_TARGET_OFFSET);
if (pAddrDecWin->enable == MV_TRUE)
{
decRegs.sizeReg |= MV_SDMMC_WIN_ENABLE_MASK;
}
else
{
decRegs.sizeReg &= ~MV_SDMMC_WIN_ENABLE_MASK;
}
MV_REG_WRITE( MV_SDMMC_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg);
MV_REG_WRITE( MV_SDMMC_WIN_BASE_REG(dev, winNum), decRegs.baseReg);
return MV_OK;
}
/*******************************************************************************
* mvSdmmcWinGet - Get SDMMC peripheral target address window.
*
* DESCRIPTION:
* Get SDMMC peripheral target address window.
*
* INPUT:
* winNum - SDMMC target address decode window number.
*d
* OUTPUT:
* pAddrDecWin - SDMMC target window data structure.
*
* RETURN:
* MV_ERROR if register parameters are invalid.
*
*******************************************************************************/
MV_STATUS mvSdmmcWinGet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin)
{
MV_DEC_REGS decRegs;
MV_TARGET_ATTRIB targetAttrib;
/* Parameter checking */
if (winNum >= MV_SDMMC_MAX_ADDR_DECODE_WIN)
{
mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n",
__FUNCTION__, dev, winNum);
return MV_NOT_SUPPORTED;
}
decRegs.baseReg = MV_REG_READ( MV_SDMMC_WIN_BASE_REG(dev, winNum) );
decRegs.sizeReg = MV_REG_READ( MV_SDMMC_WIN_CTRL_REG(dev, winNum) );
if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) )
{
mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__);
return MV_ERROR;
}
/* attrib and targetId */
targetAttrib.attrib = (decRegs.sizeReg & MV_SDMMC_WIN_ATTR_MASK) >>
MV_SDMMC_WIN_ATTR_OFFSET;
targetAttrib.targetId = (decRegs.sizeReg & MV_SDMMC_WIN_TARGET_MASK) >>
MV_SDMMC_WIN_TARGET_OFFSET;
pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
/* Check if window is enabled */
if(decRegs.sizeReg & MV_SDMMC_WIN_ENABLE_MASK)
{
pAddrDecWin->enable = MV_TRUE;
}
else
{
pAddrDecWin->enable = MV_FALSE;
}
return MV_OK;
}
/*******************************************************************************
* mvSdmmcAddrDecShow - Print the SDMMC address decode map.
*
* DESCRIPTION:
* This function print the SDMMC address decode map.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_VOID mvSdmmcAddrDecShow(MV_VOID)
{
MV_SDMMC_DEC_WIN win;
int i,j=0;
if (MV_FALSE == mvCtrlPwrClckGet(SDIO_UNIT_ID, 0))
return;
mvOsOutput( "\n" );
mvOsOutput( "SDMMC %d:\n", j );
mvOsOutput( "----\n" );
for( i = 0; i < MV_SDMMC_MAX_ADDR_DECODE_WIN; i++ )
{
memset( &win, 0, sizeof(MV_SDMMC_DEC_WIN) );
mvOsOutput( "win%d - ", i );
if( mvSdmmcWinGet(j, i, &win ) == MV_OK )
{
if( win.enable )
{
mvOsOutput( "%s base %08x, ",
mvCtrlTargetNameGet(win.target), win.addrWin.baseLow );
mvOsOutput( "...." );
mvSizePrint( win.addrWin.size );
mvOsOutput( "\n" );
}
else
mvOsOutput( "disable\n" );
}
}
}
/*******************************************************************************
* mvSdmmcWinInit - Initialize the integrated SDMMC target address window.
*
* DESCRIPTION:
* Initialize the SDMMC peripheral target address window.
*
* INPUT:
*
*
* OUTPUT:
*
*
* RETURN:
* MV_ERROR if register parameters are invalid.
*
*******************************************************************************/
MV_STATUS mvSdmmcWinInit(MV_VOID)
{
int winNum;
MV_SDMMC_DEC_WIN sdmmcWin;
MV_CPU_DEC_WIN cpuAddrDecWin;
MV_U32 status, winPrioIndex = 0;
/* Initiate Sdmmc address decode */
/* First disable all address decode windows */
for(winNum = 0; winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN; winNum++)
{
MV_U32 regVal = MV_REG_READ(MV_SDMMC_WIN_CTRL_REG(0, winNum));
regVal &= ~MV_SDMMC_WIN_ENABLE_MASK;
MV_REG_WRITE(MV_SDMMC_WIN_CTRL_REG(0, winNum), regVal);
}
winNum = 0;
while( (sdmmcAddrDecPrioTab[winPrioIndex] != TBL_TERM) &&
(winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN) )
{
/* first get attributes from CPU If */
status = mvCpuIfTargetWinGet(sdmmcAddrDecPrioTab[winPrioIndex],
&cpuAddrDecWin);
if(MV_NO_SUCH == status)
{
winPrioIndex++;
continue;
}
if (MV_OK != status)
{
mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__);
return MV_ERROR;
}
if (cpuAddrDecWin.enable == MV_TRUE)
{
sdmmcWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;
sdmmcWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow;
sdmmcWin.addrWin.size = cpuAddrDecWin.addrWin.size;
sdmmcWin.enable = MV_TRUE;
sdmmcWin.target = sdmmcAddrDecPrioTab[winPrioIndex];
if(MV_OK != mvSdmmcWinSet(0/*dev*/, winNum, &sdmmcWin))
{
return MV_ERROR;
}
winNum++;
}
winPrioIndex++;
}
return MV_OK;
}

125
target/linux/generic-2.6/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h Normal file
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@ -0,0 +1,125 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCMVSysSdmmcAddrDech
#define __INCMVSysSdmmcAddrDech
#include "mvCommon.h"
#include "ctrlEnv/mvCtrlEnvLib.h"
#include "ctrlEnv/sys/mvCpuIf.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct _mvSdmmcDecWin
{
MV_TARGET target;
MV_ADDR_WIN addrWin; /* An address window*/
MV_BOOL enable; /* Address decode window is enabled/disabled */
} MV_SDMMC_DEC_WIN;
#define MV_SDMMC_MAX_ADDR_DECODE_WIN 4
#define MV_SDMMC_WIN_CTRL_REG(dev, win) (MV_SDIO_REG_BASE + 0x108 + ((win)<<3))
#define MV_SDMMC_WIN_BASE_REG(dev, win) (MV_SDIO_REG_BASE + 0x10c + ((win)<<3))
/* BITs in Windows 0-3 Control and Base Registers */
#define MV_SDMMC_WIN_ENABLE_BIT 0
#define MV_SDMMC_WIN_ENABLE_MASK (1<<MV_SDMMC_WIN_ENABLE_BIT)
#define MV_SDMMC_WIN_TARGET_OFFSET 4
#define MV_SDMMC_WIN_TARGET_MASK (0xF<<MV_SDMMC_WIN_TARGET_OFFSET)
#define MV_SDMMC_WIN_ATTR_OFFSET 8
#define MV_SDMMC_WIN_ATTR_MASK (0xFF<<MV_SDMMC_WIN_ATTR_OFFSET)
#define MV_SDMMC_WIN_SIZE_OFFSET 16
#define MV_SDMMC_WIN_SIZE_MASK (0xFFFF<<MV_SDMMC_WIN_SIZE_OFFSET)
#define MV_SDMMC_WIN_BASE_OFFSET 16
#define MV_SDMMC_WIN_BASE_MASK (0xFFFF<<MV_SDMMC_WIN_BASE_OFFSET)
MV_STATUS mvSdmmcWinGet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin);
MV_STATUS mvSdmmcWinSet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin);
MV_STATUS mvSdmmcWinByTargetGet(MV_TARGET target, MV_SDMMC_DEC_WIN *pAddrDecWin);
MV_STATUS mvSdmmcWinInit(MV_VOID);
MV_VOID mvSdmmcAddrDecShow(MV_VOID);
#ifdef __cplusplus
}
#endif
#endif

462
target/linux/generic-2.6/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.c Normal file
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@ -0,0 +1,462 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "mvSysTdm.h"
/* defines */
#ifdef MV_DEBUG
#define DB(x) x
#else
#define DB(x)
#endif
static MV_TARGET tdmAddrDecPrioTap[] =
{
PEX0_MEM,
SDRAM_CS0,
SDRAM_CS1,
SDRAM_CS2,
SDRAM_CS3,
DEVICE_CS0,
DEVICE_CS1,
DEVICE_CS2,
DEV_BOOCS,
PEX0_IO,
TBL_TERM
};
static MV_STATUS tdmWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin);
/*******************************************************************************
* mvTdmWinInit - Initialize TDM address decode windows
*
* DESCRIPTION:
* This function initialize TDM window decode unit. It set the
* default address decode
* windows of the unit.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_ERROR if setting fail.
*******************************************************************************/
MV_STATUS mvTdmWinInit(void)
{
MV_U32 winNum;
MV_U32 winPrioIndex = 0;
MV_CPU_DEC_WIN cpuAddrDecWin;
MV_TDM_DEC_WIN tdmWin;
MV_STATUS status;
/*Disable all windows*/
for (winNum = 0; winNum < TDM_MBUS_MAX_WIN; winNum++)
{
mvTdmWinEnable(winNum, MV_FALSE);
}
for (winNum = 0; ((tdmAddrDecPrioTap[winPrioIndex] != TBL_TERM) &&
(winNum < TDM_MBUS_MAX_WIN)); )
{
status = mvCpuIfTargetWinGet(tdmAddrDecPrioTap[winPrioIndex],
&cpuAddrDecWin);
if (MV_NO_SUCH == status)
{
winPrioIndex++;
continue;
}
if (MV_OK != status)
{
mvOsPrintf("mvTdmInit: ERR. mvCpuIfTargetWinGet failed\n");
return MV_ERROR;
}
if (cpuAddrDecWin.enable == MV_TRUE)
{
tdmWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;
tdmWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow;
tdmWin.addrWin.size = cpuAddrDecWin.addrWin.size;
tdmWin.enable = MV_TRUE;
tdmWin.target = tdmAddrDecPrioTap[winPrioIndex];
if (MV_OK != mvTdmWinSet(winNum, &tdmWin))
{
return MV_ERROR;
}
winNum++;
}
winPrioIndex++;
}
return MV_OK;
}
/*******************************************************************************
* mvTdmWinSet - Set TDM target address window
*
* DESCRIPTION:
* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)
* address window, also known as address decode window.
* After setting this target window, the TDM will be able to access the
* target within the address window.
*
* INPUT:
* winNum - TDM to target address decode window number.
* pAddrDecWin - TDM target window data structure.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_ERROR if address window overlapps with other address decode windows.
* MV_BAD_PARAM if base address is invalid parameter or target is
* unknown.
*
*******************************************************************************/
MV_STATUS mvTdmWinSet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin)
{
MV_TARGET_ATTRIB targetAttribs;
MV_DEC_REGS decRegs;
MV_U32 ctrlReg = 0;
/* Parameter checking */
if (winNum >= TDM_MBUS_MAX_WIN)
{
mvOsPrintf("mvTdmWinSet: ERR. Invalid win num %d\n",winNum);
return MV_BAD_PARAM;
}
/* Check if the requested window overlapps with current windows */
if (MV_TRUE == tdmWinOverlapDetect(winNum, &pAddrDecWin->addrWin))
{
mvOsPrintf("mvTdmWinSet: ERR. Window %d overlap\n", winNum);
return MV_ERROR;
}
/* check if address is aligned to the size */
if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size))
{
mvOsPrintf("mvTdmWinSet: Error setting TDM window %d to "\
"target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n",
winNum,
mvCtrlTargetNameGet(pAddrDecWin->target),
pAddrDecWin->addrWin.baseLow,
pAddrDecWin->addrWin.size);
return MV_ERROR;
}
decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum));
decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS;
if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs))
{
mvOsPrintf("mvTdmWinSet: mvCtrlAddrDecToReg Failed\n");
return MV_ERROR;
}
mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs);
/* for the safe side we disable the window before writing the new
values */
mvTdmWinEnable(winNum, MV_FALSE);
ctrlReg |= (targetAttribs.attrib << TDM_WIN_ATTRIB_OFFS);
ctrlReg |= (targetAttribs.targetId << TDM_WIN_TARGET_OFFS);
ctrlReg |= (decRegs.sizeReg & TDM_WIN_SIZE_MASK);
/* Write to address base and control registers */
MV_REG_WRITE(TDM_WIN_BASE_REG(winNum), decRegs.baseReg);
MV_REG_WRITE(TDM_WIN_CTRL_REG(winNum), ctrlReg);
/* Enable address decode target window */
if (pAddrDecWin->enable == MV_TRUE)
{
mvTdmWinEnable(winNum, MV_TRUE);
}
return MV_OK;
}
/*******************************************************************************
* mvTdmWinGet - Get peripheral target address window.
*
* DESCRIPTION:
* Get TDM peripheral target address window.
*
* INPUT:
* winNum - TDM to target address decode window number.
*
* OUTPUT:
* pAddrDecWin - TDM target window data structure.
*
* RETURN:
* MV_ERROR if register parameters are invalid.
*
*******************************************************************************/
MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin)
{
MV_DEC_REGS decRegs;
MV_TARGET_ATTRIB targetAttrib;
/* Parameter checking */
if (winNum >= TDM_MBUS_MAX_WIN)
{
mvOsPrintf("mvTdmWinGet: ERR. Invalid winNum %d\n", winNum);
return MV_NOT_SUPPORTED;
}
decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum));
decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS;
if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin)))
{
mvOsPrintf("mvTdmWinGet: mvCtrlRegToAddrDec Failed \n");
return MV_ERROR;
}
/* attrib and targetId */
targetAttrib.attrib =
(MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ATTRIB_MASK) >> TDM_WIN_ATTRIB_OFFS;
targetAttrib.targetId =
(MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_TARGET_MASK) >> TDM_WIN_TARGET_OFFS;
pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
/* Check if window is enabled */
if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK)
{
pAddrDecWin->enable = MV_TRUE;
}
else
{
pAddrDecWin->enable = MV_FALSE;
}
return MV_OK;
}
/*******************************************************************************
* mvTdmWinEnable - Enable/disable a TDM to target address window
*
* DESCRIPTION:
* This function enable/disable a TDM to target address window.
* According to parameter 'enable' the routine will enable the
* window, thus enabling TDM accesses (before enabling the window it is
* tested for overlapping). Otherwise, the window will be disabled.
*
* INPUT:
* winNum - TDM to target address decode window number.
* enable - Enable/disable parameter.
*
* OUTPUT:
* N/A
*
* RETURN:
* MV_ERROR if decode window number was wrong or enabled window overlapps.
*
*******************************************************************************/
MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable)
{
MV_TDM_DEC_WIN addrDecWin;
if (MV_TRUE == enable)
{
if (winNum >= TDM_MBUS_MAX_WIN)
{
mvOsPrintf("mvTdmWinEnable:ERR. Invalid winNum%d\n",winNum);
return MV_ERROR;
}
/* First check for overlap with other enabled windows */
/* Get current window */
if (MV_OK != mvTdmWinGet(winNum, &addrDecWin))
{
mvOsPrintf("mvTdmWinEnable:ERR. targetWinGet fail\n");
return MV_ERROR;
}
/* Check for overlapping */
if (MV_FALSE == tdmWinOverlapDetect(winNum, &(addrDecWin.addrWin)))
{
/* No Overlap. Enable address decode target window */
MV_REG_BIT_SET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK);
}
else
{ /* Overlap detected */
mvOsPrintf("mvTdmWinEnable:ERR. Overlap detected\n");
return MV_ERROR;
}
}
else
{
MV_REG_BIT_RESET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK);
}
return MV_OK;
}
/*******************************************************************************
* tdmWinOverlapDetect - Detect TDM address windows overlapping
*
* DESCRIPTION:
* An unpredicted behaviour is expected in case TDM address decode
* windows overlapps.
* This function detects TDM address decode windows overlapping of a
* specified window. The function does not check the window itself for
* overlapping. The function also skipps disabled address decode windows.
*
* INPUT:
* winNum - address decode window number.
* pAddrDecWin - An address decode window struct.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_TRUE if the given address window overlap current address
* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data
* from registers.
*
*******************************************************************************/
static MV_STATUS tdmWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin)
{
MV_U32 winNumIndex;
MV_TDM_DEC_WIN addrDecWin;
for (winNumIndex = 0; winNumIndex < TDM_MBUS_MAX_WIN; winNumIndex++)
{
/* Do not check window itself */
if (winNumIndex == winNum)
{
continue;
}
/* Do not check disabled windows */
if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK)
{
/* Get window parameters */
if (MV_OK != mvTdmWinGet(winNumIndex, &addrDecWin))
{
DB(mvOsPrintf("dmaWinOverlapDetect: ERR. TargetWinGet failed\n"));
return MV_ERROR;
}
if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin)))
{
return MV_TRUE;
}
}
}
return MV_FALSE;
}
/*******************************************************************************
* mvTdmAddrDecShow - Print the TDM address decode map.
*
* DESCRIPTION:
* This function print the TDM address decode map.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_VOID mvTdmAddrDecShow(MV_VOID)
{
MV_TDM_DEC_WIN win;
int i;
mvOsOutput( "\n" );
mvOsOutput( "TDM:\n" );
mvOsOutput( "----\n" );
for( i = 0; i < TDM_MBUS_MAX_WIN; i++ )
{
memset( &win, 0, sizeof(MV_TDM_DEC_WIN) );
mvOsOutput( "win%d - ", i );
if (mvTdmWinGet(i, &win ) == MV_OK )
{
if( win.enable )
{
mvOsOutput( "%s base %08x, ",
mvCtrlTargetNameGet(win.target), win.addrWin.baseLow);
mvOsOutput( "...." );
mvSizePrint( win.addrWin.size );
mvOsOutput( "\n" );
}
else
mvOsOutput( "disable\n" );
}
}
}

106
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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvSysTdmh
#define __INCmvSysTdmh
#include "ctrlEnv/sys/mvCpuIf.h"
#include "ctrlEnv/mvCtrlEnvLib.h"
#include "ctrlEnv/mvCtrlEnvAddrDec.h"
typedef struct _mvTdmDecWin
{
MV_TARGET target;
MV_ADDR_WIN addrWin; /* An address window*/
MV_BOOL enable; /* Address decode window is enabled/disabled */
} MV_TDM_DEC_WIN;
MV_STATUS mvTdmWinInit(MV_VOID);
MV_STATUS mvTdmWinSet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin);
MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin);
MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable);
MV_VOID mvTdmAddrDecShow(MV_VOID);
#define TDM_MBUS_MAX_WIN 4
#define TDM_WIN_CTRL_REG(win) ((TDM_REG_BASE + 0x4030) + (win<<4))
#define TDM_WIN_BASE_REG(win) ((TDM_REG_BASE +0x4034) + (win<<4))
/* TDM_WIN_CTRL_REG bits */
#define TDM_WIN_ENABLE_OFFS 0
#define TDM_WIN_ENABLE_MASK (1<<TDM_WIN_ENABLE_OFFS)
#define TDM_WIN_ENABLE 1
#define TDM_WIN_TARGET_OFFS 4
#define TDM_WIN_TARGET_MASK (0xf<<TDM_WIN_TARGET_OFFS)
#define TDM_WIN_ATTRIB_OFFS 8
#define TDM_WIN_ATTRIB_MASK (0xff<<TDM_WIN_ATTRIB_OFFS)
#define TDM_WIN_SIZE_OFFS 16
#define TDM_WIN_SIZE_MASK (0xffff<<TDM_WIN_SIZE_OFFS)
/* TDM_WIN_BASE_REG bits */
#define TDM_BASE_OFFS 16
#define TDM_BASE_MASK (0xffff<<TDM_BASE_OFFS)
#endif /*__INCmvSysTdmh*/

591
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@ -0,0 +1,591 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "ctrlEnv/sys/mvSysTs.h"
typedef struct _mvTsuDecWin
{
MV_TARGET target;
MV_ADDR_WIN addrWin; /* An address window*/
MV_BOOL enable; /* Address decode window is enabled/disabled */
}MV_TSU_DEC_WIN;
MV_TARGET tsuAddrDecPrioTap[] =
{
#if defined(MV_INCLUDE_PEX)
PEX0_MEM,
#endif
#if defined(MV_INCLUDE_PCI)
PCI0_MEM,
#endif
#if defined(MV_INCLUDE_SDRAM_CS0)
SDRAM_CS0,
#endif
#if defined(MV_INCLUDE_SDRAM_CS1)
SDRAM_CS1,
#endif
#if defined(MV_INCLUDE_SDRAM_CS2)
SDRAM_CS2,
#endif
#if defined(MV_INCLUDE_SDRAM_CS3)
SDRAM_CS3,
#endif
#if defined(MV_INCLUDE_DEVICE_CS0)
DEVICE_CS0,
#endif
#if defined(MV_INCLUDE_DEVICE_CS1)
DEVICE_CS1,
#endif
#if defined(MV_INCLUDE_DEVICE_CS2)
DEVICE_CS2,
#endif
#if defined(MV_INCLUDE_DEVICE_CS3)
DEVICE_CS3,
#endif
#if defined(MV_INCLUDE_PEX)
PEX0_IO,
#endif
#if defined(MV_INCLUDE_PCI)
PCI0_IO,
#endif
TBL_TERM
};
static MV_STATUS tsuWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin);
static MV_STATUS mvTsuWinSet(MV_U32 winNum, MV_TSU_DEC_WIN *pAddrDecWin);
static MV_STATUS mvTsuWinGet(MV_U32 winNum, MV_TSU_DEC_WIN *pAddrDecWin);
MV_STATUS mvTsuWinEnable(MV_U32 winNum,MV_BOOL enable);
/*******************************************************************************
* mvTsuWinInit
*
* DESCRIPTION:
* Initialize the TSU unit address decode windows.
*
* INPUT:
* None.
* OUTPUT:
* None.
* RETURN:
* MV_OK - on success,
*
*******************************************************************************/
MV_STATUS mvTsuWinInit(void)
{
MV_U32 winNum, status, winPrioIndex=0;
MV_TSU_DEC_WIN tsuWin;
MV_CPU_DEC_WIN cpuAddrDecWin;
/* First disable all address decode windows */
for(winNum = 0; winNum < TSU_MAX_DECODE_WIN; winNum++)
{
MV_REG_BIT_RESET(MV_TSU_WIN_CTRL_REG(winNum),
TSU_WIN_CTRL_EN_MASK);
}
/* Go through all windows in user table until table terminator */
for(winNum = 0; ((tsuAddrDecPrioTap[winPrioIndex] != TBL_TERM) &&
(winNum < TSU_MAX_DECODE_WIN));)
{
/* first get attributes from CPU If */
status = mvCpuIfTargetWinGet(tsuAddrDecPrioTap[winPrioIndex],
&cpuAddrDecWin);
if(MV_NO_SUCH == status)
{
winPrioIndex++;
continue;
}
if(MV_OK != status)
{
mvOsPrintf("mvTsuWinInit: ERR. mvCpuIfTargetWinGet failed\n");
return MV_ERROR;
}
if (cpuAddrDecWin.enable == MV_TRUE)
{
tsuWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;
tsuWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow;
tsuWin.addrWin.size = cpuAddrDecWin.addrWin.size;
tsuWin.enable = MV_TRUE;
tsuWin.target = tsuAddrDecPrioTap[winPrioIndex];
if(MV_OK != mvTsuWinSet(winNum, &tsuWin))
{
mvOsPrintf("mvTsuWinInit: ERR. mvTsuWinSet failed winNum=%d\n",
winNum);
return MV_ERROR;
}
winNum++;
}
winPrioIndex ++;
}
return MV_OK;
}
/*******************************************************************************
* mvTsuWinSet
*
* DESCRIPTION:
* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)
* address window, also known as address decode window.
* After setting this target window, the TSU will be able to access the
* target within the address window.
*
* INPUT:
* winNum - TSU to target address decode window number.
* pAddrDecWin - TSU target window data structure.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_ERROR - if address window overlapps with other address decode
* windows.
* MV_BAD_PARAM - if base address is invalid parameter or target is
* unknown.
*
*******************************************************************************/
MV_STATUS mvTsuWinSet(MV_U32 winNum, MV_TSU_DEC_WIN *pAddrDecWin)
{
MV_TARGET_ATTRIB targetAttribs;
MV_DEC_REGS decRegs;
/* Parameter checking */
if(winNum >= TSU_MAX_DECODE_WIN)
{
mvOsPrintf("mvTsuWinSet: ERR. Invalid win num %d\n",winNum);
return MV_BAD_PARAM;
}
/* Check if the requested window overlapps with current windows */
if(MV_TRUE == tsuWinOverlapDetect(winNum, &pAddrDecWin->addrWin))
{
mvOsPrintf("mvTsuWinSet: ERR. Window %d overlap\n", winNum);
return MV_ERROR;
}
/* check if address is aligned to the size */
if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow,pAddrDecWin->addrWin.size))
{
mvOsPrintf("mvTsuWinSet: Error setting TSU window %d to target "
"%s.\nAddress 0x%08x is unaligned to size 0x%x.\n",
winNum, mvCtrlTargetNameGet(pAddrDecWin->target),
pAddrDecWin->addrWin.baseLow,
pAddrDecWin->addrWin.size);
return MV_ERROR;
}
decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum));
decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum));
if(MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs))
{
mvOsPrintf("mvTsuWinSet: mvCtrlAddrDecToReg Failed\n");
return MV_ERROR;
}
mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs);
/* set attributes */
decRegs.sizeReg &= ~TSU_WIN_CTRL_ATTR_MASK;
decRegs.sizeReg |= targetAttribs.attrib << TSU_WIN_CTRL_ATTR_OFFS;
/* set target ID */
decRegs.sizeReg &= ~TSU_WIN_CTRL_TARGET_MASK;
decRegs.sizeReg |= targetAttribs.targetId << TSU_WIN_CTRL_TARGET_OFFS;
/* for the safe side we disable the window before writing the new */
/* values */
mvTsuWinEnable(winNum, MV_FALSE);
MV_REG_WRITE(MV_TSU_WIN_CTRL_REG(winNum),decRegs.sizeReg);
/* Write to address decode Size Register */
MV_REG_WRITE(MV_TSU_WIN_BASE_REG(winNum), decRegs.baseReg);
/* Enable address decode target window */
if(pAddrDecWin->enable == MV_TRUE)
{
mvTsuWinEnable(winNum,MV_TRUE);
}
return MV_OK;
}
/*******************************************************************************
* mvTsuWinGet
*
* DESCRIPTION:
* Get TSU peripheral target address window.
*
* INPUT:
* winNum - TSU to target address decode window number.
*
* OUTPUT:
* pAddrDecWin - TSU target window data structure.
*
* RETURN:
* MV_ERROR if register parameters are invalid.
*
*******************************************************************************/
MV_STATUS mvTsuWinGet(MV_U32 winNum, MV_TSU_DEC_WIN *pAddrDecWin)
{
MV_DEC_REGS decRegs;
MV_TARGET_ATTRIB targetAttrib;
/* Parameter checking */
if(winNum >= TSU_MAX_DECODE_WIN)
{
mvOsPrintf("mvTsuWinGet: ERR. Invalid winNum %d\n", winNum);
return MV_NOT_SUPPORTED;
}
decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum));
decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum));
if(MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin)))
{
mvOsPrintf("mvTsuWinGet: mvCtrlRegToAddrDec Failed \n");
return MV_ERROR;
}
/* attrib and targetId */
targetAttrib.attrib =
(decRegs.sizeReg & TSU_WIN_CTRL_ATTR_MASK) >> TSU_WIN_CTRL_ATTR_OFFS;
targetAttrib.targetId =
(decRegs.sizeReg & TSU_WIN_CTRL_TARGET_MASK) >> TSU_WIN_CTRL_TARGET_OFFS;
pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
/* Check if window is enabled */
if((MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)) & TSU_WIN_CTRL_EN_MASK))
{
pAddrDecWin->enable = MV_TRUE;
}
else
{
pAddrDecWin->enable = MV_FALSE;
}
return MV_OK;
}
/*******************************************************************************
* mvTsuWinEnable
*
* DESCRIPTION:
* This function enable/disable a TSU to target address window.
* According to parameter 'enable' the routine will enable the
* window, thus enabling TSU accesses (before enabling the window it is
* tested for overlapping). Otherwise, the window will be disabled.
*
* INPUT:
* winNum - TSU to target address decode window number.
* enable - Enable / disable parameter.
*
* OUTPUT:
* N/A
*
* RETURN:
* MV_ERROR if decode window number was wrong or enabled window overlapps.
*
*******************************************************************************/
MV_STATUS mvTsuWinEnable(MV_U32 winNum,MV_BOOL enable)
{
MV_TSU_DEC_WIN addrDecWin;
/* Parameter checking */
if(winNum >= TSU_MAX_DECODE_WIN)
{
mvOsPrintf("mvTsuWinEnable: ERR. Invalid winNum%d\n",winNum);
return MV_ERROR;
}
if(enable == MV_TRUE)
{
/* First check for overlap with other enabled windows */
/* Get current window. */
if(MV_OK != mvTsuWinGet(winNum,&addrDecWin))
{
mvOsPrintf("mvTsuWinEnable: ERR. targetWinGet fail\n");
return MV_ERROR;
}
/* Check for overlapping. */
if(MV_FALSE == tsuWinOverlapDetect(winNum,&(addrDecWin.addrWin)))
{
/* No Overlap. Enable address decode target window */
MV_REG_BIT_SET(MV_TSU_WIN_CTRL_REG(winNum),
TSU_WIN_CTRL_EN_MASK);
}
else
{
/* Overlap detected */
mvOsPrintf("mvTsuWinEnable: ERR. Overlap detected\n");
return MV_ERROR;
}
}
else
{
/* Disable address decode target window */
MV_REG_BIT_RESET(MV_TSU_WIN_CTRL_REG(winNum),
TSU_WIN_CTRL_EN_MASK);
}
return MV_OK;
}
/*******************************************************************************
* mvTsuWinTargetGet
*
* DESCRIPTION:
* Get Window number associated with target
*
* INPUT:
* target - Target ID to get the window number for.
* OUTPUT:
*
* RETURN:
* window number or 0xFFFFFFFF on error.
*
*******************************************************************************/
MV_U32 mvTsuWinTargetGet(MV_TARGET target)
{
MV_TSU_DEC_WIN decWin;
MV_U32 winNum;
/* Check parameters */
if(target >= MAX_TARGETS)
{
mvOsPrintf("mvTsuWinTargetGet: target %d is Illigal\n", target);
return 0xffffffff;
}
for(winNum = 0; winNum < TSU_MAX_DECODE_WIN; winNum++)
{
if(mvTsuWinGet(winNum,&decWin) != MV_OK)
{
mvOsPrintf("mvTsuWinGet: window returned error\n");
return 0xffffffff;
}
if (decWin.enable == MV_TRUE)
{
if(decWin.target == target)
{
return winNum;
}
}
}
return 0xFFFFFFFF;
}
/*******************************************************************************
* tsuWinOverlapDetect
*
* DESCRIPTION:
* Detect TSU address windows overlapping
* An unpredicted behaviur is expected in case TSU address decode
* windows overlapps.
* This function detects TSU address decode windows overlapping of a
* specified window. The function does not check the window itself for
* overlapping. The function also skipps disabled address decode windows.
*
* INPUT:
* winNum - address decode window number.
* pAddrDecWin - An address decode window struct.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_TRUE if the given address window overlap current address
* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data
* from registers.
*
*******************************************************************************/
static MV_STATUS tsuWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin)
{
MV_U32 ctrlReg;
MV_U32 winNumIndex;
MV_TSU_DEC_WIN addrDecWin;
for(winNumIndex = 0; winNumIndex < TSU_MAX_DECODE_WIN; winNumIndex++)
{
/* Do not check window itself */
if(winNumIndex == winNum)
{
continue;
}
/* Do not check disabled windows */
ctrlReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNumIndex));
if((ctrlReg & TSU_WIN_CTRL_EN_MASK) == 0)
{
continue;
}
/* Get window parameters */
if (MV_OK != mvTsuWinGet(winNumIndex, &addrDecWin))
{
mvOsPrintf("tsuWinOverlapDetect: ERR. mvTsuWinGet failed\n");
return MV_ERROR;
}
if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin)))
{
return MV_TRUE;
}
}
return MV_FALSE;
}
/*******************************************************************************
* mvTsuAddrDecShow
*
* DESCRIPTION:
* Print the TSU address decode map.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
void mvTsuAddrDecShow(void)
{
MV_TSU_DEC_WIN win;
int i;
if (MV_FALSE == mvCtrlPwrClckGet(TS_UNIT_ID, 0))
return;
mvOsOutput( "\n" );
mvOsOutput( "TSU:\n");
mvOsOutput( "----\n" );
for(i = 0; i < TSU_MAX_DECODE_WIN; i++)
{
memset(&win, 0, sizeof(TSU_MAX_DECODE_WIN));
mvOsOutput( "win%d - ", i );
if(mvTsuWinGet(i, &win ) == MV_OK )
{
if(win.enable == MV_TRUE)
{
mvOsOutput("%s base %08x, ",
mvCtrlTargetNameGet(win.target),
win.addrWin.baseLow);
mvOsOutput( "...." );
mvSizePrint(win.addrWin.size );
mvOsOutput( "\n" );
}
else
{
mvOsOutput( "disable\n" );
}
}
}
return;
}
/*******************************************************************************
* mvTsuInit
*
* DESCRIPTION:
* Initialize the TSU unit, and get unit out of reset.
*
* INPUT:
* coreClock - The core clock at which the TSU should operate.
* mode - The mode on configure the unit into (serial/parallel).
* memHandle - Memory handle used for memory allocations.
* OUTPUT:
* None.
* RETURN:
* MV_OK - on success,
*
*******************************************************************************/
MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode,
void *osHandle)
{
MV_STATUS status;
status = mvTsuWinInit();
if(status == MV_OK)
status = mvTsuHalInit(coreClock,mode,osHandle);
return status;
}

110
target/linux/generic-2.6/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h Normal file
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@ -0,0 +1,110 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvSysTsh
#define __INCmvSysTsh
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* includes */
#include "ts/mvTsu.h"
#include "ctrlEnv/sys/mvCpuIf.h"
#include "ctrlEnv/mvCtrlEnvLib.h"
#include "ctrlEnv/mvCtrlEnvAddrDec.h"
#define TSU_MAX_DECODE_WIN 4
/*******************************************/
/* TSU Windows Registers */
/*******************************************/
#define MV_TSU_WIN_CTRL_REG(win) (TSU_GLOBAL_REG_BASE +0x30 + 0x10 * win)
#define MV_TSU_WIN_BASE_REG(win) (TSU_GLOBAL_REG_BASE +0x34 + 0x10 * win)
/* TSU windows control register. */
#define TSU_WIN_CTRL_EN_MASK (0x1 << 0)
#define TSU_WIN_CTRL_TARGET_OFFS 4
#define TSU_WIN_CTRL_TARGET_MASK (0xF << TSU_WIN_CTRL_TARGET_OFFS)
#define TSU_WIN_CTRL_ATTR_OFFS 8
#define TSU_WIN_CTRL_ATTR_MASK (0xFF << TSU_WIN_CTRL_ATTR_OFFS)
#define TSU_WIN_CTRL_SIZE_OFFS 16
#define TSU_WIN_CTRL_SIZE_MASK (0xFFFF << TSU_WIN_CTRL_SIZE_OFFS)
/* TSU windows base register. */
#define TSU_WIN_BASE_OFFS 16
#define TSU_WIN_BASE_MASK (0xFFFF << TSU_WIN_BASE_OFFS)
MV_STATUS mvTsuWinInit(void);
void mvTsuAddrDecShow(void);
MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode,
void *osHandle);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __INCmvTsh */

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@ -0,0 +1,497 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "ctrlEnv/sys/mvSysUsb.h"
MV_TARGET usbAddrDecPrioTab[] =
{
#if defined(MV_INCLUDE_SDRAM_CS0)
SDRAM_CS0,
#endif
#if defined(MV_INCLUDE_SDRAM_CS1)
SDRAM_CS1,
#endif
#if defined(MV_INCLUDE_SDRAM_CS2)
SDRAM_CS2,
#endif
#if defined(MV_INCLUDE_SDRAM_CS3)
SDRAM_CS3,
#endif
#if defined(MV_INCLUDE_CESA) && defined(USB_UNDERRUN_WA)
CRYPT_ENG,
#endif
#if defined(MV_INCLUDE_PEX)
PEX0_MEM,
#endif
TBL_TERM
};
MV_STATUS mvUsbInit(int dev, MV_BOOL isHost)
{
MV_STATUS status;
status = mvUsbWinInit(dev);
if(status != MV_OK)
return status;
return mvUsbHalInit(dev, isHost);
}
/*******************************************************************************
* usbWinOverlapDetect - Detect USB address windows overlapping
*
* DESCRIPTION:
* An unpredicted behaviur is expected in case USB address decode
* windows overlapps.
* This function detects USB address decode windows overlapping of a
* specified window. The function does not check the window itself for
* overlapping. The function also skipps disabled address decode windows.
*
* INPUT:
* winNum - address decode window number.
* pAddrDecWin - An address decode window struct.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_TRUE if the given address window overlap current address
* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data
* from registers.
*
*******************************************************************************/
static MV_STATUS usbWinOverlapDetect(int dev, MV_U32 winNum,
MV_ADDR_WIN *pAddrWin)
{
MV_U32 winNumIndex;
MV_DEC_WIN addrDecWin;
for(winNumIndex=0; winNumIndex<MV_USB_MAX_ADDR_DECODE_WIN; winNumIndex++)
{
/* Do not check window itself */
if (winNumIndex == winNum)
{
continue;
}
/* Get window parameters */
if (MV_OK != mvUsbWinGet(dev, winNumIndex, &addrDecWin))
{
mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__);
return MV_ERROR;
}
/* Do not check disabled windows */
if(addrDecWin.enable == MV_FALSE)
{
continue;
}
if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin)))
{
return MV_TRUE;
}
}
return MV_FALSE;
}
/*******************************************************************************
* mvUsbWinSet - Set USB target address window
*
* DESCRIPTION:
* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)
* address window, also known as address decode window.
* After setting this target window, the USB will be able to access the
* target within the address window.
*
* INPUT:
* winNum - USB target address decode window number.
* pAddrDecWin - USB target window data structure.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_ERROR if address window overlapps with other address decode windows.
* MV_BAD_PARAM if base address is invalid parameter or target is
* unknown.
*
*******************************************************************************/
MV_STATUS mvUsbWinSet(int dev, MV_U32 winNum, MV_DEC_WIN *pDecWin)
{
MV_DEC_WIN_PARAMS winParams;
MV_U32 sizeReg, baseReg;
/* Parameter checking */
if (winNum >= MV_USB_MAX_ADDR_DECODE_WIN)
{
mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum);
return MV_BAD_PARAM;
}
/* Check if the requested window overlapps with current windows */
if (MV_TRUE == usbWinOverlapDetect(dev, winNum, &pDecWin->addrWin))
{
mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum);
return MV_ERROR;
}
/* check if address is aligned to the size */
if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size))
{
mvOsPrintf("mvUsbWinSet:Error setting USB window %d to "\
"target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n",
winNum,
mvCtrlTargetNameGet(pDecWin->target),
pDecWin->addrWin.baseLow,
pDecWin->addrWin.size);
return MV_ERROR;
}
if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams))
{
mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__);
return MV_ERROR;
}
/* set Size, Attributes and TargetID */
sizeReg = (((winParams.targetId << MV_USB_WIN_TARGET_OFFSET) & MV_USB_WIN_TARGET_MASK) |
((winParams.attrib << MV_USB_WIN_ATTR_OFFSET) & MV_USB_WIN_ATTR_MASK) |
((winParams.size << MV_USB_WIN_SIZE_OFFSET) & MV_USB_WIN_SIZE_MASK));
#if defined(MV645xx) || defined(MV646xx)
/* If window is DRAM with HW cache coherency, make sure bit2 is set */
sizeReg &= ~MV_USB_WIN_BURST_WR_LIMIT_MASK;
if((MV_TARGET_IS_DRAM(pDecWin->target)) &&
(pDecWin->addrWinAttr.cachePolicy != NO_COHERENCY))
{
sizeReg |= MV_USB_WIN_BURST_WR_32BIT_LIMIT;
}
else
{
sizeReg |= MV_USB_WIN_BURST_WR_NO_LIMIT;
}
#endif /* MV645xx || MV646xx */
if (pDecWin->enable == MV_TRUE)
{
sizeReg |= MV_USB_WIN_ENABLE_MASK;
}
else
{
sizeReg &= ~MV_USB_WIN_ENABLE_MASK;
}
/* Update Base value */
baseReg = (winParams.baseAddr & MV_USB_WIN_BASE_MASK);
MV_REG_WRITE( MV_USB_WIN_CTRL_REG(dev, winNum), sizeReg);
MV_REG_WRITE( MV_USB_WIN_BASE_REG(dev, winNum), baseReg);
return MV_OK;
}
/*******************************************************************************
* mvUsbWinGet - Get USB peripheral target address window.
*
* DESCRIPTION:
* Get USB peripheral target address window.
*
* INPUT:
* winNum - USB target address decode window number.
*
* OUTPUT:
* pDecWin - USB target window data structure.
*
* RETURN:
* MV_ERROR if register parameters are invalid.
*
*******************************************************************************/
MV_STATUS mvUsbWinGet(int dev, MV_U32 winNum, MV_DEC_WIN *pDecWin)
{
MV_DEC_WIN_PARAMS winParam;
MV_U32 sizeReg, baseReg;
/* Parameter checking */
if (winNum >= MV_USB_MAX_ADDR_DECODE_WIN)
{
mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n",
__FUNCTION__, dev, winNum);
return MV_NOT_SUPPORTED;
}
baseReg = MV_REG_READ( MV_USB_WIN_BASE_REG(dev, winNum) );
sizeReg = MV_REG_READ( MV_USB_WIN_CTRL_REG(dev, winNum) );
/* Check if window is enabled */
if(sizeReg & MV_USB_WIN_ENABLE_MASK)
{
pDecWin->enable = MV_TRUE;
/* Extract window parameters from registers */
winParam.targetId = (sizeReg & MV_USB_WIN_TARGET_MASK) >> MV_USB_WIN_TARGET_OFFSET;
winParam.attrib = (sizeReg & MV_USB_WIN_ATTR_MASK) >> MV_USB_WIN_ATTR_OFFSET;
winParam.size = (sizeReg & MV_USB_WIN_SIZE_MASK) >> MV_USB_WIN_SIZE_OFFSET;
winParam.baseAddr = (baseReg & MV_USB_WIN_BASE_MASK);
/* Translate the decode window parameters to address decode struct */
if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin))
{
mvOsPrintf("Failed to translate register parameters to USB address" \
" decode window structure\n");
return MV_ERROR;
}
}
else
{
pDecWin->enable = MV_FALSE;
}
return MV_OK;
}
/*******************************************************************************
* mvUsbWinInit -
*
* INPUT:
*
* OUTPUT:
*
* RETURN:
* MV_ERROR if register parameters are invalid.
*
*******************************************************************************/
MV_STATUS mvUsbWinInit(int dev)
{
MV_STATUS status;
MV_DEC_WIN usbWin;
MV_CPU_DEC_WIN cpuAddrDecWin;
int winNum;
MV_U32 winPrioIndex = 0;
/* First disable all address decode windows */
for(winNum = 0; winNum < MV_USB_MAX_ADDR_DECODE_WIN; winNum++)
{
MV_REG_BIT_RESET(MV_USB_WIN_CTRL_REG(dev, winNum), MV_USB_WIN_ENABLE_MASK);
}
/* Go through all windows in user table until table terminator */
winNum = 0;
while( (usbAddrDecPrioTab[winPrioIndex] != TBL_TERM) &&
(winNum < MV_USB_MAX_ADDR_DECODE_WIN) )
{
/* first get attributes from CPU If */
status = mvCpuIfTargetWinGet(usbAddrDecPrioTab[winPrioIndex],
&cpuAddrDecWin);
if(MV_NO_SUCH == status)
{
winPrioIndex++;
continue;
}
if (MV_OK != status)
{
mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__);
return MV_ERROR;
}
if (cpuAddrDecWin.enable == MV_TRUE)
{
usbWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;
usbWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow;
usbWin.addrWin.size = cpuAddrDecWin.addrWin.size;
usbWin.enable = MV_TRUE;
usbWin.target = usbAddrDecPrioTab[winPrioIndex];
#if defined(MV645xx) || defined(MV646xx)
/* Get the default attributes for that target window */
mvCtrlDefAttribGet(usbWin.target, &usbWin.addrWinAttr);
#endif /* MV645xx || MV646xx */
if(MV_OK != mvUsbWinSet(dev, winNum, &usbWin))
{
return MV_ERROR;
}
winNum++;
}
winPrioIndex++;
}
return MV_OK;
}
/*******************************************************************************
* mvUsbAddrDecShow - Print the USB address decode map.
*
* DESCRIPTION:
* This function print the USB address decode map.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_VOID mvUsbAddrDecShow(MV_VOID)
{
MV_DEC_WIN addrDecWin;
int i, winNum;
mvOsOutput( "\n" );
mvOsOutput( "USB:\n" );
mvOsOutput( "----\n" );
for(i=0; i<mvCtrlUsbMaxGet(); i++)
{
mvOsOutput( "Device %d:\n", i);
for(winNum = 0; winNum < MV_USB_MAX_ADDR_DECODE_WIN; winNum++)
{
memset(&addrDecWin, 0, sizeof(MV_DEC_WIN) );
mvOsOutput( "win%d - ", winNum );
if( mvUsbWinGet(i, winNum, &addrDecWin ) == MV_OK )
{
if( addrDecWin.enable )
{
mvOsOutput( "%s base %08x, ",
mvCtrlTargetNameGet(addrDecWin.target), addrDecWin.addrWin.baseLow );
mvSizePrint( addrDecWin.addrWin.size );
#if defined(MV645xx) || defined(MV646xx)
switch( addrDecWin.addrWinAttr.swapType)
{
case MV_BYTE_SWAP:
mvOsOutput( "BYTE_SWAP, " );
break;
case MV_NO_SWAP:
mvOsOutput( "NO_SWAP , " );
break;
case MV_BYTE_WORD_SWAP:
mvOsOutput( "BYTE_WORD_SWAP, " );
break;
case MV_WORD_SWAP:
mvOsOutput( "WORD_SWAP, " );
break;
default:
mvOsOutput( "SWAP N/A , " );
}
switch( addrDecWin.addrWinAttr.cachePolicy )
{
case NO_COHERENCY:
mvOsOutput( "NO_COHERENCY , " );
break;
case WT_COHERENCY:
mvOsOutput( "WT_COHERENCY , " );
break;
case WB_COHERENCY:
mvOsOutput( "WB_COHERENCY , " );
break;
default:
mvOsOutput( "COHERENCY N/A, " );
}
switch( addrDecWin.addrWinAttr.pcixNoSnoop )
{
case 0:
mvOsOutput( "PCI-X NS inactive, " );
break;
case 1:
mvOsOutput( "PCI-X NS active , " );
break;
default:
mvOsOutput( "PCI-X NS N/A , " );
}
switch( addrDecWin.addrWinAttr.p2pReq64 )
{
case 0:
mvOsOutput( "REQ64 force" );
break;
case 1:
mvOsOutput( "REQ64 detect" );
break;
default:
mvOsOutput( "REQ64 N/A" );
}
#endif /* MV645xx || MV646xx */
mvOsOutput( "\n" );
}
else
mvOsOutput( "disable\n" );
}
}
}
}

125
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/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvSysUsbh
#define __INCmvSysUsbh
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* includes */
#include "usb/mvUsb.h"
#include "ctrlEnv/sys/mvCpuIf.h"
#include "ctrlEnv/mvCtrlEnvLib.h"
#include "ctrlEnv/mvCtrlEnvAddrDec.h"
#define MV_USB_MAX_ADDR_DECODE_WIN 4
/*******************************************/
/* USB Bridge Registers */
/*******************************************/
#define MV_USB_BRIDGE_CTRL_REG(dev) (USB_REG_BASE(dev) + 0x300)
#define MV_USB_WIN_CTRL_REG(dev, win) (USB_REG_BASE(dev) + 0x320 + ((win)<<4))
#define MV_USB_WIN_BASE_REG(dev, win) (USB_REG_BASE(dev) + 0x324 + ((win)<<4))
/* BITs in Windows 0-3 Control and Base Registers */
#define MV_USB_WIN_ENABLE_BIT 0
#define MV_USB_WIN_ENABLE_MASK (1 << MV_USB_WIN_ENABLE_BIT)
#define MV_USB_WIN_BURST_WR_LIMIT_BIT 1
#define MV_USB_WIN_BURST_WR_LIMIT_MASK (1 << MV_USB_WIN_BURST_WR_LIMIT_BIT)
#define MV_USB_WIN_BURST_WR_NO_LIMIT (0 << MV_USB_WIN_BURST_WR_LIMIT_BIT)
#define MV_USB_WIN_BURST_WR_32BIT_LIMIT (1 << MV_USB_WIN_BURST_WR_LIMIT_BIT)
#define MV_USB_WIN_TARGET_OFFSET 4
#define MV_USB_WIN_TARGET_MASK (0xF << MV_USB_WIN_TARGET_OFFSET)
#define MV_USB_WIN_ATTR_OFFSET 8
#define MV_USB_WIN_ATTR_MASK (0xFF << MV_USB_WIN_ATTR_OFFSET)
#define MV_USB_WIN_SIZE_OFFSET 16
#define MV_USB_WIN_SIZE_MASK (0xFFFF << MV_USB_WIN_SIZE_OFFSET)
#define MV_USB_WIN_BASE_OFFSET 16
#define MV_USB_WIN_BASE_MASK (0xFFFF << MV_USB_WIN_BASE_OFFSET)
#define MV_USB_BRIDGE_IPG_REG(dev) (USB_REG_BASE(dev) + 0x360)
MV_STATUS mvUsbInit(int dev, MV_BOOL isHost);
MV_STATUS mvUsbWinInit(int dev);
MV_STATUS mvUsbWinSet(int dev, MV_U32 winNum, MV_DEC_WIN *pAddrWin);
MV_STATUS mvUsbWinGet(int dev, MV_U32 winNum, MV_DEC_WIN *pAddrWin);
void mvUsbAddrDecShow(void);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __INCmvUsbh */

662
target/linux/generic-2.6/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.c Normal file
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@ -0,0 +1,662 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "xor/mvXor.h"
#include "mvSysXor.h"
/* defines */
#ifdef MV_DEBUG
#define DB(x) x
#else
#define DB(x)
#endif
static MV_STATUS xorWinOverlapDetect(MV_U32 unit,MV_U32 winNum, MV_ADDR_WIN *pAddrWin);
MV_TARGET xorAddrDecPrioTap[] =
{
#if defined(MV_INCLUDE_DEVICE_CS0)
DEVICE_CS0,
#endif
#if defined(MV_INCLUDE_PEX)
PEX0_MEM,
#endif
#if defined(MV_INCLUDE_SDRAM_CS0)
SDRAM_CS0,
#endif
#if defined(MV_INCLUDE_SDRAM_CS1)
SDRAM_CS1,
#endif
#if defined(MV_INCLUDE_SDRAM_CS2)
SDRAM_CS2,
#endif
#if defined(MV_INCLUDE_SDRAM_CS3)
SDRAM_CS3,
#endif
#if defined(MV_INCLUDE_DEVICE_CS1)
DEVICE_CS1,
#endif
#if defined(MV_INCLUDE_CESA)
CRYPT_ENG,
#endif
TBL_TERM
};
static MV_STATUS mvXorInitWinsUnit (MV_U32 unit)
{
MV_U32 winNum;
MV_XOR_DEC_WIN addrDecWin;
MV_CPU_DEC_WIN cpuAddrDecWin;
MV_U32 status;
MV_U32 winPrioIndex=0;
/* Initiate XOR address decode */
/* First disable all address decode windows */
for(winNum = 0; winNum < XOR_MAX_ADDR_DEC_WIN; winNum++)
{
mvXorTargetWinEnable(unit,winNum, MV_FALSE);
}
/* Go through all windows in user table until table terminator */
for (winNum = 0; ((xorAddrDecPrioTap[winPrioIndex] != TBL_TERM) &&
(winNum < XOR_MAX_ADDR_DEC_WIN));)
{
/* first get attributes from CPU If */
status = mvCpuIfTargetWinGet(xorAddrDecPrioTap[winPrioIndex],
&cpuAddrDecWin);
if(MV_NO_SUCH == status)
{
winPrioIndex++;
continue;
}
if (MV_OK != status)
{
mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__);
return MV_ERROR;
}
if (cpuAddrDecWin.enable == MV_TRUE)
{
addrDecWin.target = xorAddrDecPrioTap[winPrioIndex];
addrDecWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow;
addrDecWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;
addrDecWin.addrWin.size = cpuAddrDecWin.addrWin.size;
addrDecWin.enable = MV_TRUE;
if (MV_OK != mvXorTargetWinSet(unit,winNum, &addrDecWin))
{
DB(mvOsPrintf("mvXorInit: ERR. mvDmaTargetWinSet failed\n"));
return MV_ERROR;
}
winNum++;
}
winPrioIndex++;
}
return MV_OK;
}
/*******************************************************************************
* mvXorInit - Initialize XOR engine
*
* DESCRIPTION:
* This function initialize XOR unit. It set the default address decode
* windows of the unit.
* Note that if the address window is disabled in xorAddrDecMap, the
* window parameters will be set but the window will remain disabled.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
*******************************************************************************/
MV_STATUS mvXorInit (MV_VOID)
{
MV_U32 i;
/* Initiate XOR address decode */
for(i = 0; i < MV_XOR_MAX_UNIT; i++)
mvXorInitWinsUnit(i);
mvXorHalInit(MV_XOR_MAX_CHAN);
return MV_OK;
}
/*******************************************************************************
* mvXorTargetWinSet - Set XOR target address window
*
* DESCRIPTION:
* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)
* address window. After setting this target window, the XOR will be
* able to access the target within the address window.
*
* INPUT:
* winNum - One of the possible XOR memory decode windows.
* target - Peripheral target enumerator.
* base - Window base address.
* size - Window size.
* enable - Window enable/disable.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
*
*******************************************************************************/
MV_STATUS mvXorTargetWinSet(MV_U32 unit, MV_U32 winNum, MV_XOR_DEC_WIN *pAddrDecWin)
{
MV_DEC_REGS xorDecRegs;
MV_TARGET_ATTRIB targetAttribs;
MV_U32 chan;
/* Parameter checking */
if (winNum >= XOR_MAX_ADDR_DEC_WIN)
{
DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum));
return MV_BAD_PARAM;
}
if (pAddrDecWin == NULL)
{
DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ ));
return MV_BAD_PTR;
}
/* Check if the requested window overlaps with current windows */
if (MV_TRUE == xorWinOverlapDetect(unit, winNum, &pAddrDecWin->addrWin))
{
DB(mvOsPrintf("%s: ERR. Window %d overlap\n",__FUNCTION__,winNum));
return MV_ERROR;
}
xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum));
xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum));
/* Get Base Address and size registers values */
if(MV_OK != mvCtrlAddrDecToReg(&pAddrDecWin->addrWin, &xorDecRegs))
{
DB(mvOsPrintf("%s: ERR. Invalid addr dec window\n",__FUNCTION__));
return MV_BAD_PARAM;
}
mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs);
/* set attributes */
xorDecRegs.baseReg &= ~XEBARX_ATTR_MASK;
xorDecRegs.baseReg |= targetAttribs.attrib << XEBARX_ATTR_OFFS;
/* set target ID */
xorDecRegs.baseReg &= ~XEBARX_TARGET_MASK;
xorDecRegs.baseReg |= targetAttribs.targetId << XEBARX_TARGET_OFFS;
/* Write to address decode Base Address Register */
MV_REG_WRITE(XOR_BASE_ADDR_REG(unit,winNum), xorDecRegs.baseReg);
/* Write to Size Register */
MV_REG_WRITE(XOR_SIZE_MASK_REG(unit,winNum), xorDecRegs.sizeReg);
for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++)
{
if (pAddrDecWin->enable)
{
MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan),
XEXWCR_WIN_EN_MASK(winNum));
}
else
{
MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan),
XEXWCR_WIN_EN_MASK(winNum));
}
}
return MV_OK;
}
/*******************************************************************************
* mvXorTargetWinGet - Get xor peripheral target address window.
*
* DESCRIPTION:
* Get xor peripheral target address window.
*
* INPUT:
* winNum - One of the possible XOR memory decode windows.
*
* OUTPUT:
* base - Window base address.
* size - Window size.
* enable - window enable/disable.
*
* RETURN:
* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
*
*******************************************************************************/
MV_STATUS mvXorTargetWinGet(MV_U32 unit,MV_U32 winNum, MV_XOR_DEC_WIN *pAddrDecWin)
{
MV_DEC_REGS xorDecRegs;
MV_TARGET_ATTRIB targetAttrib;
MV_U32 chan=0,chanWinEn;
/* Parameter checking */
if (winNum >= XOR_MAX_ADDR_DEC_WIN)
{
DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__ , winNum));
return MV_ERROR;
}
if (NULL == pAddrDecWin)
{
DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ ));
return MV_BAD_PTR;
}
chanWinEn = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,0)) & XEXWCR_WIN_EN_MASK(winNum);
for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) /* we should scan here all channels per unit */
{
/* Check if enable bit is equal for all channels */
if ((MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) &
XEXWCR_WIN_EN_MASK(winNum)) != chanWinEn)
{
mvOsPrintf("%s: ERR. Window enable field must be equal in "
"all channels(chan=%d)\n",__FUNCTION__, chan);
return MV_ERROR;
}
}
xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum));
xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum));
if (MV_OK != mvCtrlRegToAddrDec(&xorDecRegs, &pAddrDecWin->addrWin))
{
mvOsPrintf("%s: ERR. mvCtrlRegToAddrDec failed\n", __FUNCTION__);
return MV_ERROR;
}
/* attrib and targetId */
targetAttrib.attrib =
(xorDecRegs.baseReg & XEBARX_ATTR_MASK) >> XEBARX_ATTR_OFFS;
targetAttrib.targetId =
(xorDecRegs.baseReg & XEBARX_TARGET_MASK) >> XEBARX_TARGET_OFFS;
pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
if(chanWinEn)
{
pAddrDecWin->enable = MV_TRUE;
}
else pAddrDecWin->enable = MV_FALSE;
return MV_OK;
}
/*******************************************************************************
* mvXorTargetWinEnable - Enable/disable a Xor address decode window
*
* DESCRIPTION:
* This function enable/disable a XOR address decode window.
* if parameter 'enable' == MV_TRUE the routine will enable the
* window, thus enabling XOR accesses (before enabling the window it is
* tested for overlapping). Otherwise, the window will be disabled.
*
* INPUT:
* winNum - Decode window number.
* enable - Enable/disable parameter.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
*
*******************************************************************************/
MV_STATUS mvXorTargetWinEnable(MV_U32 unit,MV_U32 winNum, MV_BOOL enable)
{
MV_XOR_DEC_WIN addrDecWin;
MV_U32 chan;
/* Parameter checking */
if (winNum >= XOR_MAX_ADDR_DEC_WIN)
{
DB(mvOsPrintf("%s: ERR. Invalid winNum%d\n", __FUNCTION__, winNum));
return MV_ERROR;
}
if (enable == MV_TRUE)
{
/* Get current window */
if (MV_OK != mvXorTargetWinGet(unit,winNum, &addrDecWin))
{
DB(mvOsPrintf("%s: ERR. targetWinGet fail\n", __FUNCTION__));
return MV_ERROR;
}
/* Check for overlapping */
if (MV_TRUE == xorWinOverlapDetect(unit,winNum, &(addrDecWin.addrWin)))
{
/* Overlap detected */
DB(mvOsPrintf("%s: ERR. Overlap detected\n", __FUNCTION__));
return MV_ERROR;
}
/* No Overlap. Enable address decode target window */
for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++)
{
MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan),
XEXWCR_WIN_EN_MASK(winNum));
}
}
else
{
/* Disable address decode target window */
for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++)
{
MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan),
XEXWCR_WIN_EN_MASK(winNum));
}
}
return MV_OK;
}
/*******************************************************************************
* mvXorSetProtWinSet - Configure access attributes of a XOR engine
* to one of the XOR memory windows.
*
* DESCRIPTION:
* Each engine can be configured with access attributes for each of the
* memory spaces. This function sets access attributes
* to a given window for the given engine
*
* INPUTS:
* chan - One of the possible engines.
* winNum - One of the possible XOR memory spaces.
* access - Protection access rights.
* write - Write rights.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
*
*******************************************************************************/
MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access,
MV_BOOL write)
{
MV_U32 temp;
/* Parameter checking */
if (chan >= MV_XOR_MAX_CHAN_PER_UNIT)
{
DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n", __FUNCTION__ , chan));
return MV_BAD_PARAM;
}
if (winNum >= XOR_MAX_ADDR_DEC_WIN)
{
DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum));
return MV_BAD_PARAM;
}
temp = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) &
(~XEXWCR_WIN_ACC_MASK(winNum));
/* if access is disable */
if (!access)
{
/* disable access */
temp |= XEXWCR_WIN_ACC_NO_ACC(winNum);
}
/* if access is enable */
else
{
/* if write is enable */
if (write)
{
/* enable write */
temp |= XEXWCR_WIN_ACC_RW(winNum);
}
/* if write is disable */
else
{
/* disable write */
temp |= XEXWCR_WIN_ACC_RO(winNum);
}
}
MV_REG_WRITE(XOR_WINDOW_CTRL_REG(unit,chan),temp);
return MV_OK;
}
/*******************************************************************************
* mvXorPciRemap - Set XOR remap register for PCI address windows.
*
* DESCRIPTION:
* only Windows 0-3 can be remapped.
*
* INPUT:
* winNum - window number
* pAddrDecWin - pointer to address space window structure
* OUTPUT:
* None.
*
* RETURN:
* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
*
*******************************************************************************/
MV_STATUS mvXorPciRemap(MV_U32 unit,MV_U32 winNum, MV_U32 addrHigh)
{
/* Parameter checking */
if (winNum >= XOR_MAX_REMAP_WIN)
{
DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum));
return MV_BAD_PARAM;
}
MV_REG_WRITE(XOR_HIGH_ADDR_REMAP_REG(unit,winNum), addrHigh);
return MV_OK;
}
/*******************************************************************************
* xorWinOverlapDetect - Detect XOR address windows overlaping
*
* DESCRIPTION:
* An unpredicted behaviour is expected in case XOR address decode
* windows overlaps.
* This function detects XOR address decode windows overlaping of a
* specified window. The function does not check the window itself for
* overlaping. The function also skipps disabled address decode windows.
*
* INPUT:
* winNum - address decode window number.
* pAddrDecWin - An address decode window struct.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_TRUE if the given address window overlap current address
* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data
* from registers.
*
*******************************************************************************/
static MV_STATUS xorWinOverlapDetect(MV_U32 unit,MV_U32 winNum, MV_ADDR_WIN *pAddrWin)
{
MV_U32 baseAddrEnableReg;
MV_U32 winNumIndex,chan;
MV_XOR_DEC_WIN addrDecWin;
if (pAddrWin == NULL)
{
DB(mvOsPrintf("%s: ERR. pAddrWin is NULL pointer\n", __FUNCTION__ ));
return MV_BAD_PTR;
}
for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++)
{
/* Read base address enable register. Do not check disabled windows */
baseAddrEnableReg = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan));
for (winNumIndex = 0; winNumIndex < XOR_MAX_ADDR_DEC_WIN; winNumIndex++)
{
/* Do not check window itself */
if (winNumIndex == winNum)
{
continue;
}
/* Do not check disabled windows */
if ((baseAddrEnableReg & XEXWCR_WIN_EN_MASK(winNumIndex)) == 0)
{
continue;
}
/* Get window parameters */
if (MV_OK != mvXorTargetWinGet(unit,winNumIndex, &addrDecWin))
{
DB(mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__ ));
return MV_ERROR;
}
if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin)))
{
return MV_TRUE;
}
}
}
return MV_FALSE;
}
static MV_VOID mvXorAddrDecShowUnit(MV_U32 unit)
{
MV_XOR_DEC_WIN win;
int i;
mvOsOutput( "\n" );
mvOsOutput( "XOR %d:\n", unit );
mvOsOutput( "----\n" );
for( i = 0; i < XOR_MAX_ADDR_DEC_WIN; i++ )
{
memset( &win, 0, sizeof(MV_XOR_DEC_WIN) );
mvOsOutput( "win%d - ", i );
if( mvXorTargetWinGet(unit, i, &win ) == MV_OK )
{
if( win.enable )
{
mvOsOutput( "%s base %x, ",
mvCtrlTargetNameGet(win.target), win.addrWin.baseLow );
mvSizePrint( win.addrWin.size );
mvOsOutput( "\n" );
}
else
mvOsOutput( "disable\n" );
}
}
}
/*******************************************************************************
* mvXorAddrDecShow - Print the XOR address decode map.
*
* DESCRIPTION:
* This function print the XOR address decode map.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_VOID mvXorAddrDecShow(MV_VOID)
{
int i;
for( i = 0; i < MV_XOR_MAX_UNIT; i++ )
mvXorAddrDecShowUnit(i);
}

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