add patches for 2.6.23 on brcm47xx (not enabled yet)

SVN-Revision: 9279

target/linux/brcm47xx/config-2.6.23

@@ -0,0 +1,242 @@
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+# CONFIG_8139TOO is not set
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_ARPD is not set
+# CONFIG_ATMEL is not set
+CONFIG_B44=y
+CONFIG_BASE_SMALL=0
+# CONFIG_BCM43XX is not set
+CONFIG_BCM947XX=y
+CONFIG_BITREVERSE=y
+# CONFIG_BONDING is not set
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIVHCI is not set
+CONFIG_CFE=y
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CLS_U32_MARK is not set
+# CONFIG_CLS_U32_PERF is not set
+CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 init=/etc/preinit noinitrd console=ttyS0,115200"
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_CONNECTOR=m
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_CPU_LOONGSON2 is not set
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+CONFIG_CPU_MIPSR1=y
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CRYPTO_HW is not set
+CONFIG_DEVPORT=y
+# CONFIG_DM9000 is not set
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_E100 is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HID=m
+# CONFIG_HID_SUPPORT is not set
+CONFIG_HW_HAS_PCI=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ=250
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_I2C is not set
+# CONFIG_IDE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=m
+# CONFIG_IP6_NF_MATCH_FRAG is not set
+# CONFIG_IP6_NF_MATCH_HL is not set
+# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set
+# CONFIG_IP6_NF_MATCH_OPTS is not set
+# CONFIG_IP6_NF_MATCH_RT is not set
+# CONFIG_IP6_NF_TARGET_HL is not set
+CONFIG_IPW2200_QOS=y
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IRQ_CPU=y
+# CONFIG_LEDS_GPIO is not set
+# CONFIG_LEMOTE_FULONG is not set
+# CONFIG_LLC2 is not set
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_MACH_VR41XX is not set
+CONFIG_MIPS=y
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_COBALT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MALTA is not set
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+# CONFIG_MIPS_SEAD is not set
+# CONFIG_MIPS_SIM is not set
+CONFIG_MTD=y
+# CONFIG_MTD_ABSENT is not set
+CONFIG_MTD_BCM47XX=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_MTD_BLOCK2MTD is not set
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_CHAR=y
+# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_ONENAND is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PLATRAM is not set
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_IPGRE_BROADCAST is not set
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NO_IOPORT is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_SYNC_TTY is not set
+# CONFIG_PROC_KCORE is not set
+# CONFIG_RTC is not set
+# CONFIG_RTL8187 is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_WAIT_SCAN=m
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+# CONFIG_SERIAL_8250_RSA is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_PTSWARM is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SSB=y
+CONFIG_SSB_DEBUG=y
+CONFIG_SSB_DRIVER_EXTIF=y
+CONFIG_SSB_DRIVER_MIPS=y
+CONFIG_SSB_DRIVER_PCICORE=y
+CONFIG_SSB_PCICORE_HOSTMODE=y
+CONFIG_SSB_PCIHOST=y
+CONFIG_SSB_SERIAL=y
+# CONFIG_SSB_SILENT is not set
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+# CONFIG_TC35815 is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_TOSHIBA_RBTX4927 is not set
+# CONFIG_TOSHIBA_RBTX4938 is not set
+CONFIG_TRAD_SIGNALS=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_USB_CATC is not set
+CONFIG_USB_EHCI_HCD=m
+CONFIG_USB_EHCI_SPLIT_ISO=y
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_HCD=m
+# CONFIG_USB_OHCI_HCD_SSB is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+CONFIG_USB_UHCI_HCD=m
+# CONFIG_USER_NS is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_ZONE_DMA_FLAG=0

target/linux/brcm47xx/files/arch/mips/bcm947xx/setup.c

@@ -31,6 +31,7 @@
 #include <linux/serial.h>
 #include <linux/serial_core.h>
 #include <linux/serial_reg.h>
+#include <linux/serial_8250.h>
 #include <asm/bootinfo.h>
 #include <asm/time.h>
 #include <asm/reboot.h>
@@ -107,13 +108,27 @@ static void bcm47xx_fill_sprom_nvram(struct ssb_sprom *sprom)
 		sprom->r1.et1phyaddr = simple_strtoul(s, NULL, 10);
 }
 
+static int bcm47xx_get_invariants(struct ssb_bus *bus, struct ssb_init_invariants *iv)
+{
+	char *s;
+	
+	// TODO
+	//iv->boardinfo.vendor = 
+	if ((s = nvram_get("boardtype")))
+		iv->boardinfo.type = (u16)simple_strtoul(s, NULL, 0);
+	if ((s = nvram_get("boardrev")))
+		iv->boardinfo.rev = (u16)simple_strtoul(s, NULL, 0);
+	bcm47xx_fill_sprom(&iv->sprom);
+	return 0;
+}
+
 void __init plat_mem_setup(void)
 {
 	int i, err;
 	char *s;
 	struct ssb_mipscore *mcore;
 
-	err = ssb_bus_ssbbus_register(&ssb, SSB_ENUM_BASE, bcm47xx_fill_sprom);
+	err = ssb_bus_ssbbus_register(&ssb, SSB_ENUM_BASE, bcm47xx_get_invariants);
 	if (err) {
 		const char *msg = "Failed to initialize SSB bus (err %d)\n";
 		cfe_printk(msg, err); /* Make sure the message gets out of the box. */

target/linux/brcm47xx/patches-2.6.22/230-ssb_arch_setup.patch

@@ -1,33 +0,0 @@
-Index: linux-2.6.22-rc5/arch/mips/bcm947xx/setup.c
-===================================================================
---- linux-2.6.22-rc5.orig/arch/mips/bcm947xx/setup.c	2007-06-24 19:51:21.000000000 +0100
-+++ linux-2.6.22-rc5/arch/mips/bcm947xx/setup.c	2007-06-24 20:26:12.000000000 +0100
-@@ -107,13 +107,27 @@
- 		sprom->r1.et1phyaddr = simple_strtoul(s, NULL, 10);
- }
- 
-+static int bcm47xx_get_invariants(struct ssb_bus *bus, struct ssb_init_invariants *iv)
-+{
-+	char *s;
-+	
-+	// TODO
-+	//iv->boardinfo.vendor = 
-+	if ((s = nvram_get("boardtype")))
-+		iv->boardinfo.type = (u16)simple_strtoul(s, NULL, 0);
-+	if ((s = nvram_get("boardrev")))
-+		iv->boardinfo.rev = (u16)simple_strtoul(s, NULL, 0);
-+	bcm47xx_fill_sprom(&iv->sprom);
-+	return 0;
-+}
-+
- void __init plat_mem_setup(void)
- {
- 	int i, err;
- 	char *s;
- 	struct ssb_mipscore *mcore;
- 
--	err = ssb_bus_ssbbus_register(&ssb, SSB_ENUM_BASE, bcm47xx_fill_sprom);
-+	err = ssb_bus_ssbbus_register(&ssb, SSB_ENUM_BASE, bcm47xx_get_invariants);
- 	if (err) {
- 		const char *msg = "Failed to initialize SSB bus (err %d)\n";
- 		cfe_printk(msg, err); /* Make sure the message gets out of the box. */

target/linux/brcm47xx/patches-2.6.23/100-board_support.patch

@@ -0,0 +1,212 @@
+Index: linux-2.6.23/arch/mips/Kconfig
+===================================================================
+--- linux-2.6.23.orig/arch/mips/Kconfig	2007-10-13 02:23:06.662507926 +0200
++++ linux-2.6.23/arch/mips/Kconfig	2007-10-13 02:23:41.484492317 +0200
+@@ -4,6 +4,10 @@
+ 	# Horrible source of confusion.  Die, die, die ...
+ 	select EMBEDDED
+ 
++config CFE
++	bool
++	# Common Firmware Environment
++
+ mainmenu "Linux/MIPS Kernel Configuration"
+ 
+ menu "Machine selection"
+@@ -44,6 +48,23 @@
+ 	  note that a kernel built with this option selected will not be
+ 	  able to run on normal units.
+ 
++config BCM947XX
++	bool "Support for BCM947xx based boards"
++	select DMA_NONCOHERENT
++	select HW_HAS_PCI
++	select IRQ_CPU
++	select SYS_HAS_CPU_MIPS32_R1
++	select SYS_SUPPORTS_32BIT_KERNEL
++	select SYS_SUPPORTS_LITTLE_ENDIAN
++	select SSB
++	select SSB_SERIAL
++	select SSB_DRIVER_PCICORE
++	select SSB_PCICORE_HOSTMODE
++	select CFE
++	select GENERIC_GPIO
++	help
++	 Support for BCM947xx based boards
++
+ config MIPS_COBALT
+ 	bool "Cobalt Server"
+ 	select DMA_NONCOHERENT
+Index: linux-2.6.23/arch/mips/kernel/cpu-probe.c
+===================================================================
+--- linux-2.6.23.orig/arch/mips/kernel/cpu-probe.c	2007-10-13 02:23:06.666508151 +0200
++++ linux-2.6.23/arch/mips/kernel/cpu-probe.c	2007-10-13 02:23:11.210767122 +0200
+@@ -793,6 +793,28 @@
+ }
+ 
+ 
++static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
++{
++	decode_config1(c);
++	switch (c->processor_id & 0xff00) {
++		case PRID_IMP_BCM3302:
++			c->cputype = CPU_BCM3302;
++			c->isa_level = MIPS_CPU_ISA_M32R1;
++			c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
++					MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
++		break;
++		case PRID_IMP_BCM4710:
++			c->cputype = CPU_BCM4710;
++			c->isa_level = MIPS_CPU_ISA_M32R1;
++			c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
++					MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
++		break;
++	default:
++		c->cputype = CPU_UNKNOWN;
++		break;
++	}
++}
++
+ __init void cpu_probe(void)
+ {
+ 	struct cpuinfo_mips *c = &current_cpu_data;
+@@ -815,6 +837,9 @@
+ 	case PRID_COMP_SIBYTE:
+ 		cpu_probe_sibyte(c);
+ 		break;
++	case PRID_COMP_BROADCOM:
++		cpu_probe_broadcom(c);
++		break;
+ 	case PRID_COMP_SANDCRAFT:
+ 		cpu_probe_sandcraft(c);
+ 		break;
+Index: linux-2.6.23/arch/mips/kernel/proc.c
+===================================================================
+--- linux-2.6.23.orig/arch/mips/kernel/proc.c	2007-10-13 02:23:06.678508839 +0200
++++ linux-2.6.23/arch/mips/kernel/proc.c	2007-10-13 02:23:11.210767122 +0200
+@@ -82,6 +82,8 @@
+ 	[CPU_VR4181]	= "NEC VR4181",
+ 	[CPU_VR4181A]	= "NEC VR4181A",
+ 	[CPU_SR71000]	= "Sandcraft SR71000",
++	[CPU_BCM3302]	= "Broadcom BCM3302",
++	[CPU_BCM4710]	= "Broadcom BCM4710",
+ 	[CPU_PR4450]	= "Philips PR4450",
+ 	[CPU_LOONGSON2]	= "ICT Loongson-2",
+ };
+Index: linux-2.6.23/arch/mips/Makefile
+===================================================================
+--- linux-2.6.23.orig/arch/mips/Makefile	2007-10-13 02:23:06.682509066 +0200
++++ linux-2.6.23/arch/mips/Makefile	2007-10-13 02:23:11.210767122 +0200
+@@ -533,6 +533,18 @@
+ load-$(CONFIG_SIBYTE_BIGSUR)	:= 0xffffffff80100000
+ 
+ #
++# Broadcom BCM47XX boards
++#
++core-$(CONFIG_BCM947XX)		+= arch/mips/bcm947xx/
++cflags-$(CONFIG_BCM947XX)	+= -Iarch/mips/bcm947xx/include -Iinclude/asm-mips/mach-bcm947xx
++load-$(CONFIG_BCM947XX)		:= 0xffffffff80001000
++
++#
++# Common Firmware Environment
++#
++core-$(CONFIG_CFE)		+= arch/mips/cfe/
++
++#
+ # SNI RM
+ #
+ core-$(CONFIG_SNI_RM)		+= arch/mips/sni/
+Index: linux-2.6.23/arch/mips/mm/tlbex.c
+===================================================================
+--- linux-2.6.23.orig/arch/mips/mm/tlbex.c	2007-10-13 02:23:06.694509748 +0200
++++ linux-2.6.23/arch/mips/mm/tlbex.c	2007-10-13 02:26:00.272401391 +0200
+@@ -895,6 +895,8 @@
+ 	case CPU_AU1550:
+ 	case CPU_AU1200:
+ 	case CPU_PR4450:
++	case CPU_BCM3302:
++	case CPU_BCM4710:
+ 		i_nop(p);
+ 		tlbw(p);
+ 		break;
+Index: linux-2.6.23/drivers/Kconfig
+===================================================================
+--- linux-2.6.23.orig/drivers/Kconfig	2007-10-13 02:23:06.702510206 +0200
++++ linux-2.6.23/drivers/Kconfig	2007-10-13 02:23:11.214767346 +0200
+@@ -58,6 +58,8 @@
+ 
+ source "drivers/hwmon/Kconfig"
+ 
++source "drivers/ssb/Kconfig"
++
+ source "drivers/mfd/Kconfig"
+ 
+ source "drivers/media/Kconfig"
+Index: linux-2.6.23/drivers/Makefile
+===================================================================
+--- linux-2.6.23.orig/drivers/Makefile	2007-10-13 02:23:06.710510659 +0200
++++ linux-2.6.23/drivers/Makefile	2007-10-13 02:27:08.120267817 +0200
+@@ -88,3 +88,4 @@
+ obj-$(CONFIG_HID)		+= hid/
+ obj-$(CONFIG_PPC_PS3)		+= ps3/
+ obj-$(CONFIG_OF)		+= of/
++obj-$(CONFIG_SSB)		+= ssb/
+Index: linux-2.6.23/include/asm-mips/bootinfo.h
+===================================================================
+--- linux-2.6.23.orig/include/asm-mips/bootinfo.h	2007-10-13 02:23:06.718511119 +0200
++++ linux-2.6.23/include/asm-mips/bootinfo.h	2007-10-13 02:23:11.214767346 +0200
+@@ -208,6 +208,12 @@
+ #define MACH_GROUP_WINDRIVER   28	/* Windriver boards */
+ #define MACH_WRPPMC             1
+ 
++/*
++ * Valid machtype for group Broadcom
++ */
++#define MACH_GROUP_BRCM		23	/* Broadcom			*/
++#define MACH_BCM47XX		1	/* Broadcom BCM47xx		*/
++
+ #define CL_SIZE			COMMAND_LINE_SIZE
+ 
+ const char *get_system_type(void);
+Index: linux-2.6.23/include/asm-mips/cpu.h
+===================================================================
+--- linux-2.6.23.orig/include/asm-mips/cpu.h	2007-10-13 02:23:06.726511570 +0200
++++ linux-2.6.23/include/asm-mips/cpu.h	2007-10-13 02:27:43.994312161 +0200
+@@ -106,6 +106,13 @@
+ #define PRID_IMP_SR71000        0x0400
+ 
+ /*
++ * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
++ */
++
++#define PRID_IMP_BCM4710	0x4000
++#define PRID_IMP_BCM3302	0x9000
++
++/*
+  * Definitions for 7:0 on legacy processors
+  */
+ 
+@@ -217,8 +224,10 @@
+ #define CPU_R14000		64
+ #define CPU_LOONGSON1           65
+ #define CPU_LOONGSON2           66
++#define CPU_BCM3302		67
++#define CPU_BCM4710		68
+ 
+-#define CPU_LAST		66
++#define CPU_LAST		68
+ 
+ /*
+  * ISA Level encodings
+Index: linux-2.6.23/include/linux/pci_ids.h
+===================================================================
+--- linux-2.6.23.orig/include/linux/pci_ids.h	2007-10-13 02:23:06.734512028 +0200
++++ linux-2.6.23/include/linux/pci_ids.h	2007-10-13 02:23:11.218767569 +0200
+@@ -1972,6 +1972,7 @@
+ #define PCI_DEVICE_ID_TIGON3_5906M	0x1713
+ #define PCI_DEVICE_ID_BCM4401		0x4401
+ #define PCI_DEVICE_ID_BCM4401B0		0x4402
++#define PCI_DEVICE_ID_BCM4713		0x4713
+ 
+ #define PCI_VENDOR_ID_TOPIC		0x151f
+ #define PCI_DEVICE_ID_TOPIC_TP560	0x0000

target/linux/brcm47xx/patches-2.6.23/110-flash_map.patch

@@ -0,0 +1,29 @@
+Index: linux-2.6.23/drivers/mtd/maps/Kconfig
+===================================================================
+--- linux-2.6.23.orig/drivers/mtd/maps/Kconfig	2007-10-09 22:31:38.000000000 +0200
++++ linux-2.6.23/drivers/mtd/maps/Kconfig	2007-10-13 02:28:13.644001805 +0200
+@@ -352,6 +352,12 @@
+ 	  Mapping for the Flaga digital module. If you don't have one, ignore
+ 	  this setting.
+ 
++config MTD_BCM47XX
++	tristate "BCM47xx flash device"
++	depends on MIPS && MTD_CFI && BCM947XX
++	help
++	  Support for the flash chips on the BCM947xx board.
++
+ config MTD_WALNUT
+ 	tristate "Flash device mapped on IBM 405GP Walnut"
+ 	depends on MTD_JEDECPROBE && WALNUT
+Index: linux-2.6.23/drivers/mtd/maps/Makefile
+===================================================================
+--- linux-2.6.23.orig/drivers/mtd/maps/Makefile	2007-10-09 22:31:38.000000000 +0200
++++ linux-2.6.23/drivers/mtd/maps/Makefile	2007-10-13 02:27:56.727037761 +0200
+@@ -33,6 +33,7 @@
+ obj-$(CONFIG_MTD_PCMCIA)	+= pcmciamtd.o
+ obj-$(CONFIG_MTD_RPXLITE)	+= rpxlite.o
+ obj-$(CONFIG_MTD_TQM8XXL)	+= tqm8xxl.o
++obj-$(CONFIG_MTD_BCM47XX)	+= bcm47xx-flash.o
+ obj-$(CONFIG_MTD_SA1100)	+= sa1100-flash.o
+ obj-$(CONFIG_MTD_IPAQ)		+= ipaq-flash.o
+ obj-$(CONFIG_MTD_SBC_GXX)	+= sbc_gxx.o

target/linux/brcm47xx/patches-2.6.23/130-remove_scache.patch

@@ -0,0 +1,97 @@
+Index: linux-2.6.23/arch/mips/Kconfig
+===================================================================
+--- linux-2.6.23.orig/arch/mips/Kconfig	2007-10-13 02:23:41.484492317 +0200
++++ linux-2.6.23/arch/mips/Kconfig	2007-10-13 02:47:02.784347843 +0200
+@@ -192,7 +192,6 @@
+ 	select I8259
+ 	select MIPS_BOARDS_GEN
+ 	select MIPS_BONITO64
+-	select MIPS_CPU_SCACHE
+ 	select PCI_GT64XXX_PCI0
+ 	select MIPS_MSC
+ 	select SWAP_IO_SPACE
+@@ -1281,13 +1280,6 @@
+ 	bool
+ 	select BOARD_SCACHE
+ 
+-#
+-# Support for a MIPS32 / MIPS64 style S-caches
+-#
+-config MIPS_CPU_SCACHE
+-	bool
+-	select BOARD_SCACHE
+-
+ config R5000_CPU_SCACHE
+ 	bool
+ 	select BOARD_SCACHE
+Index: linux-2.6.23/arch/mips/kernel/cpu-probe.c
+===================================================================
+--- linux-2.6.23.orig/arch/mips/kernel/cpu-probe.c	2007-10-13 02:23:11.210767122 +0200
++++ linux-2.6.23/arch/mips/kernel/cpu-probe.c	2007-10-13 02:47:02.788348072 +0200
+@@ -701,6 +701,8 @@
+ 		break;
+ 	case PRID_IMP_25KF:
+ 		c->cputype = CPU_25KF;
++		/* Probe for L2 cache */
++		c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
+ 		break;
+ 	case PRID_IMP_34K:
+ 		c->cputype = CPU_34K;
+Index: linux-2.6.23/arch/mips/mm/c-r4k.c
+===================================================================
+--- linux-2.6.23.orig/arch/mips/mm/c-r4k.c	2007-10-09 22:31:38.000000000 +0200
++++ linux-2.6.23/arch/mips/mm/c-r4k.c	2007-10-13 02:47:02.792348301 +0200
+@@ -1086,7 +1086,6 @@
+ 
+ extern int r5k_sc_init(void);
+ extern int rm7k_sc_init(void);
+-extern int mips_sc_init(void);
+ 
+ static void __init setup_scache(void)
+ {
+@@ -1140,29 +1139,17 @@
+ #endif
+ 
+ 	default:
+-		if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
+-		    c->isa_level == MIPS_CPU_ISA_M32R2 ||
+-		    c->isa_level == MIPS_CPU_ISA_M64R1 ||
+-		    c->isa_level == MIPS_CPU_ISA_M64R2) {
+-#ifdef CONFIG_MIPS_CPU_SCACHE
+-			if (mips_sc_init ()) {
+-				scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
+-				printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
+-				       scache_size >> 10,
+-				       way_string[c->scache.ways], c->scache.linesz);
+-			}
+-#else
+-			if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
+-				panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
+-#endif
+-			return;
+-		}
+ 		sc_present = 0;
+ 	}
+ 
+ 	if (!sc_present)
+ 		return;
+ 
++	if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
++	     c->isa_level == MIPS_CPU_ISA_M64R1) &&
++	    !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
++		panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
++
+ 	/* compute a couple of other cache variables */
+ 	c->scache.waysize = scache_size / c->scache.ways;
+ 
+Index: linux-2.6.23/arch/mips/mm/Makefile
+===================================================================
+--- linux-2.6.23.orig/arch/mips/mm/Makefile	2007-10-09 22:31:38.000000000 +0200
++++ linux-2.6.23/arch/mips/mm/Makefile	2007-10-13 02:47:23.393522295 +0200
+@@ -31,6 +31,5 @@
+ obj-$(CONFIG_IP22_CPU_SCACHE)	+= sc-ip22.o
+ obj-$(CONFIG_R5000_CPU_SCACHE)  += sc-r5k.o
+ obj-$(CONFIG_RM7000_CPU_SCACHE)	+= sc-rm7k.o
+-obj-$(CONFIG_MIPS_CPU_SCACHE)	+= sc-mips.o
+ 
+ EXTRA_CFLAGS += -Werror

target/linux/brcm47xx/patches-2.6.23/150-cpu_fixes.patch

@@ -0,0 +1,643 @@
+Index: linux-2.6.23/arch/mips/kernel/genex.S
+===================================================================
+--- linux-2.6.23.orig/arch/mips/kernel/genex.S	2007-10-09 22:31:38.000000000 +0200
++++ linux-2.6.23/arch/mips/kernel/genex.S	2007-10-13 02:47:32.546043867 +0200
+@@ -51,6 +51,10 @@
+ NESTED(except_vec3_generic, 0, sp)
+ 	.set	push
+ 	.set	noat
++#ifdef CONFIG_BCM947XX
++	nop
++	nop
++#endif
+ #if R5432_CP0_INTERRUPT_WAR
+ 	mfc0	k0, CP0_INDEX
+ #endif
+Index: linux-2.6.23/arch/mips/mm/c-r4k.c
+===================================================================
+--- linux-2.6.23.orig/arch/mips/mm/c-r4k.c	2007-10-13 02:47:02.792348301 +0200
++++ linux-2.6.23/arch/mips/mm/c-r4k.c	2007-10-13 02:55:35.877587360 +0200
+@@ -30,6 +30,9 @@
+ #include <asm/cacheflush.h> /* for run_uncached() */
+ 
+ 
++/* For enabling BCM4710 cache workarounds */
++int bcm4710 = 0;
++
+ /*
+  * Special Variant of smp_call_function for use by cache functions:
+  *
+@@ -86,14 +89,21 @@
+ 
+ static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
+ {
++	unsigned long flags;
++
++	local_irq_save(flags);
+ 	R4600_HIT_CACHEOP_WAR_IMPL;
+ 	blast_dcache32_page(addr);
++	local_irq_restore(flags);
+ }
+ 
+ static void __init r4k_blast_dcache_page_setup(void)
+ {
+ 	unsigned long  dc_lsize = cpu_dcache_line_size();
+ 
++	if (bcm4710)
++		r4k_blast_dcache_page = blast_dcache_page;
++	else
+ 	if (dc_lsize == 0)
+ 		r4k_blast_dcache_page = (void *)cache_noop;
+ 	else if (dc_lsize == 16)
+@@ -108,6 +118,9 @@
+ {
+ 	unsigned long dc_lsize = cpu_dcache_line_size();
+ 
++	if (bcm4710)
++		r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
++	else
+ 	if (dc_lsize == 0)
+ 		r4k_blast_dcache_page_indexed = (void *)cache_noop;
+ 	else if (dc_lsize == 16)
+@@ -122,6 +135,9 @@
+ {
+ 	unsigned long dc_lsize = cpu_dcache_line_size();
+ 
++	if (bcm4710)
++		r4k_blast_dcache = blast_dcache;
++	else
+ 	if (dc_lsize == 0)
+ 		r4k_blast_dcache = (void *)cache_noop;
+ 	else if (dc_lsize == 16)
+@@ -203,8 +219,12 @@
+ 
+ static void (* r4k_blast_icache_page)(unsigned long addr);
+ 
++static void r4k_flush_cache_all(void);
+ static void __init r4k_blast_icache_page_setup(void)
+ {
++#ifdef CONFIG_BCM947XX
++	r4k_blast_icache_page = (void *)r4k_flush_cache_all;
++#else
+ 	unsigned long ic_lsize = cpu_icache_line_size();
+ 
+ 	if (ic_lsize == 0)
+@@ -215,6 +235,7 @@
+ 		r4k_blast_icache_page = blast_icache32_page;
+ 	else if (ic_lsize == 64)
+ 		r4k_blast_icache_page = blast_icache64_page;
++#endif
+ }
+ 
+ 
+@@ -222,6 +243,9 @@
+ 
+ static void __init r4k_blast_icache_page_indexed_setup(void)
+ {
++#ifdef CONFIG_BCM947XX
++	r4k_blast_icache_page_indexed = (void *)r4k_flush_cache_all;
++#else
+ 	unsigned long ic_lsize = cpu_icache_line_size();
+ 
+ 	if (ic_lsize == 0)
+@@ -240,6 +264,7 @@
+ 				blast_icache32_page_indexed;
+ 	} else if (ic_lsize == 64)
+ 		r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
++#endif
+ }
+ 
+ static void (* r4k_blast_icache)(void);
+@@ -323,12 +348,17 @@
+  */
+ static inline void local_r4k_flush_cache_all(void * args)
+ {
++	unsigned long flags;
++
++	local_irq_save(flags);
+ 	r4k_blast_dcache();
++	r4k_blast_icache();
++	local_irq_restore(flags);
+ }
+ 
+ static void r4k_flush_cache_all(void)
+ {
+-	if (!cpu_has_dc_aliases)
++	if (!cpu_has_dc_aliases && cpu_use_kmap_coherent)
+ 		return;
+ 
+ 	r4k_on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1);
+@@ -336,6 +366,9 @@
+ 
+ static inline void local_r4k___flush_cache_all(void * args)
+ {
++	unsigned long flags;
++
++	local_irq_save(flags);
+ #if defined(CONFIG_CPU_LOONGSON2)
+ 	r4k_blast_scache();
+ 	return;
+@@ -353,6 +386,7 @@
+ 	case CPU_R14000:
+ 		r4k_blast_scache();
+ 	}
++	local_irq_restore(flags);
+ }
+ 
+ static void r4k___flush_cache_all(void)
+@@ -363,17 +397,21 @@
+ static inline void local_r4k_flush_cache_range(void * args)
+ {
+ 	struct vm_area_struct *vma = args;
++	unsigned long flags;
+ 
+ 	if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
+ 		return;
+ 
++	local_irq_save(flags);
+ 	r4k_blast_dcache();
++	r4k_blast_icache();
++	local_irq_restore(flags);
+ }
+ 
+ static void r4k_flush_cache_range(struct vm_area_struct *vma,
+ 	unsigned long start, unsigned long end)
+ {
+-	if (!cpu_has_dc_aliases)
++	if (!cpu_has_dc_aliases && cpu_use_kmap_coherent)
+ 		return;
+ 
+ 	r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
+@@ -382,6 +420,7 @@
+ static inline void local_r4k_flush_cache_mm(void * args)
+ {
+ 	struct mm_struct *mm = args;
++	unsigned long flags;
+ 
+ 	if (!cpu_context(smp_processor_id(), mm))
+ 		return;
+@@ -400,12 +439,15 @@
+ 		return;
+ 	}
+ 
++	local_irq_save(flags);
+ 	r4k_blast_dcache();
++	r4k_blast_icache();
++	local_irq_restore(flags);
+ }
+ 
+ static void r4k_flush_cache_mm(struct mm_struct *mm)
+ {
+-	if (!cpu_has_dc_aliases)
++	if (!cpu_has_dc_aliases && cpu_use_kmap_coherent)
+ 		return;
+ 
+ 	r4k_on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1);
+@@ -425,6 +467,7 @@
+ 	unsigned long paddr = fcp_args->pfn << PAGE_SHIFT;
+ 	int exec = vma->vm_flags & VM_EXEC;
+ 	struct mm_struct *mm = vma->vm_mm;
++	unsigned long flags;
+ 	pgd_t *pgdp;
+ 	pud_t *pudp;
+ 	pmd_t *pmdp;
+@@ -456,8 +499,9 @@
+ 	 * for every cache flush operation.  So we do indexed flushes
+ 	 * in that case, which doesn't overly flush the cache too much.
+ 	 */
++	local_irq_save(flags);
+ 	if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
+-		if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
++		if (!cpu_use_kmap_coherent || cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
+ 			r4k_blast_dcache_page(addr);
+ 			if (exec && !cpu_icache_snoops_remote_store)
+ 				r4k_blast_scache_page(addr);
+@@ -465,14 +509,14 @@
+ 		if (exec)
+ 			r4k_blast_icache_page(addr);
+ 
+-		return;
++		goto done;
+ 	}
+ 
+ 	/*
+ 	 * Do indexed flush, too much work to get the (possible) TLB refills
+ 	 * to work correctly.
+ 	 */
+-	if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
++	if (!cpu_use_kmap_coherent || cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
+ 		r4k_blast_dcache_page_indexed(cpu_has_pindexed_dcache ?
+ 					      paddr : addr);
+ 		if (exec && !cpu_icache_snoops_remote_store) {
+@@ -488,6 +532,8 @@
+ 		} else
+ 			r4k_blast_icache_page_indexed(addr);
+ 	}
++done:
++	local_irq_restore(flags);
+ }
+ 
+ static void r4k_flush_cache_page(struct vm_area_struct *vma,
+@@ -504,7 +550,11 @@
+ 
+ static inline void local_r4k_flush_data_cache_page(void * addr)
+ {
++	unsigned long flags;
++
++	local_irq_save(flags);
+ 	r4k_blast_dcache_page((unsigned long) addr);
++	local_irq_restore(flags);
+ }
+ 
+ static void r4k_flush_data_cache_page(unsigned long addr)
+@@ -547,6 +597,9 @@
+ 
+ static void r4k_flush_icache_range(unsigned long start, unsigned long end)
+ {
++#ifdef CONFIG_BCM947XX
++	r4k_flush_cache_all();
++#else
+ 	struct flush_icache_range_args args;
+ 
+ 	args.start = start;
+@@ -554,12 +607,15 @@
+ 
+ 	r4k_on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
+ 	instruction_hazard();
++#endif
+ }
+ 
+ #ifdef CONFIG_DMA_NONCOHERENT
+ 
+ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
+ {
++	unsigned long flags;
++
+ 	/* Catch bad driver code */
+ 	BUG_ON(size == 0);
+ 
+@@ -576,18 +632,21 @@
+ 	 * subset property so we have to flush the primary caches
+ 	 * explicitly
+ 	 */
++	local_irq_save(flags);
+ 	if (size >= dcache_size) {
+ 		r4k_blast_dcache();
+ 	} else {
+ 		R4600_HIT_CACHEOP_WAR_IMPL;
+ 		blast_dcache_range(addr, addr + size);
+ 	}
+-
+ 	bc_wback_inv(addr, size);
++	local_irq_restore(flags);
+ }
+ 
+ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
+ {
++	unsigned long flags;
++
+ 	/* Catch bad driver code */
+ 	BUG_ON(size == 0);
+ 
+@@ -599,6 +658,7 @@
+ 		return;
+ 	}
+ 
++	local_irq_save(flags);
+ 	if (size >= dcache_size) {
+ 		r4k_blast_dcache();
+ 	} else {
+@@ -607,6 +667,7 @@
+ 	}
+ 
+ 	bc_inv(addr, size);
++	local_irq_restore(flags);
+ }
+ #endif /* CONFIG_DMA_NONCOHERENT */
+ 
+@@ -621,8 +682,12 @@
+ 	unsigned long dc_lsize = cpu_dcache_line_size();
+ 	unsigned long sc_lsize = cpu_scache_line_size();
+ 	unsigned long addr = (unsigned long) arg;
++	unsigned long flags;
+ 
++	local_irq_save(flags);
+ 	R4600_HIT_CACHEOP_WAR_IMPL;
++	BCM4710_PROTECTED_FILL_TLB(addr);
++	BCM4710_PROTECTED_FILL_TLB(addr + 4);
+ 	if (dc_lsize)
+ 		protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
+ 	if (!cpu_icache_snoops_remote_store && scache_size)
+@@ -649,6 +714,7 @@
+ 	}
+ 	if (MIPS_CACHE_SYNC_WAR)
+ 		__asm__ __volatile__ ("sync");
++	local_irq_restore(flags);
+ }
+ 
+ static void r4k_flush_cache_sigtramp(unsigned long addr)
+@@ -1198,6 +1264,17 @@
+ 	 * silly idea of putting something else there ...
+ 	 */
+ 	switch (current_cpu_data.cputype) {
++	case CPU_BCM3302:
++		{
++			u32 cm;
++			cm = read_c0_diag();
++			/* Enable icache */
++			cm |= (1 << 31);
++			/* Enable dcache */
++			cm |= (1 << 30);
++			write_c0_diag(cm);
++		}
++		break;
+ 	case CPU_R4000PC:
+ 	case CPU_R4000SC:
+ 	case CPU_R4000MC:
+@@ -1228,6 +1305,15 @@
+ 	/* Default cache error handler for R4000 and R5000 family */
+ 	set_uncached_handler (0x100, &except_vec2_generic, 0x80);
+ 
++	/* Check if special workarounds are required */
++#ifdef CONFIG_BCM947XX
++	if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
++		printk("Enabling BCM4710A0 cache workarounds.\n");
++		bcm4710 = 1;
++	} else
++#endif
++		bcm4710 = 0;
++
+ 	probe_pcache();
+ 	setup_scache();
+ 
+@@ -1273,5 +1359,13 @@
+ 	build_clear_page();
+ 	build_copy_page();
+ 	local_r4k___flush_cache_all(NULL);
++#ifdef CONFIG_BCM947XX
++	{
++		static void (*_coherency_setup)(void);
++		_coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
++		_coherency_setup();
++	}
++#else
+ 	coherency_setup();
++#endif
+ }
+Index: linux-2.6.23/arch/mips/mm/tlbex.c
+===================================================================
+--- linux-2.6.23.orig/arch/mips/mm/tlbex.c	2007-10-13 02:26:00.272401391 +0200
++++ linux-2.6.23/arch/mips/mm/tlbex.c	2007-10-13 02:47:32.550044103 +0200
+@@ -1247,6 +1247,10 @@
+ #endif
+ }
+ 
++#ifdef CONFIG_BCM947XX
++extern int bcm4710;
++#endif
++
+ static void __init build_r4000_tlb_refill_handler(void)
+ {
+ 	u32 *p = tlb_handler;
+@@ -1261,6 +1265,10 @@
+ 	memset(relocs, 0, sizeof(relocs));
+ 	memset(final_handler, 0, sizeof(final_handler));
+ 
++#ifdef CONFIG_BCM947XX
++	i_nop(&p);
++#endif
++
+ 	/*
+ 	 * create the plain linear handler
+ 	 */
+@@ -1756,6 +1764,9 @@
+ 	memset(labels, 0, sizeof(labels));
+ 	memset(relocs, 0, sizeof(relocs));
+ 
++#ifdef CONFIG_BCM947XX
++	i_nop(&p);
++#endif
+ 	if (bcm1250_m3_war()) {
+ 		i_MFC0(&p, K0, C0_BADVADDR);
+ 		i_MFC0(&p, K1, C0_ENTRYHI);
+Index: linux-2.6.23/include/asm-mips/r4kcache.h
+===================================================================
+--- linux-2.6.23.orig/include/asm-mips/r4kcache.h	2007-10-09 22:31:38.000000000 +0200
++++ linux-2.6.23/include/asm-mips/r4kcache.h	2007-10-13 02:47:32.554044332 +0200
+@@ -17,6 +17,20 @@
+ #include <asm/cpu-features.h>
+ #include <asm/mipsmtregs.h>
+ 
++#ifdef CONFIG_BCM947XX
++#include <asm/paccess.h>
++#include <linux/ssb/ssb.h>
++#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE + SSB_IMSTATE)))
++
++#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
++#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
++#else
++#define BCM4710_DUMMY_RREG()
++
++#define BCM4710_FILL_TLB(addr)
++#define BCM4710_PROTECTED_FILL_TLB(addr)
++#endif
++
+ /*
+  * This macro return a properly sign-extended address suitable as base address
+  * for indexed cache operations.  Two issues here:
+@@ -150,6 +164,7 @@
+ static inline void flush_dcache_line_indexed(unsigned long addr)
+ {
+ 	__dflush_prologue
++	BCM4710_DUMMY_RREG();
+ 	cache_op(Index_Writeback_Inv_D, addr);
+ 	__dflush_epilogue
+ }
+@@ -169,6 +184,7 @@
+ static inline void flush_dcache_line(unsigned long addr)
+ {
+ 	__dflush_prologue
++	BCM4710_DUMMY_RREG();
+ 	cache_op(Hit_Writeback_Inv_D, addr);
+ 	__dflush_epilogue
+ }
+@@ -176,6 +192,7 @@
+ static inline void invalidate_dcache_line(unsigned long addr)
+ {
+ 	__dflush_prologue
++	BCM4710_DUMMY_RREG();
+ 	cache_op(Hit_Invalidate_D, addr);
+ 	__dflush_epilogue
+ }
+@@ -208,6 +225,7 @@
+  */
+ static inline void protected_flush_icache_line(unsigned long addr)
+ {
++	BCM4710_DUMMY_RREG();
+ 	protected_cache_op(Hit_Invalidate_I, addr);
+ }
+ 
+@@ -219,6 +237,7 @@
+  */
+ static inline void protected_writeback_dcache_line(unsigned long addr)
+ {
++	BCM4710_DUMMY_RREG();
+ 	protected_cache_op(Hit_Writeback_Inv_D, addr);
+ }
+ 
+@@ -339,8 +358,52 @@
+ 		: "r" (base),						\
+ 		  "i" (op));
+ 
++static inline void blast_dcache(void)
++{
++	unsigned long start = KSEG0;
++	unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
++	unsigned long end = (start + dcache_size);
++
++	do {
++		BCM4710_DUMMY_RREG();
++		cache_op(Index_Writeback_Inv_D, start);
++		start += current_cpu_data.dcache.linesz;
++	} while(start < end);
++}
++
++static inline void blast_dcache_page(unsigned long page)
++{
++	unsigned long start = page;
++	unsigned long end = start + PAGE_SIZE;
++
++	BCM4710_FILL_TLB(start);
++	do {
++		BCM4710_DUMMY_RREG();
++		cache_op(Hit_Writeback_Inv_D, start);
++		start += current_cpu_data.dcache.linesz;
++	} while(start < end);
++}
++
++static inline void blast_dcache_page_indexed(unsigned long page)
++{
++	unsigned long start = page;
++	unsigned long end = start + PAGE_SIZE;
++	unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
++	unsigned long ws_end = current_cpu_data.dcache.ways <<
++	                       current_cpu_data.dcache.waybit;
++	unsigned long ws, addr;
++	for (ws = 0; ws < ws_end; ws += ws_inc) {
++		start = page + ws;
++		for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
++			BCM4710_DUMMY_RREG();
++			cache_op(Index_Writeback_Inv_D, addr);
++		}
++	}
++}
++
++
+ /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
+-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
++#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, war) \
+ static inline void blast_##pfx##cache##lsize(void)			\
+ {									\
+ 	unsigned long start = INDEX_BASE;				\
+@@ -352,6 +415,7 @@
+ 									\
+ 	__##pfx##flush_prologue						\
+ 									\
++	war								\
+ 	for (ws = 0; ws < ws_end; ws += ws_inc)				\
+ 		for (addr = start; addr < end; addr += lsize * 32)	\
+ 			cache##lsize##_unroll32(addr|ws,indexop);	\
+@@ -366,6 +430,7 @@
+ 									\
+ 	__##pfx##flush_prologue						\
+ 									\
++	war								\
+ 	do {								\
+ 		cache##lsize##_unroll32(start,hitop);			\
+ 		start += lsize * 32;					\
+@@ -384,6 +449,8 @@
+ 	                       current_cpu_data.desc.waybit;		\
+ 	unsigned long ws, addr;						\
+ 									\
++	war								\
++									\
+ 	__##pfx##flush_prologue						\
+ 									\
+ 	for (ws = 0; ws < ws_end; ws += ws_inc)				\
+@@ -393,28 +460,30 @@
+ 	__##pfx##flush_epilogue						\
+ }
+ 
+-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
+-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);)
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, BCM4710_FILL_TLB(start);)
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);)
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
+ 
+ /* build blast_xxx_range, protected_blast_xxx_range */
+-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
++#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war, war2) \
+ static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
+ 						    unsigned long end)	\
+ {									\
+ 	unsigned long lsize = cpu_##desc##_line_size();			\
+ 	unsigned long addr = start & ~(lsize - 1);			\
+ 	unsigned long aend = (end - 1) & ~(lsize - 1);			\
++	war								\
+ 									\
+ 	__##pfx##flush_prologue						\
+ 									\
+ 	while (1) {							\
++		war2						\
+ 		prot##cache_op(hitop, addr);				\
+ 		if (addr == aend)					\
+ 			break;						\
+@@ -424,13 +493,13 @@
+ 	__##pfx##flush_epilogue						\
+ }
+ 
+-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
+-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
+-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
+-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
+-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_,, )
++__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_,, )
++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D,, BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD,,, )
+ /* blast_inv_dcache_range */
+-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
+-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
++__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D,,,BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
+ 
+ #endif /* _ASM_R4KCACHE_H */
+Index: linux-2.6.23/include/asm-mips/stackframe.h
+===================================================================
+--- linux-2.6.23.orig/include/asm-mips/stackframe.h	2007-10-09 22:31:38.000000000 +0200
++++ linux-2.6.23/include/asm-mips/stackframe.h	2007-10-13 02:47:32.554044332 +0200
+@@ -350,6 +350,10 @@
+ 		.macro	RESTORE_SP_AND_RET
+ 		LONG_L	sp, PT_R29(sp)
+ 		.set	mips3
++#ifdef CONFIG_BCM947XX
++		nop
++		nop
++#endif
+ 		eret
+ 		.set	mips0
+ 		.endm

target/linux/brcm47xx/patches-2.6.23/160-kmap_coherent.patch

@@ -0,0 +1,63 @@
+Index: linux-2.6.23/arch/mips/mm/init.c
+===================================================================
+--- linux-2.6.23.orig/arch/mips/mm/init.c	2007-10-09 22:31:38.000000000 +0200
++++ linux-2.6.23/arch/mips/mm/init.c	2007-10-13 02:57:18.483434538 +0200
+@@ -211,7 +211,7 @@
+ 	void *vfrom, *vto;
+ 
+ 	vto = kmap_atomic(to, KM_USER1);
+-	if (cpu_has_dc_aliases && !Page_dcache_dirty(from)) {
++	if (cpu_has_dc_aliases && cpu_use_kmap_coherent && !Page_dcache_dirty(from)) {
+ 		vfrom = kmap_coherent(from, vaddr);
+ 		copy_page(vto, vfrom);
+ 		kunmap_coherent();
+@@ -234,7 +234,7 @@
+ 	struct page *page, unsigned long vaddr, void *dst, const void *src,
+ 	unsigned long len)
+ {
+-	if (cpu_has_dc_aliases) {
++	if (cpu_has_dc_aliases && cpu_use_kmap_coherent) {
+ 		void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
+ 		memcpy(vto, src, len);
+ 		kunmap_coherent();
+@@ -250,7 +250,7 @@
+ 	struct page *page, unsigned long vaddr, void *dst, const void *src,
+ 	unsigned long len)
+ {
+-	if (cpu_has_dc_aliases) {
++	if (cpu_has_dc_aliases && cpu_use_kmap_coherent) {
+ 		void *vfrom =
+ 			kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
+ 		memcpy(dst, vfrom, len);
+Index: linux-2.6.23/include/asm-mips/mach-bcm947xx/cpu-feature-overrides.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.23/include/asm-mips/mach-bcm947xx/cpu-feature-overrides.h	2007-10-13 02:56:22.020216880 +0200
+@@ -0,0 +1,13 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
++ */
++#ifndef __ASM_MACH_BCM947XX_CPU_FEATURE_OVERRIDES_H
++#define __ASM_MACH_BCM947XX_CPU_FEATURE_OVERRIDES_H
++
++#define cpu_use_kmap_coherent	0
++
++#endif /* __ASM_MACH_BCM947XX_CPU_FEATURE_OVERRIDES_H */
+Index: linux-2.6.23/include/asm-mips/cpu-features.h
+===================================================================
+--- linux-2.6.23.orig/include/asm-mips/cpu-features.h	2007-10-09 22:31:38.000000000 +0200
++++ linux-2.6.23/include/asm-mips/cpu-features.h	2007-10-13 02:56:22.028217337 +0200
+@@ -101,6 +101,9 @@
+ #ifndef cpu_has_pindexed_dcache
+ #define cpu_has_pindexed_dcache	(cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
+ #endif
++#ifndef cpu_use_kmap_coherent
++#define cpu_use_kmap_coherent 1
++#endif
+ 
+ /*
+  * I-Cache snoops remote store.  This only matters on SMP.  Some multiprocessors

target/linux/brcm47xx/patches-2.6.23/170-cpu_wait.patch

@@ -0,0 +1,12 @@
+Index: linux-2.6.23/arch/mips/kernel/cpu-probe.c
+===================================================================
+--- linux-2.6.23.orig/arch/mips/kernel/cpu-probe.c	2007-10-13 02:47:02.788348072 +0200
++++ linux-2.6.23/arch/mips/kernel/cpu-probe.c	2007-10-13 02:57:46.293019312 +0200
+@@ -159,6 +159,7 @@
+ 	case CPU_5KC:
+ 	case CPU_25KF:
+ 	case CPU_PR4450:
++ 	case CPU_BCM3302:
+ 		cpu_wait = r4k_wait;
+ 		break;
+ 

target/linux/brcm47xx/patches-2.6.23/200-b44_ssb_fixup.patch

@@ -0,0 +1,274 @@
+Index: linux-2.6.23/drivers/net/b44.c
+===================================================================
+--- linux-2.6.23.orig/drivers/net/b44.c	2007-10-13 02:46:38.946989430 +0200
++++ linux-2.6.23/drivers/net/b44.c	2007-10-13 03:15:34.889915180 +0200
+@@ -129,7 +129,7 @@
+ 	                                       unsigned long offset,
+ 	                                       enum dma_data_direction dir)
+ {
+-	dma_sync_single_range_for_device(&sdev->dev, dma_base,
++	dma_sync_single_range_for_device(sdev->dev, dma_base,
+ 		                        offset & dma_desc_align_mask,
+ 		                        dma_desc_sync_size, dir);
+ }
+@@ -139,7 +139,7 @@
+ 	                                    unsigned long offset,
+ 	                                    enum dma_data_direction dir)
+ {
+-	dma_sync_single_range_for_cpu(&sdev->dev, dma_base,
++	dma_sync_single_range_for_cpu(sdev->dev, dma_base,
+ 		                     offset & dma_desc_align_mask,
+ 		                     dma_desc_sync_size, dir);
+ }
+@@ -563,7 +563,7 @@
+ 
+ 		BUG_ON(skb == NULL);
+ 
+-		dma_unmap_single(&bp->sdev->dev,
++		dma_unmap_single(bp->sdev->dev,
+ 				 pci_unmap_addr(rp, mapping),
+ 				 skb->len,
+ 				 DMA_TO_DEVICE);
+@@ -603,7 +603,7 @@
+ 	if (skb == NULL)
+ 		return -ENOMEM;
+ 
+-	mapping = dma_map_single(&bp->sdev->dev, skb->data,
++	mapping = dma_map_single(bp->sdev->dev, skb->data,
+ 				 RX_PKT_BUF_SZ,
+ 				 DMA_FROM_DEVICE);
+ 
+@@ -613,18 +613,18 @@
+ 		mapping + RX_PKT_BUF_SZ > DMA_30BIT_MASK) {
+ 		/* Sigh... */
+ 		if (!dma_mapping_error(mapping))
+-			dma_unmap_single(&bp->sdev->dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
++			dma_unmap_single(bp->sdev->dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
+ 		dev_kfree_skb_any(skb);
+ 		skb = __netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ, GFP_ATOMIC|GFP_DMA);
+ 		if (skb == NULL)
+ 			return -ENOMEM;
+-		mapping = dma_map_single(&bp->sdev->dev, skb->data,
++		mapping = dma_map_single(bp->sdev->dev, skb->data,
+ 					 RX_PKT_BUF_SZ,
+ 					 DMA_FROM_DEVICE);
+ 		if (dma_mapping_error(mapping) ||
+ 			mapping + RX_PKT_BUF_SZ > DMA_30BIT_MASK) {
+ 			if (!dma_mapping_error(mapping))
+-				dma_unmap_single(&bp->sdev->dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
++				dma_unmap_single(bp->sdev->dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
+ 			dev_kfree_skb_any(skb);
+ 			return -ENOMEM;
+ 		}
+@@ -700,7 +700,7 @@
+ 			                    dest_idx * sizeof(dest_desc),
+ 			                    DMA_BIDIRECTIONAL);
+ 
+-	dma_sync_single_for_device(&bp->sdev->dev, le32_to_cpu(src_desc->addr),
++	dma_sync_single_for_device(bp->sdev->dev, le32_to_cpu(src_desc->addr),
+ 				       RX_PKT_BUF_SZ,
+ 				       DMA_FROM_DEVICE);
+ }
+@@ -722,7 +722,7 @@
+ 		struct rx_header *rh;
+ 		u16 len;
+ 
+-		dma_sync_single_for_cpu(&bp->sdev->dev, map,
++		dma_sync_single_for_cpu(bp->sdev->dev, map,
+ 					    RX_PKT_BUF_SZ,
+ 					    DMA_FROM_DEVICE);
+ 		rh = (struct rx_header *) skb->data;
+@@ -756,7 +756,7 @@
+ 			skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
+ 			if (skb_size < 0)
+ 				goto drop_it;
+-			dma_unmap_single(&bp->sdev->dev, map,
++			dma_unmap_single(bp->sdev->dev, map,
+ 					 skb_size, DMA_FROM_DEVICE);
+ 			/* Leave out rx_header */
+                 	skb_put(skb, len + RX_PKT_OFFSET);
+@@ -928,23 +928,23 @@
+ 		goto err_out;
+ 	}
+ 
+-	mapping = dma_map_single(&bp->sdev->dev, skb->data, len, DMA_TO_DEVICE);
++	mapping = dma_map_single(bp->sdev->dev, skb->data, len, DMA_TO_DEVICE);
+ 	if (dma_mapping_error(mapping) || mapping + len > DMA_30BIT_MASK) {
+ 		struct sk_buff *bounce_skb;
+ 
+ 		/* Chip can't handle DMA to/from >1GB, use bounce buffer */
+ 		if (!dma_mapping_error(mapping))
+-			dma_unmap_single(&bp->sdev->dev, mapping, len, DMA_TO_DEVICE);
++			dma_unmap_single(bp->sdev->dev, mapping, len, DMA_TO_DEVICE);
+ 
+ 		bounce_skb = __dev_alloc_skb(len, GFP_ATOMIC | GFP_DMA);
+ 		if (!bounce_skb)
+ 			goto err_out;
+ 
+-		mapping = dma_map_single(&bp->sdev->dev, bounce_skb->data,
++		mapping = dma_map_single(bp->sdev->dev, bounce_skb->data,
+ 					 len, DMA_TO_DEVICE);
+ 		if (dma_mapping_error(mapping) || mapping + len > DMA_30BIT_MASK) {
+ 			if (!dma_mapping_error(mapping))
+-				dma_unmap_single(&bp->sdev->dev, mapping,
++				dma_unmap_single(bp->sdev->dev, mapping,
+ 						 len, DMA_TO_DEVICE);
+ 			dev_kfree_skb_any(bounce_skb);
+ 			goto err_out;
+@@ -1043,7 +1043,7 @@
+ 
+ 		if (rp->skb == NULL)
+ 			continue;
+-		dma_unmap_single(&bp->sdev->dev,
++		dma_unmap_single(bp->sdev->dev,
+ 				 pci_unmap_addr(rp, mapping),
+ 				 RX_PKT_BUF_SZ,
+ 				 DMA_FROM_DEVICE);
+@@ -1057,7 +1057,7 @@
+ 
+ 		if (rp->skb == NULL)
+ 			continue;
+-		dma_unmap_single(&bp->sdev->dev,
++		dma_unmap_single(bp->sdev->dev,
+ 				 pci_unmap_addr(rp, mapping),
+ 				 rp->skb->len,
+ 				 DMA_TO_DEVICE);
+@@ -1082,12 +1082,12 @@
+ 	memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
+ 
+ 	if (bp->flags & B44_FLAG_RX_RING_HACK)
+-		dma_sync_single_for_device(&bp->sdev->dev, bp->rx_ring_dma,
++		dma_sync_single_for_device(bp->sdev->dev, bp->rx_ring_dma,
+ 			                  DMA_TABLE_BYTES,
+ 			                  DMA_BIDIRECTIONAL);
+ 
+ 	if (bp->flags & B44_FLAG_TX_RING_HACK)
+-		dma_sync_single_for_device(&bp->sdev->dev, bp->tx_ring_dma,
++		dma_sync_single_for_device(bp->sdev->dev, bp->tx_ring_dma,
+ 			                  DMA_TABLE_BYTES,
+ 			                  DMA_TO_DEVICE);
+ 
+@@ -1109,24 +1109,24 @@
+ 	bp->tx_buffers = NULL;
+ 	if (bp->rx_ring) {
+ 		if (bp->flags & B44_FLAG_RX_RING_HACK) {
+-			dma_unmap_single(&bp->sdev->dev, bp->rx_ring_dma,
++			dma_unmap_single(bp->sdev->dev, bp->rx_ring_dma,
+ 					DMA_TABLE_BYTES,
+ 					DMA_BIDIRECTIONAL);
+ 			kfree(bp->rx_ring);
+ 		} else
+-			dma_free_coherent(&bp->sdev->dev, DMA_TABLE_BYTES,
++			dma_free_coherent(bp->sdev->dev, DMA_TABLE_BYTES,
+ 					    bp->rx_ring, bp->rx_ring_dma);
+ 		bp->rx_ring = NULL;
+ 		bp->flags &= ~B44_FLAG_RX_RING_HACK;
+ 	}
+ 	if (bp->tx_ring) {
+ 		if (bp->flags & B44_FLAG_TX_RING_HACK) {
+-			dma_unmap_single(&bp->sdev->dev, bp->tx_ring_dma,
++			dma_unmap_single(bp->sdev->dev, bp->tx_ring_dma,
+ 					DMA_TABLE_BYTES,
+ 					DMA_TO_DEVICE);
+ 			kfree(bp->tx_ring);
+ 		} else
+-			dma_free_coherent(&bp->sdev->dev, DMA_TABLE_BYTES,
++			dma_free_coherent(bp->sdev->dev, DMA_TABLE_BYTES,
+ 					    bp->tx_ring, bp->tx_ring_dma);
+ 		bp->tx_ring = NULL;
+ 		bp->flags &= ~B44_FLAG_TX_RING_HACK;
+@@ -1152,7 +1152,7 @@
+ 		goto out_err;
+ 
+ 	size = DMA_TABLE_BYTES;
+-	bp->rx_ring = dma_alloc_coherent(&bp->sdev->dev, size, &bp->rx_ring_dma, GFP_ATOMIC);
++	bp->rx_ring = dma_alloc_coherent(bp->sdev->dev, size, &bp->rx_ring_dma, GFP_ATOMIC);
+ 	if (!bp->rx_ring) {
+ 		/* Allocation may have failed due to pci_alloc_consistent
+ 		   insisting on use of GFP_DMA, which is more restrictive
+@@ -1164,7 +1164,7 @@
+ 		if (!rx_ring)
+ 			goto out_err;
+ 
+-		rx_ring_dma = dma_map_single(&bp->sdev->dev, rx_ring,
++		rx_ring_dma = dma_map_single(bp->sdev->dev, rx_ring,
+ 			                    DMA_TABLE_BYTES,
+ 			                    DMA_BIDIRECTIONAL);
+ 
+@@ -1179,7 +1179,7 @@
+ 		bp->flags |= B44_FLAG_RX_RING_HACK;
+ 	}
+ 
+-	bp->tx_ring = dma_alloc_coherent(&bp->sdev->dev, size, &bp->tx_ring_dma, GFP_ATOMIC);
++	bp->tx_ring = dma_alloc_coherent(bp->sdev->dev, size, &bp->tx_ring_dma, GFP_ATOMIC);
+ 	if (!bp->tx_ring) {
+ 		/* Allocation may have failed due to dma_alloc_coherent
+ 		   insisting on use of GFP_DMA, which is more restrictive
+@@ -1191,7 +1191,7 @@
+ 		if (!tx_ring)
+ 			goto out_err;
+ 
+-		tx_ring_dma = dma_map_single(&bp->sdev->dev, tx_ring,
++		tx_ring_dma = dma_map_single(bp->sdev->dev, tx_ring,
+ 			                    DMA_TABLE_BYTES,
+ 			                    DMA_TO_DEVICE);
+ 
+@@ -2288,7 +2288,7 @@
+ 	   bp->flags |= B44_FLAG_BUGGY_TXPTR;
+          */
+ 
+-	if (bp->sdev->dev->id.revision >= 7)
++	if (bp->sdev->id.revision >= 7)
+  		bp->flags |= B44_FLAG_B0_ANDLATER;
+ 
+ 	return err;
+@@ -2298,7 +2298,6 @@
+ 				  const struct ssb_device_id *ent)
+ {
+ 	static int b44_version_printed = 0;
+-	unsigned long b44reg_base, b44reg_len;
+ 	struct net_device *dev;
+ 	struct b44 *bp;
+ 	int err, i;
+@@ -2310,13 +2309,13 @@
+ 
+ 	dev = alloc_etherdev(sizeof(*bp));
+ 	if (!dev) {
+-		dev_err(&pdev->dev, "Etherdev alloc failed, aborting.\n");
++		dev_err(sdev->dev, "Etherdev alloc failed, aborting.\n");
+ 		err = -ENOMEM;
+ 		goto out;
+ 	}
+ 
+ 	SET_MODULE_OWNER(dev);
+-	SET_NETDEV_DEV(dev,&sdev->dev);
++	SET_NETDEV_DEV(dev,sdev->dev);
+ 
+ 	/* No interesting netdevice features in this card... */
+ 	dev->features |= 0;
+@@ -2354,7 +2353,7 @@
+ 
+ 	err = b44_get_invariants(bp);
+ 	if (err) {
+-		dev_err(&sdev->dev,
++		dev_err(sdev->dev,
+ 			"Problem fetching invariants of chip, aborting.\n");
+ 		goto err_out_free_dev;
+ 	}
+@@ -2375,7 +2374,7 @@
+ 
+ 	err = register_netdev(dev);
+ 	if (err) {
+-		dev_err(&sdev->dev, "Cannot register net device, aborting.\n");
++		dev_err(sdev->dev, "Cannot register net device, aborting.\n");
+ 		goto out;
+ 	}
+ 
+@@ -2454,7 +2453,6 @@
+ 	rc = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
+ 	if (rc) {
+ 		printk(KERN_ERR PFX "%s: request_irq failed\n", dev->name);
+-		pci_disable_device(pdev);
+ 		return rc;
+ 	}
+ 

target/linux/brcm47xx/patches-2.6.23/210-ssb_fixes.patch

@@ -0,0 +1,372 @@
+Index: linux-2.6.22-rc5/drivers/ssb/driver_chipcommon.c
+===================================================================
+--- linux-2.6.22-rc5.orig/drivers/ssb/driver_chipcommon.c	2007-06-21 23:04:38.000000000 +0100
++++ linux-2.6.22-rc5/drivers/ssb/driver_chipcommon.c	2007-06-24 20:07:15.000000000 +0100
+@@ -264,6 +264,31 @@
+ 	ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
+ }
+ 
++/* TODO: These two functions are a clear candidate for merging, but one gets
++ * the processor clock, and the other gets the bus clock.
++ */
++void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
++                             u32 *plltype, u32 *n, u32 *m)
++{
++	*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
++	*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
++	switch (*plltype) {
++		case SSB_PLLTYPE_2:
++		case SSB_PLLTYPE_4:
++		case SSB_PLLTYPE_6:
++		case SSB_PLLTYPE_7:
++			*m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
++			break;
++		case SSB_PLLTYPE_3:
++			/* 5350 uses m2 to control mips */
++			*m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
++			break;
++		default:
++			*m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
++			break;
++	}
++}
++
+ void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
+ 				 u32 *plltype, u32 *n, u32 *m)
+ {
+@@ -400,3 +425,13 @@
+ 	return nr_ports;
+ }
+ #endif /* CONFIG_SSB_SERIAL */
++
++/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
++int
++ssb_chipco_watchdog(struct ssb_chipcommon *cc, uint ticks)
++{
++	/* instant NMI */
++	chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
++	return 0;
++}
++EXPORT_SYMBOL(ssb_chipco_watchdog);
+Index: linux-2.6.22-rc5/drivers/ssb/driver_mipscore.c
+===================================================================
+--- linux-2.6.22-rc5.orig/drivers/ssb/driver_mipscore.c	2007-06-10 16:44:31.000000000 +0100
++++ linux-2.6.22-rc5/drivers/ssb/driver_mipscore.c	2007-06-24 20:48:52.000000000 +0100
+@@ -4,6 +4,7 @@
+  *
+  * Copyright 2005, Broadcom Corporation
+  * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
++ * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
+  *
+  * Licensed under the GNU/GPL. See COPYING for details.
+  */
+@@ -31,6 +32,16 @@
+ 	ssb_write32(mcore->dev, offset, value);
+ }
+ 
++static inline u32 extif_read32(struct ssb_extif *extif, u16 offset)
++{
++	return ssb_read32(extif->dev, offset);
++}
++
++static inline void extif_write32(struct ssb_extif *extif, u16 offset, u32 value)
++{
++	ssb_write32(extif->dev, offset, value);
++}
++
+ static const u32 ipsflag_irq_mask[] = {
+ 	0,
+ 	SSB_IPSFLAG_IRQ1,
+@@ -118,9 +129,9 @@
+ }
+ 
+ /* XXX: leave here or move into separate extif driver? */
+-static int ssb_extif_serial_init(struct ssb_device *dev, struct ssb_serial_ports *ports)
++static int ssb_extif_serial_init(struct ssb_extif *dev, struct ssb_serial_port *ports)
+ {
+-
++	return 0;
+ }
+ 
+ 
+@@ -174,23 +185,76 @@
+ {
+ 	struct ssb_bus *bus = mcore->dev->bus;
+ 
++	mcore->flash_buswidth = 2;
+ 	if (bus->chipco.dev) {
+ 		mcore->flash_window = 0x1c000000;
+-		mcore->flash_window_size = 0x800000;
++		mcore->flash_window_size = 0x02000000;
++		if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
++		               & SSB_CHIPCO_CFG_DS16) == 0)
++			mcore->flash_buswidth = 1;
+ 	} else {
+ 		mcore->flash_window = 0x1fc00000;
+-		mcore->flash_window_size = 0x400000;
++		mcore->flash_window_size = 0x00400000;
+ 	}
+ }
+ 
++static void ssb_extif_timing_init(struct ssb_extif *extif, u32 ns)
++{
++	u32 tmp;
++
++	/* Initialize extif so we can get to the LEDs and external UART */
++	extif_write32(extif, SSB_EXTIF_PROG_CFG, SSB_EXTCFG_EN);
++
++	/* Set timing for the flash */
++	tmp  = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT;
++	tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT;
++	tmp |= DIV_ROUND_UP(120, ns);
++	extif_write32(extif, SSB_EXTIF_PROG_WAITCNT, tmp);
++
++	/* Set programmable interface timing for external uart */
++	tmp  = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT;
++	tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT;
++	tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT;
++	tmp |= DIV_ROUND_UP(120, ns);
++	extif_write32(extif, SSB_EXTIF_PROG_WAITCNT, tmp);
++}
+ 
+-static void ssb_cpu_clock(struct ssb_mipscore *mcore)
++static inline void ssb_extif_get_clockcontrol(struct ssb_extif *extif,
++                                              u32 *pll_type, u32 *n, u32 *m)
+ {
++	*pll_type = SSB_PLLTYPE_1;
++	*n = extif_read32(extif, SSB_EXTIF_CLOCK_N);
++	*m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
+ }
+ 
+-void ssb_mipscore_init(struct ssb_mipscore *mcore)
++u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
+ {
+ 	struct ssb_bus *bus = mcore->dev->bus;
++	u32 pll_type, n, m, rate = 0;
++
++	if (bus->extif.dev) {
++		ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
++	} else if (bus->chipco.dev) {
++		ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
++	} else
++		return 0;
++
++	if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
++		rate = 200000000;
++	} else {
++		rate = ssb_calc_clock_rate(pll_type, n, m);
++	}
++
++	if (pll_type == SSB_PLLTYPE_6) {
++		rate *= 2;
++	}
++
++	return rate;
++}
++
++void ssb_mipscore_init(struct ssb_mipscore *mcore)
++{
++	struct ssb_bus *bus;
+ 	struct ssb_device *dev;
+ 	unsigned long hz, ns;
+ 	unsigned int irq, i;
+@@ -198,6 +262,8 @@
+ 	if (!mcore->dev)
+ 		return; /* We don't have a MIPS core */
+ 
++	bus = mcore->dev->bus;
++
+ 	ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n");
+ 
+ 	hz = ssb_clockspeed(bus);
+@@ -205,28 +271,9 @@
+ 		hz = 100000000;
+ 	ns = 1000000000 / hz;
+ 
+-//TODO
+-#if 0
+-	if (have EXTIF) {
+-		/* Initialize extif so we can get to the LEDs and external UART */
+-		W_REG(&eir->prog_config, CF_EN);
+-
+-		/* Set timing for the flash */
+-		tmp = CEIL(10, ns) << FW_W3_SHIFT;	/* W3 = 10nS */
+-		tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
+-		tmp = tmp | CEIL(120, ns);		/* W0 = 120nS */
+-		W_REG(&eir->prog_waitcount, tmp);	/* 0x01020a0c for a 100Mhz clock */
+-
+-		/* Set programmable interface timing for external uart */
+-		tmp = CEIL(10, ns) << FW_W3_SHIFT;	/* W3 = 10nS */
+-		tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
+-		tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
+-		tmp = tmp | CEIL(120, ns);		/* W0 = 120nS */
+-		W_REG(&eir->prog_waitcount, tmp);
+-	}
+-	else... chipcommon
+-#endif
+-	if (bus->chipco.dev)
++	if (bus->extif.dev)
++		ssb_extif_timing_init(&bus->extif, ns);
++	else if (bus->chipco.dev)
+ 		ssb_chipco_timing_init(&bus->chipco, ns);
+ 
+ 	/* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
+@@ -256,3 +303,5 @@
+ 	ssb_mips_serial_init(mcore);
+ 	ssb_mips_flash_detect(mcore);
+ }
++
++EXPORT_SYMBOL(ssb_mips_irq);
+Index: linux-2.6.22-rc5/include/linux/ssb/ssb_driver_chipcommon.h
+===================================================================
+--- linux-2.6.22-rc5.orig/include/linux/ssb/ssb_driver_chipcommon.h	2007-06-10 16:44:47.000000000 +0100
++++ linux-2.6.22-rc5/include/linux/ssb/ssb_driver_chipcommon.h	2007-06-24 20:07:15.000000000 +0100
+@@ -364,6 +364,8 @@
+ extern void ssb_chipco_suspend(struct ssb_chipcommon *cc, pm_message_t state);
+ extern void ssb_chipco_resume(struct ssb_chipcommon *cc);
+ 
++extern void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
++                                    u32 *plltype, u32 *n, u32 *m);
+ extern void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
+ 					u32 *plltype, u32 *n, u32 *m);
+ extern void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
+@@ -378,6 +380,46 @@
+ extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
+ 				     enum ssb_clkmode mode);
+ 
++/* GPIO functions */
++static inline u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc,
++                                     u32 mask)
++{
++	return ssb_read32(cc->dev, SSB_CHIPCO_GPIOIN) & mask;
++}
++
++static inline u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc,
++                                      u32 mask, u32 value)
++{
++	return ssb_write32_masked(cc->dev, SSB_CHIPCO_GPIOOUT, mask, value);
++}
++
++static inline u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc,
++                                        u32 mask, u32 value)
++{
++	return ssb_write32_masked(cc->dev, SSB_CHIPCO_GPIOOUTEN, mask, value);
++}
++
++static inline u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc,
++                                          u32 mask, u32 value)
++{
++	return ssb_write32_masked(cc->dev, SSB_CHIPCO_GPIOCTL, mask, value);
++}
++
++static inline u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc,
++                                          u32 mask, u32 value)
++{
++	return ssb_write32_masked(cc->dev, SSB_CHIPCO_GPIOIRQ, mask, value);
++}
++
++static inline u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc,
++                                           u32 mask, u32 value)
++{
++	return ssb_write32_masked(cc->dev, SSB_CHIPCO_GPIOPOL, mask, value);
++}
++/* TODO: GPIO reservation */
++
++extern int ssb_chipco_watchdog(struct ssb_chipcommon *cc, uint ticks);
++
+ #ifdef CONFIG_SSB_SERIAL
+ extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
+ 				  struct ssb_serial_port *ports);
+Index: linux-2.6.22-rc5/include/linux/ssb/ssb_driver_extif.h
+===================================================================
+--- linux-2.6.22-rc5.orig/include/linux/ssb/ssb_driver_extif.h	2007-06-10 16:44:47.000000000 +0100
++++ linux-2.6.22-rc5/include/linux/ssb/ssb_driver_extif.h	2007-06-24 20:07:15.000000000 +0100
+@@ -158,6 +158,36 @@
+ /* watchdog */
+ #define SSB_EXTIF_WATCHDOG_CLK		48000000	/* Hz */
+ 
++/* GPIO functions */
++static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif,
++                                    u32 mask)
++{
++	return ssb_read32(extif->dev, SSB_EXTIF_GPIO_IN) & mask;
++}
++
++static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif,
++                                     u32 mask, u32 value)
++{
++	return ssb_write32_masked(extif->dev, SSB_EXTIF_GPIO_OUT(0), mask, value);
++}
++
++static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif,
++                                       u32 mask, u32 value)
++{
++	return ssb_write32_masked(extif->dev, SSB_EXTIF_GPIO_OUTEN(0), mask, value);
++}
++
++static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif,
++                                          u32 mask, u32 value)
++{
++	return ssb_write32_masked(extif->dev, SSB_EXTIF_GPIO_INTPOL, mask, value);
++}
++
++static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif,
++                                         u32 mask, u32 value)
++{
++	return ssb_write32_masked(extif->dev, SSB_EXTIF_GPIO_INTMASK, mask, value);
++}
+ 
+ #endif /* __KERNEL__ */
+ #endif /* LINUX_SSB_EXTIFCORE_H_ */
+Index: linux-2.6.22-rc5/include/linux/ssb/ssb_driver_mips.h
+===================================================================
+--- linux-2.6.22-rc5.orig/include/linux/ssb/ssb_driver_mips.h	2007-06-10 16:44:47.000000000 +0100
++++ linux-2.6.22-rc5/include/linux/ssb/ssb_driver_mips.h	2007-06-24 20:07:15.000000000 +0100
+@@ -22,11 +22,13 @@
+ 	int nr_serial_ports;
+ 	struct ssb_serial_port serial_ports[4];
+ 
++	int flash_buswidth;
+ 	u32 flash_window;
+ 	u32 flash_window_size;
+ };
+ 
+ extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
++extern u32 ssb_cpu_clock(struct ssb_mipscore *mcore);
+ 
+ extern unsigned int ssb_mips_irq(struct ssb_device *dev);
+ 
+Index: linux-2.6.22-rc5/include/linux/ssb/ssb.h
+===================================================================
+--- linux-2.6.22-rc5.orig/include/linux/ssb/ssb.h	2007-06-24 19:49:56.000000000 +0100
++++ linux-2.6.22-rc5/include/linux/ssb/ssb.h	2007-06-24 20:07:15.000000000 +0100
+@@ -270,6 +270,12 @@
+ #define SSB_CHIPPACK_BCM4712M	2	/* Medium 225pin 4712 */
+ #define SSB_CHIPPACK_BCM4712L	0	/* Large 340pin 4712 */
+ 
++static inline u16 ssb_read16(struct ssb_device *dev, u16 offset);
++static inline u32 ssb_read32(struct ssb_device *dev, u16 offset);
++static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value);
++static inline void ssb_write32(struct ssb_device *dev, u16 offset, u32 value);
++static inline u32 ssb_write32_masked(struct ssb_device *dev, u16 offset, u32 mask, u32 value);
++
+ #include <linux/ssb/ssb_driver_chipcommon.h>
+ #include <linux/ssb/ssb_driver_mips.h>
+ #include <linux/ssb/ssb_driver_extif.h>
+@@ -388,6 +394,16 @@
+ 	dev->ops->write32(dev, offset, value);
+ }
+ 
++static inline u32 ssb_write32_masked(struct ssb_device *dev,
++                                     u16 offset,
++                                     u32 mask,
++                                     u32 value)
++{
++	value &= mask;
++	value |= ssb_read32(dev, offset) & ~mask;
++	ssb_write32(dev, offset, value);
++	return value;
++}
+ 
+ /* Translation (routing) bits that need to be ORed to DMA
+  * addresses before they are given to a device. */

target/linux/brcm47xx/patches-2.6.23/240-extif_fixes.patch

@@ -0,0 +1,152 @@
+Index: linux-2.6.23/drivers/ssb/driver_mipscore.c
+===================================================================
+--- linux-2.6.23.orig/drivers/ssb/driver_mipscore.c	2007-10-13 03:01:19.829188047 +0200
++++ linux-2.6.23/drivers/ssb/driver_mipscore.c	2007-10-13 03:01:21.777299062 +0200
+@@ -128,10 +128,46 @@
+ 	ssb_write32(mdev, SSB_IPSFLAG, irqflag);
+ }
+ 
+-/* XXX: leave here or move into separate extif driver? */
++static inline bool serial_exists(u8 *regs)
++{
++	u8 save_mcr, status1 = 0;
++
++	if (regs) {
++		save_mcr = regs[UART_MCR];
++		regs[UART_MCR] = (UART_MCR_LOOP | 0x0a);
++		// Fixme UART_MSR_DSR appears in status1
++		status1 = regs[UART_MSR] & 0xd0;
++		regs[UART_MCR] = save_mcr;
++    }
++	return (status1 == (UART_MSR_DCD | UART_MSR_CTS));
++}
++
+ static int ssb_extif_serial_init(struct ssb_extif *dev, struct ssb_serial_port *ports)
+ {
+-	return 0;
++	u32 i, nr_ports = 0;
++
++	/* Disable GPIO interrupt initially */
++	extif_write32(dev, SSB_EXTIF_GPIO_INTPOL, 0);
++	extif_write32(dev, SSB_EXTIF_GPIO_INTMASK, 0);
++
++	for (i = 0; i < 2; i++) {
++		void __iomem *uart_regs;
++
++		uart_regs = ioremap_nocache(SSB_EUART, 16);
++		uart_regs += (i * 8);
++
++		if (serial_exists(uart_regs) && ports) {
++			extif_write32(dev, SSB_EXTIF_GPIO_INTMASK, 2);
++
++			nr_ports++;
++			ports[i].regs = uart_regs;
++			ports[i].irq = 2;
++			ports[i].baud_base = 13500000;
++			ports[i].reg_shift = 0;
++	    }
++		iounmap(uart_regs);
++    }
++	return nr_ports;
+ }
+ 
+ 
+@@ -139,40 +175,6 @@
+ {
+ 	struct ssb_bus *bus = mcore->dev->bus;
+ 
+-	//TODO if (EXTIF available
+-#if 0
+-		extifregs_t *eir = (extifregs_t *) regs;
+-		sbconfig_t *sb;
+-
+-		/* Determine external UART register base */
+-		sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
+-		base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
+-
+-		/* Determine IRQ */
+-		irq = sb_irq(sbh);
+-
+-		/* Disable GPIO interrupt initially */
+-		W_REG(&eir->gpiointpolarity, 0);
+-		W_REG(&eir->gpiointmask, 0);
+-
+-		/* Search for external UARTs */
+-		n = 2;
+-		for (i = 0; i < 2; i++) {
+-			regs = (void *) REG_MAP(base + (i * 8), 8);
+-			if (BCMINIT(serial_exists)(regs)) {
+-				/* Set GPIO 1 to be the external UART IRQ */
+-				W_REG(&eir->gpiointmask, 2);
+-				if (add)
+-					add(regs, irq, 13500000, 0);
+-			}
+-		}
+-
+-		/* Add internal UART if enabled */
+-		if (R_REG(&eir->corecontrol) & CC_UE)
+-			if (add)
+-				add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
+-
+-#endif
+ 	if (bus->extif.dev)
+ 		mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
+ 	else if (bus->chipco.dev)
+@@ -219,7 +221,7 @@
+ 	extif_write32(extif, SSB_EXTIF_PROG_WAITCNT, tmp);
+ }
+ 
+-static inline void ssb_extif_get_clockcontrol(struct ssb_extif *extif,
++void ssb_extif_get_clockcontrol(struct ssb_extif *extif,
+                                               u32 *pll_type, u32 *n, u32 *m)
+ {
+ 	*pll_type = SSB_PLLTYPE_1;
+Index: linux-2.6.23/drivers/ssb/main.c
+===================================================================
+--- linux-2.6.23.orig/drivers/ssb/main.c	2007-10-11 19:38:13.198446000 +0200
++++ linux-2.6.23/drivers/ssb/main.c	2007-10-13 03:01:21.785299518 +0200
+@@ -774,12 +774,12 @@
+ 	u32 plltype;
+ 	u32 clkctl_n, clkctl_m;
+ 
+-	//TODO if EXTIF: PLLTYPE == 1, read n from clockcontrol_n, m from clockcontrol_sb
+-
+-	if (bus->chipco.dev) {
++	if (bus->extif.dev)
++		ssb_extif_get_clockcontrol(&bus->extif, &plltype, &clkctl_n, &clkctl_m);
++	else if (bus->chipco.dev)
+ 		ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
+ 					    &clkctl_n, &clkctl_m);
+-	} else
++	else
+ 		return 0;
+ 
+ 	if (bus->chip_id == 0x5365) {
+Index: linux-2.6.23/include/linux/ssb/ssb_driver_extif.h
+===================================================================
+--- linux-2.6.23.orig/include/linux/ssb/ssb_driver_extif.h	2007-10-13 03:01:19.841188731 +0200
++++ linux-2.6.23/include/linux/ssb/ssb_driver_extif.h	2007-10-13 03:01:21.789299747 +0200
+@@ -158,6 +158,8 @@
+ /* watchdog */
+ #define SSB_EXTIF_WATCHDOG_CLK		48000000	/* Hz */
+ 
++extern void ssb_extif_get_clockcontrol(struct ssb_extif *, u32 *, u32 *, u32 *);
++
+ /* GPIO functions */
+ static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif,
+                                     u32 mask)
+Index: linux-2.6.23/include/linux/ssb/ssb_regs.h
+===================================================================
+--- linux-2.6.23.orig/include/linux/ssb/ssb_regs.h	2007-10-11 19:38:13.206447000 +0200
++++ linux-2.6.23/include/linux/ssb/ssb_regs.h	2007-10-13 03:01:21.793299976 +0200
+@@ -24,8 +24,8 @@
+ #define SSB_PCI_DMA_SZ		0x40000000	/* Client Mode sb2pcitranslation2 size in bytes */
+ #define SSB_PCIE_DMA_L32		0x00000000	/* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
+ #define SSB_PCIE_DMA_H32		0x80000000	/* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
+-#define	SSB_EUART		(SB_EXTIF_BASE + 0x00800000)
+-#define	SSB_LED			(SB_EXTIF_BASE + 0x00900000)
++#define	SSB_EUART		(SSB_EXTIF_BASE + 0x00800000)
++#define	SSB_LED			(SSB_EXTIF_BASE + 0x00900000)
+ 
+ 
+ /* Enumeration space constants */

target/linux/generic-2.6/files/drivers/ssb/driver_pcicore.c

@@ -93,10 +93,13 @@ static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
 
 	/* Enable PCI bridge BAR1 prefetch and burst */
 	pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
+
+	/* Make sure our latency is high enough to handle the devices behind us */
+	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xa8);
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
 
-int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
 	return ssb_mips_irq(extpci_core->dev) + 2;
 }
@@ -110,7 +113,7 @@ static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
 
 	if (unlikely(pc->cardbusmode && dev > 1))
 		goto out;
-	if (bus == 0) {
+	if (bus == 0) {//FIXME busnumber ok?
 		/* Type 0 transaction */
 		if (unlikely(dev >= SSB_PCI_SLOT_MAX))
 			goto out;
@@ -224,7 +227,7 @@ static int ssb_extpci_write_config(struct ssb_pcicore *pc,
 		val = *((const u32 *)buf);
 		break;
 	}
-	writel(*((const u32 *)buf), mmio);
+	writel(val, mmio);
 
 	err = 0;
 unmap:
@@ -307,6 +310,8 @@ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
 	udelay(150);
 	val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
 	pcicore_write32(pc, SSB_PCICORE_CTL, val);
+	val = SSB_PCICORE_ARBCTL_INTERN;
+	pcicore_write32(pc, SSB_PCICORE_ARBCTL, val); 
 	udelay(1);
 
 	//TODO cardbus mode
@@ -336,6 +341,7 @@ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
 	 * The following needs change, if we want to port hostmode
 	 * to non-MIPS platform. */
 	set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
+	mdelay(300);
 	register_pci_controller(&ssb_pcicore_controller);
 }