brcm63xx: update irq affinity code to latest version
Reduces code size a bit and sets affinity to boot cpu by default. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 41591
This commit is contained in:
Jonas Gorski
parent
ba9d2f397a
commit
2b6403722b
20 changed files with 170 additions and 128 deletions
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@ -1,8 +1,7 @@
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From 653dcc09407a695efb203337c6f72515d4c4ee43 Mon Sep 17 00:00:00 2001
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From a2015bfad293a7eb79519beb60381cb996c6e298 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Thu, 21 Mar 2013 17:05:15 +0100
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Subject: [PATCH 29/53] MIPS: BCM63XX: rename __dispatch_internal to
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__dispatch_internal_32
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Subject: [PATCH 01/10] MIPS: BCM63XX: add width to __dispatch_internal
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Make it follow the same naming convention as the other functions.
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@ -1,9 +1,11 @@
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From c28c639b031385ecf965eecf3bfb532e88044c89 Mon Sep 17 00:00:00 2001
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From 6e79c6dd02aa56e37eb071797f0eb5e3fb588cba Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Sun, 15 Dec 2013 20:52:53 +0100
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Subject: [PATCH 30/53] MIPS: BCM63XX: move bcm63xx_init_irq down
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Subject: [PATCH 02/10] MIPS: BCM63XX: move bcm63xx_init_irq down
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Allows up to drop the prototypes from the top.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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arch/mips/bcm63xx/irq.c | 190 +++++++++++++++++++++++-------------------------
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1 file changed, 92 insertions(+), 98 deletions(-)
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@ -1,15 +1,22 @@
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From 01bf26c51b427e24ac69f604d33f7d9360a9e470 Mon Sep 17 00:00:00 2001
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From 39b46ed1c9fe71890566e129d9ac5feb8421b3b4 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Thu, 18 Apr 2013 21:14:49 +0200
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Subject: [PATCH 31/53] MIPS: BCM63XX: replace irq dispatch code with a generic
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Subject: [PATCH 03/10] MIPS: BCM63XX: replace irq dispatch code with a generic
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version
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The generic version uses a variable length of u32 registers of u32/u64.
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This allows easier support for longer registers without having to rewrite
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verything.
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The generic version uses a variable length of u32 registers instead of u32/u64.
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This allows easier support for "wider" registers without having to rewrite
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everything.
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This "generic" version is not slower than the old version in the best case
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(= i == next set bit), and twice as fast in the worst case in 64 bits.
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This "generic" version is as fast as the old version in the best case
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(i == next set bit), and twice as fast in the worst case in 64 bits.
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Using a macro was chosen over a (forced) inline version because gcc generated
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more compact code with the macro.
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The change from (signed) int to unsigned int for i and to_call was intentional
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as the value can be only between 0 and (width - 1) anyway, and allowed gcc to
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optimise the code a bit further.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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@ -47,7 +54,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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+ u32 pending[width / 32]; \
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+ unsigned int src, tgt; \
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+ bool irqs_pending = false; \
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+ static int i; \
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+ static unsigned int i; \
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+ \
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+ /* read registers in reverse order */ \
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+ for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
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@ -65,7 +72,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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+ return; \
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+ \
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+ while (1) { \
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+ int to_call = i; \
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+ unsigned int to_call = i; \
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+ \
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+ i = (i + 1) & (width - 1); \
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+ if (pending[to_call / 32] & (1 << (to_call & 0x1f))) { \
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@ -1,10 +1,9 @@
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From 1003fb4a5ee9fcff518f20eefdee1a9bf500af7e Mon Sep 17 00:00:00 2001
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From 96ce0a9d195b2781d6f8d919dea8056b1c409703 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Thu, 25 Apr 2013 00:24:06 +0200
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Subject: [PATCH 32/53] MIPS: BCM63XX: append irq line number to
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irq_{stat,mask}*
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Subject: [PATCH 04/10] MIPS: BCM63XX: append irq line to irq_{stat,mask}*
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The SMP capable irq controllers have two interupt output pins which are
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The SMP capable irq controllers have two interrupt output pins which are
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controlled through separate registers, so make the variables arrays.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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@ -1,8 +1,10 @@
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From 842f213228e6fc9fd6cca01ab5128623112aa7a9 Mon Sep 17 00:00:00 2001
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From ff61c72a7a260ab4c4abbddb72c3cd2aea5e0687 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Thu, 25 Apr 2013 00:31:29 +0200
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Subject: [PATCH 33/53] MIPS: BCM63XX: populate irq_{stat,mask}_addr for second
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pin
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Subject: [PATCH 05/10] MIPS: BCM63XX: populate irq_{stat,mask}_addr for second
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cpu
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Set it to zero if there is no second set.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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@ -1,7 +1,7 @@
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From a33bb660c712447ba8b561109cda6734954a6efa Mon Sep 17 00:00:00 2001
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From 43ebef8162adfa7789cb915e60e46103965d7efd Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Fri, 26 Apr 2013 11:21:16 +0200
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Subject: [PATCH 34/53] MIPS: BCM63XX: add pin argument to dispatch internal
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Subject: [PATCH 06/10] MIPS: BCM63XX: add cpu argument to dispatch internal
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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@ -18,7 +18,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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static u32 irq_stat_addr[2];
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static u32 irq_mask_addr[2];
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-static void (*dispatch_internal)(void);
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+static void (*dispatch_internal)(int pin);
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+static void (*dispatch_internal)(int cpu);
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static int is_ext_irq_cascaded;
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static unsigned int ext_irq_count;
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static unsigned int ext_irq_start, ext_irq_end;
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@ -27,14 +27,14 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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#define BUILD_IPIC_INTERNAL(width) \
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-void __dispatch_internal_##width(void) \
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+void __dispatch_internal_##width(int pin) \
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+void __dispatch_internal_##width(int cpu) \
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{ \
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u32 pending[width / 32]; \
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unsigned int src, tgt; \
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bool irqs_pending = false; \
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- static int i; \
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+ static int i[2]; \
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+ int *next = &i[pin]; \
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- static unsigned int i; \
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+ static unsigned int i[2]; \
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+ unsigned int *next = &i[cpu]; \
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\
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/* read registers in reverse order */ \
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for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
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@ -42,8 +42,8 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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\
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- val = bcm_readl(irq_stat_addr[0] + src * sizeof(u32)); \
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- val &= bcm_readl(irq_mask_addr[0] + src * sizeof(u32)); \
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+ val = bcm_readl(irq_stat_addr[pin] + src * sizeof(u32)); \
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+ val &= bcm_readl(irq_mask_addr[pin] + src * sizeof(u32)); \
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+ val = bcm_readl(irq_stat_addr[cpu] + src * sizeof(u32)); \
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+ val &= bcm_readl(irq_mask_addr[cpu] + src * sizeof(u32)); \
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pending[--tgt] = val; \
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\
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if (val) \
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@ -51,8 +51,8 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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return; \
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\
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while (1) { \
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- int to_call = i; \
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+ int to_call = *next; \
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- unsigned int to_call = i; \
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+ unsigned int to_call = *next; \
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\
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- i = (i + 1) & (width - 1); \
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+ *next = (*next + 1) & (width - 1); \
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@ -1,8 +1,12 @@
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From 85257b702e1d4c6dcc839c737833c42ca53bae93 Mon Sep 17 00:00:00 2001
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From 5e86f3988854c62c0788e4820caf722fec7c791b Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Sun, 21 Apr 2013 15:38:56 +0200
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Subject: [PATCH 35/53] MIPS: BCM63XX: protect irq register accesses
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Subject: [PATCH 07/10] MIPS: BCM63XX: protect irq register accesses
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Since we will have the chance of accessing the registers concurrently,
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protect any accesses through a spinlock.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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arch/mips/bcm63xx/irq.c | 26 ++++++++++++++++++++++++++
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1 file changed, 26 insertions(+)
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@ -26,11 +30,11 @@ Subject: [PATCH 35/53] MIPS: BCM63XX: protect irq register accesses
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+
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static u32 irq_stat_addr[2];
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static u32 irq_mask_addr[2];
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static void (*dispatch_internal)(int pin);
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@@ -62,8 +66,10 @@ void __dispatch_internal_##width(int pin
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static void (*dispatch_internal)(int cpu);
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@@ -62,8 +66,10 @@ void __dispatch_internal_##width(int cpu
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bool irqs_pending = false; \
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static int i[2]; \
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int *next = &i[pin]; \
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static unsigned int i[2]; \
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unsigned int *next = &i[cpu]; \
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+ unsigned long flags; \
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\
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/* read registers in reverse order */ \
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@ -38,7 +42,7 @@ Subject: [PATCH 35/53] MIPS: BCM63XX: protect irq register accesses
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for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
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u32 val; \
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\
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@@ -74,6 +80,7 @@ void __dispatch_internal_##width(int pin
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@@ -74,6 +80,7 @@ void __dispatch_internal_##width(int cpu
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if (val) \
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irqs_pending = true; \
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} \
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@ -1,8 +1,9 @@
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From df6661d1b5c001eb91ce07f364fd5b6468fd6f99 Mon Sep 17 00:00:00 2001
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From 6e74b82aca08a5ecc4d2f0780254468659427e82 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Fri, 26 Apr 2013 12:03:15 +0200
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Subject: [PATCH 36/53] MIPS: BCM63XX: wire up the second cpu's irq line
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Subject: [PATCH 08/10] MIPS: BCM63XX: wire up the second cpu's irq line
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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arch/mips/bcm63xx/irq.c | 44 +++++++++++++++++++++++++++++++++++++-------
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1 file changed, 37 insertions(+), 7 deletions(-)
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@ -1,7 +1,7 @@
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From b665117faa0dfde70689502fc420d72bbf8e6bd4 Mon Sep 17 00:00:00 2001
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From e23dc903cd69d32d407ea1b7310bc9a71e00d359 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Tue, 30 Apr 2013 11:26:53 +0200
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Subject: [PATCH 37/53] MIPS: BCM63XX: use irq_desc as argument for (un)mask
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Subject: [PATCH 09/10] MIPS: BCM63XX: use irq_desc as argument for (un)mask
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In preparation for applying affinity, use the irq descriptor as the
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argument for (un)mask.
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@ -24,7 +24,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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static inline u32 get_ext_irq_perf_reg(int irq)
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@@ -96,9 +96,10 @@ void __dispatch_internal_##width(int pin
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@@ -96,9 +96,10 @@ void __dispatch_internal_##width(int cpu
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} \
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} \
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\
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@ -1,12 +1,16 @@
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From 9249f2f6a309e3f45c35d16decdcc5b2cadcadb8 Mon Sep 17 00:00:00 2001
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From 23493b47d8caaa59b18627a01bf443c3b50bb530 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Fri, 26 Apr 2013 12:06:03 +0200
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Subject: [PATCH 38/53] MIPS: BCM63XX: allow setting affinity for IPIC
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Subject: [PATCH 10/10] MIPS: BCM63XX: allow setting affinity for IPIC
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Wire up the set_affinity call for the internal PIC if booting on
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a cpu supporting it.
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Affinity is kept to boot cpu as default.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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arch/mips/bcm63xx/irq.c | 43 +++++++++++++++++++++++++++++++++++++------
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1 file changed, 37 insertions(+), 6 deletions(-)
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arch/mips/bcm63xx/irq.c | 46 ++++++++++++++++++++++++++++++++++++++++------
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1 file changed, 40 insertions(+), 6 deletions(-)
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--- a/arch/mips/bcm63xx/irq.c
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+++ b/arch/mips/bcm63xx/irq.c
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@ -27,8 +31,8 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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+ const struct cpumask *m)
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+{
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+ bool enable = cpu_online(cpu);
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+#ifdef CONFIG_SMP
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+
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+#ifdef CONFIG_SMP
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+ if (m)
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+ enable &= cpu_isset(cpu, *m);
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+ else if (irqd_affinity_was_set(d))
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@ -97,7 +101,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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static struct irq_chip bcm63xx_internal_irq_chip = {
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.name = "bcm63xx_ipic",
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.irq_mask = bcm63xx_internal_irq_mask,
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@@ -523,7 +551,10 @@ void __init arch_init_irq(void)
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@@ -523,7 +551,13 @@ void __init arch_init_irq(void)
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setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
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#ifdef CONFIG_SMP
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@ -106,6 +110,9 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action);
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+ bcm63xx_internal_irq_chip.irq_set_affinity =
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+ bcm63xx_internal_set_affinity;
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+
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+ cpumask_clear(irq_default_affinity);
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+ cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
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+ }
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#endif
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}
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@ -1,8 +1,7 @@
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From 653dcc09407a695efb203337c6f72515d4c4ee43 Mon Sep 17 00:00:00 2001
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From a2015bfad293a7eb79519beb60381cb996c6e298 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Thu, 21 Mar 2013 17:05:15 +0100
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Subject: [PATCH 29/53] MIPS: BCM63XX: rename __dispatch_internal to
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__dispatch_internal_32
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Subject: [PATCH 01/10] MIPS: BCM63XX: add width to __dispatch_internal
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Make it follow the same naming convention as the other functions.
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@ -1,9 +1,11 @@
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From c28c639b031385ecf965eecf3bfb532e88044c89 Mon Sep 17 00:00:00 2001
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From 6e79c6dd02aa56e37eb071797f0eb5e3fb588cba Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Sun, 15 Dec 2013 20:52:53 +0100
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Subject: [PATCH 30/53] MIPS: BCM63XX: move bcm63xx_init_irq down
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Subject: [PATCH 02/10] MIPS: BCM63XX: move bcm63xx_init_irq down
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Allows up to drop the prototypes from the top.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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arch/mips/bcm63xx/irq.c | 190 +++++++++++++++++++++++-------------------------
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1 file changed, 92 insertions(+), 98 deletions(-)
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@ -1,15 +1,22 @@
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From 01bf26c51b427e24ac69f604d33f7d9360a9e470 Mon Sep 17 00:00:00 2001
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From 39b46ed1c9fe71890566e129d9ac5feb8421b3b4 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Thu, 18 Apr 2013 21:14:49 +0200
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Subject: [PATCH 31/53] MIPS: BCM63XX: replace irq dispatch code with a generic
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Subject: [PATCH 03/10] MIPS: BCM63XX: replace irq dispatch code with a generic
|
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version
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|
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The generic version uses a variable length of u32 registers of u32/u64.
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This allows easier support for longer registers without having to rewrite
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verything.
|
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The generic version uses a variable length of u32 registers instead of u32/u64.
|
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This allows easier support for "wider" registers without having to rewrite
|
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everything.
|
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|
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This "generic" version is not slower than the old version in the best case
|
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(= i == next set bit), and twice as fast in the worst case in 64 bits.
|
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This "generic" version is as fast as the old version in the best case
|
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(i == next set bit), and twice as fast in the worst case in 64 bits.
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Using a macro was chosen over a (forced) inline version because gcc generated
|
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more compact code with the macro.
|
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|
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The change from (signed) int to unsigned int for i and to_call was intentional
|
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as the value can be only between 0 and (width - 1) anyway, and allowed gcc to
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optimise the code a bit further.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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@ -47,7 +54,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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+ u32 pending[width / 32]; \
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+ unsigned int src, tgt; \
|
||||
+ bool irqs_pending = false; \
|
||||
+ static int i; \
|
||||
+ static unsigned int i; \
|
||||
+ \
|
||||
+ /* read registers in reverse order */ \
|
||||
+ for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
|
||||
|
|
@ -65,7 +72,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
|
|||
+ return; \
|
||||
+ \
|
||||
+ while (1) { \
|
||||
+ int to_call = i; \
|
||||
+ unsigned int to_call = i; \
|
||||
+ \
|
||||
+ i = (i + 1) & (width - 1); \
|
||||
+ if (pending[to_call / 32] & (1 << (to_call & 0x1f))) { \
|
||||
|
|
|
|||
|
|
@ -1,10 +1,9 @@
|
|||
From 1003fb4a5ee9fcff518f20eefdee1a9bf500af7e Mon Sep 17 00:00:00 2001
|
||||
From 96ce0a9d195b2781d6f8d919dea8056b1c409703 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Gorski <jogo@openwrt.org>
|
||||
Date: Thu, 25 Apr 2013 00:24:06 +0200
|
||||
Subject: [PATCH 32/53] MIPS: BCM63XX: append irq line number to
|
||||
irq_{stat,mask}*
|
||||
Subject: [PATCH 04/10] MIPS: BCM63XX: append irq line to irq_{stat,mask}*
|
||||
|
||||
The SMP capable irq controllers have two interupt output pins which are
|
||||
The SMP capable irq controllers have two interrupt output pins which are
|
||||
controlled through separate registers, so make the variables arrays.
|
||||
|
||||
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
|
||||
|
|
@ -1,8 +1,10 @@
|
|||
From 842f213228e6fc9fd6cca01ab5128623112aa7a9 Mon Sep 17 00:00:00 2001
|
||||
From ff61c72a7a260ab4c4abbddb72c3cd2aea5e0687 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Gorski <jogo@openwrt.org>
|
||||
Date: Thu, 25 Apr 2013 00:31:29 +0200
|
||||
Subject: [PATCH 33/53] MIPS: BCM63XX: populate irq_{stat,mask}_addr for second
|
||||
pin
|
||||
Subject: [PATCH 05/10] MIPS: BCM63XX: populate irq_{stat,mask}_addr for second
|
||||
cpu
|
||||
|
||||
Set it to zero if there is no second set.
|
||||
|
||||
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
|
||||
---
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From a33bb660c712447ba8b561109cda6734954a6efa Mon Sep 17 00:00:00 2001
|
||||
From 43ebef8162adfa7789cb915e60e46103965d7efd Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Gorski <jogo@openwrt.org>
|
||||
Date: Fri, 26 Apr 2013 11:21:16 +0200
|
||||
Subject: [PATCH 34/53] MIPS: BCM63XX: add pin argument to dispatch internal
|
||||
Subject: [PATCH 06/10] MIPS: BCM63XX: add cpu argument to dispatch internal
|
||||
|
||||
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
|
||||
---
|
||||
|
|
@ -18,7 +18,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
|
|||
static u32 irq_stat_addr[2];
|
||||
static u32 irq_mask_addr[2];
|
||||
-static void (*dispatch_internal)(void);
|
||||
+static void (*dispatch_internal)(int pin);
|
||||
+static void (*dispatch_internal)(int cpu);
|
||||
static int is_ext_irq_cascaded;
|
||||
static unsigned int ext_irq_count;
|
||||
static unsigned int ext_irq_start, ext_irq_end;
|
||||
|
|
@ -27,14 +27,14 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
|
|||
|
||||
#define BUILD_IPIC_INTERNAL(width) \
|
||||
-void __dispatch_internal_##width(void) \
|
||||
+void __dispatch_internal_##width(int pin) \
|
||||
+void __dispatch_internal_##width(int cpu) \
|
||||
{ \
|
||||
u32 pending[width / 32]; \
|
||||
unsigned int src, tgt; \
|
||||
bool irqs_pending = false; \
|
||||
- static int i; \
|
||||
+ static int i[2]; \
|
||||
+ int *next = &i[pin]; \
|
||||
- static unsigned int i; \
|
||||
+ static unsigned int i[2]; \
|
||||
+ unsigned int *next = &i[cpu]; \
|
||||
\
|
||||
/* read registers in reverse order */ \
|
||||
for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
|
||||
|
|
@ -42,8 +42,8 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
|
|||
\
|
||||
- val = bcm_readl(irq_stat_addr[0] + src * sizeof(u32)); \
|
||||
- val &= bcm_readl(irq_mask_addr[0] + src * sizeof(u32)); \
|
||||
+ val = bcm_readl(irq_stat_addr[pin] + src * sizeof(u32)); \
|
||||
+ val &= bcm_readl(irq_mask_addr[pin] + src * sizeof(u32)); \
|
||||
+ val = bcm_readl(irq_stat_addr[cpu] + src * sizeof(u32)); \
|
||||
+ val &= bcm_readl(irq_mask_addr[cpu] + src * sizeof(u32)); \
|
||||
pending[--tgt] = val; \
|
||||
\
|
||||
if (val) \
|
||||
|
|
@ -51,8 +51,8 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
|
|||
return; \
|
||||
\
|
||||
while (1) { \
|
||||
- int to_call = i; \
|
||||
+ int to_call = *next; \
|
||||
- unsigned int to_call = i; \
|
||||
+ unsigned int to_call = *next; \
|
||||
\
|
||||
- i = (i + 1) & (width - 1); \
|
||||
+ *next = (*next + 1) & (width - 1); \
|
||||
|
|
@ -1,8 +1,12 @@
|
|||
From 85257b702e1d4c6dcc839c737833c42ca53bae93 Mon Sep 17 00:00:00 2001
|
||||
From 5e86f3988854c62c0788e4820caf722fec7c791b Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Gorski <jogo@openwrt.org>
|
||||
Date: Sun, 21 Apr 2013 15:38:56 +0200
|
||||
Subject: [PATCH 35/53] MIPS: BCM63XX: protect irq register accesses
|
||||
Subject: [PATCH 07/10] MIPS: BCM63XX: protect irq register accesses
|
||||
|
||||
Since we will have the chance of accessing the registers concurrently,
|
||||
protect any accesses through a spinlock.
|
||||
|
||||
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
|
||||
---
|
||||
arch/mips/bcm63xx/irq.c | 26 ++++++++++++++++++++++++++
|
||||
1 file changed, 26 insertions(+)
|
||||
|
|
@ -26,11 +30,11 @@ Subject: [PATCH 35/53] MIPS: BCM63XX: protect irq register accesses
|
|||
+
|
||||
static u32 irq_stat_addr[2];
|
||||
static u32 irq_mask_addr[2];
|
||||
static void (*dispatch_internal)(int pin);
|
||||
@@ -62,8 +66,10 @@ void __dispatch_internal_##width(int pin
|
||||
static void (*dispatch_internal)(int cpu);
|
||||
@@ -62,8 +66,10 @@ void __dispatch_internal_##width(int cpu
|
||||
bool irqs_pending = false; \
|
||||
static int i[2]; \
|
||||
int *next = &i[pin]; \
|
||||
static unsigned int i[2]; \
|
||||
unsigned int *next = &i[cpu]; \
|
||||
+ unsigned long flags; \
|
||||
\
|
||||
/* read registers in reverse order */ \
|
||||
|
|
@ -38,7 +42,7 @@ Subject: [PATCH 35/53] MIPS: BCM63XX: protect irq register accesses
|
|||
for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
|
||||
u32 val; \
|
||||
\
|
||||
@@ -74,6 +80,7 @@ void __dispatch_internal_##width(int pin
|
||||
@@ -74,6 +80,7 @@ void __dispatch_internal_##width(int cpu
|
||||
if (val) \
|
||||
irqs_pending = true; \
|
||||
} \
|
||||
|
|
|
|||
|
|
@ -1,8 +1,9 @@
|
|||
From df6661d1b5c001eb91ce07f364fd5b6468fd6f99 Mon Sep 17 00:00:00 2001
|
||||
From 6e74b82aca08a5ecc4d2f0780254468659427e82 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Gorski <jogo@openwrt.org>
|
||||
Date: Fri, 26 Apr 2013 12:03:15 +0200
|
||||
Subject: [PATCH 36/53] MIPS: BCM63XX: wire up the second cpu's irq line
|
||||
Subject: [PATCH 08/10] MIPS: BCM63XX: wire up the second cpu's irq line
|
||||
|
||||
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
|
||||
---
|
||||
arch/mips/bcm63xx/irq.c | 44 +++++++++++++++++++++++++++++++++++++-------
|
||||
1 file changed, 37 insertions(+), 7 deletions(-)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
From b665117faa0dfde70689502fc420d72bbf8e6bd4 Mon Sep 17 00:00:00 2001
|
||||
From e23dc903cd69d32d407ea1b7310bc9a71e00d359 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Gorski <jogo@openwrt.org>
|
||||
Date: Tue, 30 Apr 2013 11:26:53 +0200
|
||||
Subject: [PATCH 37/53] MIPS: BCM63XX: use irq_desc as argument for (un)mask
|
||||
Subject: [PATCH 09/10] MIPS: BCM63XX: use irq_desc as argument for (un)mask
|
||||
|
||||
In preparation for applying affinity, use the irq descriptor as the
|
||||
argument for (un)mask.
|
||||
|
|
@ -24,7 +24,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
|
|||
|
||||
|
||||
static inline u32 get_ext_irq_perf_reg(int irq)
|
||||
@@ -96,9 +96,10 @@ void __dispatch_internal_##width(int pin
|
||||
@@ -96,9 +96,10 @@ void __dispatch_internal_##width(int cpu
|
||||
} \
|
||||
} \
|
||||
\
|
||||
|
|
|
|||
|
|
@ -1,12 +1,16 @@
|
|||
From 9249f2f6a309e3f45c35d16decdcc5b2cadcadb8 Mon Sep 17 00:00:00 2001
|
||||
From 23493b47d8caaa59b18627a01bf443c3b50bb530 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Gorski <jogo@openwrt.org>
|
||||
Date: Fri, 26 Apr 2013 12:06:03 +0200
|
||||
Subject: [PATCH 38/53] MIPS: BCM63XX: allow setting affinity for IPIC
|
||||
Subject: [PATCH 10/10] MIPS: BCM63XX: allow setting affinity for IPIC
|
||||
|
||||
Wire up the set_affinity call for the internal PIC if booting on
|
||||
a cpu supporting it.
|
||||
Affinity is kept to boot cpu as default.
|
||||
|
||||
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
|
||||
---
|
||||
arch/mips/bcm63xx/irq.c | 43 +++++++++++++++++++++++++++++++++++++------
|
||||
1 file changed, 37 insertions(+), 6 deletions(-)
|
||||
arch/mips/bcm63xx/irq.c | 46 ++++++++++++++++++++++++++++++++++++++++------
|
||||
1 file changed, 40 insertions(+), 6 deletions(-)
|
||||
|
||||
--- a/arch/mips/bcm63xx/irq.c
|
||||
+++ b/arch/mips/bcm63xx/irq.c
|
||||
|
|
@ -27,8 +31,8 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
|
|||
+ const struct cpumask *m)
|
||||
+{
|
||||
+ bool enable = cpu_online(cpu);
|
||||
+#ifdef CONFIG_SMP
|
||||
+
|
||||
+#ifdef CONFIG_SMP
|
||||
+ if (m)
|
||||
+ enable &= cpu_isset(cpu, *m);
|
||||
+ else if (irqd_affinity_was_set(d))
|
||||
|
|
@ -97,7 +101,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
|
|||
static struct irq_chip bcm63xx_internal_irq_chip = {
|
||||
.name = "bcm63xx_ipic",
|
||||
.irq_mask = bcm63xx_internal_irq_mask,
|
||||
@@ -523,7 +551,10 @@ void __init arch_init_irq(void)
|
||||
@@ -523,7 +551,13 @@ void __init arch_init_irq(void)
|
||||
|
||||
setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
|
||||
#ifdef CONFIG_SMP
|
||||
|
|
@ -106,6 +110,9 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
|
|||
setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action);
|
||||
+ bcm63xx_internal_irq_chip.irq_set_affinity =
|
||||
+ bcm63xx_internal_set_affinity;
|
||||
+
|
||||
+ cpumask_clear(irq_default_affinity);
|
||||
+ cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
|
||||
+ }
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue