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uboot-lantiq: upgrade to 2013.01

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SVN-Revision: 35292
This commit is contained in:
Luka Perkov 2013-01-22 12:55:01 +00:00
parent bab482b93f
commit 2245726371
29 changed files with 13461 additions and 27 deletions
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62
package/boot/uboot-lantiq/Makefile
View file

@ -1,22 +1,20 @@
#
# Copyright (C) 2012 OpenWrt.org
# Copyright (C) 2012-2013 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=u-boot
PKG_VERSION:=2012.07
PKG_VERSION:=2013.01
PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=git://dev.phrozen.org/uboot-upstream.git
PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
PKG_SOURCE_VERSION:=a0342fc87a884a2f60e2849bcd48fe366ccf9366
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)-$(PKG_SOURCE_VERSION).tar.gz
PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:=ftp://ftp.denx.de/pub/u-boot
PKG_MD5SUM:=e58a8a7f78972248190d83de0dc362ce
PKG_TARGETS:=bin
PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
@ -25,35 +23,42 @@ include $(INCLUDE_DIR)/package.mk
define uboot/Default
TITLE:=
CONFIG:=
SOC:=
DDR_SETTINGS:=
IMAGE:=
endef
define uboot/arv4519pw_ram
TITLE:=U-Boot for Arcadyan arv4519pw (RAM)
SOC:=danube
DDR_SETTINGS:=board/arcadyan/arv4519pw/ddr_settings.h
endef
define uboot/arv4519pw_nor
TITLE:=U-Boot for Arcadyan arv4519pw (NOR)
SOC:=danube
endef
define uboot/arv7518pw_ram
TITLE:=U-Boot for Arcadyan arv7518pw (RAM)
SOC:=danube
DDR_SETTINGS:=board/arcadyan/arv7518pw/ddr_settings.h
endef
define uboot/arv7518pw_nor
TITLE:=U-Boot for Arcadyan arv7518pw (NOR)
SOC:=danube
endef
define uboot/gigasx76x_ram
TITLE:=U-Boot for Siemens Gigaset sx76x (RAM)
SOC:=danube
DDR_SETTINGS:=board/gigaset/sx76x/ddr_settings.h
endef
define uboot/gigasx76x_nor
TITLE:=U-Boot for Siemens Gigaset sx76x (NOR)
SOC:=danube
endef
UBOOTS:= \
@ -79,37 +84,40 @@ define BuildUBootPackage
$(call Package/uboot/template,$(1),$(TITLE))
endef
$(eval $(call uboot/$(BUILD_VARIANT)))
define Build/Configure
$(MAKE) -C $(PKG_BUILD_DIR) $(BUILD_VARIANT)_config
endef
define Build/Compile
$(MAKE) -C $(PKG_BUILD_DIR) $(BUILD_VARIANT) CROSS_COMPILE=$(TARGET_CROSS)
ifneq ($(DDR_SETTINGS),)
awk -f $(PKG_BUILD_DIR)/tools/lantiq_ram_init_uart.awk $(PKG_BUILD_DIR)/$(DDR_SETTINGS) > $(PKG_BUILD_DIR)/$(BUILD_VARIANT)_ddr_settings
perl $(PKG_BUILD_DIR)/tools/gct.pl $(PKG_BUILD_DIR)/$(BUILD_VARIANT)_ddr_settings $(PKG_BUILD_DIR)/u-boot.srec $(PKG_BUILD_DIR)/u-boot.asc
endif
$(MAKE) -C $(PKG_BUILD_DIR) CROSS_COMPILE=$(TARGET_CROSS)
endef
define Package/uboot/install/default
$(INSTALL_DIR) $(BIN_DIR)/uboot-$(BOARD)-$(1)
$(CP) $(PKG_BUILD_DIR)/u-boot.bin \
$(BIN_DIR)/uboot-$(BOARD)-$(1)/openwrt-$(BOARD)-$(1)-u-boot.bin
ifneq ($(DDR_SETTINGS),)
$(CP) $(PKG_BUILD_DIR)/u-boot.asc \
$(BIN_DIR)/uboot-$(BOARD)-$(1)/openwrt-$(BOARD)-$(1)-u-boot.asc
endif
$(CP) \
$(PKG_BUILD_DIR)/$(2) \
$(BIN_DIR)/uboot-$(BOARD)-$(1)/openwrt-$(BOARD)-$(1)-u-boot.img
endef
define Package/uboot/install/uart
awk -f $(PKG_BUILD_DIR)/tools/lantiq_ram_init_uart.awk \
-v soc=$(2) $(PKG_BUILD_DIR)/$(3) \
> $(PKG_BUILD_DIR)/ddr_settings
perl $(PKG_BUILD_DIR)/tools/gct.pl \
$(PKG_BUILD_DIR)/ddr_settings $(PKG_BUILD_DIR)/u-boot.srec \
$(BIN_DIR)/uboot-$(BOARD)-$(1)/openwrt-$(BOARD)-$(1)-u-boot.asc
endef
define Package/uboot/install/template
define Package/uboot-lantiq-$(1)/install
$(call Package/uboot/install/default,$(2))
$(call Package/uboot/install/default,$(1),$(if $(IMAGE),$(IMAGE),u-boot.bin))
$(if $(DDR_SETTINGS), \
$(call Package/uboot/install/uart,$(1),$(SOC),$(DDR_SETTINGS)) \
)
endef
endef
$(foreach u,$(UBOOTS), \
$(eval $(call Package/uboot/install/template,$(u),$(u))) \
)
$(foreach u,$(UBOOTS), \
$(eval $(call BuildUBootPackage,$(u))) \
$(eval $(call Package/uboot/install/template,$(u))) \
$(eval $(call BuildPackage,uboot-lantiq-$(u))) \
)

46
package/boot/uboot-lantiq/patches/0002-sf-handle-CONFIG_MANUAL_RELOC.patch Normal file
View file

@ -0,0 +1,46 @@
From 60e8a35f0efa5a7e5d797a3f239971c84061ef11 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Tue, 6 Nov 2012 21:39:47 +0100
Subject: sf: handle CONFIG_MANUAL_RELOC
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -293,7 +293,7 @@ int spi_flash_cmd_write_status(struct sp
*/
#define IDCODE_CONT_LEN 0
#define IDCODE_PART_LEN 5
-static const struct {
+static struct {
const u8 shift;
const u8 idcode;
struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode);
@@ -335,6 +335,10 @@ static const struct {
};
#define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN)
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode)
{
@@ -342,6 +346,16 @@ struct spi_flash *spi_flash_probe(unsign
struct spi_flash *flash = NULL;
int ret, i, shift;
u8 idcode[IDCODE_LEN], *idp;
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
+ static int relocated;
+
+ if (!relocated) {
+ for (i = 0; i < ARRAY_SIZE(flashes); i++)
+ flashes[i].probe += gd->reloc_off;
+
+ relocated = 1;
+ }
+#endif
spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
if (!spi) {

719
package/boot/uboot-lantiq/patches/0003-sf-factor-out-malloc-from-SPI-flash-drivers.patch Normal file
View file

@ -0,0 +1,719 @@
From 73d127565b5a4b19bcaacabc505689ee039f16fd Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Sun, 11 Nov 2012 03:11:38 +0100
Subject: sf: factor out malloc from SPI flash drivers
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/atmel.c
+++ b/drivers/mtd/spi/atmel.c
@@ -40,18 +40,6 @@ struct atmel_spi_flash_params {
const char *name;
};
-/* spi_flash needs to be first so upper layers can free() it */
-struct atmel_spi_flash {
- struct spi_flash flash;
- const struct atmel_spi_flash_params *params;
-};
-
-static inline struct atmel_spi_flash *
-to_atmel_spi_flash(struct spi_flash *flash)
-{
- return container_of(flash, struct atmel_spi_flash, flash);
-}
-
static const struct atmel_spi_flash_params atmel_spi_flash_table[] = {
{
.idcode1 = 0x22,
@@ -156,7 +144,8 @@ static int at45_wait_ready(struct spi_fl
* Assemble the address part of a command for AT45 devices in
* non-power-of-two page size mode.
*/
-static void at45_build_address(struct atmel_spi_flash *asf, u8 *cmd, u32 offset)
+static void at45_build_address(const struct atmel_spi_flash_params *params,
+ u8 *cmd, u32 offset)
{
unsigned long page_addr;
unsigned long byte_addr;
@@ -167,7 +156,7 @@ static void at45_build_address(struct at
* The "extra" space per page is the power-of-two page size
* divided by 32.
*/
- page_shift = asf->params->l2_page_size;
+ page_shift = params->l2_page_size;
page_size = (1 << page_shift) + (1 << (page_shift - 5));
page_shift++;
page_addr = offset / page_size;
@@ -181,11 +170,11 @@ static void at45_build_address(struct at
static int dataflash_read_fast_at45(struct spi_flash *flash,
u32 offset, size_t len, void *buf)
{
- struct atmel_spi_flash *asf = to_atmel_spi_flash(flash);
+ const struct atmel_spi_flash_params *params = flash->priv;
u8 cmd[5];
cmd[0] = CMD_READ_ARRAY_FAST;
- at45_build_address(asf, cmd + 1, offset);
+ at45_build_address(params, cmd + 1, offset);
cmd[4] = 0x00;
return spi_flash_read_common(flash, cmd, sizeof(cmd), buf, len);
@@ -197,7 +186,7 @@ static int dataflash_read_fast_at45(stru
static int dataflash_write_p2(struct spi_flash *flash,
u32 offset, size_t len, const void *buf)
{
- struct atmel_spi_flash *asf = to_atmel_spi_flash(flash);
+ const struct atmel_spi_flash_params *params = flash->priv;
unsigned long page_size;
u32 addr = offset;
size_t chunk_len;
@@ -211,7 +200,7 @@ static int dataflash_write_p2(struct spi
* the other is being programmed into main memory.
*/
- page_size = (1 << asf->params->l2_page_size);
+ page_size = (1 << params->l2_page_size);
ret = spi_claim_bus(flash->spi);
if (ret) {
@@ -263,7 +252,7 @@ out:
static int dataflash_write_at45(struct spi_flash *flash,
u32 offset, size_t len, const void *buf)
{
- struct atmel_spi_flash *asf = to_atmel_spi_flash(flash);
+ const struct atmel_spi_flash_params *params = flash->priv;
unsigned long page_addr;
unsigned long byte_addr;
unsigned long page_size;
@@ -279,7 +268,7 @@ static int dataflash_write_at45(struct s
* the other is being programmed into main memory.
*/
- page_shift = asf->params->l2_page_size;
+ page_shift = params->l2_page_size;
page_size = (1 << page_shift) + (1 << (page_shift - 5));
page_shift++;
page_addr = offset / page_size;
@@ -338,7 +327,7 @@ out:
*/
static int dataflash_erase_p2(struct spi_flash *flash, u32 offset, size_t len)
{
- struct atmel_spi_flash *asf = to_atmel_spi_flash(flash);
+ const struct atmel_spi_flash_params *params = flash->priv;
unsigned long page_size;
size_t actual;
@@ -351,7 +340,7 @@ static int dataflash_erase_p2(struct spi
* when possible.
*/
- page_size = (1 << asf->params->l2_page_size);
+ page_size = (1 << params->l2_page_size);
if (offset % page_size || len % page_size) {
debug("SF: Erase offset/length not multiple of page size\n");
@@ -397,7 +386,7 @@ out:
static int dataflash_erase_at45(struct spi_flash *flash, u32 offset, size_t len)
{
- struct atmel_spi_flash *asf = to_atmel_spi_flash(flash);
+ const struct atmel_spi_flash_params *params = flash->priv;
unsigned long page_addr;
unsigned long page_size;
unsigned int page_shift;
@@ -411,7 +400,7 @@ static int dataflash_erase_at45(struct s
* when possible.
*/
- page_shift = asf->params->l2_page_size;
+ page_shift = params->l2_page_size;
page_size = (1 << page_shift) + (1 << (page_shift - 5));
page_shift++;
page_addr = offset / page_size;
@@ -458,12 +447,12 @@ out:
return ret;
}
-struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode)
+int spi_flash_probe_atmel(struct spi_flash *flash, u8 *idcode)
{
const struct atmel_spi_flash_params *params;
+ struct spi_slave *spi = flash->spi;
unsigned page_size;
unsigned int family;
- struct atmel_spi_flash *asf;
unsigned int i;
int ret;
u8 status;
@@ -477,18 +466,11 @@ struct spi_flash *spi_flash_probe_atmel(
if (i == ARRAY_SIZE(atmel_spi_flash_table)) {
debug("SF: Unsupported DataFlash ID %02x\n",
idcode[1]);
- return NULL;
- }
-
- asf = malloc(sizeof(struct atmel_spi_flash));
- if (!asf) {
- debug("SF: Failed to allocate memory\n");
- return NULL;
+ return 0;
}
- asf->params = params;
- asf->flash.spi = spi;
- asf->flash.name = params->name;
+ flash->priv = (void *)params;
+ flash->name = params->name;
/* Assuming power-of-two page size initially. */
page_size = 1 << params->l2_page_size;
@@ -503,48 +485,44 @@ struct spi_flash *spi_flash_probe_atmel(
*/
ret = spi_flash_cmd(spi, CMD_AT45_READ_STATUS, &status, 1);
if (ret)
- goto err;
+ return -1;
debug("SF: AT45 status register: %02x\n", status);
if (!(status & AT45_STATUS_P2_PAGE_SIZE)) {
- asf->flash.read = dataflash_read_fast_at45;
- asf->flash.write = dataflash_write_at45;
- asf->flash.erase = dataflash_erase_at45;
+ flash->read = dataflash_read_fast_at45;
+ flash->write = dataflash_write_at45;
+ flash->erase = dataflash_erase_at45;
page_size += 1 << (params->l2_page_size - 5);
} else {
- asf->flash.read = spi_flash_cmd_read_fast;
- asf->flash.write = dataflash_write_p2;
- asf->flash.erase = dataflash_erase_p2;
+ flash->read = spi_flash_cmd_read_fast;
+ flash->write = dataflash_write_p2;
+ flash->erase = dataflash_erase_p2;
}
- asf->flash.page_size = page_size;
- asf->flash.sector_size = page_size;
+ flash->page_size = page_size;
+ flash->sector_size = page_size;
break;
case DF_FAMILY_AT26F:
case DF_FAMILY_AT26DF:
- asf->flash.read = spi_flash_cmd_read_fast;
- asf->flash.write = spi_flash_cmd_write_multi;
- asf->flash.erase = spi_flash_cmd_erase;
- asf->flash.page_size = page_size;
- asf->flash.sector_size = 4096;
+ flash->read = spi_flash_cmd_read_fast;
+ flash->write = spi_flash_cmd_write_multi;
+ flash->erase = spi_flash_cmd_erase;
+ flash->page_size = page_size;
+ flash->sector_size = 4096;
/* clear SPRL# bit for locked flash */
- spi_flash_cmd_write_status(&asf->flash, 0);
+ spi_flash_cmd_write_status(flash, 0);
break;
default:
debug("SF: Unsupported DataFlash family %u\n", family);
- goto err;
+ return -1;
}
- asf->flash.size = page_size * params->pages_per_block
+ flash->size = page_size * params->pages_per_block
* params->blocks_per_sector
* params->nr_sectors;
- return &asf->flash;
-
-err:
- free(asf);
- return NULL;
+ return 1;
}
--- a/drivers/mtd/spi/eon.c
+++ b/drivers/mtd/spi/eon.c
@@ -29,10 +29,9 @@ static const struct eon_spi_flash_params
},
};
-struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode)
+int spi_flash_probe_eon(struct spi_flash *flash, u8 *idcode)
{
const struct eon_spi_flash_params *params;
- struct spi_flash *flash;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(eon_spi_flash_table); ++i) {
@@ -43,16 +42,10 @@ struct spi_flash *spi_flash_probe_eon(st
if (i == ARRAY_SIZE(eon_spi_flash_table)) {
debug("SF: Unsupported EON ID %02x\n", idcode[1]);
- return NULL;
+ return 0;
}
- flash = malloc(sizeof(*flash));
- if (!flash) {
- debug("SF: Failed to allocate memory\n");
- return NULL;
- }
-
- flash->spi = spi;
+ flash->priv = (void *)params;
flash->name = params->name;
flash->write = spi_flash_cmd_write_multi;
@@ -63,5 +56,5 @@ struct spi_flash *spi_flash_probe_eon(st
flash->size = 256 * 16
* params->nr_sectors;
- return flash;
+ return 1;
}
--- a/drivers/mtd/spi/macronix.c
+++ b/drivers/mtd/spi/macronix.c
@@ -79,10 +79,9 @@ static const struct macronix_spi_flash_p
},
};
-struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode)
+int spi_flash_probe_macronix(struct spi_flash *flash, u8 *idcode)
{
const struct macronix_spi_flash_params *params;
- struct spi_flash *flash;
unsigned int i;
u16 id = idcode[2] | idcode[1] << 8;
@@ -94,16 +93,10 @@ struct spi_flash *spi_flash_probe_macron
if (i == ARRAY_SIZE(macronix_spi_flash_table)) {
debug("SF: Unsupported Macronix ID %04x\n", id);
- return NULL;
+ return 0;
}
- flash = malloc(sizeof(*flash));
- if (!flash) {
- debug("SF: Failed to allocate memory\n");
- return NULL;
- }
-
- flash->spi = spi;
+ flash->priv = (void *)params;
flash->name = params->name;
flash->write = spi_flash_cmd_write_multi;
@@ -116,5 +109,5 @@ struct spi_flash *spi_flash_probe_macron
/* Clear BP# bits for read-only flash */
spi_flash_cmd_write_status(flash, 0);
- return flash;
+ return 1;
}
--- a/drivers/mtd/spi/ramtron.c
+++ b/drivers/mtd/spi/ramtron.c
@@ -69,17 +69,6 @@ struct ramtron_spi_fram_params {
const char *name; /* name for display and/or matching */
};
-struct ramtron_spi_fram {
- struct spi_flash flash;
- const struct ramtron_spi_fram_params *params;
-};
-
-static inline struct ramtron_spi_fram *to_ramtron_spi_fram(struct spi_flash
- *flash)
-{
- return container_of(flash, struct ramtron_spi_fram, flash);
-}
-
/*
* table describing supported FRAM chips:
* chips without RDID command must have the values 0xff for id1 and id2
@@ -155,18 +144,18 @@ static const struct ramtron_spi_fram_par
static int ramtron_common(struct spi_flash *flash,
u32 offset, size_t len, void *buf, u8 command)
{
- struct ramtron_spi_fram *sn = to_ramtron_spi_fram(flash);
+ const struct ramtron_spi_fram_params *params = flash->priv;
u8 cmd[4];
int cmd_len;
int ret;
- if (sn->params->addr_len == 3 && sn->params->merge_cmd == 0) {
+ if (params->addr_len == 3 && params->merge_cmd == 0) {
cmd[0] = command;
cmd[1] = offset >> 16;
cmd[2] = offset >> 8;
cmd[3] = offset;
cmd_len = 4;
- } else if (sn->params->addr_len == 2 && sn->params->merge_cmd == 0) {
+ } else if (params->addr_len == 2 && params->merge_cmd == 0) {
cmd[0] = command;
cmd[1] = offset >> 8;
cmd[2] = offset;
@@ -230,10 +219,9 @@ static int ramtron_erase(struct spi_flas
* nore: we are called here with idcode pointing to the first non-0x7f byte
* already!
*/
-struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode)
+int spi_fram_probe_ramtron(struct spi_flash *flash, u8 *idcode)
{
const struct ramtron_spi_fram_params *params;
- struct ramtron_spi_fram *sn;
unsigned int i;
#ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
int ret;
@@ -259,11 +247,11 @@ struct spi_flash *spi_fram_probe_ramtron
*/
ret = spi_flash_cmd(spi, CMD_READ_STATUS, &sr, 1);
if (ret)
- return NULL;
+ return 0;
/* Bits 5,4,0 are fixed 0 for all devices */
if ((sr & 0x31) != 0x00)
- return NULL;
+ return 0;
/* now find the device */
for (i = 0; i < ARRAY_SIZE(ramtron_spi_fram_table); i++) {
params = &ramtron_spi_fram_table[i];
@@ -281,23 +269,16 @@ struct spi_flash *spi_fram_probe_ramtron
/* arriving here means no method has found a device we can handle */
debug("SF/ramtron: unsupported device id0=%02x id1=%02x id2=%02x\n",
idcode[0], idcode[1], idcode[2]);
- return NULL;
+ return 0;
found:
- sn = malloc(sizeof(*sn));
- if (!sn) {
- debug("SF: Failed to allocate memory\n");
- return NULL;
- }
+ flash->priv = (void *)params;
+ flash->name = params->name;
- sn->params = params;
- sn->flash.spi = spi;
- sn->flash.name = params->name;
-
- sn->flash.write = ramtron_write;
- sn->flash.read = ramtron_read;
- sn->flash.erase = ramtron_erase;
- sn->flash.size = params->size;
+ flash->write = ramtron_write;
+ flash->read = ramtron_read;
+ flash->erase = ramtron_erase;
+ flash->size = params->size;
- return &sn->flash;
+ return 1;
}
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd/spi/spansion.c
@@ -105,10 +105,9 @@ static const struct spansion_spi_flash_p
},
};
-struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode)
+int spi_flash_probe_spansion(struct spi_flash *flash, u8 *idcode)
{
const struct spansion_spi_flash_params *params;
- struct spi_flash *flash;
unsigned int i;
unsigned short jedec, ext_jedec;
@@ -125,16 +124,10 @@ struct spi_flash *spi_flash_probe_spansi
if (i == ARRAY_SIZE(spansion_spi_flash_table)) {
debug("SF: Unsupported SPANSION ID %04x %04x\n", jedec, ext_jedec);
- return NULL;
+ return 0;
}
- flash = malloc(sizeof(*flash));
- if (!flash) {
- debug("SF: Failed to allocate memory\n");
- return NULL;
- }
-
- flash->spi = spi;
+ flash->priv = (void *)params;
flash->name = params->name;
flash->write = spi_flash_cmd_write_multi;
@@ -144,5 +137,5 @@ struct spi_flash *spi_flash_probe_spansi
flash->sector_size = 256 * params->pages_per_sector;
flash->size = flash->sector_size * params->nr_sectors;
- return flash;
+ return 1;
}
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -296,7 +296,7 @@ int spi_flash_cmd_write_status(struct sp
static struct {
const u8 shift;
const u8 idcode;
- struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode);
+ int (*probe) (struct spi_flash *flash, u8 *idcode);
} flashes[] = {
/* Keep it sorted by define name */
#ifdef CONFIG_SPI_FLASH_ATMEL
@@ -343,7 +343,7 @@ struct spi_flash *spi_flash_probe(unsign
unsigned int max_hz, unsigned int spi_mode)
{
struct spi_slave *spi;
- struct spi_flash *flash = NULL;
+ struct spi_flash *flash;
int ret, i, shift;
u8 idcode[IDCODE_LEN], *idp;
#ifdef CONFIG_NEEDS_MANUAL_RELOC
@@ -379,6 +379,15 @@ struct spi_flash *spi_flash_probe(unsign
print_buffer(0, idcode, 1, sizeof(idcode), 0);
#endif
+ flash = malloc(sizeof(*flash));
+ if (!flash) {
+ debug("SF: failed to alloc memory\n");
+ goto err_malloc;
+ }
+
+ memset(flash, 0, sizeof(*flash));
+ flash->spi = spi;
+
/* count the number of continuation bytes */
for (shift = 0, idp = idcode;
shift < IDCODE_CONT_LEN && *idp == 0x7f;
@@ -389,12 +398,12 @@ struct spi_flash *spi_flash_probe(unsign
for (i = 0; i < ARRAY_SIZE(flashes); ++i)
if (flashes[i].shift == shift && flashes[i].idcode == *idp) {
/* we have a match, call probe */
- flash = flashes[i].probe(spi, idp);
- if (flash)
+ ret = flashes[i].probe(flash, idp);
+ if (ret)
break;
}
- if (!flash) {
+ if (ret <= 0) {
printf("SF: Unsupported manufacturer %02x\n", *idp);
goto err_manufacturer_probe;
}
@@ -408,6 +417,8 @@ struct spi_flash *spi_flash_probe(unsign
return flash;
err_manufacturer_probe:
+ free(flash);
+err_malloc:
err_read_id:
spi_release_bus(spi);
err_claim_bus:
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -98,11 +98,11 @@ int spi_flash_cmd_wait_ready(struct spi_
int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len);
/* Manufacturer-specific probe functions */
-struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode);
-struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode);
-struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode);
-struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode);
-struct spi_flash *spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode);
-struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode);
-struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode);
-struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode);
+int spi_flash_probe_spansion(struct spi_flash *flash, u8 *idcode);
+int spi_flash_probe_atmel(struct spi_flash *flash, u8 *idcode);
+int spi_flash_probe_eon(struct spi_flash *flash, u8 *idcode);
+int spi_flash_probe_macronix(struct spi_flash *flash, u8 *idcode);
+int spi_flash_probe_sst(struct spi_flash *flash, u8 *idcode);
+int spi_flash_probe_stmicro(struct spi_flash *flash, u8 *idcode);
+int spi_flash_probe_winbond(struct spi_flash *flash, u8 *idcode);
+int spi_fram_probe_ramtron(struct spi_flash *flash, u8 *idcode);
--- a/drivers/mtd/spi/sst.c
+++ b/drivers/mtd/spi/sst.c
@@ -39,11 +39,6 @@ struct sst_spi_flash_params {
const char *name;
};
-struct sst_spi_flash {
- struct spi_flash flash;
- const struct sst_spi_flash_params *params;
-};
-
static const struct sst_spi_flash_params sst_spi_flash_table[] = {
{
.idcode1 = 0x8d,
@@ -185,11 +180,9 @@ sst_write_wp(struct spi_flash *flash, u3
return ret;
}
-struct spi_flash *
-spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode)
+int spi_flash_probe_sst(struct spi_flash *flash, u8 *idcode)
{
const struct sst_spi_flash_params *params;
- struct sst_spi_flash *stm;
size_t i;
for (i = 0; i < ARRAY_SIZE(sst_spi_flash_table); ++i) {
@@ -200,31 +193,24 @@ spi_flash_probe_sst(struct spi_slave *sp
if (i == ARRAY_SIZE(sst_spi_flash_table)) {
debug("SF: Unsupported SST ID %02x\n", idcode[1]);
- return NULL;
- }
-
- stm = malloc(sizeof(*stm));
- if (!stm) {
- debug("SF: Failed to allocate memory\n");
- return NULL;
+ return 0;
}
- stm->params = params;
- stm->flash.spi = spi;
- stm->flash.name = params->name;
+ flash->priv = (void *)params;
+ flash->name = params->name;
- if (stm->params->flags & SST_FEAT_WP)
- stm->flash.write = sst_write_wp;
+ if (params->flags & SST_FEAT_WP)
+ flash->write = sst_write_wp;
else
- stm->flash.write = spi_flash_cmd_write_multi;
- stm->flash.erase = spi_flash_cmd_erase;
- stm->flash.read = spi_flash_cmd_read_fast;
- stm->flash.page_size = 256;
- stm->flash.sector_size = 4096;
- stm->flash.size = stm->flash.sector_size * params->nr_sectors;
+ flash->write = spi_flash_cmd_write_multi;
+ flash->erase = spi_flash_cmd_erase;
+ flash->read = spi_flash_cmd_read_fast;
+ flash->page_size = 256;
+ flash->sector_size = 4096;
+ flash->size = flash->sector_size * params->nr_sectors;
/* Flash powers up read-only, so clear BP# bits */
- spi_flash_cmd_write_status(&stm->flash, 0);
+ spi_flash_cmd_write_status(flash, 0);
- return &stm->flash;
+ return 1;
}
--- a/drivers/mtd/spi/stmicro.c
+++ b/drivers/mtd/spi/stmicro.c
@@ -112,10 +112,10 @@ static const struct stmicro_spi_flash_pa
},
};
-struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode)
+int spi_flash_probe_stmicro(struct spi_flash *flash, u8 * idcode)
{
const struct stmicro_spi_flash_params *params;
- struct spi_flash *flash;
+ struct spi_slave *spi = flash->spi;
unsigned int i;
u16 id;
@@ -123,13 +123,13 @@ struct spi_flash *spi_flash_probe_stmicr
i = spi_flash_cmd(spi, CMD_M25PXX_RES,
idcode, 4);
if (i)
- return NULL;
+ return 0;
if ((idcode[3] & 0xf0) == 0x10) {
idcode[0] = 0x20;
idcode[1] = 0x20;
idcode[2] = idcode[3] + 1;
} else
- return NULL;
+ return 0;
}
id = ((idcode[1] << 8) | idcode[2]);
@@ -143,16 +143,10 @@ struct spi_flash *spi_flash_probe_stmicr
if (i == ARRAY_SIZE(stmicro_spi_flash_table)) {
debug("SF: Unsupported STMicro ID %04x\n", id);
- return NULL;
+ return 0;
}
- flash = malloc(sizeof(*flash));
- if (!flash) {
- debug("SF: Failed to allocate memory\n");
- return NULL;
- }
-
- flash->spi = spi;
+ flash->priv = (void *)params;
flash->name = params->name;
flash->write = spi_flash_cmd_write_multi;
@@ -162,5 +156,5 @@ struct spi_flash *spi_flash_probe_stmicr
flash->sector_size = 256 * params->pages_per_sector;
flash->size = flash->sector_size * params->nr_sectors;
- return flash;
+ return 1;
}
--- a/drivers/mtd/spi/winbond.c
+++ b/drivers/mtd/spi/winbond.c
@@ -69,10 +69,9 @@ static const struct winbond_spi_flash_pa
},
};
-struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode)
+int spi_flash_probe_winbond(struct spi_flash *flash, u8 *idcode)
{
const struct winbond_spi_flash_params *params;
- struct spi_flash *flash;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(winbond_spi_flash_table); i++) {
@@ -84,16 +83,10 @@ struct spi_flash *spi_flash_probe_winbon
if (i == ARRAY_SIZE(winbond_spi_flash_table)) {
debug("SF: Unsupported Winbond ID %02x%02x\n",
idcode[1], idcode[2]);
- return NULL;
+ return 0;
}
- flash = malloc(sizeof(*flash));
- if (!flash) {
- debug("SF: Failed to allocate memory\n");
- return NULL;
- }
-
- flash->spi = spi;
+ flash->priv = (void *)params;
flash->name = params->name;
flash->write = spi_flash_cmd_write_multi;
@@ -103,5 +96,5 @@ struct spi_flash *spi_flash_probe_winbon
flash->sector_size = 4096;
flash->size = 4096 * 16 * params->nr_blocks;
- return flash;
+ return 1;
}
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -31,6 +31,7 @@ struct spi_flash {
struct spi_slave *spi;
const char *name;
+ void *priv;
/* Total flash size */
u32 size;

131
package/boot/uboot-lantiq/patches/0004-sf-add-malloc-free-probe-functions-dedicated-for-SPL.patch Normal file
View file

@ -0,0 +1,131 @@
From f9ab44c271fbd82a5702b6ba067fa90e33a30089 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Wed, 7 Nov 2012 15:29:27 +0100
Subject: sf: add malloc-free probe functions dedicated for SPL
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -339,11 +339,11 @@ static struct {
DECLARE_GLOBAL_DATA_PTR;
#endif
-struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int spi_mode)
+int spi_flash_probe_spl(struct spi_flash *flash, unsigned int bus,
+ unsigned int cs, unsigned int max_hz,
+ unsigned int spi_mode)
{
struct spi_slave *spi;
- struct spi_flash *flash;
int ret, i, shift;
u8 idcode[IDCODE_LEN], *idp;
#ifdef CONFIG_NEEDS_MANUAL_RELOC
@@ -359,8 +359,8 @@ struct spi_flash *spi_flash_probe(unsign
spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
if (!spi) {
- printf("SF: Failed to set up slave\n");
- return NULL;
+ debug("SF: Failed to set up slave\n");
+ return -1;
}
ret = spi_claim_bus(spi);
@@ -379,13 +379,6 @@ struct spi_flash *spi_flash_probe(unsign
print_buffer(0, idcode, 1, sizeof(idcode), 0);
#endif
- flash = malloc(sizeof(*flash));
- if (!flash) {
- debug("SF: failed to alloc memory\n");
- goto err_malloc;
- }
-
- memset(flash, 0, sizeof(*flash));
flash->spi = spi;
/* count the number of continuation bytes */
@@ -404,30 +397,58 @@ struct spi_flash *spi_flash_probe(unsign
}
if (ret <= 0) {
- printf("SF: Unsupported manufacturer %02x\n", *idp);
+ debug("SF: Unsupported manufacturer %02x\n", *idp);
goto err_manufacturer_probe;
}
- printf("SF: Detected %s with page size ", flash->name);
- print_size(flash->sector_size, ", total ");
- print_size(flash->size, "\n");
-
spi_release_bus(spi);
- return flash;
+ return 0;
err_manufacturer_probe:
- free(flash);
-err_malloc:
err_read_id:
spi_release_bus(spi);
err_claim_bus:
spi_free_slave(spi);
+
+ return ret;
+}
+
+struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode)
+{
+ struct spi_flash *flash;
+ int ret;
+
+ flash = malloc(sizeof(*flash));
+ if (!flash) {
+ debug("SF: Failed to malloc spi_flash\n");
+ return NULL;
+ }
+ memset(flash, 0, sizeof(*flash));
+
+ ret = spi_flash_probe_spl(flash, bus, cs, max_hz, spi_mode);
+ if (ret)
+ goto err_probe;
+
+ printf("SF: %s, page size ", flash->name);
+ print_size(flash->sector_size, ", total ");
+ print_size(flash->size, "\n");
+
+ return flash;
+
+err_probe:
+ free(flash);
return NULL;
}
-void spi_flash_free(struct spi_flash *flash)
+void spi_flash_free_spl(struct spi_flash *flash)
{
spi_free_slave(flash->spi);
+}
+
+void spi_flash_free(struct spi_flash *flash)
+{
+ spi_flash_free_spl(flash);
free(flash);
}
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -52,6 +52,11 @@ struct spi_flash *spi_flash_probe(unsign
unsigned int max_hz, unsigned int spi_mode);
void spi_flash_free(struct spi_flash *flash);
+int spi_flash_probe_spl(struct spi_flash *flash, unsigned int bus,
+ unsigned int cs, unsigned int max_hz,
+ unsigned int spi_mode);
+void spi_flash_free_spl(struct spi_flash *flash);
+
static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
size_t len, void *buf)
{

107
package/boot/uboot-lantiq/patches/0005-sf-factor-out-the-flash-address-calculation.patch Normal file
View file

@ -0,0 +1,107 @@
From acb2721e1cd2e7488a7b08a4ed590177369a1689 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Tue, 6 Nov 2012 19:10:40 +0100
Subject: sf: factor out the flash address calculation
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -15,12 +15,22 @@
#include "spi_flash_internal.h"
-static void spi_flash_addr(u32 addr, u8 *cmd)
+static void spi_flash_addr(struct spi_flash *flash, u32 addr, u8 *cmd, u8 *cmd_len)
{
/* cmd[0] is actual command */
cmd[1] = addr >> 16;
cmd[2] = addr >> 8;
cmd[3] = addr >> 0;
+ *cmd_len = 4;
+}
+
+static void spi_flash_page_addr(struct spi_flash *flash, u32 page_addr, u32 byte_addr, u8 *cmd, u8 *cmd_len)
+{
+ /* cmd[0] is actual command */
+ cmd[1] = page_addr >> 8;
+ cmd[2] = page_addr >> 0;
+ cmd[3] = byte_addr;
+ *cmd_len = 4;
}
static int spi_flash_read_write(struct spi_slave *spi,
@@ -71,7 +81,7 @@ int spi_flash_cmd_write_multi(struct spi
unsigned long page_addr, byte_addr, page_size;
size_t chunk_len, actual;
int ret;
- u8 cmd[4];
+ u8 cmd[4], cmd_len;
page_size = flash->page_size;
page_addr = offset / page_size;
@@ -87,9 +97,7 @@ int spi_flash_cmd_write_multi(struct spi
for (actual = 0; actual < len; actual += chunk_len) {
chunk_len = min(len - actual, page_size - byte_addr);
- cmd[1] = page_addr >> 8;
- cmd[2] = page_addr;
- cmd[3] = byte_addr;
+ spi_flash_page_addr(flash, page_addr, byte_addr, cmd, &cmd_len);
debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
@@ -100,7 +108,7 @@ int spi_flash_cmd_write_multi(struct spi
break;
}
- ret = spi_flash_cmd_write(flash->spi, cmd, 4,
+ ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
buf + actual, chunk_len);
if (ret < 0) {
debug("SF: write failed\n");
@@ -138,13 +146,13 @@ int spi_flash_read_common(struct spi_fla
int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
- u8 cmd[5];
+ u8 cmd[5], cmd_len;
cmd[0] = CMD_READ_ARRAY_FAST;
- spi_flash_addr(offset, cmd);
- cmd[4] = 0x00;
+ spi_flash_addr(flash, offset, cmd, &cmd_len);
+ cmd[cmd_len] = 0x00;
- return spi_flash_read_common(flash, cmd, sizeof(cmd), data, len);
+ return spi_flash_read_common(flash, cmd, cmd_len + 1, data, len);
}
int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
@@ -194,7 +202,7 @@ int spi_flash_cmd_erase(struct spi_flash
{
u32 start, end, erase_size;
int ret;
- u8 cmd[4];
+ u8 cmd[4], cmd_len;
erase_size = flash->sector_size;
if (offset % erase_size || len % erase_size) {
@@ -216,7 +224,7 @@ int spi_flash_cmd_erase(struct spi_flash
end = start + len;
while (offset < end) {
- spi_flash_addr(offset, cmd);
+ spi_flash_addr(flash, offset, cmd, &cmd_len);
offset += erase_size;
debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
@@ -226,7 +234,7 @@ int spi_flash_cmd_erase(struct spi_flash
if (ret)
goto out;
- ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), NULL, 0);
+ ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, NULL, 0);
if (ret)
goto out;

161
package/boot/uboot-lantiq/patches/0006-sf-add-generic-support-for-4-byte-address-mode.patch Normal file
View file

@ -0,0 +1,161 @@
From fb9ed0ef6f0ba6b6535c64dcfcf45c161723e56f Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Tue, 6 Nov 2012 19:31:38 +0100
Subject: sf: add generic support for 4-byte address mode
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -18,19 +18,35 @@
static void spi_flash_addr(struct spi_flash *flash, u32 addr, u8 *cmd, u8 *cmd_len)
{
/* cmd[0] is actual command */
- cmd[1] = addr >> 16;
- cmd[2] = addr >> 8;
- cmd[3] = addr >> 0;
- *cmd_len = 4;
+ if (spi_flash_use_4byte_mode(flash)) {
+ cmd[1] = addr >> 24;
+ cmd[2] = addr >> 16;
+ cmd[3] = addr >> 8;
+ cmd[4] = addr >> 0;
+ *cmd_len = 5;
+ } else {
+ cmd[1] = addr >> 16;
+ cmd[2] = addr >> 8;
+ cmd[3] = addr >> 0;
+ *cmd_len = 4;
+ }
}
static void spi_flash_page_addr(struct spi_flash *flash, u32 page_addr, u32 byte_addr, u8 *cmd, u8 *cmd_len)
{
/* cmd[0] is actual command */
- cmd[1] = page_addr >> 8;
- cmd[2] = page_addr >> 0;
- cmd[3] = byte_addr;
- *cmd_len = 4;
+ if (spi_flash_use_4byte_mode(flash)) {
+ cmd[1] = page_addr >> 16;
+ cmd[2] = page_addr >> 8;
+ cmd[3] = page_addr >> 0;
+ cmd[4] = byte_addr;
+ *cmd_len = 5;
+ } else {
+ cmd[1] = page_addr >> 8;
+ cmd[2] = page_addr >> 0;
+ cmd[3] = byte_addr;
+ *cmd_len = 4;
+ }
}
static int spi_flash_read_write(struct spi_slave *spi,
@@ -81,7 +97,7 @@ int spi_flash_cmd_write_multi(struct spi
unsigned long page_addr, byte_addr, page_size;
size_t chunk_len, actual;
int ret;
- u8 cmd[4], cmd_len;
+ u8 cmd[5], cmd_len;
page_size = flash->page_size;
page_addr = offset / page_size;
@@ -99,8 +115,8 @@ int spi_flash_cmd_write_multi(struct spi
spi_flash_page_addr(flash, page_addr, byte_addr, cmd, &cmd_len);
- debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
- buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+ debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x%02x } chunk_len = %zu\n",
+ buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], cmd[4], chunk_len);
ret = spi_flash_cmd_write_enable(flash);
if (ret < 0) {
@@ -146,7 +162,7 @@ int spi_flash_read_common(struct spi_fla
int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
- u8 cmd[5], cmd_len;
+ u8 cmd[6], cmd_len;
cmd[0] = CMD_READ_ARRAY_FAST;
spi_flash_addr(flash, offset, cmd, &cmd_len);
@@ -202,7 +218,7 @@ int spi_flash_cmd_erase(struct spi_flash
{
u32 start, end, erase_size;
int ret;
- u8 cmd[4], cmd_len;
+ u8 cmd[5], cmd_len;
erase_size = flash->sector_size;
if (offset % erase_size || len % erase_size) {
@@ -227,8 +243,8 @@ int spi_flash_cmd_erase(struct spi_flash
spi_flash_addr(flash, offset, cmd, &cmd_len);
offset += erase_size;
- debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
- cmd[2], cmd[3], offset);
+ debug("SF: erase %2x %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
+ cmd[2], cmd[3], cmd[4], offset);
ret = spi_flash_cmd_write_enable(flash);
if (ret)
@@ -409,6 +425,12 @@ int spi_flash_probe_spl(struct spi_flash
goto err_manufacturer_probe;
}
+ ret = spi_flash_set_4byte_mode(flash);
+ if (ret) {
+ debug("SF: Failed to enable 4 byte mode: %d\n", ret);
+ goto err_manufacturer_probe;
+ }
+
spi_release_bus(spi);
return 0;
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -97,6 +97,31 @@ int spi_flash_cmd_wait_ready(struct spi_
/* Erase sectors. */
int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len);
+#ifdef CONFIG_SPI_FLASH_4BYTE_MODE
+static inline int spi_flash_use_4byte_mode(struct spi_flash *flash)
+{
+ return NULL != flash->set_4byte_mode;
+}
+
+static inline int spi_flash_set_4byte_mode(struct spi_flash *flash)
+{
+ if (spi_flash_use_4byte_mode(flash))
+ return flash->set_4byte_mode(flash);
+
+ return 0;
+}
+#else
+static inline int spi_flash_use_4byte_mode(struct spi_flash *flash)
+{
+ return 0;
+}
+
+static inline int spi_flash_set_4byte_mode(struct spi_flash *flash)
+{
+ return 0;
+}
+#endif
+
/* Manufacturer-specific probe functions */
int spi_flash_probe_spansion(struct spi_flash *flash, u8 *idcode);
int spi_flash_probe_atmel(struct spi_flash *flash, u8 *idcode);
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -46,6 +46,9 @@ struct spi_flash {
size_t len, const void *buf);
int (*erase)(struct spi_flash *flash, u32 offset,
size_t len);
+#ifdef CONFIG_SPI_FLASH_4BYTE_MODE
+ int (*set_4byte_mode)(struct spi_flash *flash);
+#endif
};
struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,

45
package/boot/uboot-lantiq/patches/0007-sf-eon-use-16-bit-ID-for-comparison.patch Normal file
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@ -0,0 +1,45 @@
From d32f45357f0475a2f810752eeb9412fe692e1c0a Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Wed, 7 Nov 2012 14:09:21 +0100
Subject: sf: eon: use 16 bit ID for comparison
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/eon.c
+++ b/drivers/mtd/spi/eon.c
@@ -11,19 +11,19 @@
#include "spi_flash_internal.h"
struct eon_spi_flash_params {
- u8 idcode1;
+ u16 idcode;
u16 nr_sectors;
const char *name;
};
static const struct eon_spi_flash_params eon_spi_flash_table[] = {
{
- .idcode1 = 0x16,
+ .idcode = 0x3016,
.nr_sectors = 1024,
.name = "EN25Q32B",
},
{
- .idcode1 = 0x18,
+ .idcode = 0x3018,
.nr_sectors = 4096,
.name = "EN25Q128",
},
@@ -33,10 +33,11 @@ int spi_flash_probe_eon(struct spi_flash
{
const struct eon_spi_flash_params *params;
unsigned int i;
+ u16 id = idcode[2] | idcode[1] << 8;
for (i = 0; i < ARRAY_SIZE(eon_spi_flash_table); ++i) {
params = &eon_spi_flash_table[i];
- if (params->idcode1 == idcode[2])
+ if (params->idcode == id)
break;
}

43
package/boot/uboot-lantiq/patches/0008-sf-eon-add-support-for-4-byte-address-mode.patch Normal file
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@ -0,0 +1,43 @@
From 37254e3284f61ea495f73a78b7c8efae983781e2 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Wed, 7 Nov 2012 14:10:07 +0100
Subject: sf: eon: add support for 4-byte address mode
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/eon.c
+++ b/drivers/mtd/spi/eon.c
@@ -10,6 +10,8 @@
#include "spi_flash_internal.h"
+#define EN25XX_EN4B 0xb7 /* Enter 4-byte mode */
+
struct eon_spi_flash_params {
u16 idcode;
u16 nr_sectors;
@@ -29,6 +31,13 @@ static const struct eon_spi_flash_params
},
};
+static __maybe_unused int eon_set_4byte_mode(struct spi_flash *flash)
+{
+ struct spi_slave *spi = flash->spi;
+
+ return spi_flash_cmd(spi, EN25XX_EN4B, NULL, 0);
+}
+
int spi_flash_probe_eon(struct spi_flash *flash, u8 *idcode)
{
const struct eon_spi_flash_params *params;
@@ -57,5 +66,10 @@ int spi_flash_probe_eon(struct spi_flash
flash->size = 256 * 16
* params->nr_sectors;
+#ifdef CONFIG_SPI_FLASH_4BYTE_MODE
+ if (flash->size > (1 << 24))
+ flash->set_4byte_mode = eon_set_4byte_mode;
+#endif
+
return 1;
}

21
package/boot/uboot-lantiq/patches/0009-sf-eon-add-support-for-EN25QH256.patch Normal file
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@ -0,0 +1,21 @@
From e510be1145796cd44cf5800e187a94ad7c19e764 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Wed, 7 Nov 2012 14:10:34 +0100
Subject: sf: eon: add support for EN25QH256
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/eon.c
+++ b/drivers/mtd/spi/eon.c
@@ -29,6 +29,11 @@ static const struct eon_spi_flash_params
.nr_sectors = 4096,
.name = "EN25Q128",
},
+ {
+ .idcode = 0x7019,
+ .nr_sectors = 8192,
+ .name = "EN25QH256",
+ },
};
static __maybe_unused int eon_set_4byte_mode(struct spi_flash *flash)

30
package/boot/uboot-lantiq/patches/0010-sf-spansion-fix-device-IDs-and-sector-architecture-f.patch Normal file
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@ -0,0 +1,30 @@
From 81a8e9e192d53ce8b5cafd47190d6c6826519d09 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Wed, 7 Nov 2012 14:58:59 +0100
Subject: sf: spansion: fix device IDs and sector architecture for S25FL256S
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd/spi/spansion.c
@@ -97,11 +97,18 @@ static const struct spansion_spi_flash_p
.name = "S25FL129P_64K",
},
{
- .idcode1 = 0x2019,
+ .idcode1 = 0x0219,
.idcode2 = 0x4d01,
.pages_per_sector = 256,
.nr_sectors = 512,
- .name = "S25FL256S",
+ .name = "S25FL256S_64K",
+ },
+ {
+ .idcode1 = 0x0219,
+ .idcode2 = 0x4d00,
+ .pages_per_sector = 1024,
+ .nr_sectors = 128,
+ .name = "S25FL256S_256K",
},
};

55
package/boot/uboot-lantiq/patches/0011-sf-spansion-add-support-for-4-byte-address-mode.patch Normal file
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@ -0,0 +1,55 @@
From 0add8e5c60961d2b99174610df8d3d9d6d192b74 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Wed, 7 Nov 2012 14:16:11 +0100
Subject: sf: spansion: add support for 4-byte address mode
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd/spi/spansion.c
@@ -31,6 +31,10 @@
#include "spi_flash_internal.h"
+#define S25FLXX_BRRD 0x16 /* Read Bank Register */
+#define S25FLXX_BRWR 0x17 /* Write Bank Register */
+#define S25FLXX_BAR_EXTADD (1 << 7) /* Extended address enable */
+
struct spansion_spi_flash_params {
u16 idcode1;
u16 idcode2;
@@ -112,6 +116,23 @@ static const struct spansion_spi_flash_p
},
};
+static __maybe_unused int spansion_set_4byte_mode(struct spi_flash *flash)
+{
+ struct spi_slave *spi = flash->spi;
+ u8 bar, cmd;
+ int err;
+
+ cmd = S25FLXX_BRRD;
+ err = spi_flash_cmd(spi, cmd, &bar, 1);
+ if (err)
+ return err;
+
+ bar |= S25FLXX_BAR_EXTADD;
+ cmd = S25FLXX_BRWR;
+
+ return spi_flash_cmd_write(spi, &cmd, 1, &bar, 1);
+}
+
int spi_flash_probe_spansion(struct spi_flash *flash, u8 *idcode)
{
const struct spansion_spi_flash_params *params;
@@ -144,5 +165,10 @@ int spi_flash_probe_spansion(struct spi_
flash->sector_size = 256 * params->pages_per_sector;
flash->size = flash->sector_size * params->nr_sectors;
+#ifdef CONFIG_SPI_FLASH_4BYTE_MODE
+ if (flash->size > (1 << 24))
+ flash->set_4byte_mode = spansion_set_4byte_mode;
+#endif
+
return 1;
}

23
package/boot/uboot-lantiq/patches/0012-sf-spansion-add-support-for-S25FL512S.patch Normal file
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@ -0,0 +1,23 @@
From bff335ac524843bc90163c3b231091a5016f8670 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Wed, 7 Nov 2012 15:07:54 +0100
Subject: sf: spansion: add support for S25FL512S
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd/spi/spansion.c
@@ -114,6 +114,13 @@ static const struct spansion_spi_flash_p
.nr_sectors = 128,
.name = "S25FL256S_256K",
},
+ {
+ .idcode1 = 0x0220,
+ .idcode2 = 0x4d00,
+ .pages_per_sector = 1024,
+ .nr_sectors = 256,
+ .name = "S25FL512S_256K",
+ },
};
static __maybe_unused int spansion_set_4byte_mode(struct spi_flash *flash)

44
package/boot/uboot-lantiq/patches/0013-sf-macronix-add-support-for-4-byte-address-mode.patch Normal file
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@ -0,0 +1,44 @@
From 207662a9270cc542709fbab0d25fbc361b39748c Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Wed, 7 Nov 2012 15:13:49 +0100
Subject: sf: macronix: add support for 4-byte address mode
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/macronix.c
+++ b/drivers/mtd/spi/macronix.c
@@ -35,6 +35,8 @@
#include "spi_flash_internal.h"
+#define MX25XX_EN4B 0xb7 /* Enter 4-byte mode */
+
struct macronix_spi_flash_params {
u16 idcode;
u16 nr_blocks;
@@ -79,6 +81,13 @@ static const struct macronix_spi_flash_p
},
};
+static __maybe_unused int macronix_set_4byte_mode(struct spi_flash *flash)
+{
+ struct spi_slave *spi = flash->spi;
+
+ return spi_flash_cmd(spi, MX25XX_EN4B, NULL, 0);
+}
+
int spi_flash_probe_macronix(struct spi_flash *flash, u8 *idcode)
{
const struct macronix_spi_flash_params *params;
@@ -106,6 +115,11 @@ int spi_flash_probe_macronix(struct spi_
flash->sector_size = 256 * 16 * 16;
flash->size = flash->sector_size * params->nr_blocks;
+#ifdef CONFIG_SPI_FLASH_4BYTE_MODE
+ if (flash->size > (1 << 24))
+ flash->set_4byte_mode = macronix_set_4byte_mode;
+#endif
+
/* Clear BP# bits for read-only flash */
spi_flash_cmd_write_status(flash, 0);

21
package/boot/uboot-lantiq/patches/0014-sf-macronix-add-support-for-MX25L25635E.patch Normal file
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@ -0,0 +1,21 @@
From 0f31fef3d6a5110684ea31c5064c45fc448013d6 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Wed, 7 Nov 2012 15:14:24 +0100
Subject: sf: macronix: add support for MX25L25635E
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/macronix.c
+++ b/drivers/mtd/spi/macronix.c
@@ -79,6 +79,11 @@ static const struct macronix_spi_flash_p
.nr_blocks = 256,
.name = "MX25L12855E",
},
+ {
+ .idcode = 0x2019,
+ .nr_blocks = 512,
+ .name = "MX25L25635E",
+ },
};
static __maybe_unused int macronix_set_4byte_mode(struct spi_flash *flash)

21
package/boot/uboot-lantiq/patches/0015-sf-macronix-add-support-for-MX66L51235L.patch Normal file
View file

@ -0,0 +1,21 @@
From a2d80b6b91ac63beea31455ce8d136230c030500 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Wed, 7 Nov 2012 15:14:40 +0100
Subject: sf: macronix: add support for MX66L51235L
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/macronix.c
+++ b/drivers/mtd/spi/macronix.c
@@ -84,6 +84,11 @@ static const struct macronix_spi_flash_p
.nr_blocks = 512,
.name = "MX25L25635E",
},
+ {
+ .idcode = 0x201A,
+ .nr_blocks = 1024,
+ .name = "MX66L51235L",
+ },
};
static __maybe_unused int macronix_set_4byte_mode(struct spi_flash *flash)

133
package/boot/uboot-lantiq/patches/0016-sf-add-MTD-layer-driver-for-SPI-flash-devices.patch Normal file
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@ -0,0 +1,133 @@
From 7f6ded11965b09daf6da44d4fa98da17b9fba36c Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Tue, 6 Nov 2012 19:41:26 +0100
Subject: sf: add MTD layer driver for SPI flash devices
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -30,6 +30,7 @@ COBJS-$(CONFIG_SPL_SPI_LOAD) += spi_spl_
endif
COBJS-$(CONFIG_SPI_FLASH) += spi_flash.o
+COBJS-$(CONFIG_SPI_FLASH_MTD) += spi_flash_mtd.o
COBJS-$(CONFIG_SPI_FLASH_ATMEL) += atmel.o
COBJS-$(CONFIG_SPI_FLASH_EON) += eon.o
COBJS-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.o
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -122,6 +122,9 @@ static inline int spi_flash_set_4byte_mo
}
#endif
+/* SPI flash MTD adapter init */
+int spi_flash_mtd_init(struct spi_flash *flash);
+
/* Manufacturer-specific probe functions */
int spi_flash_probe_spansion(struct spi_flash *flash, u8 *idcode);
int spi_flash_probe_atmel(struct spi_flash *flash, u8 *idcode);
--- /dev/null
+++ b/drivers/mtd/spi/spi_flash_mtd.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * MTD layer driver for SPI flash devices
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/errno.h>
+#include <linux/mtd/mtd.h>
+#include <spi_flash.h>
+
+static struct mtd_info sf_mtd_info;
+static char sf_mtd_name[8];
+
+static int spi_flash_mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+ struct spi_flash *flash = mtd->priv;
+ int err;
+
+ instr->state = MTD_ERASING;
+
+ err = spi_flash_erase(flash, instr->addr, instr->len);
+ if (err) {
+ instr->state = MTD_ERASE_FAILED;
+ instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
+ return -EIO;
+ }
+
+ instr->state = MTD_ERASE_DONE;
+ mtd_erase_callback(instr);
+
+ return 0;
+}
+
+static int spi_flash_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ struct spi_flash *flash = mtd->priv;
+ int err;
+
+ err = spi_flash_read(flash, from, len, buf);
+ if (!err)
+ *retlen = len;
+
+ return err;
+}
+
+static int spi_flash_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t *retlen, const u_char *buf)
+{
+ struct spi_flash *flash = mtd->priv;
+ int err;
+
+ err = spi_flash_write(flash, to, len, buf);
+ if (!err)
+ *retlen = len;
+
+ return err;
+}
+
+static void spi_flash_mtd_sync(struct mtd_info *mtd)
+{
+}
+
+static int spi_flash_mtd_number(void)
+{
+#ifdef CONFIG_SYS_MAX_FLASH_BANKS
+ return CONFIG_SYS_MAX_FLASH_BANKS;
+#else
+ return 0;
+#endif
+}
+
+int spi_flash_mtd_init(struct spi_flash *flash)
+{
+ memset(&sf_mtd_info, 0, sizeof(sf_mtd_info));
+ sprintf(sf_mtd_name, "nor%d", spi_flash_mtd_number());
+
+ sf_mtd_info.name = sf_mtd_name;
+ sf_mtd_info.type = MTD_NORFLASH;
+ sf_mtd_info.flags = MTD_CAP_NORFLASH;
+ sf_mtd_info.writesize = 1;
+
+ sf_mtd_info.erase = spi_flash_mtd_erase;
+ sf_mtd_info.read = spi_flash_mtd_read;
+ sf_mtd_info.write = spi_flash_mtd_write;
+ sf_mtd_info.sync = spi_flash_mtd_sync;
+
+ sf_mtd_info.size = flash->size;
+ sf_mtd_info.priv = flash;
+
+ /* Only uniform flash devices for now */
+ sf_mtd_info.numeraseregions = 0;
+ sf_mtd_info.erasesize = flash->sector_size;
+
+ return add_mtd_device(&sf_mtd_info);
+}

57
package/boot/uboot-lantiq/patches/0017-sf-add-init-function.patch Normal file
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@ -0,0 +1,57 @@
From aa9d5d64ca6441cb24e22dc3c1f707da62da2887 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Tue, 6 Nov 2012 19:35:17 +0100
Subject: sf: add init function
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -482,3 +482,36 @@ void spi_flash_free(struct spi_flash *fl
spi_flash_free_spl(flash);
free(flash);
}
+
+#ifdef CONFIG_SPI_FLASH_MTD
+static int spi_flash_mtd_register(void)
+{
+ struct spi_flash *flash;
+ int err;
+
+ flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+ CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+ if (!flash)
+ return -1;
+
+ err = spi_flash_mtd_init(flash);
+ if (err)
+ spi_flash_free(flash);
+
+ return err;
+}
+#else
+static int spi_flash_mtd_register(void)
+{
+ return 0;
+}
+#endif
+
+int spi_flash_init(void)
+{
+ int err;
+
+ err = spi_flash_mtd_register();
+
+ return err;
+}
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -51,6 +51,8 @@ struct spi_flash {
#endif
};
+int spi_flash_init(void);
+
struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode);
void spi_flash_free(struct spi_flash *flash);

47
package/boot/uboot-lantiq/patches/0018-MIPS-add-SPI-flash-init-hook.patch Normal file
View file

@ -0,0 +1,47 @@
From 888b33e84082fe72d60d528c05c885c0c9d70bc4 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Tue, 6 Nov 2012 21:19:43 +0100
Subject: MIPS: add SPI flash init hook
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/arch/mips/lib/board.c
+++ b/arch/mips/lib/board.c
@@ -32,6 +32,7 @@
#include <nand.h>
#include <onenand_uboot.h>
#include <spi.h>
+#include <spi_flash.h>
#ifdef CONFIG_BITBANGMII
#include <miiphy.h>
@@ -312,6 +313,16 @@ void board_init_r(gd_t *id, ulong dest_a
onenand_init();
#endif
+#ifdef CONFIG_CMD_SPI
+ puts("SPI: ");
+ spi_init(); /* go init the SPI */
+ puts("ready\n");
+#endif
+
+#if defined(CONFIG_SPI_FLASH)
+ spi_flash_init();
+#endif
+
/* relocate environment function pointers etc. */
env_relocate();
@@ -335,12 +346,6 @@ void board_init_r(gd_t *id, ulong dest_a
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
-#ifdef CONFIG_CMD_SPI
- puts("SPI: ");
- spi_init(); /* go init the SPI */
- puts("ready\n");
-#endif
-
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
misc_init_r();

239
package/boot/uboot-lantiq/patches/0019-net-switchlib-add-framework-for-ethernet-switch-driv.patch Normal file
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@ -0,0 +1,239 @@
From d8b1597130d228bc7e2bafd0c8d097529018c833 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Wed, 29 Aug 2012 22:08:15 +0200
Subject: net: switchlib: add framework for ethernet switch drivers
Add a generic framework similar to phylib for ethernet switch
drivers and devices. This is useful to share the init and
setup code for switch devices across different boards.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
--- a/Makefile
+++ b/Makefile
@@ -291,6 +291,7 @@ LIBS-y += drivers/mtd/ubi/libubi.o
LIBS-y += drivers/mtd/spi/libspi_flash.o
LIBS-y += drivers/net/libnet.o
LIBS-y += drivers/net/phy/libphy.o
+LIBS-y += drivers/net/switch/libswitch.o
LIBS-y += drivers/pci/libpci.o
LIBS-y += drivers/pcmcia/libpcmcia.o
LIBS-y += drivers/power/libpower.o \
--- /dev/null
+++ b/drivers/net/switch/Makefile
@@ -0,0 +1,31 @@
+#
+# This file is released under the terms of GPL v2 and any later version.
+# See the file COPYING in the root directory of the source tree for details.
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+# Copyright (C) 2011-2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+#
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)libswitch.o
+
+COBJS-$(CONFIG_SWITCH_MULTI) += switch.o
+
+COBJS := $(COBJS-y)
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(LIB)
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/drivers/net/switch/switch.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2011-2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <switch.h>
+
+static struct list_head switch_drivers;
+static struct list_head switch_devices;
+
+void switch_init(void)
+{
+ INIT_LIST_HEAD(&switch_drivers);
+ INIT_LIST_HEAD(&switch_devices);
+
+ board_switch_init();
+}
+
+void switch_driver_register(struct switch_driver *drv)
+{
+ INIT_LIST_HEAD(&drv->list);
+ list_add_tail(&drv->list, &switch_drivers);
+}
+
+int switch_device_register(struct switch_device *dev)
+{
+ struct switch_driver *drv;
+
+ /* Add switch device only, if an adequate driver is registered */
+ list_for_each_entry(drv, &switch_drivers, list) {
+ if (!strcmp(drv->name, dev->name)) {
+ dev->drv = drv;
+
+ INIT_LIST_HEAD(&dev->list);
+ list_add_tail(&dev->list, &switch_devices);
+
+ return 0;
+ }
+ }
+
+ return -1;
+}
+
+struct switch_device *switch_connect(struct mii_dev *bus)
+{
+ struct switch_device *sw;
+ int err;
+
+ list_for_each_entry(sw, &switch_devices, list) {
+ sw->bus = bus;
+
+ err = sw->drv->probe(sw);
+ if (!err)
+ return sw;
+ }
+
+ return NULL;
+}
--- /dev/null
+++ b/include/switch.h
@@ -0,0 +1,95 @@
+/*
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
+ */
+
+#ifndef __SWITCH_H
+#define __SWITCH_H
+
+#include <linux/list.h>
+
+#define SWITCH_NAME_SIZE 32
+
+struct switch_device;
+struct mii_dev;
+
+struct switch_driver {
+ struct list_head list;
+
+ /* Switch device name */
+ const char name[SWITCH_NAME_SIZE];
+
+ /*
+ * Called to probe the switch chip. Must return 0 if the switch
+ * chip matches the given switch device/driver combination. Otherwise
+ * 1 must be returned.
+ */
+ int (*probe) (struct switch_device *dev);
+
+ /*
+ * Called to initialize the switch chip.
+ */
+ void (*setup) (struct switch_device *dev);
+};
+
+struct switch_device {
+ struct list_head list;
+ struct switch_driver *drv;
+
+ /* MII bus the switch chip is connected to */
+ struct mii_dev *bus;
+
+ /* Switch device name */
+ const char name[SWITCH_NAME_SIZE];
+
+ /* Bitmask for board specific setup of used switch ports */
+ u16 port_mask;
+
+ /* Number of switch port that is connected to host CPU */
+ u16 cpu_port;
+};
+
+/*
+ * Board specific switch initialization.
+ *
+ * Called from switch_init to register the board specific switch_device
+ * structure.
+ */
+extern int board_switch_init(void);
+
+/* Initialize switch subsystem */
+#ifdef CONFIG_SWITCH_MULTI
+extern void switch_init(void);
+#else
+static inline void switch_init(void)
+{
+}
+#endif
+
+/* Register a switch driver */
+extern void switch_driver_register(struct switch_driver *drv);
+
+/* Register a switch device */
+extern int switch_device_register(struct switch_device *dev);
+
+/*
+ * Probe the available switch chips and connect the found one
+ * with the given MII bus
+ */
+extern struct switch_device *switch_connect(struct mii_dev *bus);
+
+/*
+ * Setup the given switch device
+ */
+static inline void switch_setup(struct switch_device *dev)
+{
+ if (dev->drv->setup)
+ dev->drv->setup(dev);
+}
+
+/* Init functions for supported Switch drivers */
+
+#endif /* __SWITCH_H */
+
--- a/net/eth.c
+++ b/net/eth.c
@@ -26,6 +26,7 @@
#include <net.h>
#include <miiphy.h>
#include <phy.h>
+#include <switch.h>
void eth_parse_enetaddr(const char *addr, uchar *enetaddr)
{
@@ -303,6 +304,8 @@ int eth_initialize(bd_t *bis)
phy_init();
#endif
+ switch_init();
+
eth_env_init(bis);
/*

162
package/boot/uboot-lantiq/patches/0020-net-switchlib-add-driver-for-Lantiq-PSB697X-switch-f.patch Normal file
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@ -0,0 +1,162 @@
From b8c666eda693906488637c414db9db35b6760e4a Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Wed, 29 Aug 2012 22:08:15 +0200
Subject: net: switchlib: add driver for Lantiq PSB697X switch family
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/net/switch/Makefile
+++ b/drivers/net/switch/Makefile
@@ -11,6 +11,7 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libswitch.o
COBJS-$(CONFIG_SWITCH_MULTI) += switch.o
+COBJS-$(CONFIG_SWITCH_PSB697X) += psb697x.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+++ b/drivers/net/switch/psb697x.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2011-2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <switch.h>
+#include <miiphy.h>
+
+#define PSB697X_CHIPID1 0x2599
+#define PSB697X_PORT_COUNT 7
+
+#define PSB697X_PORT_BASE(p) (p * 0x20)
+#define PSB697X_REG_PS(p) (PSB697X_PORT_BASE(p) + 0x00)
+#define PSB697X_REG_PBC(p) (PSB697X_PORT_BASE(p) + 0x01)
+#define PSB697X_REG_PEC(p) (PSB697X_PORT_BASE(p) + 0x02)
+
+#define PSB697X_REG_SGC1 0x0E0 /* Switch Global Control Register 1 */
+#define PSB697X_REG_SGC2 0x0E1 /* Switch Global Control Register 2 */
+#define PSB697X_REG_CMH 0x0E2 /* CPU Port & Mirror Control */
+#define PSB697X_REG_MIICR 0x0F5 /* MII Port Control */
+#define PSB697X_REG_CI0 0x100 /* Chip Identifier 0 */
+#define PSB697X_REG_CI1 0x101 /* Chip Identifier 1 */
+#define PSB697X_REG_MIIAC 0x120 /* MII Indirect Access Control */
+#define PSB697X_REG_MIIWD 0x121 /* MII Indirect Write Data */
+#define PSB697X_REG_MIIRD 0x122 /* MII Indirect Read Data */
+
+#define PSB697X_REG_PORT_FLP (1 << 2) /* Force link up */
+#define PSB697X_REG_PORT_FLD (1 << 1) /* Force link down */
+
+#define PSB697X_REG_SGC2_SE (1 << 15) /* Switch enable */
+
+#define PSB697X_REG_CMH_CPN_MASK 0x7
+#define PSB697X_REG_CMH_CPN_SHIFT 5
+
+
+static inline int psb697x_mii_read(struct mii_dev *bus, u16 reg)
+{
+ int ret;
+
+ ret = bus->read(bus, (reg >> 5) & 0x1f, MDIO_DEVAD_NONE, reg & 0x1f);
+
+ return ret;
+}
+
+static inline int psb697x_mii_write(struct mii_dev *bus, u16 reg, u16 val)
+{
+ int ret;
+
+ ret = bus->write(bus, (reg >> 5) & 0x1f, MDIO_DEVAD_NONE,
+ reg & 0x1f, val);
+
+ return ret;
+}
+
+static int psb697x_probe(struct switch_device *dev)
+{
+ struct mii_dev *bus = dev->bus;
+ int ci1;
+
+ ci1 = psb697x_mii_read(bus, PSB697X_REG_CI1);
+
+ if (ci1 == PSB697X_CHIPID1)
+ return 0;
+
+ return 1;
+}
+
+static void psb697x_setup(struct switch_device *dev)
+{
+ struct mii_dev *bus = dev->bus;
+ int i, state;
+
+ /* Enable switch */
+ psb697x_mii_write(bus, PSB697X_REG_SGC2, PSB697X_REG_SGC2_SE);
+
+ /*
+ * Force 100 Mbps as default value for CPU ports 5 and 6 to get
+ * full speed.
+ */
+ psb697x_mii_write(bus, PSB697X_REG_MIICR, 0x0773);
+
+ for (i = 0; i < PSB697X_PORT_COUNT; i++) {
+ state = dev->port_mask & (1 << i);
+
+ /*
+ * Software workaround from Errata Sheet:
+ * Force link down and reset internal PHY, keep that state
+ * for all unconnected ports and disable force link down
+ * for all connected ports
+ */
+ psb697x_mii_write(bus, PSB697X_REG_PBC(i),
+ PSB697X_REG_PORT_FLD);
+
+ if (i == dev->cpu_port)
+ /* Force link up for CPU port */
+ psb697x_mii_write(bus, PSB697X_REG_PBC(i),
+ PSB697X_REG_PORT_FLP);
+ else if (state)
+ /* Disable force link down for active LAN ports */
+ psb697x_mii_write(bus, PSB697X_REG_PBC(i), 0);
+ }
+}
+
+static struct switch_driver psb697x_drv = {
+ .name = "psb697x",
+};
+
+void switch_psb697x_init(void)
+{
+ /* For archs with manual relocation */
+ psb697x_drv.probe = psb697x_probe;
+ psb697x_drv.setup = psb697x_setup;
+
+ switch_driver_register(&psb697x_drv);
+}
--- a/drivers/net/switch/switch.c
+++ b/drivers/net/switch/switch.c
@@ -18,6 +18,10 @@ void switch_init(void)
INIT_LIST_HEAD(&switch_drivers);
INIT_LIST_HEAD(&switch_devices);
+#if defined(CONFIG_SWITCH_PSB697X)
+ switch_psb697x_init();
+#endif
+
board_switch_init();
}
--- a/include/switch.h
+++ b/include/switch.h
@@ -90,6 +90,7 @@ static inline void switch_setup(struct s
}
/* Init functions for supported Switch drivers */
+extern void switch_psb697x_init(void);
#endif /* __SWITCH_H */

158
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@ -0,0 +1,158 @@
From fcbbb1beb2ae862f5c703c5719ed0e155cbbf82f Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Wed, 29 Aug 2012 22:08:16 +0200
Subject: net: switchlib: add driver for Lantiq ADM6996I switch family
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/net/switch/Makefile
+++ b/drivers/net/switch/Makefile
@@ -12,6 +12,7 @@ LIB := $(obj)libswitch.o
COBJS-$(CONFIG_SWITCH_MULTI) += switch.o
COBJS-$(CONFIG_SWITCH_PSB697X) += psb697x.o
+COBJS-$(CONFIG_SWITCH_ADM6996I) += adm6996i.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+++ b/drivers/net/switch/adm6996i.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2011-2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <switch.h>
+#include <miiphy.h>
+
+#define ADM6996I_CHIPID0 0x1020
+#define ADM6996I_CHIPID1 0x0007
+#define ADM6996I_PORT_COUNT 6
+
+#define ADM6996I_REG_P0BC 0x001 /* P0 Basic Control */
+#define ADM6996I_REG_P1BC 0x003 /* P1 Basic Control */
+#define ADM6996I_REG_P2BC 0x005 /* P2 Basic Control */
+#define ADM6996I_REG_P3BC 0x007 /* P3 Basic Control */
+#define ADM6996I_REG_P4BC 0x008 /* P4 Basic Control */
+#define ADM6996I_REG_P5BC 0x009 /* P5 Basic Control */
+
+#define ADM6996I_REG_P0EC 0x002 /* P0 Extended Control */
+#define ADM6996I_REG_P1EC 0x002 /* P1 Extended Control */
+#define ADM6996I_REG_P2EC 0x004 /* P2 Extended Control */
+#define ADM6996I_REG_P3EC 0x004 /* P3 Extended Control */
+#define ADM6996I_REG_P4EC 0x006 /* P4 Extended Control */
+#define ADM6996I_REG_P5EC 0x006 /* P5 Extended Control */
+
+#define ADM6996I_REG_SC4 0x012 /* System Control 4 */
+
+#define ADM6996I_REG_CI0 0xA0 /* Chip Identifier 0 */
+#define ADM6996I_REG_CI1 0xA1 /* Chip Identifier 1 */
+
+#define ADM6996I_REG_PXBC_DEFAULT 0x040F
+#define ADM6996I_REG_PXBC_CROSS_EE (1 << 15)
+#define ADM6996I_REG_PXBC_PD (1 << 5)
+
+#define ADM6996I_REG_SC4_DEFAULT 0x3600
+#define ADM6996I_REG_SC4_LED_ENABLE (1 << 1)
+
+#define ADM6996I_REG_CI0_PC_MASK 0xFFF0
+#define ADM6996I_REG_CI0_VN_MASK 0xF
+#define ADM6996I_REG_CI1_PC_MASK 0xF
+
+
+static inline int adm6996i_mii_read(struct mii_dev *bus, u16 reg)
+{
+ int ret;
+
+ ret = bus->read(bus, (reg >> 5) & 0x1f, MDIO_DEVAD_NONE, reg & 0x1f);
+
+ return ret;
+}
+
+static inline int adm6996i_mii_write(struct mii_dev *bus, u16 reg, u16 val)
+{
+ int ret;
+
+ ret = bus->write(bus, (reg >> 5) & 0x1f, MDIO_DEVAD_NONE,
+ reg & 0x1f, val);
+
+ return ret;
+}
+
+static int adm6996i_probe(struct switch_device *dev)
+{
+ struct mii_dev *bus = dev->bus;
+ u16 ci0, ci1;
+
+ ci0 = adm6996i_mii_read(bus, ADM6996I_REG_CI0);
+ ci1 = adm6996i_mii_read(bus, ADM6996I_REG_CI1);
+
+ ci0 &= ADM6996I_REG_CI0_PC_MASK;
+ ci1 &= ADM6996I_REG_CI1_PC_MASK;
+
+ if (ci0 == ADM6996I_CHIPID0 && ci1 == ADM6996I_CHIPID1)
+ return 0;
+
+ return 1;
+}
+
+static void adm6996i_setup(struct switch_device *dev)
+{
+ struct mii_dev *bus = dev->bus;
+ u16 val;
+
+ /*
+ * Write default values (Port enable, 100 Mbps, Full Duplex,
+ * Auto negotiation, Flow control) and enable crossover auto-detect
+ */
+ val = ADM6996I_REG_PXBC_DEFAULT | ADM6996I_REG_PXBC_CROSS_EE;
+ adm6996i_mii_write(bus, ADM6996I_REG_P0BC, val);
+ adm6996i_mii_write(bus, ADM6996I_REG_P1BC, val);
+ adm6996i_mii_write(bus, ADM6996I_REG_P2BC, val);
+ adm6996i_mii_write(bus, ADM6996I_REG_P3BC, val);
+ adm6996i_mii_write(bus, ADM6996I_REG_P4BC, val);
+ adm6996i_mii_write(bus, ADM6996I_REG_P5BC, val);
+
+ val = ADM6996I_REG_SC4_DEFAULT | ADM6996I_REG_SC4_LED_ENABLE;
+ adm6996i_mii_write(bus, ADM6996I_REG_SC4, val);
+}
+
+static struct switch_driver adm6996i_drv = {
+ .name = "adm6996i",
+};
+
+void switch_adm6996i_init(void)
+{
+ /* For archs with manual relocation */
+ adm6996i_drv.probe = adm6996i_probe;
+ adm6996i_drv.setup = adm6996i_setup;
+
+ switch_driver_register(&adm6996i_drv);
+}
--- a/drivers/net/switch/switch.c
+++ b/drivers/net/switch/switch.c
@@ -21,6 +21,9 @@ void switch_init(void)
#if defined(CONFIG_SWITCH_PSB697X)
switch_psb697x_init();
#endif
+#if defined(CONFIG_SWITCH_ADM6996I)
+ switch_adm6996i_init();
+#endif
board_switch_init();
}
--- a/include/switch.h
+++ b/include/switch.h
@@ -91,6 +91,7 @@ static inline void switch_setup(struct s
/* Init functions for supported Switch drivers */
extern void switch_psb697x_init(void);
+extern void switch_adm6996i_init(void);
#endif /* __SWITCH_H */

158
package/boot/uboot-lantiq/patches/0022-net-switchlib-add-driver-for-Atheros-AR8216.patch Normal file
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@ -0,0 +1,158 @@
From 16b8c52f80f20e07866e397ff52ff9658766437b Mon Sep 17 00:00:00 2001
From: Luka Perkov <luka@openwrt.org>
Date: Wed, 29 Aug 2012 22:08:16 +0200
Subject: net: switchlib: add driver for Atheros AR8216
Signed-off-by: Luka Perkov <luka@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/net/switch/Makefile
+++ b/drivers/net/switch/Makefile
@@ -13,6 +13,7 @@ LIB := $(obj)libswitch.o
COBJS-$(CONFIG_SWITCH_MULTI) += switch.o
COBJS-$(CONFIG_SWITCH_PSB697X) += psb697x.o
COBJS-$(CONFIG_SWITCH_ADM6996I) += adm6996i.o
+COBJS-$(CONFIG_SWITCH_AR8216) += ar8216.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+++ b/drivers/net/switch/ar8216.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <switch.h>
+#include <netdev.h>
+
+#define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
+
+#define AR8216_REG_CTRL 0x0000
+#define AR8216_CTRL_REVISION BITS(0, 8)
+#define AR8216_CTRL_VERSION BITS(8, 8)
+
+#define AR8216_PROBE_RETRIES 10
+
+static void split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
+{
+ regaddr >>= 1;
+ *r1 = regaddr & 0x1e;
+
+ regaddr >>= 5;
+ *r2 = regaddr & 0x7;
+
+ regaddr >>= 3;
+ *page = regaddr & 0x1ff;
+}
+
+static int ar8216_mii_read(struct mii_dev *bus, u32 reg)
+{
+ u16 r1, r2, page;
+ u16 lo, hi;
+
+ split_addr(reg, &r1, &r2, &page);
+
+ bus->write(bus, 0x18, MDIO_DEVAD_NONE, 0, page);
+ __udelay(1000);
+
+ lo = bus->read(bus, 0x10 | r2, MDIO_DEVAD_NONE, r1);
+ hi = bus->read(bus, 0x10 | r2, MDIO_DEVAD_NONE, r1 + 1);
+
+ return (hi << 16) | lo;
+}
+
+static void ar8216_mii_write(struct mii_dev *bus, u16 reg, u32 val)
+{
+ u16 r1, r2, r3;
+ u16 lo, hi;
+
+ split_addr((u32) reg, &r1, &r2, &r3);
+
+ bus->write(bus, 0x18, MDIO_DEVAD_NONE, 0, r3);
+ __udelay(1000);
+
+ lo = val & 0xffff;
+ hi = (u16) (val >> 16);
+ bus->write(bus, 0x10 | r2, MDIO_DEVAD_NONE, r1 + 1, hi);
+ bus->write(bus, 0x10 | r2, MDIO_DEVAD_NONE, r1, lo);
+}
+
+static int ar8216_probe(struct switch_device *dev)
+{
+ struct mii_dev *bus = dev->bus;
+ u32 val;
+ u16 id;
+
+ val = ar8216_mii_read(bus, AR8216_REG_CTRL);
+ if (val == ~0)
+ return 1;
+
+ id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
+
+ switch (id) {
+ case 0x0101:
+ return 0;
+ default:
+ return 1;
+ }
+}
+
+static void ar8216_setup(struct switch_device *dev)
+{
+ struct mii_dev *bus = dev->bus;
+
+ ar8216_mii_write(bus, 0x200, 0x200);
+ ar8216_mii_write(bus, 0x300, 0x200);
+ ar8216_mii_write(bus, 0x400, 0x200);
+ ar8216_mii_write(bus, 0x500, 0x200);
+ ar8216_mii_write(bus, 0x600, 0x7d);
+ ar8216_mii_write(bus, 0x38, 0xc000050e);
+ ar8216_mii_write(bus, 0x104, 0x4004);
+ ar8216_mii_write(bus, 0x60, 0xffffffff);
+ ar8216_mii_write(bus, 0x64, 0xaaaaaaaa);
+ ar8216_mii_write(bus, 0x68, 0x55555555);
+ ar8216_mii_write(bus, 0x6c, 0x0);
+ ar8216_mii_write(bus, 0x70, 0x41af);
+}
+
+static struct switch_driver ar8216_drv = {
+ .name = "ar8216",
+};
+
+void switch_ar8216_init(void)
+{
+ /* for archs with manual relocation */
+ ar8216_drv.probe = ar8216_probe;
+ ar8216_drv.setup = ar8216_setup;
+
+ switch_driver_register(&ar8216_drv);
+}
--- a/drivers/net/switch/switch.c
+++ b/drivers/net/switch/switch.c
@@ -24,6 +24,9 @@ void switch_init(void)
#if defined(CONFIG_SWITCH_ADM6996I)
switch_adm6996i_init();
#endif
+#if defined(CONFIG_SWITCH_AR8216)
+ switch_ar8216_init();
+#endif
board_switch_init();
}
--- a/include/switch.h
+++ b/include/switch.h
@@ -92,6 +92,7 @@ static inline void switch_setup(struct s
/* Init functions for supported Switch drivers */
extern void switch_psb697x_init(void);
extern void switch_adm6996i_init(void);
+extern void switch_ar8216_init(void);
#endif /* __SWITCH_H */

9496
package/boot/uboot-lantiq/patches/0023-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch Normal file
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File diff suppressed because it is too large Load diff

33
package/boot/uboot-lantiq/patches/0024-MIPS-VRX200-add-option-to-boot-from-AVM-EVA-loader.patch Normal file
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@ -0,0 +1,33 @@
From 2c6115188c7353a601835885a6c544240cfc479e Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Fri, 30 Nov 2012 18:09:25 +0100
Subject: MIPS: VRX200: add option to boot from AVM EVA loader
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/arch/mips/cpu/mips32/vrx200/config.mk
+++ b/arch/mips/cpu/mips32/vrx200/config.mk
@@ -17,6 +17,9 @@ endif
LIBS-y += $(CPUDIR)/lantiq-common/liblantiq-common.o
ifndef CONFIG_SPL_BUILD
+ifdef CONFIG_SYS_BOOT_EVA
+ALL-y += $(obj)u-boot.bin.lzma
+endif
ifdef CONFIG_SYS_BOOT_SFSPL
ALL-y += $(obj)u-boot.ltq.sfspl
ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.sfspl
--- a/arch/mips/include/asm/arch-vrx200/config.h
+++ b/arch/mips/include/asm/arch-vrx200/config.h
@@ -161,6 +161,11 @@
#define CONFIG_SYS_DISABLE_CACHE
#endif
+#if defined(CONFIG_SYS_BOOT_EVA)
+#define CONFIG_SYS_TEXT_BASE 0x80100000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
#if defined(CONFIG_SYS_BOOT_NOR)
#define CONFIG_SYS_TEXT_BASE 0xB0000000
#endif

355
package/boot/uboot-lantiq/patches/0025-MIPS-add-board-support-for-AVM-FritzBox-3370.patch Normal file
View file

@ -0,0 +1,355 @@
From 51f04c00e831b49587f9f766ff1af67d2122feb2 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Fri, 30 Nov 2012 18:09:47 +0100
Subject: MIPS: add board support for AVM FritzBox 3370
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- /dev/null
+++ b/board/avm/fb3370/Makefile
@@ -0,0 +1,29 @@
+#
+# This file is released under the terms of GPL v2 and any later version.
+# See the file COPYING in the root directory of the source tree for details.
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/board/avm/fb3370/config.mk
@@ -0,0 +1,8 @@
+#
+# This file is released under the terms of GPL v2 and any later version.
+# See the file COPYING in the root directory of the source tree for details.
+#
+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/avm/fb3370/ddr_settings.h
@@ -0,0 +1,70 @@
+/*
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
+ */
+
+#define MC_CCR00_VALUE 0x101
+#define MC_CCR01_VALUE 0x1000100
+#define MC_CCR02_VALUE 0x1010000
+#define MC_CCR03_VALUE 0x101
+#define MC_CCR04_VALUE 0x1000000
+#define MC_CCR05_VALUE 0x1000101
+#define MC_CCR06_VALUE 0x1000100
+#define MC_CCR07_VALUE 0x1010000
+#define MC_CCR08_VALUE 0x1000101
+#define MC_CCR09_VALUE 0x0
+#define MC_CCR10_VALUE 0x2000100
+#define MC_CCR11_VALUE 0x2000300
+#define MC_CCR12_VALUE 0x30000
+#define MC_CCR13_VALUE 0x202
+#define MC_CCR14_VALUE 0x7080A0F
+#define MC_CCR15_VALUE 0x2040F
+#define MC_CCR16_VALUE 0x40000
+#define MC_CCR17_VALUE 0x70102
+#define MC_CCR18_VALUE 0x4020002
+#define MC_CCR19_VALUE 0x30302
+#define MC_CCR20_VALUE 0x8000700
+#define MC_CCR21_VALUE 0x40F020A
+#define MC_CCR22_VALUE 0x0
+#define MC_CCR23_VALUE 0xC020000
+#define MC_CCR24_VALUE 0x4401B04
+#define MC_CCR25_VALUE 0x0
+#define MC_CCR26_VALUE 0x0
+#define MC_CCR27_VALUE 0x6420000
+#define MC_CCR28_VALUE 0x0
+#define MC_CCR29_VALUE 0x0
+#define MC_CCR30_VALUE 0x798
+#define MC_CCR31_VALUE 0x0
+#define MC_CCR32_VALUE 0x0
+#define MC_CCR33_VALUE 0x650000
+#define MC_CCR34_VALUE 0x200C8
+#define MC_CCR35_VALUE 0x1D445D
+#define MC_CCR36_VALUE 0xC8
+#define MC_CCR37_VALUE 0xC351
+#define MC_CCR38_VALUE 0x0
+#define MC_CCR39_VALUE 0x141F04
+#define MC_CCR40_VALUE 0x142704
+#define MC_CCR41_VALUE 0x141b42
+#define MC_CCR42_VALUE 0x141b42
+#define MC_CCR43_VALUE 0x566504
+#define MC_CCR44_VALUE 0x566504
+#define MC_CCR45_VALUE 0x565F17
+#define MC_CCR46_VALUE 0x565F17
+#define MC_CCR47_VALUE 0x0
+#define MC_CCR48_VALUE 0x0
+#define MC_CCR49_VALUE 0x0
+#define MC_CCR50_VALUE 0x0
+#define MC_CCR51_VALUE 0x0
+#define MC_CCR52_VALUE 0x133
+#define MC_CCR53_VALUE 0xF3014B27
+#define MC_CCR54_VALUE 0xF3014B27
+#define MC_CCR55_VALUE 0xF3014B27
+#define MC_CCR56_VALUE 0xF3014B27
+#define MC_CCR57_VALUE 0x7800301
+#define MC_CCR58_VALUE 0x7800301
+#define MC_CCR59_VALUE 0x7800301
+#define MC_CCR60_VALUE 0x7800301
+#define MC_CCR61_VALUE 0x4
--- /dev/null
+++ b/board/avm/fb3370/fb3370.c
@@ -0,0 +1,139 @@
+/*
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/chipid.h>
+#include <asm/lantiq/cpu.h>
+#include <asm/arch/gphy.h>
+
+#if defined(CONFIG_SPL_BUILD)
+#define do_gpio_init 1
+#define do_pll_init 1
+#define do_dcdc_init 0
+#elif defined(CONFIG_SYS_BOOT_RAM)
+#define do_gpio_init 1
+#define do_pll_init 0
+#define do_dcdc_init 1
+#elif defined(CONFIG_SYS_BOOT_NOR)
+#define do_gpio_init 1
+#define do_pll_init 1
+#define do_dcdc_init 1
+#else
+#define do_gpio_init 0
+#define do_pll_init 0
+#define do_dcdc_init 1
+#endif
+
+static void gpio_init(void)
+{
+ /* SPI CS 0.4 to serial flash */
+ gpio_direction_output(10, 1);
+
+ /* EBU.FL_CS1 as output for NAND CE */
+ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* EBU.FL_A23 as output for NAND CLE */
+ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* EBU.FL_A24 as output for NAND ALE */
+ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* GPIO 3.0 as input for NAND Ready Busy */
+ gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);
+ /* GPIO 3.1 as output for NAND Read */
+ gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+}
+
+int board_early_init_f(void)
+{
+ if (do_gpio_init)
+ gpio_init();
+
+ if (do_pll_init)
+ ltq_pll_init();
+
+ if (do_dcdc_init)
+ ltq_dcdc_init(0x7F);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */
+ { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+ /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */
+ { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+ /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */
+ { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
+ /* GMAC3: unused */
+ { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
+ /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */
+ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
+ /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */
+ { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t * bis)
+{
+ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
+ const ulong fw_addr = 0x80FF0000;
+
+ ltq_gphy_phy11g_a1x_load(fw_addr);
+
+ ltq_cgu_gphy_clk_src(clk);
+
+ ltq_rcu_gphy_boot(0, fw_addr);
+ ltq_rcu_gphy_boot(1, fw_addr);
+
+ return ltq_eth_initialize(&eth_board_config);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ if (bus)
+ return 0;
+
+ if (cs == 4)
+ return 1;
+
+ return 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 4:
+ gpio_set_value(10, 0);
+ break;
+ default:
+ break;
+ }
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 4:
+ gpio_set_value(10, 1);
+ break;
+ default:
+ break;
+ }
+}
--- a/boards.cfg
+++ b/boards.cfg
@@ -451,6 +451,9 @@ incaip mips
incaip_100MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=100000000
incaip_133MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=133000000
incaip_150MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=150000000
+fb3370_ram mips mips32 fb3370 avm vrx200 fb3370:SYS_BOOT_RAM
+fb3370_eva mips mips32 fb3370 avm vrx200 fb3370:SYS_BOOT_EVA
+fb3370_sfspl mips mips32 fb3370 avm vrx200 fb3370:SYS_BOOT_SFSPL
easy80920_nor mips mips32 easy80920 lantiq vrx200 easy80920:SYS_BOOT_NOR
easy80920_norspl mips mips32 easy80920 lantiq vrx200 easy80920:SYS_BOOT_NORSPL
easy80920_ram mips mips32 easy80920 lantiq vrx200 easy80920:SYS_BOOT_RAM
--- /dev/null
+++ b/include/configs/fb3370.h
@@ -0,0 +1,75 @@
+/*
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "FB3370"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "AVM FritzBox 3370"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+
+#define CONFIG_LTQ_SUPPORT_SPI_FLASH
+#define CONFIG_SPI_FLASH_MACRONIX /* Have a MX29LV620 serial flash */
+
+#define CONFIG_LTQ_SUPPORT_NAND_FLASH
+
+#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH /* Build SPI flash SPL */
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 4
+#define CONFIG_SPL_SPI_MAX_HZ 25000000
+#define CONFIG_SPL_SPI_MODE 0
+
+#define CONFIG_LTQ_SPL_COMP_LZO
+#define CONFIG_LTQ_SPL_CONSOLE
+
+#define CONFIG_SYS_DRAM_PROBE
+
+/* Environment */
+#define CONFIG_ENV_SPI_BUS CONFIG_SPL_SPI_BUS
+#define CONFIG_ENV_SPI_CS CONFIG_SPL_SPI_CS
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SPL_SPI_MAX_HZ
+#define CONFIG_ENV_SPI_MODE CONFIG_SPL_SPI_MODE
+
+#if defined(CONFIG_SYS_BOOT_SFSPL)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (192 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Commands */
+#define CONFIG_CMD_PING
+
+/* Pull in default board configs for Lantiq XWAY VRX200 */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+#define CONFIG_ENV_UPDATE_UBOOT_SF \
+ "update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ CONFIG_ENV_UPDATE_UBOOT_SF
+
+#endif /* __CONFIG_H */

264
package/boot/uboot-lantiq/patches/0026-MIPS-add-board-support-for-Gigaset-SX76X.patch Normal file
View file

@ -0,0 +1,264 @@
From 66b56aa3a4810f10e0b0c77bb87279a8d64b566b Mon Sep 17 00:00:00 2001
From: Luka Perkov <luka@openwrt.org>
Date: Fri, 16 Dec 2011 11:55:45 +0100
Subject: MIPS: add board support for Gigaset SX76X
Signed-off-by: Luka Perkov <luka@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- /dev/null
+++ b/board/gigaset/sx76x/Makefile
@@ -0,0 +1,29 @@
+#
+# This file is released under the terms of GPL v2 and any later version.
+# See the file COPYING in the root directory of the source tree for details.
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/board/gigaset/sx76x/config.mk
@@ -0,0 +1,8 @@
+#
+# This file is released under the terms of GPL v2 and any later version.
+# See the file COPYING in the root directory of the source tree for details.
+#
+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/gigaset/sx76x/ddr_settings.h
@@ -0,0 +1,56 @@
+/*
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ * generated with lantiq_ram_extract_magic.awk
+ *
+ * Copyright (C) 2011 Luka Perkov <luka@openwrt.org>
+ */
+
+#define MC_DC00_VALUE 0x1B1B
+#define MC_DC01_VALUE 0x0
+#define MC_DC02_VALUE 0x0
+#define MC_DC03_VALUE 0x0
+#define MC_DC04_VALUE 0x0
+#define MC_DC05_VALUE 0x200
+#define MC_DC06_VALUE 0x605
+#define MC_DC07_VALUE 0x303
+#define MC_DC08_VALUE 0x202
+#define MC_DC09_VALUE 0x70A
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xC02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0xF3E
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xD
+#define MC_DC18_VALUE 0x300
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA04
+#define MC_DC21_VALUE 0xF00
+#define MC_DC22_VALUE 0xF0F
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x63
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x100
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x514
+#define MC_DC29_VALUE 0x2D89
+#define MC_DC30_VALUE 0x8300
+#define MC_DC31_VALUE 0x2002
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+#define MC_DC46_VALUE 0x0
--- /dev/null
+++ b/board/gigaset/sx76x/sx76x.c
@@ -0,0 +1,66 @@
+/*
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ * Copyright (C) 2011 Luka Perkov <luka@openwrt.org>
+ */
+
+#include <common.h>
+#include <switch.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/reset.h>
+#include <asm/lantiq/chipid.h>
+
+static void gpio_init(void)
+{
+ /* Activate reset line of ADM6996I switch */
+ gpio_direction_output(19, 0);
+}
+
+int board_early_init_f(void)
+{
+ gpio_init();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* MAC0: Lantiq ADM6996I switch */
+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t *bis)
+{
+ return ltq_eth_initialize(&eth_board_config);
+}
+
+static struct switch_device adm6996i_dev = {
+ .name = "adm6996i",
+ .cpu_port = 5,
+ .port_mask = 0xF,
+};
+
+int board_switch_init(void)
+{
+ /* Deactivate reset line of ADM6996I switch */
+ gpio_set_value(19, 1);
+
+ /* ADM6996I needs some time to come out of reset */
+ __udelay(50000);
+
+ return switch_device_register(&adm6996i_dev);
+}
--- a/boards.cfg
+++ b/boards.cfg
@@ -447,6 +447,8 @@ pb1000 mips
easy50712_nor mips mips32 easy50712 lantiq danube easy50712:SYS_BOOT_NOR
easy50712_norspl mips mips32 easy50712 lantiq danube easy50712:SYS_BOOT_NORSPL
easy50712_ram mips mips32 easy50712 lantiq danube easy50712:SYS_BOOT_RAM
+gigasx76x_nor mips mips32 sx76x gigaset danube sx76x:SYS_BOOT_NOR
+gigasx76x_ram mips mips32 sx76x gigaset danube sx76x:SYS_BOOT_RAM
incaip mips mips32 incaip - incaip
incaip_100MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=100000000
incaip_133MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=133000000
--- /dev/null
+++ b/include/configs/sx76x.h
@@ -0,0 +1,71 @@
+/*
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ * Copyright (C) 2011 Luka Perkov <luka@openwrt.org>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "GIGASX76X"
+#define CONFIG_IDENT_STRING " sx76x"
+#define CONFIG_BOARD_NAME "Gigaset sx76x"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+
+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
+
+/* Switch devices */
+#define CONFIG_SWITCH_MULTI
+#define CONFIG_SWITCH_ADM6996I
+
+/* Environment */
+#if defined(CONFIG_SYS_BOOT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (256 * 1024)
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE (2 * 1024)
+#endif
+
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Commands */
+#define CONFIG_CMD_PING
+
+/* Pull in default board configs for Lantiq XWAY Danube */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+/* Compression */
+#define CONFIG_LZMA
+
+/* Auto boot */
+#define CONFIG_BOOTDELAY 2
+
+/* Environment configuration */
+#define CONFIG_BOOTCOMMAND \
+ "run addeth; bootm ${kernel_addr}"
+
+#define CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "kernel_addr=0xB0040000\0"
+
+#endif /* __CONFIG_H */

248
package/boot/uboot-lantiq/patches/0027-MIPS-add-board-support-for-Arcadyan-ARV7518.patch Normal file
View file

@ -0,0 +1,248 @@
From 289f7ed5d725067b4eb4b1a105bb63d55bf20392 Mon Sep 17 00:00:00 2001
From: Luka Perkov <luka@openwrt.org>
Date: Wed, 29 Aug 2012 22:08:41 +0200
Subject: MIPS: add board support for Arcadyan ARV7518
Signed-off-by: Luka Perkov <luka@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- /dev/null
+++ b/board/arcadyan/arv7518pw/Makefile
@@ -0,0 +1,29 @@
+#
+# This file is released under the terms of GPL v2 and any later version.
+# See the file COPYING in the root directory of the source tree for details.
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/board/arcadyan/arv7518pw/arv7518pw.c
@@ -0,0 +1,52 @@
+/*
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>
+ */
+
+#include <common.h>
+#include <switch.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/reset.h>
+#include <asm/lantiq/chipid.h>
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* MAC0: Atheros ar8216 switch */
+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_NONE },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t *bis)
+{
+ return ltq_eth_initialize(&eth_board_config);
+}
+
+static struct switch_device ar8216_dev = {
+ .name = "ar8216",
+ .cpu_port = 0,
+ .port_mask = 0xF,
+};
+
+int board_switch_init(void)
+{
+ return switch_device_register(&ar8216_dev);
+}
--- /dev/null
+++ b/board/arcadyan/arv7518pw/config.mk
@@ -0,0 +1,8 @@
+#
+# This file is released under the terms of GPL v2 and any later version.
+# See the file COPYING in the root directory of the source tree for details.
+#
+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/arcadyan/arv7518pw/ddr_settings.h
@@ -0,0 +1,56 @@
+/*
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ * generated with lantiq_ram_extract_magic.awk
+ *
+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>
+ */
+
+#define MC_DC00_VALUE 0x1B1B
+#define MC_DC01_VALUE 0x0
+#define MC_DC02_VALUE 0x0
+#define MC_DC03_VALUE 0x0
+#define MC_DC04_VALUE 0x0
+#define MC_DC05_VALUE 0x200
+#define MC_DC06_VALUE 0x605
+#define MC_DC07_VALUE 0x303
+#define MC_DC08_VALUE 0x102
+#define MC_DC09_VALUE 0x70A
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xC02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0x134
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xD
+#define MC_DC18_VALUE 0x301
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA03
+#define MC_DC21_VALUE 0x1400
+#define MC_DC22_VALUE 0x1414
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x5B
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x4E20
+#define MC_DC30_VALUE 0x8235
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+#define MC_DC46_VALUE 0x0
--- a/boards.cfg
+++ b/boards.cfg
@@ -438,6 +438,8 @@ vct_premium mips
vct_premium_onenand mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_ONENAND
vct_premium_onenand_small mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE
vct_premium_small mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_SMALL_IMAGE
+arv7518pw_ram mips mips32 arv7518pw arcadyan danube arv7518pw:SYS_BOOT_RAM
+arv7518pw_nor mips mips32 arv7518pw arcadyan danube arv7518pw:SYS_BOOT_NOR
dbau1000 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1000
dbau1100 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1100
dbau1500 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1500
--- /dev/null
+++ b/include/configs/arv7518pw.h
@@ -0,0 +1,69 @@
+/*
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "ARV7518PW"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "Arcadyan ARV7518PW"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
+
+/* Switch devices */
+#define CONFIG_SWITCH_MULTI
+#define CONFIG_SWITCH_AR8216
+
+/* Environment */
+#if defined(CONFIG_SYS_BOOT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (192 * 1024)
+#define CONFIG_ENV_SIZE (64 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE (2 * 1024)
+#endif
+
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Commands */
+#define CONFIG_CMD_PING
+
+/* Pull in default board configs for Lantiq XWAY Danube */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+/* Compression */
+#define CONFIG_LZMA
+
+/* Auto boot */
+#define CONFIG_BOOTDELAY 2
+
+/* Environment configuration */
+#define CONFIG_BOOTCOMMAND \
+ "run addeth; bootm ${kernel_addr}"
+
+#define CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "kernel_addr=0xB0040000\0"
+
+#endif /* __CONFIG_H */

248
package/boot/uboot-lantiq/patches/0028-MIPS-add-board-support-for-Arcadyan-ARV4519.patch Normal file
View file

@ -0,0 +1,248 @@
From 4a738c02a7190756e01ba58c93c4b07bc6d6c2aa Mon Sep 17 00:00:00 2001
From: Luka Perkov <luka@openwrt.org>
Date: Wed, 29 Aug 2012 22:08:42 +0200
Subject: MIPS: add board support for Arcadyan ARV4519
Signed-off-by: Luka Perkov <luka@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- /dev/null
+++ b/board/arcadyan/arv4519pw/Makefile
@@ -0,0 +1,29 @@
+#
+# This file is released under the terms of GPL v2 and any later version.
+# See the file COPYING in the root directory of the source tree for details.
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/board/arcadyan/arv4519pw/arv4519pw.c
@@ -0,0 +1,52 @@
+/*
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>
+ */
+
+#include <common.h>
+#include <switch.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/reset.h>
+#include <asm/lantiq/chipid.h>
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* MAC0: Atheros ar8216 switch */
+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_NONE },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t *bis)
+{
+ return ltq_eth_initialize(&eth_board_config);
+}
+
+static struct switch_device ar8216_dev = {
+ .name = "ar8216",
+ .cpu_port = 0,
+ .port_mask = 0xF,
+};
+
+int board_switch_init(void)
+{
+ return switch_device_register(&ar8216_dev);
+}
--- /dev/null
+++ b/board/arcadyan/arv4519pw/config.mk
@@ -0,0 +1,8 @@
+#
+# This file is released under the terms of GPL v2 and any later version.
+# See the file COPYING in the root directory of the source tree for details.
+#
+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/arcadyan/arv4519pw/ddr_settings.h
@@ -0,0 +1,56 @@
+/*
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ * generated with lantiq_ram_extract_magic.awk
+ *
+ * Copyright (C) 2011 Luka Perkov <luka@openwrt.org>
+ */
+
+#define MC_DC00_VALUE 0x1B1B
+#define MC_DC01_VALUE 0x0
+#define MC_DC02_VALUE 0x0
+#define MC_DC03_VALUE 0x0
+#define MC_DC04_VALUE 0x0
+#define MC_DC05_VALUE 0x200
+#define MC_DC06_VALUE 0x605
+#define MC_DC07_VALUE 0x303
+#define MC_DC08_VALUE 0x102
+#define MC_DC09_VALUE 0x70A
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xC02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0x131
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xD
+#define MC_DC18_VALUE 0x301
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA04
+#define MC_DC21_VALUE 0x1700
+#define MC_DC22_VALUE 0x1717
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x5A
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x4E20
+#define MC_DC30_VALUE 0x8235
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+#define MC_DC46_VALUE 0x0
--- a/boards.cfg
+++ b/boards.cfg
@@ -438,6 +438,8 @@ vct_premium mips
vct_premium_onenand mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_ONENAND
vct_premium_onenand_small mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE
vct_premium_small mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_SMALL_IMAGE
+arv4519pw_ram mips mips32 arv4519pw arcadyan danube arv4519pw:SYS_BOOT_RAM
+arv4519pw_nor mips mips32 arv4519pw arcadyan danube arv4519pw:SYS_BOOT_NOR
arv7518pw_ram mips mips32 arv7518pw arcadyan danube arv7518pw:SYS_BOOT_RAM
arv7518pw_nor mips mips32 arv7518pw arcadyan danube arv7518pw:SYS_BOOT_NOR
dbau1000 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1000
--- /dev/null
+++ b/include/configs/arv4519pw.h
@@ -0,0 +1,69 @@
+/*
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "ARV4519PW"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "Arcadyan ARV4519PW"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
+
+/* Switch devices */
+#define CONFIG_SWITCH_MULTI
+#define CONFIG_SWITCH_AR8216
+
+/* Environment */
+#if defined(CONFIG_SYS_BOOT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (192 * 1024)
+#define CONFIG_ENV_SIZE (64 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE (2 * 1024)
+#endif
+
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Commands */
+#define CONFIG_CMD_PING
+
+/* Pull in default board configs for Lantiq XWAY Danube */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+/* Compression */
+#define CONFIG_LZMA
+
+/* Auto boot */
+#define CONFIG_BOOTDELAY 2
+
+/* Environment configuration */
+#define CONFIG_BOOTCOMMAND \
+ "run addeth; bootm ${kernel_addr}"
+
+#define CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "kernel_addr=0xB0040000\0"
+
+#endif /* __CONFIG_H */

361
package/boot/uboot-lantiq/patches/0029-tools-add-some-helper-tools-for-Lantiq-SoCs.patch Normal file
View file

@ -0,0 +1,361 @@
From 1b77d4249b5addbf3b0848db6992a445019a1865 Mon Sep 17 00:00:00 2001
From: Luka Perkov <luka@openwrt.org>
Date: Wed, 29 Aug 2012 22:08:42 +0200
Subject: tools: add some helper tools for Lantiq SoCs
Signed-off-by: Luka Perkov Luka Perkov <luka@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- /dev/null
+++ b/tools/gct.pl
@@ -0,0 +1,155 @@
+#!/usr/bin/perl
+
+#use strict;
+#use Cwd;
+#use Env;
+
+my $aline;
+my $lineid;
+my $length;
+my $address;
+my @bytes;
+my $addstr;
+my $chsum=0;
+my $count=0;
+my $firstime=1;
+my $i;
+my $currentaddr;
+my $tmp;
+my $holder="";
+my $loadaddr;
+
+if(@ARGV < 2){
+ die("\n Syntax: perl gct.pl uart_ddr_settings.conf u-boot.srec u-boot.asc\n");
+}
+
+open(IN_UART_DDR_SETTINGS, "<$ARGV[0]") || die("failed to open uart_ddr_settings.conf\n");
+open(IN_UART_SREC, "<$ARGV[1]") || die("failed to open u-boot.srec\n");
+open(OUT_UBOOT_ASC, ">$ARGV[2]") || die("failed to open u-boot.asc\n");
+
+$i=0;
+while ($line = <IN_UART_DDR_SETTINGS>){
+ if($line=~/\w/){
+ if($line!~/[;#\*]/){
+ if($i eq 0){
+ printf OUT_UBOOT_ASC ("33333333");
+ }
+ chomp($line);
+ $line=~s/\t//;
+ @array=split(/ +/,$line);
+ $j=0;
+ while(@array[$j]!~/\w/){
+ $j=$j+1;
+ }
+ $addr=@array[$j];
+ $regval=@array[$j+1];
+ $addr=~s/0x//;
+ $regval=~s/0x//;
+ printf OUT_UBOOT_ASC ("%08x%08x",hex($addr),hex($regval));
+ $i=$i+1;
+ if($i eq 8){
+ $i=0;
+ printf OUT_UBOOT_ASC ("\n");
+ }
+ }
+ }
+}
+
+while($i lt 8 && $i gt 0){
+ printf OUT_UBOOT_ASC "00"x8;
+ $i=$i+1;
+}
+
+if($i eq 8){
+ printf OUT_UBOOT_ASC ("\n");
+}
+
+while($aline=<IN_UART_SREC>){
+ $aline=uc($aline);
+ chomp($aline);
+ next if(($aline=~/^S0/) || ($aline=~/^S7/));
+ ($lineid, $length, $address, @bytes) = unpack"A2A2A8"."A2"x300, $aline;
+ $length = hex($length);
+ $address = hex($address);
+ $length -=5;
+ $i=0;
+
+ while($length>0){
+ if($firstime==1){
+ $addstr = sprintf("%x", $address);
+ $addstr = "0"x(8-length($addstr)).$addstr;
+ print OUT_UBOOT_ASC $addstr;
+ addchsum($addstr);
+ $firstime=0;
+ $currentaddr=$address;
+ $loadaddr = $addstr;
+ }
+ else{
+ if($count==64){
+ $addstr = sprintf("%x", $currentaddr);
+ $addstr = "0"x(8-length($addstr)).$addstr;
+ print OUT_UBOOT_ASC $addstr;
+ addchsum($addstr);
+ $count=0;
+ }
+#printf("*** %x != %x\n", $address, $currentaddr) if $address != $currentaddr;
+ }
+ if($currentaddr < $address) {
+ print OUT_UBOOT_ASC "00";
+ addchsum("00");
+ $count++;
+ $currentaddr++;
+ }
+ else {
+ while($count<64){
+ $bytes[$i]=~tr/ABCDEF/abcdef/;
+ print OUT_UBOOT_ASC "$bytes[$i]";
+ addchsum($bytes[$i]);
+ $i++;
+ $count++;
+ $currentaddr++;
+ $length--;
+ last if($length==0);
+ }
+ }
+ if($count==64){
+ print OUT_UBOOT_ASC "\n";
+ }
+ }
+}
+if($count != 64){
+ $tmp = "00";
+ for($i=0;$i<(64-$count);$i++){
+ print OUT_UBOOT_ASC "00";
+ addchsum($tmp);
+ }
+ print OUT_UBOOT_ASC "\n";
+}
+
+
+print OUT_UBOOT_ASC "11"x4;
+use integer;
+$chsum=$chsum & 0xffffffff;
+$chsum = sprintf("%X", $chsum);
+$chsum = "0"x(8-length($chsum)).$chsum;
+$chsum =~tr/ABCDEF/abcdef/;
+print OUT_UBOOT_ASC $chsum;
+print OUT_UBOOT_ASC "00"x60;
+print OUT_UBOOT_ASC "\n";
+
+print OUT_UBOOT_ASC "99"x4;
+print OUT_UBOOT_ASC $loadaddr;
+print OUT_UBOOT_ASC "00"x60;
+print OUT_UBOOT_ASC "\n";
+
+close OUT_UBOOT_ASC;
+
+sub addchsum{
+ my $cc=$_[0];
+ $holder=$holder.$cc;
+ if(length($holder)==8){
+ $holder = hex($holder);
+ $chsum+=$holder;
+ $holder="";
+ }
+}
--- /dev/null
+++ b/tools/lantiq_extract_openwrt_patches.sh
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+set -e
+set -x
+
+test $# -eq 1
+
+openwrt_root=$(readlink -f $1)
+test -d $openwrt_root
+
+uboot_lantiq_dir=$openwrt_root/package/boot/uboot-lantiq/patches
+test -d $uboot_lantiq_dir
+
+rm -vf $uboot_lantiq_dir/*
+git format-patch -k -p --no-renames --text --full-index -o $uboot_lantiq_dir v2012.10..openwrt/v2013.01
--- /dev/null
+++ b/tools/lantiq_ram_extract_magic.awk
@@ -0,0 +1,70 @@
+#
+# This file is released under the terms of GPL v2 and any later version.
+# See the file COPYING in the root directory of the source tree for details.
+#
+# Copyright (C) 2011 Luka Perkov <luka@openwrt.org>
+#
+# usage: mips-openwrt-linux-objdump -EB -b binary -m mips:isa32r2 -D YOUR_IMAGE_DUMP | awk -f lantiq_ram_extract_magic.awk
+#
+
+BEGIN {
+ print "/* "
+ print " * This file is released under the terms of GPL v2 and any later version. "
+ print " * See the file COPYING in the root directory of the source tree for details. "
+ print " * "
+ print " * generated with lantiq_ram_extract_magic.awk "
+ print " * "
+ print " * Copyright (C) 2011 Luka Perkov <luka@openwrt.org> "
+ print " */ "
+ print ""
+
+ mc_dc_value=0
+ mc_dc_number=0
+ right_section=0
+ mc_dc_value_print=0
+ mc_dc_number_print=0
+}
+
+/t2,[0-9]+$/ {
+ if (right_section) {
+ split($4, tmp, ",")
+ mc_dc_value=sprintf("%X", tmp[2])
+ mc_dc_value_print=1
+ }
+}
+
+/t2,0x[0-9a-f]+$/ {
+ if (right_section) {
+ split($4, tmp, ",0x")
+ mc_dc_value=sprintf("%s", tmp[2])
+ mc_dc_value=toupper(mc_dc_value)
+ mc_dc_value_print=1
+ }
+}
+
+/t2,[0-9]+\(t1\)$/ {
+ if (right_section) {
+ split($4, tmp, ",")
+ split(tmp[2], tmp, "(")
+ mc_dc_number=tmp[1]/16
+ mc_dc_number_print=1
+ }
+}
+
+{
+ if (right_section && mc_dc_number_print && mc_dc_value_print) {
+ if (mc_dc_number < 10)
+ print "#define MC_DC0" mc_dc_number "_VALUE\t0x" mc_dc_value
+ else
+ print "#define MC_DC" mc_dc_number "_VALUE\t0x" mc_dc_value
+ mc_dc_value_print=0
+ mc_dc_number_print=0
+ }
+
+ if ($4 == "t1,t1,0x1000")
+ right_section=1
+
+
+ if ($4 == "t2,736(t1)")
+ right_section=0
+}
--- /dev/null
+++ b/tools/lantiq_ram_init_uart.awk
@@ -0,0 +1,101 @@
+#!/usr/bin/awk -f
+#
+# This file is released under the terms of GPL v2 and any later version.
+# See the file COPYING in the root directory of the source tree for details.
+#
+# Copyright (C) 2011-2012 Luka Perkov <luka@openwrt.org>
+# Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+#
+# usage: awk -f lantiq_ram_init_uart.awk -v soc=<danube|ar9|vr9> PATH_TO_BOARD/ddr_settings.h
+#
+
+function print_header()
+{
+ print "; "
+ print "; This file is released under the terms of GPL v2 and any later version. "
+ print "; See the file COPYING in the root directory of the source tree for details. "
+ print "; "
+ print "; generated with lantiq_ram_init_uart.awk "
+ print "; "
+ print "; Copyright (C) 2011-2012 Luka Perkov <luka@openwrt.org> "
+ print "; Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@gmail.com> "
+ print "; "
+ print ""
+}
+
+function mc_ddr1_prologue()
+{
+ /* Clear access error log registers */
+ print "0xbf800010", "0x0"
+ print "0xbf800020", "0x0"
+
+ /* Enable DDR and SRAM module in memory controller */
+ print "0xbf800060", "0x5"
+
+ /* Clear start bit of DDR memory controller */
+ print "0xbf801030", "0x0"
+}
+
+function mc_ddr1_epilogue()
+{
+ /* Set start bit of DDR memory controller */
+ print "0xbf801030", "0x100"
+}
+
+function mc_ddr2_prologue()
+{
+ /* Put memory controller in inactive mode */
+ print "0xbf401070", "0x0"
+}
+
+function mc_ddr2_epilogue(mc_ccr07_value)
+{
+ /* Put memory controller in active mode */
+ mc_ccr07_value = or(mc_ccr07_value, 0x100)
+ printf("0xbf401070 0x%x\n", mc_ccr07_value)
+}
+
+BEGIN {
+ switch (soc) {
+ case "danube":
+ case "ar9":
+ reg_base = 0xbf801000
+ print_header()
+ mc_ddr1_prologue()
+ break
+ case "vr9":
+ reg_base = 0xbf401000
+ print_header()
+ mc_ddr2_prologue()
+ break
+ default:
+ print "Invalid or no value for soc specified!"
+ exit 1
+ }
+
+ mc_ccr07_value = 0
+}
+
+/^#define/ {
+ printf("0x%x %s\n", reg_base, tolower($3))
+ reg_base += 0x10
+}
+
+/^#define(.*)MC_CCR07_VALUE/ {
+ printf("0x%x %s\n", reg_base, tolower($3))
+ reg_base += 0x10
+ mc_ccr07_value = strtonum($3)
+}
+
+END {
+ switch (soc) {
+ case "danube":
+ case "ar9":
+ mc_ddr1_epilogue()
+ break
+ case "vr9":
+ mc_ddr2_epilogue(mc_ccr07_value)
+ break
+ default:
+ }
+}