cleanup and make interrupt code more robust
Signed-off-by: Florian Fainelli <florian@openwrt.org> SVN-Revision: 34552
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3 changed files with 39 additions and 19 deletions
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@ -1,5 +1,6 @@
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/*
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* Copyright (C) 2010 Scott Nicholas <neutronscott@scottn.us>
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* Copyright (C) 2012 Florian Fainelli <florian@openwrt.org>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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@ -20,15 +21,38 @@
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#include <asm/irq.h>
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#include <adm8668.h>
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/* interrupt controller */
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#define IRQ_STATUS_REG 0x00 /* Read */
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#define IRQ_ENABLE_REG 0x08 /* Read/Write */
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#define IRQ_DISABLE_REG 0x0C /* Write */
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#define IRQ_MASK 0xffff
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static inline void intc_write_reg(u32 val, unsigned int reg)
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{
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void __iomem *base = (void __iomem *)KSEG1ADDR(ADM8668_INTC_BASE);
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__raw_writel(val, base + reg);
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}
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static inline u32 intc_read_reg(unsigned int reg)
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{
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void __iomem *base = (void __iomem *)KSEG1ADDR(ADM8668_INTC_BASE);
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return __raw_readl(base + reg);
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}
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static void adm8668_irq_cascade(void)
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{
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int i;
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unsigned long intsrc;
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int irq;
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u32 intsrc;
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intsrc = ADM8668_INTC_REG(IRQ_STATUS_REG) & IRQ_MASK;
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for (i = 0; intsrc; intsrc >>= 1, i++)
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if (intsrc & 0x1)
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do_IRQ(i);
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intsrc = intc_read_reg(IRQ_STATUS_REG) & IRQ_MASK;
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if (intsrc) {
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irq = fls(intsrc) - 1;
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do_IRQ(irq);
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} else
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spurious_interrupt();
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}
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/*
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@ -43,8 +67,10 @@ void plat_irq_dispatch(void)
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/* timer interrupt, that we renumbered */
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if (pending & STATUSF_IP7)
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do_IRQ(MIPS_CPU_IRQ_BASE + 7);
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if (pending & STATUSF_IP2)
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else if (pending & STATUSF_IP2)
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adm8668_irq_cascade();
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else
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spurious_interrupt();
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}
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/*
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@ -52,13 +78,13 @@ void plat_irq_dispatch(void)
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*/
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static void enable_adm8668_irq(struct irq_data *d)
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{
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ADM8668_INTC_REG(IRQ_ENABLE_REG) = (1 << d->irq);
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intc_write_reg((1 << d->irq), IRQ_ENABLE_REG);
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}
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static void ack_adm8668_irq(struct irq_data *d)
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{
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ADM8668_INTC_REG(IRQ_DISABLE_REG) = (1 << d->irq);
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intc_write_reg((1 << d->irq), IRQ_DISABLE_REG);
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}
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/*
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@ -79,6 +105,9 @@ static void __init init_adm8668_irqs(void)
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{
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int i;
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/* disable all interrupts for the moment */
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intc_write_reg(IRQ_MASK, IRQ_DISABLE_REG);
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for (i = 0; i <= INT_LVL_MAX; i++)
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irq_set_chip_and_handler(i, &adm8668_irq_type,
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handle_level_irq);
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@ -32,11 +32,6 @@
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/** onboard uart **/
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#define ADM8668_UARTCLK_FREQ 62500000
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/* interrupt controller */
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#define IRQ_STATUS_REG 0x00 /* Read */
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#define IRQ_ENABLE_REG 0x08 /* Read/Write */
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#define IRQ_DISABLE_REG 0x0C /* Write */
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/* interrupt levels */
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#define INT_LVL_SWI 1
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#define INT_LVL_COMMS_RX 2
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@ -56,8 +51,6 @@
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#define INT_LVL_MAX INT_LVL_USB
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/* register access macros */
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#define ADM8668_INTC_REG(_reg) \
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(*((volatile unsigned long *)(KSEG1ADDR(ADM8668_INTC_BASE + (_reg)))))
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#define ADM8668_LAN_REG(_reg) \
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(*((volatile unsigned int *)(KSEG1ADDR(ADM8668_LAN_BASE + (_reg)))))
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#define ADM8668_WAN_REG(_reg) \
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@ -11,6 +11,4 @@
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#define NR_IRQS 32
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#define MIPS_CPU_IRQ_BASE 16
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#define IRQ_MASK 0xffff
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#endif /* __ASM_MACH_ADM8668_IRQ_H */
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