update brcm-2.4 to 2.4.35.4, integrate new broadcom system code, update broadcom-wl to a contributed version (v4.150.10.5) - no bcm57xx support yet, will follow shortly
SVN-Revision: 10137
This commit is contained in:
parent
563d234596
commit
178721f76b
165 changed files with 20348 additions and 10073 deletions
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@ -1,7 +1,7 @@
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# Use the default kernel version if the Makefile doesn't override it
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ifeq ($(KERNEL),2.4)
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LINUX_VERSION?=2.4.34
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LINUX_VERSION?=2.4.35.4
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else
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LINUX_VERSION?=2.6.21.5
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endif
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@ -10,6 +10,9 @@ LINUX_RELEASE?=1
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ifeq ($(LINUX_VERSION),2.4.34)
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LINUX_KERNEL_MD5SUM:=f59665540a7f3351ea416a0dad104b55
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endif
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ifeq ($(LINUX_VERSION),2.4.35.4)
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LINUX_KERNEL_MD5SUM:=34066faff3d8c042df1c7600b08b8070
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endif
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ifeq ($(LINUX_VERSION),2.6.22.4)
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LINUX_KERNEL_MD5SUM:=6cf83acf21e65dcea4a5170c0bbc7125
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endif
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@ -10,13 +10,15 @@ include $(TOPDIR)/rules.mk
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include $(INCLUDE_DIR)/kernel.mk
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PKG_NAME:=broadcom-wl
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PKG_VERSION:=4.80.53.0
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PKG_VERSION:=4.150.10.5
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PKG_RELEASE:=1
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WLC_VERSION:=0.1
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PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
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PKG_SOURCE_URL:=http://downloads.openwrt.org/sources
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PKG_MD5SUM:=a7d8dde3ce474c361143b83e1d9890b1
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PKG_MD5SUM:=0c6ba9687114c6b598e8019e262d9a60
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WL_WEXT=1
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include $(INCLUDE_DIR)/package.mk
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@ -107,7 +109,7 @@ endef
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define Package/wl
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$(call Package/broadcom-wl/Default)
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TITLE:=Proprietary Broadcom wl driver config utility
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DEPENDS+=+brcm-compat-ldso
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# DEPENDS+=+brcm-compat-ldso
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endef
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define Package/wl/description
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@ -118,7 +120,7 @@ endef
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define Package/nas
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$(call Package/broadcom-wl/Default)
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DEPENDS+= +nvram
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DEPENDS+= +brcm-compat-ldso
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# DEPENDS+= +brcm-compat-ldso
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TITLE:=Proprietary Broadcom WPA/WPA2 authenticator
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endef
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@ -127,20 +129,6 @@ define Package/nas/description
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proprietary Broadcom wl driver.
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endef
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define install_template
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$(INSTALL_DIR) $(1)/lib/modules/$(LINUX_VERSION)
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$(INSTALL_DATA) $(PKG_BUILD_DIR)/driver/wl$(2).o.patch $(1)/lib/modules/$(LINUX_VERSION)/
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endef
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define KernelPackage/brcm-wl/install
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$(call install_template,$(1),)
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endef
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define KernelPackage/brcm-wl_mimo/install
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$(call install_template,$(1),_mimo)
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endef
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MAKE_KMOD := $(MAKE) -C "$(LINUX_DIR)" \
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CROSS_COMPILE="$(TARGET_CROSS)" \
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ARCH="$(LINUX_KARCH)" \
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@ -149,7 +137,6 @@ MAKE_KMOD := $(MAKE) -C "$(LINUX_DIR)" \
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define Build/Prepare
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$(call Build/Prepare/Default)
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mv $(PKG_BUILD_DIR)/kmod $(PKG_BUILD_DIR)/driver
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$(CP) src/* $(PKG_BUILD_DIR)/
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endef
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@ -164,10 +151,12 @@ define Build/Compile
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modules
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$(MAKE_KMOD) \
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SUBDIRS="$(PKG_BUILD_DIR)/wlcompat" \
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$(if $(WL_WEXT),WL_WEXT=1) \
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modules
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$(MAKE_KMOD) \
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SUBDIRS="$(PKG_BUILD_DIR)/wlcompat" \
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DEBUG=1 \
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$(if $(WL_WEXT),WL_WEXT=1) \
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modules
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# Compile wlc
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@ -175,10 +164,12 @@ define Build/Compile
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$(TARGET_CONFIGURE_OPTS) \
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CFLAGS="$(TARGET_CFLAGS)" \
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all
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$(NO_TRACE_MAKE) -C compat-ldso -f build.mk PKG_INSTALL_DIR="$(PKG_BUILD_DIR)" BUILD_DIR="$(PKG_BUILD_DIR)"
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$(SED) 's,ld-uClibc.so.0,ld-uClibc.brcm,' \
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$(PKG_BUILD_DIR)/wl \
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$(PKG_BUILD_DIR)/nas
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$(TARGET_CC) -o $(PKG_BUILD_DIR)/nas $(PKG_BUILD_DIR)/nas_exe.o -L$(STAGING_DIR)/usr/lib -lnvram
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$(TARGET_CC) -o $(PKG_BUILD_DIR)/wl $(PKG_BUILD_DIR)/wl_exe.o
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# $(NO_TRACE_MAKE) -C compat-ldso -f build.mk PKG_INSTALL_DIR="$(PKG_BUILD_DIR)"
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# $(SED) 's,ld-uClibc.so.0,ld-uClibc.brcm,' \
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# $(PKG_BUILD_DIR)/wl \
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# $(PKG_BUILD_DIR)/nas
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endef
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define Package/brcm-compat-ldso/install
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@ -198,8 +189,6 @@ define Package/wl/install
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endef
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define Package/nas/install
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$(INSTALL_DIR) $(1)/usr/lib
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$(INSTALL_BIN) $(PKG_BUILD_DIR)/libbcmcrypto.so $(1)/usr/lib/
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$(INSTALL_DIR) $(1)/usr/sbin
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$(INSTALL_BIN) $(PKG_BUILD_DIR)/nas $(1)/usr/sbin/
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ln -sf nas $(1)/usr/sbin/nas4not
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@ -208,7 +197,7 @@ endef
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$(eval $(call KernelPackage,brcm-wl))
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$(eval $(call KernelPackage,brcm-wl-mimo))
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$(eval $(call BuildPackage,brcm-compat-ldso))
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#$(eval $(call BuildPackage,brcm-compat-ldso))
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$(eval $(call KernelPackage,wlcompat))
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$(eval $(call KernelPackage,wlcompat-debug))
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$(eval $(call BuildPackage,wlc))
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@ -52,7 +52,7 @@ scan_broadcom() {
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case "$adhoc:$sta:$apmode" in
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1*)
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ap=0
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mssid=0
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mssid=
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infra=0
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;;
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:1:1)
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:1:)
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wet=1
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ap=0
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mssid=0
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mssid=
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;;
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::)
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radio=0
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@ -158,11 +158,11 @@ enable_broadcom() {
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config_get k "$vif" key$knr
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[ -n "$k" ] || continue
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[ "$defkey" = "$knr" ] && def="=" || def=""
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append vif_pre_up "wepkey $def$knr,$k" "$N"
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append vif_do_up "wepkey $def$knr,$k" "$N"
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done
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;;
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"");;
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*) append vif_pre_up "wepkey =1,$key" "$N";;
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*) append vif_do_up "wepkey =1,$key" "$N";;
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esac
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;;
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*psk*|*PSK*)
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nasopts="-r \"\$${vif}_key\" -h $server -p $port"
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;;
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esac
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append vif_post_up "wsec $wsec" "$N"
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append vif_post_up "wpa_auth $auth" "$N"
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append vif_post_up "wsec_restrict $wsec_r" "$N"
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append vif_post_up "eap_restrict $eap_r" "$N"
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append vif_do_up "wsec $wsec" "$N"
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append vif_do_up "wpa_auth $auth" "$N"
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append vif_do_up "wsec_restrict $wsec_r" "$N"
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append vif_do_up "eap_restrict $eap_r" "$N"
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config_get ssid "$vif" ssid
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append vif_post_up "vlan_mode 0" "$N"
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append vif_post_up "ssid $ssid" "$N"
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case "$mode" in
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sta|adhoc) append vif_do_up "ssid $ssid" "$N";;
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esac
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append vif_do_up "ssid $ssid" "$N"
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append vif_post_up "enabled 1" "$N"
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@ -221,8 +219,8 @@ enable_broadcom() {
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[ "$mode" = "sta" ] && {
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nas_mode="-S"
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[ -z "$bridge" ] || {
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append vif_pre_up "supplicant 1" "$N"
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append vif_pre_up "passphrase $key" "$N"
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append vif_post_up "supplicant 1" "$N"
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append vif_post_up "passphrase $key" "$N"
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use_nas=0
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}
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@ -236,7 +234,7 @@ enable_broadcom() {
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$ifdown
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ap $ap
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mssid $mssid
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${mssid:+mssid $mssid}
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apsta $apsta
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infra $infra
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${wet:+wet 1}
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@ -23,9 +23,6 @@ obj-m := $(O_TARGET)
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wl_mod$(MOD_NAME).o: wl_apsta$(MOD_NAME).o
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perl -ne 's,eth%d,wl%d\x00,g,print' < $< > $@
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wl$(MOD_NAME).o.patch: wl$(MOD_NAME).o
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$(OBJDUMP) -d $< | perl patchtable.pl > $@
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modules: wl$(MOD_NAME).o.patch
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modules: wl$(MOD_NAME).o
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include $(TOPDIR)/Rules.make
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File diff suppressed because it is too large
Load diff
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@ -1,22 +1,21 @@
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/*
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* Misc useful os-independent macros and functions.
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*
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* Copyright 2006, Broadcom Corporation
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* Copyright 2007, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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* $Id: bcmutils.h,v 1.1.1.16 2006/04/08 06:13:39 honor Exp $
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* $Id$
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*/
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#ifndef _bcmutils_h_
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#define _bcmutils_h_
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#include "linux_osl.h"
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/* ** driver-only section ** */
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#ifdef BCMDRIVER
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/* ctype replacement */
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#define _BCM_U 0x01 /* upper */
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#define _BCM_L 0x02 /* lower */
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#define _BCM_D 0x04 /* digit */
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#define _BCM_X 0x40 /* hex digit */
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#define _BCM_SP 0x80 /* hard space (0x20) */
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#define GPIO_PIN_NOTDEFINED 0x20 /* Pin not defined */
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extern unsigned char bcm_ctype[];
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#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
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extern const unsigned char bcm_ctype[];
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#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
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#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
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#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
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@ -42,36 +39,154 @@ extern unsigned char bcm_ctype[];
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#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
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#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
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#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
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#define bcm_tolower(c) (bcm_isupper((c)) ? ((c) + 'a' - 'A') : (c))
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#define bcm_toupper(c) (bcm_islower((c)) ? ((c) + 'A' - 'a') : (c))
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/*
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* Spin at most 'us' microseconds while 'exp' is true.
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* Caller should explicitly test 'exp' when this completes
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* and take appropriate error action if 'exp' is still true.
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*/
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#define SPINWAIT(exp, us) { \
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uint countdown = (us) + 9; \
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while ((exp) && (countdown >= 10)) {\
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OSL_DELAY(10); \
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countdown -= 10; \
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} \
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}
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/* Buffer structure for collecting string-formatted data
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* using bcm_bprintf() API.
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* Use bcm_binit() to initialize before use
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*/
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struct ether_addr {
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uint8 octet[6];
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} __attribute__((packed));
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struct bcmstrbuf {
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char *buf; /* pointer to current position in origbuf */
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unsigned int size; /* current (residual) size in bytes */
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char *origbuf; /* unmodified pointer to orignal buffer */
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unsigned int origsize; /* unmodified orignal buffer size in bytes */
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};
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/* ** driver-only section ** */
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#include <osl.h>
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#define GPIO_PIN_NOTDEFINED 0x20 /* Pin not defined */
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/* osl multi-precedence packet queue */
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#ifndef PKTQ_LEN_DEFAULT
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#define PKTQ_LEN_DEFAULT 128 /* Max 128 packets */
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#endif
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#ifndef PKTQ_MAX_PREC
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#define PKTQ_MAX_PREC 16 /* Maximum precedence levels */
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#endif
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typedef struct pktq_prec {
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void *head; /* first packet to dequeue */
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void *tail; /* last packet to dequeue */
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uint16 len; /* number of queued packets */
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uint16 max; /* maximum number of queued packets */
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} pktq_prec_t;
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/* multi-priority pkt queue */
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struct pktq {
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uint16 num_prec; /* number of precedences in use */
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uint16 hi_prec; /* rapid dequeue hint (>= highest non-empty prec) */
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uint16 max; /* total max packets */
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uint16 len; /* total number of packets */
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/* q array must be last since # of elements can be either PKTQ_MAX_PREC or 1 */
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struct pktq_prec q[PKTQ_MAX_PREC];
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};
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/* simple, non-priority pkt queue */
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struct spktq {
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uint16 num_prec; /* number of precedences in use (always 1) */
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uint16 hi_prec; /* rapid dequeue hint (>= highest non-empty prec) */
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uint16 max; /* total max packets */
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uint16 len; /* total number of packets */
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/* q array must be last since # of elements can be either PKTQ_MAX_PREC or 1 */
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struct pktq_prec q[1];
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};
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#define PKTQ_PREC_ITER(pq, prec) for (prec = (pq)->num_prec - 1; prec >= 0; prec--)
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/* forward definition of ether_addr structure used by some function prototypes */
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struct ether_addr;
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/* operations on a specific precedence in packet queue */
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#define pktq_psetmax(pq, prec, _max) ((pq)->q[prec].max = (_max))
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#define pktq_plen(pq, prec) ((pq)->q[prec].len)
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#define pktq_pavail(pq, prec) ((pq)->q[prec].max - (pq)->q[prec].len)
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#define pktq_pfull(pq, prec) ((pq)->q[prec].len >= (pq)->q[prec].max)
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#define pktq_pempty(pq, prec) ((pq)->q[prec].len == 0)
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#define pktq_ppeek(pq, prec) ((pq)->q[prec].head)
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#define pktq_ppeek_tail(pq, prec) ((pq)->q[prec].tail)
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extern void *pktq_penq(struct pktq *pq, int prec, void *p);
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extern void *pktq_penq_head(struct pktq *pq, int prec, void *p);
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extern void *pktq_pdeq(struct pktq *pq, int prec);
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extern void *pktq_pdeq_tail(struct pktq *pq, int prec);
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/* Empty the queue at particular precedence level */
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extern void pktq_pflush(osl_t *osh, struct pktq *pq, int prec, bool dir);
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/* Remove a specified packet from its queue */
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extern bool pktq_pdel(struct pktq *pq, void *p, int prec);
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/* operations on a set of precedences in packet queue */
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extern int pktq_mlen(struct pktq *pq, uint prec_bmp);
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extern void *pktq_mdeq(struct pktq *pq, uint prec_bmp, int *prec_out);
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/* operations on packet queue as a whole */
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#define pktq_len(pq) ((int)(pq)->len)
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#define pktq_max(pq) ((int)(pq)->max)
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#define pktq_avail(pq) ((int)((pq)->max - (pq)->len))
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#define pktq_full(pq) ((pq)->len >= (pq)->max)
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#define pktq_empty(pq) ((pq)->len == 0)
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/* operations for single precedence queues */
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#define pktenq(pq, p) pktq_penq(((struct pktq *)pq), 0, (p))
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#define pktenq_head(pq, p) pktq_penq_head(((struct pktq *)pq), 0, (p))
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#define pktdeq(pq) pktq_pdeq(((struct pktq *)pq), 0)
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#define pktdeq_tail(pq) pktq_pdeq_tail(((struct pktq *)pq), 0)
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#define pktqinit(pq, len) pktq_init(((struct pktq *)pq), 1, len)
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extern void pktq_init(struct pktq *pq, int num_prec, int max_len);
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/* prec_out may be NULL if caller is not interested in return value */
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extern void *pktq_deq(struct pktq *pq, int *prec_out);
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extern void *pktq_deq_tail(struct pktq *pq, int *prec_out);
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extern void *pktq_peek(struct pktq *pq, int *prec_out);
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extern void *pktq_peek_tail(struct pktq *pq, int *prec_out);
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extern void pktq_flush(osl_t *osh, struct pktq *pq, bool dir); /* Empty the entire queue */
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extern int pktq_setmax(struct pktq *pq, int max_len);
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/* externs */
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/* packet */
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extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
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extern uint pkttotlen(osl_t *osh, void *p);
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extern void *pktlast(osl_t *osh, void *p);
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/* Get priority from a packet and pass it back in scb (or equiv) */
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extern uint pktsetprio(void *pkt, bool update_vtag);
|
||||
#define PKTPRIO_VDSCP 0x100 /* DSCP prio found after VLAN tag */
|
||||
#define PKTPRIO_VLAN 0x200 /* VLAN prio found */
|
||||
#define PKTPRIO_UPD 0x400 /* DSCP used to update VLAN prio */
|
||||
#define PKTPRIO_DSCP 0x800 /* DSCP prio found */
|
||||
|
||||
/* string */
|
||||
extern uchar bcm_toupper(uchar c);
|
||||
extern ulong bcm_strtoul(char *cp, char **endp, uint base);
|
||||
extern char *bcmstrstr(char *haystack, char *needle);
|
||||
extern char *bcmstrcat(char *dest, const char *src);
|
||||
extern int BCMROMFN(bcm_atoi)(char *s);
|
||||
extern ulong BCMROMFN(bcm_strtoul)(char *cp, char **endp, uint base);
|
||||
extern char *BCMROMFN(bcmstrstr)(char *haystack, char *needle);
|
||||
extern char *BCMROMFN(bcmstrcat)(char *dest, const char *src);
|
||||
extern char *BCMROMFN(bcmstrncat)(char *dest, const char *src, uint size);
|
||||
extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
|
||||
/* ethernet address */
|
||||
extern char *bcm_ether_ntoa(struct ether_addr *ea, char *buf);
|
||||
extern int BCMROMFN(bcm_ether_atoe)(char *p, struct ether_addr *ea);
|
||||
|
||||
/* ip address */
|
||||
struct ipv4_addr;
|
||||
extern char *bcm_ip_ntoa(struct ipv4_addr *ia, char *buf);
|
||||
|
||||
/* delay */
|
||||
extern void bcm_mdelay(uint ms);
|
||||
/* variable access */
|
||||
extern char *getvar(char *vars, char *name);
|
||||
extern int getintvar(char *vars, char *name);
|
||||
extern char *getvar(char *vars, const char *name);
|
||||
extern int getintvar(char *vars, const char *name);
|
||||
extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
|
||||
#ifdef BCMDBG
|
||||
extern void prpkt(const char *msg, osl_t *osh, void *p0);
|
||||
#endif /* BCMDBG */
|
||||
#ifdef BCMPERFSTATS
|
||||
extern void bcm_perf_enable(void);
|
||||
extern void bcmstats(char *fmt);
|
||||
|
@ -117,6 +232,9 @@ typedef struct bcm_iovar {
|
|||
|
||||
/* flags are per-driver based on driver attributes */
|
||||
|
||||
extern const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t *table, const char *name);
|
||||
extern int bcm_iovar_lencheck(const bcm_iovar_t *table, void *arg, int len, bool set);
|
||||
|
||||
/* Base type definitions */
|
||||
#define IOVT_VOID 0 /* no value (implictly set only) */
|
||||
#define IOVT_BOOL 1 /* any value ok (zero/nonzero) */
|
||||
|
@ -127,11 +245,29 @@ typedef struct bcm_iovar {
|
|||
#define IOVT_INT32 6 /* int 32 bits */
|
||||
#define IOVT_UINT32 7 /* unsigned int 32 bits */
|
||||
#define IOVT_BUFFER 8 /* buffer is size-checked as per minlen */
|
||||
#define BCM_IOVT_VALID(type) (((unsigned int)(type)) <= IOVT_BUFFER)
|
||||
|
||||
extern const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t *table, const char *name);
|
||||
extern int bcm_iovar_lencheck(const bcm_iovar_t *table, void *arg, int len, bool set);
|
||||
/* Initializer for IOV type strings */
|
||||
#define BCM_IOV_TYPE_INIT { \
|
||||
"void", \
|
||||
"bool", \
|
||||
"int8", \
|
||||
"uint8", \
|
||||
"int16", \
|
||||
"uint16", \
|
||||
"int32", \
|
||||
"uint32", \
|
||||
"buffer", \
|
||||
"" }
|
||||
|
||||
#endif /* #ifdef BCMDRIVER */
|
||||
#define BCM_IOVT_IS_INT(type) (\
|
||||
(type == IOVT_BOOL) || \
|
||||
(type == IOVT_INT8) || \
|
||||
(type == IOVT_UINT8) || \
|
||||
(type == IOVT_INT16) || \
|
||||
(type == IOVT_UINT16) || \
|
||||
(type == IOVT_INT32) || \
|
||||
(type == IOVT_UINT32))
|
||||
|
||||
/* ** driver/apps-shared section ** */
|
||||
|
||||
|
@ -184,7 +320,8 @@ extern int bcm_iovar_lencheck(const bcm_iovar_t *table, void *arg, int len, bool
|
|||
#define BCME_NOT_WME_ASSOCIATION -34 /* Not WME Association */
|
||||
#define BCME_SDIO_ERROR -35 /* SDIO Bus Error */
|
||||
#define BCME_DONGLE_DOWN -36 /* Dongle Not Accessible */
|
||||
#define BCME_LAST BCME_DONGLE_DOWN
|
||||
#define BCME_VERSION -37 /* Incorrect version */
|
||||
#define BCME_LAST BCME_VERSION
|
||||
|
||||
/* These are collection of BCME Error strings */
|
||||
#define BCMERRSTRINGTABLE { \
|
||||
|
@ -224,7 +361,8 @@ extern int bcm_iovar_lencheck(const bcm_iovar_t *table, void *arg, int len, bool
|
|||
"ACM Not Supported", \
|
||||
"Not WME Association", \
|
||||
"SDIO Bus Error", \
|
||||
"Dongle Not Accessible" \
|
||||
"Dongle Not Accessible", \
|
||||
"Incorrect version" \
|
||||
}
|
||||
|
||||
#ifndef ABS
|
||||
|
@ -244,8 +382,12 @@ extern int bcm_iovar_lencheck(const bcm_iovar_t *table, void *arg, int len, bool
|
|||
#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
|
||||
#define ISPOWEROF2(x) ((((x)-1)&(x)) == 0)
|
||||
#define VALID_MASK(mask) !((mask) & ((mask) + 1))
|
||||
#ifndef OFFSETOF
|
||||
#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
|
||||
#endif /* OFFSETOF */
|
||||
#ifndef ARRAYSIZE
|
||||
#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
|
||||
#endif
|
||||
|
||||
/* bit map related macros */
|
||||
#ifndef setbit
|
||||
|
@ -254,8 +396,8 @@ extern int bcm_iovar_lencheck(const bcm_iovar_t *table, void *arg, int len, bool
|
|||
#endif /* #ifndef NBBY */
|
||||
#define setbit(a, i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
|
||||
#define clrbit(a, i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
|
||||
#define isset(a, i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
|
||||
#define isclr(a, i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
|
||||
#define isset(a, i) (((const uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
|
||||
#define isclr(a, i) ((((const uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
|
||||
#endif /* setbit */
|
||||
|
||||
#define NBITS(type) (sizeof(type) * 8)
|
||||
|
@ -296,7 +438,7 @@ extern int bcm_iovar_lencheck(const bcm_iovar_t *table, void *arg, int len, bool
|
|||
/* bcm_format_flags() bit description structure */
|
||||
typedef struct bcm_bit_desc {
|
||||
uint32 bit;
|
||||
char* name;
|
||||
const char* name;
|
||||
} bcm_bit_desc_t;
|
||||
|
||||
/* tag_ID/length/value_buffer tuple */
|
||||
|
@ -342,7 +484,7 @@ store16_ua(uint8 *a, uint16 v)
|
|||
a[1] = v & 0xff;
|
||||
}
|
||||
|
||||
#else
|
||||
#else /* IL_BIGENDIAN */
|
||||
|
||||
static INLINE uint32
|
||||
load32_ua(uint8 *a)
|
||||
|
@ -376,50 +518,45 @@ store16_ua(uint8 *a, uint16 v)
|
|||
|
||||
/* externs */
|
||||
/* crc */
|
||||
extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
|
||||
extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
|
||||
extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
|
||||
extern uint8 BCMROMFN(hndcrc8)(uint8 *p, uint nbytes, uint8 crc);
|
||||
extern uint16 BCMROMFN(hndcrc16)(uint8 *p, uint nbytes, uint16 crc);
|
||||
extern uint32 BCMROMFN(hndcrc32)(uint8 *p, uint nbytes, uint32 crc);
|
||||
/* format/print */
|
||||
#ifdef BCMDBG
|
||||
extern int bcm_format_flags(const bcm_bit_desc_t *bd, uint32 flags, char* buf, int len);
|
||||
extern int bcm_format_hex(char *str, const void *bytes, int len);
|
||||
extern void deadbeef(void *p, uint len);
|
||||
extern void prhex(const char *msg, uchar *buf, uint len);
|
||||
#endif /* BCMDBG */
|
||||
extern char *bcm_brev_str(uint16 brev, char *buf);
|
||||
extern void printfbig(char *buf);
|
||||
|
||||
/* IE parsing */
|
||||
extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
|
||||
extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
|
||||
extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
|
||||
extern bcm_tlv_t *BCMROMFN(bcm_next_tlv)(bcm_tlv_t *elt, int *buflen);
|
||||
extern bcm_tlv_t *BCMROMFN(bcm_parse_tlvs)(void *buf, int buflen, uint key);
|
||||
extern bcm_tlv_t *BCMROMFN(bcm_parse_ordered_tlvs)(void *buf, int buflen, uint key);
|
||||
|
||||
/* bcmerror */
|
||||
extern const char *bcmerrorstr(int bcmerror);
|
||||
|
||||
/* multi-bool data type: set of bools, mbool is true if any is set */
|
||||
typedef uint32 mbool;
|
||||
#define mboolset(mb, bit) (mb |= bit) /* set one bool */
|
||||
#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
|
||||
#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
|
||||
#define mboolset(mb, bit) ((mb) |= (bit)) /* set one bool */
|
||||
#define mboolclr(mb, bit) ((mb) &= ~(bit)) /* clear one bool */
|
||||
#define mboolisset(mb, bit) (((mb) & (bit)) != 0) /* TRUE if one bool is set */
|
||||
#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
|
||||
|
||||
/* power conversion */
|
||||
extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
|
||||
extern uint8 bcm_mw_to_qdbm(uint16 mw);
|
||||
extern uint16 BCMROMFN(bcm_qdbm_to_mw)(uint8 qdbm);
|
||||
extern uint8 BCMROMFN(bcm_mw_to_qdbm)(uint16 mw);
|
||||
|
||||
/* generic datastruct to help dump routines */
|
||||
struct fielddesc {
|
||||
char *nameandfmt;
|
||||
const char *nameandfmt;
|
||||
uint32 offset;
|
||||
uint32 len;
|
||||
};
|
||||
|
||||
/* Buffer structure for collecting string-formatted data
|
||||
* using bcm_bprintf() API.
|
||||
* Use bcm_binit() to initialize before use
|
||||
*/
|
||||
struct bcmstrbuf
|
||||
{
|
||||
char *buf; /* pointer to current position in origbuf */
|
||||
uint size; /* current (residual) size in bytes */
|
||||
char *origbuf; /* unmodified pointer to orignal buffer */
|
||||
uint origsize; /* unmodified orignal buffer size in bytes */
|
||||
};
|
||||
|
||||
extern void bcm_binit(struct bcmstrbuf *b, char *buf, uint size);
|
||||
extern int bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...);
|
||||
|
||||
|
@ -428,6 +565,18 @@ extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct f
|
|||
char *buf, uint32 bufsize);
|
||||
|
||||
extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
|
||||
extern uint bcm_bitcount(uint8 *bitmap, uint bytelength);
|
||||
extern uint BCMROMFN(bcm_bitcount)(uint8 *bitmap, uint bytelength);
|
||||
|
||||
#ifdef BCMDBG_PKT /* pkt logging for debugging */
|
||||
#define PKTLIST_SIZE 1000
|
||||
typedef struct {
|
||||
void *list[PKTLIST_SIZE]; /* List of pointers to packets */
|
||||
uint count; /* Total count of the packets */
|
||||
} pktlist_info_t;
|
||||
|
||||
extern void pktlist_add(pktlist_info_t *pktlist, void *p);
|
||||
extern void pktlist_remove(pktlist_info_t *pktlist, void *p);
|
||||
extern char* pktlist_dump(pktlist_info_t *pktlist, char *buf);
|
||||
#endif /* BCMDBG_PKT */
|
||||
|
||||
#endif /* _bcmutils_h_ */
|
File diff suppressed because it is too large
Load diff
|
@ -2,14 +2,14 @@
|
|||
* Generic Broadcom Home Networking Division (HND) DMA engine SW interface
|
||||
* This supports the following chips: BCM42xx, 44xx, 47xx .
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
* $Id: hnddma.h,v 1.1.1.13 2006/04/08 06:13:39 honor Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _hnddma_h_
|
||||
|
@ -39,7 +39,7 @@ typedef void* (*di_rx_t)(hnddma_t *dmah);
|
|||
typedef void (*di_rxfill_t)(hnddma_t *dmah);
|
||||
typedef void (*di_txreclaim_t)(hnddma_t *dmah, bool forceall);
|
||||
typedef void (*di_rxreclaim_t)(hnddma_t *dmah);
|
||||
typedef uintptr (*di_getvar_t)(hnddma_t *dmah, char *name);
|
||||
typedef uintptr (*di_getvar_t)(hnddma_t *dmah, const char *name);
|
||||
typedef void* (*di_getnexttxp_t)(hnddma_t *dmah, bool forceall);
|
||||
typedef void* (*di_getnextrxp_t)(hnddma_t *dmah, bool forceall);
|
||||
typedef void* (*di_peeknexttxp_t)(hnddma_t *dmah);
|
||||
|
@ -141,8 +141,12 @@ extern hnddma_t * dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx,
|
|||
#define dma_txactive(di) ((di)->di_fn.txactive(di))
|
||||
#define dma_txrotate(di) ((di)->di_fn.txrotate(di))
|
||||
#define dma_counterreset(di) ((di)->di_fn.counterreset(di))
|
||||
#ifdef BCMDBG
|
||||
#define dma_dump(di, buf, dumpring) ((di)->di_fn.dump(di, buf, dumpring))
|
||||
#define dma_dumptx(di, buf, dumpring) ((di)->di_fn.dumptx(di, buf, dumpring))
|
||||
#define dma_dumprx(di, buf, dumpring) ((di)->di_fn.dumprx(di, buf, dumpring))
|
||||
#endif
|
||||
|
||||
#define DMA_DUMP_SIZE 2048
|
||||
/* return addresswidth allowed
|
||||
* This needs to be done after SB attach but before dma attach.
|
||||
* SB attach provides ability to probe backplane and dma core capabilities
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Linux OS Independent Layer
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -9,7 +9,7 @@
|
|||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id: linux_osl.h,v 1.1.1.13 2006/04/08 06:13:39 honor Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _linux_osl_h_
|
||||
|
@ -19,17 +19,25 @@
|
|||
#include <linuxver.h>
|
||||
#include <osl.h>
|
||||
|
||||
#define OSL_PKTTAG_SZ 32 /* Size of PktTag */
|
||||
#define OSL_PKTTAG_SZ 32 /* Size of PktTag */
|
||||
|
||||
/* osl handle type forward declaration */
|
||||
typedef struct osl_dmainfo osldma_t;
|
||||
/* microsecond delay */
|
||||
extern void osl_delay(uint usec);
|
||||
|
||||
/* OSL initialization */
|
||||
extern osl_t *osl_attach(void *pdev, bool pkttag);
|
||||
extern osl_t *osl_attach(void *pdev, uint bustype, bool pkttag);
|
||||
extern void osl_detach(osl_t *osh);
|
||||
|
||||
#define PKTFREESETCB(osh, _tx_fn, _tx_ctx) \
|
||||
do { \
|
||||
((osl_pubinfo_t*)osh)->tx_fn = _tx_fn; \
|
||||
((osl_pubinfo_t*)osh)->tx_ctx = _tx_ctx; \
|
||||
} while (0)
|
||||
|
||||
/* host/bus architecture-specific byte swap */
|
||||
#define BUS_SWAP32(v) (v)
|
||||
|
||||
|
||||
#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
|
||||
|
||||
extern void *osl_malloc(osl_t *osh, uint size);
|
||||
|
@ -37,61 +45,110 @@ extern void osl_mfree(osl_t *osh, void *addr, uint size);
|
|||
extern uint osl_malloced(osl_t *osh);
|
||||
extern uint osl_malloc_failed(osl_t *osh);
|
||||
|
||||
/* API for DMA addressing capability */
|
||||
#define DMA_MAP(osh, va, size, direction, p) \
|
||||
osl_dma_map((osh), (va), (size), (direction))
|
||||
#define DMA_UNMAP(osh, pa, size, direction, p) \
|
||||
osl_dma_unmap((osh), (pa), (size), (direction))
|
||||
static inline uint
|
||||
osl_dma_map(void *osh, void *va, uint size, int direction)
|
||||
{
|
||||
int dir;
|
||||
struct pci_dev *dev;
|
||||
|
||||
dev = (osh == NULL ? NULL : ((osl_t *)osh)->pdev);
|
||||
dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
|
||||
return (pci_map_single(dev, va, size, dir));
|
||||
}
|
||||
|
||||
static inline void
|
||||
osl_dma_unmap(void *osh, uint pa, uint size, int direction)
|
||||
{
|
||||
int dir;
|
||||
struct pci_dev *dev;
|
||||
|
||||
dev = (osh == NULL ? NULL : ((osl_t *)osh)->pdev);
|
||||
dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
|
||||
pci_unmap_single(dev, (uint32)pa, size, dir);
|
||||
}
|
||||
|
||||
#define OSL_DMADDRWIDTH(osh, addrwidth) do {} while (0)
|
||||
/* allocate/free shared (dma-able) consistent memory */
|
||||
#define DMA_CONSISTENT_ALIGN PAGE_SIZE
|
||||
#define DMA_ALLOC_CONSISTENT(osh, size, pap, dmah) \
|
||||
osl_dma_alloc_consistent((osh), (size), (pap))
|
||||
#define DMA_FREE_CONSISTENT(osh, va, size, pa, dmah) \
|
||||
osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
|
||||
static inline void*
|
||||
osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap)
|
||||
{
|
||||
return (pci_alloc_consistent(osh->pdev, size, (dma_addr_t*)pap));
|
||||
}
|
||||
extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap);
|
||||
extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa);
|
||||
|
||||
static inline void
|
||||
osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa)
|
||||
{
|
||||
pci_free_consistent(osh->pdev, size, va, (dma_addr_t)pa);
|
||||
}
|
||||
/* map/unmap direction */
|
||||
#define DMA_TX 1 /* TX direction for DMA */
|
||||
#define DMA_RX 2 /* RX direction for DMA */
|
||||
|
||||
/* map/unmap shared (dma-able) memory */
|
||||
#define DMA_MAP(osh, va, size, direction, p, dmah) \
|
||||
osl_dma_map((osh), (va), (size), (direction))
|
||||
#define DMA_UNMAP(osh, pa, size, direction, p, dmah) \
|
||||
osl_dma_unmap((osh), (pa), (size), (direction))
|
||||
extern uint osl_dma_map(osl_t *osh, void *va, uint size, int direction);
|
||||
extern void osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction);
|
||||
|
||||
/* API for DMA addressing capability */
|
||||
#define OSL_DMADDRWIDTH(osh, addrwidth) do {} while (0)
|
||||
|
||||
/* register access macros */
|
||||
#if defined(BCMJTAG)
|
||||
#include <bcmjtag.h>
|
||||
#define R_REG(osh, r) bcmjtag_read(NULL, (uint32)(r), sizeof(*(r)))
|
||||
#define W_REG(osh, r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof(*(r)))
|
||||
#endif /* defined(BCMSDIO) */
|
||||
#define OSL_WRITE_REG(osh, r, v) (bcmjtag_write(NULL, (uintptr)(r), (v), sizeof(*(r))))
|
||||
#define OSL_READ_REG(osh, r) (bcmjtag_read(NULL, (uintptr)(r), sizeof(*(r))))
|
||||
#endif
|
||||
|
||||
#if defined(BCMJTAG)
|
||||
#define SELECT_BUS_WRITE(osh, mmap_op, bus_op) if (((osl_pubinfo_t*)(osh))->mmbus) \
|
||||
mmap_op else bus_op
|
||||
#define SELECT_BUS_READ(osh, mmap_op, bus_op) (((osl_pubinfo_t*)(osh))->mmbus) ? \
|
||||
mmap_op : bus_op
|
||||
#else
|
||||
#define SELECT_BUS_WRITE(osh, mmap_op, bus_op) mmap_op
|
||||
#define SELECT_BUS_READ(osh, mmap_op, bus_op) mmap_op
|
||||
#endif
|
||||
|
||||
/*
|
||||
* BINOSL selects the slightly slower function-call-based binary compatible osl.
|
||||
* Macros expand to calls to functions defined in linux_osl.c .
|
||||
*/
|
||||
#ifndef BINOSL
|
||||
|
||||
/* string library, kernel mode */
|
||||
#ifndef printf
|
||||
#define printf(fmt, args...) printk(fmt, ## args)
|
||||
#endif /* printf */
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
/* register access macros */
|
||||
#define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v))
|
||||
#define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v))
|
||||
|
||||
/* bcopy, bcmp, and bzero */
|
||||
#define bcopy(src, dst, len) memcpy((dst), (src), (len))
|
||||
#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
|
||||
#define bzero(b, len) memset((b), '\0', (len))
|
||||
|
||||
/* uncached virtual address */
|
||||
#ifdef mips
|
||||
#define OSL_UNCACHED(va) KSEG1ADDR((va))
|
||||
#include <asm/addrspace.h>
|
||||
#else
|
||||
#define OSL_UNCACHED(va) (va)
|
||||
#endif /* mips */
|
||||
|
||||
/* get processor cycle count */
|
||||
#if defined(mips)
|
||||
#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
|
||||
#elif defined(__i386__)
|
||||
#define OSL_GETCYCLES(x) rdtscl((x))
|
||||
#else
|
||||
#define OSL_GETCYCLES(x) ((x) = 0)
|
||||
#endif /* defined(mips) */
|
||||
|
||||
/* dereference an address that may cause a bus exception */
|
||||
#ifdef mips
|
||||
#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 17))
|
||||
#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into"\
|
||||
" a module")
|
||||
#else
|
||||
#define BUSPROBE(val, addr) get_dbe((val), (addr))
|
||||
#include <asm/paccess.h>
|
||||
#endif /* defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 17)) */
|
||||
#else
|
||||
#define BUSPROBE(val, addr) ({ (val) = R_REG(NULL, (addr)); 0; })
|
||||
#endif /* mips */
|
||||
|
||||
/* map/unmap physical to virtual I/O */
|
||||
#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
|
||||
#define REG_UNMAP(va) iounmap((void *)(va))
|
||||
|
||||
/* shared (dma-able) memory access macros */
|
||||
#define R_SM(r) *(r)
|
||||
#define W_SM(r, v) (*(r) = (v))
|
||||
#define BZERO_SM(r, len) memset((r), '\0', (len))
|
||||
|
||||
/* packet primitives */
|
||||
#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
|
||||
#define PKTGET(osh, len, send) osl_pktget((osh), (len))
|
||||
#define PKTFREE(osh, skb, send) osl_pktfree((osh), (skb), (send))
|
||||
#define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data)
|
||||
#define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len)
|
||||
|
@ -104,15 +161,25 @@ osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa)
|
|||
#define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
|
||||
#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
|
||||
#define PKTTAG(skb) ((void*)(((struct sk_buff*)(skb))->cb))
|
||||
#define PKTALLOCED(osh) osl_pktalloced((osh))
|
||||
#define PKTALLOCED(osh) ((osl_pubinfo_t *)(osh))->pktalloced
|
||||
#ifdef BCMDBG_PKT /* pkt logging for debugging */
|
||||
#define PKTLIST_DUMP(osh, buf) osl_pktlist_dump(osh, buf)
|
||||
#else /* BCMDBG_PKT */
|
||||
#define PKTLIST_DUMP(osh, buf)
|
||||
#endif /* BCMDBG_PKT */
|
||||
|
||||
#ifdef BCMDBG_PKT /* pkt logging for debugging */
|
||||
extern void osl_pktlist_add(osl_t *osh, void *p);
|
||||
extern void osl_pktlist_remove(osl_t *osh, void *p);
|
||||
extern char *osl_pktlist_dump(osl_t *osh, char *buf);
|
||||
#endif /* BCMDBG_PKT */
|
||||
|
||||
/* Convert a native(OS) packet to driver packet.
|
||||
* In the process, native packet is destroyed, there is no copying
|
||||
* Also, a packettag is zeroed out
|
||||
*/
|
||||
static INLINE void *
|
||||
osl_pkt_frmnative(osl_pubinfo_t*osh, struct sk_buff *skb)
|
||||
osl_pkt_frmnative(osl_pubinfo_t *osh, struct sk_buff *skb)
|
||||
{
|
||||
struct sk_buff *nskb;
|
||||
|
||||
|
@ -121,13 +188,15 @@ osl_pkt_frmnative(osl_pubinfo_t*osh, struct sk_buff *skb)
|
|||
|
||||
/* Increment the packet counter */
|
||||
for (nskb = skb; nskb; nskb = nskb->next) {
|
||||
#ifdef BCMDBG_PKT
|
||||
osl_pktlist_add((osl_t *)osh, (void *) nskb);
|
||||
#endif /* BCMDBG_PKT */
|
||||
osh->pktalloced++;
|
||||
}
|
||||
|
||||
return (void *)skb;
|
||||
}
|
||||
#define PKTFRMNATIVE(osh, skb) osl_pkt_frmnative(((osl_pubinfo_t*)osh), \
|
||||
(struct sk_buff*)(skb))
|
||||
#define PKTFRMNATIVE(osh, skb) osl_pkt_frmnative(((osl_pubinfo_t *)osh), (struct sk_buff*)(skb))
|
||||
|
||||
/* Convert a driver packet to native(OS) packet
|
||||
* In the process, packettag is zeroed out before sending up
|
||||
|
@ -135,7 +204,7 @@ osl_pkt_frmnative(osl_pubinfo_t*osh, struct sk_buff *skb)
|
|||
* In our case, that means it should be 0
|
||||
*/
|
||||
static INLINE struct sk_buff *
|
||||
osl_pkt_tonative(osl_pubinfo_t*osh, void *pkt)
|
||||
osl_pkt_tonative(osl_pubinfo_t *osh, void *pkt)
|
||||
{
|
||||
struct sk_buff *nskb;
|
||||
|
||||
|
@ -144,24 +213,167 @@ osl_pkt_tonative(osl_pubinfo_t*osh, void *pkt)
|
|||
|
||||
/* Decrement the packet counter */
|
||||
for (nskb = (struct sk_buff *)pkt; nskb; nskb = nskb->next) {
|
||||
#ifdef BCMDBG_PKT
|
||||
osl_pktlist_remove((osl_t *)osh, (void *) nskb);
|
||||
#endif /* BCMDBG_PKT */
|
||||
osh->pktalloced--;
|
||||
}
|
||||
|
||||
return (struct sk_buff *)pkt;
|
||||
}
|
||||
#define PKTTONATIVE(osh, pkt) osl_pkt_tonative((osl_pubinfo_t*)(osh), (pkt))
|
||||
#define PKTTONATIVE(osh, pkt) osl_pkt_tonative((osl_pubinfo_t *)(osh), (pkt))
|
||||
|
||||
#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
|
||||
#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
|
||||
#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
|
||||
#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
|
||||
#define PKTSUMNEEDED(skb) (((struct sk_buff*)(skb))->ip_summed == CHECKSUM_HW)
|
||||
#define PKTSETSUMGOOD(skb, x) (((struct sk_buff*)(skb))->ip_summed = \
|
||||
((x) ? CHECKSUM_UNNECESSARY : CHECKSUM_NONE))
|
||||
/* PKTSETSUMNEEDED and PKTSUMGOOD are not possible because skb->ip_summed is overloaded */
|
||||
#define PKTSHARED(skb) (((struct sk_buff*)(skb))->cloned)
|
||||
|
||||
extern void *osl_pktget(osl_t *osh, uint len, bool send);
|
||||
extern void *osl_pktget(osl_t *osh, uint len);
|
||||
extern void osl_pktfree(osl_t *osh, void *skb, bool send);
|
||||
extern void *osl_pktdup(osl_t *osh, void *skb);
|
||||
#else /* BINOSL */
|
||||
|
||||
/* string library */
|
||||
#ifndef LINUX_OSL
|
||||
#undef printf
|
||||
#define printf(fmt, args...) osl_printf((fmt), ## args)
|
||||
#undef sprintf
|
||||
#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
|
||||
#undef strcmp
|
||||
#define strcmp(s1, s2) osl_strcmp((s1), (s2))
|
||||
#undef strncmp
|
||||
#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
|
||||
#undef strlen
|
||||
#define strlen(s) osl_strlen((s))
|
||||
#undef strcpy
|
||||
#define strcpy(d, s) osl_strcpy((d), (s))
|
||||
#undef strncpy
|
||||
#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
|
||||
#endif /* LINUX_OSL */
|
||||
extern int osl_printf(const char *format, ...);
|
||||
extern int osl_sprintf(char *buf, const char *format, ...);
|
||||
extern int osl_strcmp(const char *s1, const char *s2);
|
||||
extern int osl_strncmp(const char *s1, const char *s2, uint n);
|
||||
extern int osl_strlen(const char *s);
|
||||
extern char* osl_strcpy(char *d, const char *s);
|
||||
extern char* osl_strncpy(char *d, const char *s, uint n);
|
||||
|
||||
/* register access macros */
|
||||
#if !defined(BCMJTAG)
|
||||
#define R_REG(osh, r) (\
|
||||
sizeof(*(r)) == sizeof(uint8) ? osl_readb((volatile uint8*)(r)) : \
|
||||
sizeof(*(r)) == sizeof(uint16) ? osl_readw((volatile uint16*)(r)) : \
|
||||
osl_readl((volatile uint32*)(r)) \
|
||||
)
|
||||
#define W_REG(osh, r, v) do { \
|
||||
switch (sizeof(*(r))) { \
|
||||
case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
|
||||
case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
|
||||
case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
|
||||
} \
|
||||
} while (0)
|
||||
#endif
|
||||
|
||||
#define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v))
|
||||
#define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v))
|
||||
extern uint8 osl_readb(volatile uint8 *r);
|
||||
extern uint16 osl_readw(volatile uint16 *r);
|
||||
extern uint32 osl_readl(volatile uint32 *r);
|
||||
extern void osl_writeb(uint8 v, volatile uint8 *r);
|
||||
extern void osl_writew(uint16 v, volatile uint16 *r);
|
||||
extern void osl_writel(uint32 v, volatile uint32 *r);
|
||||
|
||||
/* bcopy, bcmp, and bzero */
|
||||
extern void bcopy(const void *src, void *dst, int len);
|
||||
extern int bcmp(const void *b1, const void *b2, int len);
|
||||
extern void bzero(void *b, int len);
|
||||
|
||||
/* uncached virtual address */
|
||||
#define OSL_UNCACHED(va) osl_uncached((va))
|
||||
extern void *osl_uncached(void *va);
|
||||
|
||||
/* get processor cycle count */
|
||||
#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
|
||||
extern uint osl_getcycles(void);
|
||||
|
||||
/* dereference an address that may target abort */
|
||||
#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
|
||||
extern int osl_busprobe(uint32 *val, uint32 addr);
|
||||
|
||||
/* map/unmap physical to virtual */
|
||||
#define REG_MAP(pa, size) osl_reg_map((pa), (size))
|
||||
#define REG_UNMAP(va) osl_reg_unmap((va))
|
||||
extern void *osl_reg_map(uint32 pa, uint size);
|
||||
extern void osl_reg_unmap(void *va);
|
||||
|
||||
/* shared (dma-able) memory access macros */
|
||||
#define R_SM(r) *(r)
|
||||
#define W_SM(r, v) (*(r) = (v))
|
||||
#define BZERO_SM(r, len) bzero((r), (len))
|
||||
|
||||
/* packet primitives */
|
||||
#define PKTGET(osh, len, send) osl_pktget((osh), (len))
|
||||
#define PKTFREE(osh, skb, send) osl_pktfree((osh), (skb), (send))
|
||||
#define PKTDATA(osh, skb) osl_pktdata((osh), (skb))
|
||||
#define PKTLEN(osh, skb) osl_pktlen((osh), (skb))
|
||||
#define PKTHEADROOM(osh, skb) osl_pktheadroom((osh), (skb))
|
||||
#define PKTTAILROOM(osh, skb) osl_pkttailroom((osh), (skb))
|
||||
#define PKTNEXT(osh, skb) osl_pktnext((osh), (skb))
|
||||
#define PKTSETNEXT(osh, skb, x) osl_pktsetnext((skb), (x))
|
||||
#define PKTSETLEN(osh, skb, len) osl_pktsetlen((osh), (skb), (len))
|
||||
#define PKTPUSH(osh, skb, bytes) osl_pktpush((osh), (skb), (bytes))
|
||||
#define PKTPULL(osh, skb, bytes) osl_pktpull((osh), (skb), (bytes))
|
||||
#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
|
||||
#define PKTTAG(skb) osl_pkttag((skb))
|
||||
#define PKTFRMNATIVE(osh, skb) osl_pkt_frmnative((osh), (struct sk_buff*)(skb))
|
||||
#define PKTTONATIVE(osh, pkt) osl_pkt_tonative((osh), (pkt))
|
||||
#define PKTLINK(skb) osl_pktlink((skb))
|
||||
#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
|
||||
#define PKTPRIO(skb) osl_pktprio((skb))
|
||||
#define PKTSETPRIO(skb, x) osl_pktsetprio((skb), (x))
|
||||
#define PKTSHARED(skb) osl_pktshared((skb))
|
||||
#define PKTALLOCED(osh) osl_pktalloced((osh))
|
||||
#ifdef BCMDBG_PKT
|
||||
#define PKTLIST_DUMP(osh, buf) osl_pktlist_dump(osh, buf)
|
||||
#else /* BCMDBG_PKT */
|
||||
#define PKTLIST_DUMP(osh, buf)
|
||||
#endif /* BCMDBG_PKT */
|
||||
|
||||
extern void *osl_pktget(osl_t *osh, uint len);
|
||||
extern void osl_pktfree(osl_t *osh, void *skb, bool send);
|
||||
extern uchar *osl_pktdata(osl_t *osh, void *skb);
|
||||
extern uint osl_pktlen(osl_t *osh, void *skb);
|
||||
extern uint osl_pktheadroom(osl_t *osh, void *skb);
|
||||
extern uint osl_pkttailroom(osl_t *osh, void *skb);
|
||||
extern void *osl_pktnext(osl_t *osh, void *skb);
|
||||
extern void osl_pktsetnext(void *skb, void *x);
|
||||
extern void osl_pktsetlen(osl_t *osh, void *skb, uint len);
|
||||
extern uchar *osl_pktpush(osl_t *osh, void *skb, int bytes);
|
||||
extern uchar *osl_pktpull(osl_t *osh, void *skb, int bytes);
|
||||
extern void *osl_pktdup(osl_t *osh, void *skb);
|
||||
extern void *osl_pkttag(void *skb);
|
||||
extern void *osl_pktlink(void *skb);
|
||||
extern void osl_pktsetlink(void *skb, void *x);
|
||||
extern uint osl_pktprio(void *skb);
|
||||
extern void osl_pktsetprio(void *skb, uint x);
|
||||
extern void *osl_pkt_frmnative(osl_t *osh, struct sk_buff *skb);
|
||||
extern struct sk_buff *osl_pkt_tonative(osl_t *osh, void *pkt);
|
||||
extern bool osl_pktshared(void *skb);
|
||||
extern uint osl_pktalloced(osl_t *osh);
|
||||
|
||||
#ifdef BCMDBG_PKT /* pkt logging for debugging */
|
||||
extern char *osl_pktlist_dump(osl_t *osh, char *buf);
|
||||
extern void osl_pktlist_add(osl_t *osh, void *p);
|
||||
extern void osl_pktlist_remove(osl_t *osh, void *p);
|
||||
#endif /* BCMDBG_PKT */
|
||||
|
||||
#endif /* BINOSL */
|
||||
|
||||
#define OSL_ERROR(bcmerror) osl_error(bcmerror)
|
||||
extern int osl_error(int bcmerror);
|
||||
|
||||
|
|
|
@ -1,61 +0,0 @@
|
|||
#!/usr/bin/perl
|
||||
#
|
||||
# Copyright (C) 2006 OpenWrt.org
|
||||
# Copyright (C) 2006 Felix Fietkau
|
||||
#
|
||||
# This is free software, licensed under the GNU General Public License v2.
|
||||
# See /LICENSE for more information.
|
||||
#
|
||||
use strict;
|
||||
|
||||
my $TABLE = pack("V", 0xbadc0ded);
|
||||
my $TABLE_SIZE = 512;
|
||||
my $SLT1 = "\x01\x00\x00\x00";
|
||||
my $SLT2 = "\x02\x00\x00\x00";
|
||||
my $ACKW = "\x03\x00\x00\x00";
|
||||
my $PTABLE_END = "\xff\xff\xff\xff";
|
||||
|
||||
my $addr = "";
|
||||
my $opcode = "";
|
||||
my $function = "";
|
||||
|
||||
sub add_entry {
|
||||
my $key = shift;
|
||||
my $value = shift;
|
||||
my $default = shift;
|
||||
|
||||
$TABLE .= $key;
|
||||
$TABLE .= pack("V", $value);
|
||||
$TABLE .= pack("V", $default);
|
||||
}
|
||||
|
||||
while (<>) {
|
||||
$addr = $opcode = "";
|
||||
/^\w{8}\s*<(.*)>:$/ and $function = $1;
|
||||
/^\s*(\w+):\s*(\w{8})\s*/ and do {
|
||||
$addr = $1;
|
||||
$opcode = $2;
|
||||
};
|
||||
|
||||
($function eq 'wlc_update_slot_timing') and do {
|
||||
# li a2,9 -- short slot time
|
||||
($opcode eq '24060009') and add_entry($SLT1, hex($addr), hex($opcode));
|
||||
# li v0,519 -- 510 + short slot time
|
||||
($opcode eq '24020207') and add_entry($SLT2, hex($addr), hex($opcode));
|
||||
|
||||
# li a2,20 -- long slot time
|
||||
($opcode eq '24060014') and add_entry($SLT1, hex($addr), hex($opcode));
|
||||
# li v0,530 -- 510 + long slot time
|
||||
($opcode eq '24020212') and add_entry($SLT2, hex($addr), hex($opcode));
|
||||
};
|
||||
($function eq 'wlc_d11hdrs') and do {
|
||||
# ori s6,s6,0x1 -- ack flag (new)
|
||||
($opcode eq '36d60001') and add_entry($ACKW, hex($addr), hex($opcode));
|
||||
# ori s3,s3,0x1 -- ack flag (old)
|
||||
($opcode eq '36730001') and add_entry($ACKW, hex($addr), hex($opcode));
|
||||
}
|
||||
}
|
||||
|
||||
$TABLE .= $PTABLE_END;
|
||||
$TABLE .= ("\x00" x ($TABLE_SIZE - length($TABLE)));
|
||||
print $TABLE;
|
|
@ -1,97 +0,0 @@
|
|||
/*
|
||||
* Misc useful os-independent macros and functions.
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
* $Id: bcmutils.h,v 1.1.1.16 2006/04/08 06:13:39 honor Exp $
|
||||
*/
|
||||
|
||||
#ifndef _pktq_h_
|
||||
#define _pktq_h_
|
||||
#include <osl.h>
|
||||
|
||||
/* osl multi-precedence packet queue */
|
||||
|
||||
#define PKTQ_LEN_DEFAULT 128 /* Max 128 packets */
|
||||
#define PKTQ_MAX_PREC 16 /* Maximum precedence levels */
|
||||
|
||||
struct pktq {
|
||||
struct pktq_prec {
|
||||
void *head; /* first packet to dequeue */
|
||||
void *tail; /* last packet to dequeue */
|
||||
uint16 len; /* number of queued packets */
|
||||
uint16 max; /* maximum number of queued packets */
|
||||
} q[PKTQ_MAX_PREC];
|
||||
uint16 num_prec; /* number of precedences in use */
|
||||
uint16 hi_prec; /* rapid dequeue hint (>= highest non-empty prec) */
|
||||
uint16 max; /* total max packets */
|
||||
uint16 len; /* total number of packets */
|
||||
};
|
||||
|
||||
#define PKTQ_PREC_ITER(pq, prec) for (prec = (pq)->num_prec - 1; prec >= 0; prec--)
|
||||
|
||||
/* forward definition of ether_addr structure used by some function prototypes */
|
||||
|
||||
struct ether_addr;
|
||||
|
||||
/* operations on a specific precedence in packet queue */
|
||||
|
||||
#define pktq_psetmax(pq, prec, _max) ((pq)->q[prec].max = (_max))
|
||||
#define pktq_plen(pq, prec) ((pq)->q[prec].len)
|
||||
#define pktq_pavail(pq, prec) ((pq)->q[prec].max - (pq)->q[prec].len)
|
||||
#define pktq_pfull(pq, prec) ((pq)->q[prec].len >= (pq)->q[prec].max)
|
||||
#define pktq_pempty(pq, prec) ((pq)->q[prec].len == 0)
|
||||
|
||||
#define pktq_ppeek(pq, prec) ((pq)->q[prec].head)
|
||||
#define pktq_ppeek_tail(pq, prec) ((pq)->q[prec].tail)
|
||||
|
||||
extern void *pktq_penq(struct pktq *pq, int prec, void *p);
|
||||
extern void *pktq_penq_head(struct pktq *pq, int prec, void *p);
|
||||
extern void *pktq_pdeq(struct pktq *pq, int prec);
|
||||
extern void *pktq_pdeq_tail(struct pktq *pq, int prec);
|
||||
/* Empty the queue at particular precedence level */
|
||||
extern void pktq_pflush(osl_t *osh, struct pktq *pq, int prec, bool dir);
|
||||
/* Remove a specified packet from its queue */
|
||||
extern bool pktq_pdel(struct pktq *pq, void *p, int prec);
|
||||
|
||||
/* operations on a set of precedences in packet queue */
|
||||
|
||||
extern int pktq_mlen(struct pktq *pq, uint prec_bmp);
|
||||
extern void *pktq_mdeq(struct pktq *pq, uint prec_bmp, int *prec_out);
|
||||
|
||||
/* operations on packet queue as a whole */
|
||||
|
||||
#define pktq_len(pq) ((int)(pq)->len)
|
||||
#define pktq_max(pq) ((int)(pq)->max)
|
||||
#define pktq_avail(pq) ((int)((pq)->max - (pq)->len))
|
||||
#define pktq_full(pq) ((pq)->len >= (pq)->max)
|
||||
#define pktq_empty(pq) ((pq)->len == 0)
|
||||
|
||||
/* operations for single precedence queues */
|
||||
#define pktenq(pq, p) pktq_penq((pq), 0, (p))
|
||||
#define pktenq_head(pq, p) pktq_penq_head((pq), 0, (p))
|
||||
#define pktdeq(pq) pktq_pdeq((pq), 0)
|
||||
#define pktdeq_tail(pq) pktq_pdeq_tail((pq), 0)
|
||||
|
||||
extern void pktq_init(struct pktq *pq, int num_prec, int max_len);
|
||||
/* prec_out may be NULL if caller is not interested in return value */
|
||||
extern void *pktq_deq(struct pktq *pq, int *prec_out);
|
||||
extern void *pktq_deq_tail(struct pktq *pq, int *prec_out);
|
||||
extern void *pktq_peek(struct pktq *pq, int *prec_out);
|
||||
extern void *pktq_peek_tail(struct pktq *pq, int *prec_out);
|
||||
extern void pktq_flush(osl_t *osh, struct pktq *pq, bool dir); /* Empty the entire queue */
|
||||
|
||||
/* externs */
|
||||
/* packet */
|
||||
extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
|
||||
extern uint pkttotlen(osl_t *osh, void *p);
|
||||
extern void *pktlast(osl_t *osh, void *p);
|
||||
|
||||
extern void pktsetprio(void *pkt, bool update_vtag);
|
||||
|
||||
#endif /* _pktq_h_ */
|
1387
package/broadcom-wl/src/driver/proto/802.11.h
Normal file
1387
package/broadcom-wl/src/driver/proto/802.11.h
Normal file
File diff suppressed because it is too large
Load diff
123
package/broadcom-wl/src/driver/proto/802.11e.h
Normal file
123
package/broadcom-wl/src/driver/proto/802.11e.h
Normal file
|
@ -0,0 +1,123 @@
|
|||
/*
|
||||
* 802.11e protocol header file
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _802_11e_H_
|
||||
#define _802_11e_H_
|
||||
|
||||
/* enable structure packing */
|
||||
#if defined(__GNUC__)
|
||||
#define PACKED __attribute__((packed))
|
||||
#else
|
||||
#pragma pack(1)
|
||||
#define PACKED
|
||||
#endif
|
||||
|
||||
#ifdef BCMDBG
|
||||
extern const char *aci_names[];
|
||||
#endif /* BCMDBG */
|
||||
|
||||
/* WME Traffic Specification (TSPEC) element */
|
||||
#define WME_TSPEC_HDR_LEN 2 /* WME TSPEC header length */
|
||||
#define WME_TSPEC_BODY_OFF 2 /* WME TSPEC body offset */
|
||||
|
||||
#define WME_CATEGORY_CODE_OFFSET 0 /* WME Category code offset */
|
||||
#define WME_ACTION_CODE_OFFSET 1 /* WME Action code offset */
|
||||
#define WME_TOKEN_CODE_OFFSET 2 /* WME Token code offset */
|
||||
#define WME_STATUS_CODE_OFFSET 3 /* WME Status code offset */
|
||||
|
||||
struct tsinfo {
|
||||
uint8 octets[3];
|
||||
} PACKED;
|
||||
|
||||
typedef struct tsinfo tsinfo_t;
|
||||
|
||||
/* 802.11e TSPEC IE */
|
||||
typedef struct tspec {
|
||||
uint8 oui[DOT11_OUI_LEN]; /* WME_OUI */
|
||||
uint8 type; /* WME_TYPE */
|
||||
uint8 subtype; /* WME_SUBTYPE_TSPEC */
|
||||
uint8 version; /* WME_VERSION */
|
||||
tsinfo_t tsinfo; /* TS Info bit field */
|
||||
uint16 nom_msdu_size; /* (Nominal or fixed) MSDU Size (bytes) */
|
||||
uint16 max_msdu_size; /* Maximum MSDU Size (bytes) */
|
||||
uint32 min_srv_interval; /* Minimum Service Interval (us) */
|
||||
uint32 max_srv_interval; /* Maximum Service Interval (us) */
|
||||
uint32 inactivity_interval; /* Inactivity Interval (us) */
|
||||
uint32 suspension_interval; /* Suspension Interval (us) */
|
||||
uint32 srv_start_time; /* Service Start Time (us) */
|
||||
uint32 min_data_rate; /* Minimum Data Rate (bps) */
|
||||
uint32 mean_data_rate; /* Mean Data Rate (bps) */
|
||||
uint32 peak_data_rate; /* Peak Data Rate (bps) */
|
||||
uint32 max_burst_size; /* Maximum Burst Size (bytes) */
|
||||
uint32 delay_bound; /* Delay Bound (us) */
|
||||
uint32 min_phy_rate; /* Minimum PHY Rate (bps) */
|
||||
uint16 surplus_bw; /* Surplus Bandwidth Allowance Factor */
|
||||
uint16 medium_time; /* Medium Time (32 us/s periods) */
|
||||
} PACKED tspec_t;
|
||||
|
||||
#define WME_TSPEC_LEN (sizeof(tspec_t)) /* not including 2-bytes of header */
|
||||
|
||||
/* ts_info */
|
||||
/* 802.1D priority is duplicated - bits 13-11 AND bits 3-1 */
|
||||
#define TS_INFO_TID_SHIFT 1 /* TS info. TID shift */
|
||||
#define TS_INFO_TID_MASK (0xf << TS_INFO_TID_SHIFT) /* TS info. TID mask */
|
||||
#define TS_INFO_CONTENTION_SHIFT 7 /* TS info. contention shift */
|
||||
#define TS_INFO_CONTENTION_MASK (0x1 << TS_INFO_CONTENTION_SHIFT) /* TS info. contention mask */
|
||||
#define TS_INFO_DIRECTION_SHIFT 5 /* TS info. direction shift */
|
||||
#define TS_INFO_DIRECTION_MASK (0x3 << TS_INFO_DIRECTION_SHIFT) /* TS info. direction mask */
|
||||
#define TS_INFO_PSB_SHIFT 2 /* TS info. PSB bit Shift */
|
||||
#define TS_INFO_PSB_MASK (1 << TS_INFO_PSB_SHIFT) /* TS info. PSB mask */
|
||||
#define TS_INFO_UPLINK (0 << TS_INFO_DIRECTION_SHIFT) /* TS info. uplink */
|
||||
#define TS_INFO_DOWNLINK (1 << TS_INFO_DIRECTION_SHIFT) /* TS info. downlink */
|
||||
#define TS_INFO_BIDIRECTIONAL (3 << TS_INFO_DIRECTION_SHIFT) /* TS info. bidirectional */
|
||||
#define TS_INFO_USER_PRIO_SHIFT 3 /* TS info. user priority shift */
|
||||
/* TS info. user priority mask */
|
||||
#define TS_INFO_USER_PRIO_MASK (0x7 << TS_INFO_USER_PRIO_SHIFT)
|
||||
|
||||
/* Macro to get/set bit(s) field in TSINFO */
|
||||
#define WLC_CAC_GET_TID(pt) ((((pt).octets[0]) & TS_INFO_TID_MASK) >> TS_INFO_TID_SHIFT)
|
||||
#define WLC_CAC_GET_DIR(pt) ((((pt).octets[0]) & \
|
||||
TS_INFO_DIRECTION_MASK) >> TS_INFO_DIRECTION_SHIFT)
|
||||
#define WLC_CAC_GET_PSB(pt) ((((pt).octets[1]) & WLC_CAC_PSB_MASK) >> WLC_CAC_PSB_SHIFT)
|
||||
#define WLC_CAC_GET_USER_PRIO(pt) ((((pt).octets[1]) & \
|
||||
TS_INFO_USER_PRIO_MASK) >> TS_INFO_USER_PRIO_SHIFT)
|
||||
|
||||
#define WLC_CAC_SET_TID(pt, id) ((((pt).octets[0]) & (~TS_INFO_TID_MASK)) | \
|
||||
((id) << TS_INFO_TID_SHIFT))
|
||||
#define WLC_CAC_SET_USER_PRIO(pt, prio) ((((pt).octets[0]) & (~TS_INFO_USER_PRIO_MASK)) | \
|
||||
((prio) << TS_INFO_USER_PRIO_SHIFT))
|
||||
|
||||
/* 802.11e QBSS Load IE */
|
||||
#define QBSS_LOAD_IE_LEN 5 /* QBSS Load IE length */
|
||||
#define QBSS_LOAD_AAC_OFF 3 /* AAC offset in IE */
|
||||
|
||||
#define CAC_ADDTS_RESP_TIMEOUT 300 /* default ADDTS response timeout in ms */
|
||||
|
||||
/* 802.11e ADDTS status code */
|
||||
#define DOT11E_STATUS_ADMISSION_ACCEPTED 0 /* TSPEC Admission accepted status */
|
||||
#define DOT11E_STATUS_ADDTS_INVALID_PARAM 1 /* TSPEC invalid parameter status */
|
||||
#define DOT11E_STATUS_ADDTS_REFUSED_NSBW 3 /* ADDTS refused (non-sufficient BW) */
|
||||
|
||||
/* 802.11e DELTS status code */
|
||||
#define DOT11E_STATUS_QSTA_LEAVE_QBSS 36 /* STA leave QBSS */
|
||||
#define DOT11E_STATUS_END_TS 37 /* END TS */
|
||||
#define DOT11E_STATUS_UNKNOWN_TS 38 /* UNKNOWN TS */
|
||||
#define DOT11E_STATUS_QSTA_REQ_TIMEOUT 39 /* STA ADDTS request timeout */
|
||||
|
||||
#undef PACKED
|
||||
#if !defined(__GNUC__)
|
||||
#pragma pack()
|
||||
#endif
|
||||
|
||||
#endif /* _802_11e_CAC_H_ */
|
38
package/broadcom-wl/src/driver/proto/802.1d.h
Normal file
38
package/broadcom-wl/src/driver/proto/802.1d.h
Normal file
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* Fundamental types and constants relating to 802.1D
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _802_1_D_
|
||||
#define _802_1_D_
|
||||
|
||||
/* 802.1D priority defines */
|
||||
#define PRIO_8021D_NONE 2 /* None = - */
|
||||
#define PRIO_8021D_BK 1 /* BK - Background */
|
||||
#define PRIO_8021D_BE 0 /* BE - Best-effort */
|
||||
#define PRIO_8021D_EE 3 /* EE - Excellent-effort */
|
||||
#define PRIO_8021D_CL 4 /* CL - Controlled Load */
|
||||
#define PRIO_8021D_VI 5 /* Vi - Video */
|
||||
#define PRIO_8021D_VO 6 /* Vo - Voice */
|
||||
#define PRIO_8021D_NC 7 /* NC - Network Control */
|
||||
#define MAXPRIO 7 /* 0-7 */
|
||||
#define NUMPRIO (MAXPRIO + 1)
|
||||
|
||||
#define ALLPRIO -1 /* All prioirty */
|
||||
|
||||
/* Converts prio to precedence since the numerical value of
|
||||
* PRIO_8021D_BE and PRIO_8021D_NONE are swapped.
|
||||
*/
|
||||
#define PRIO2PREC(prio) \
|
||||
(((prio) == PRIO_8021D_NONE || (prio) == PRIO_8021D_BE) ? ((prio^2)) : (prio))
|
||||
|
||||
#endif /* _802_1_D__ */
|
20
package/broadcom-wl/src/driver/proto/802.3.h
Normal file
20
package/broadcom-wl/src/driver/proto/802.3.h
Normal file
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
|
||||
* the contents of this file may not be disclosed to third parties, copied
|
||||
* or duplicated in any form, in whole or in part, without the prior
|
||||
* written permission of Broadcom Corporation.
|
||||
*
|
||||
* Fundamental constants relating to 802.3
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _802_3_h_
|
||||
#define _802_3_h_
|
||||
|
||||
#define SNAP_HDR_LEN 6 /* 802.3 LLC/SNAP header length */
|
||||
|
||||
#endif /* #ifndef _802_3_h_ */
|
60
package/broadcom-wl/src/driver/proto/bcmarp.h
Normal file
60
package/broadcom-wl/src/driver/proto/bcmarp.h
Normal file
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
|
||||
* the contents of this file may not be disclosed to third parties, copied
|
||||
* or duplicated in any form, in whole or in part, without the prior
|
||||
* written permission of Broadcom Corporation.
|
||||
*
|
||||
* Fundamental constants relating to ARP Protocol
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _bcmarp_h_
|
||||
#define _bcmarp_h_
|
||||
|
||||
/* enable structure packing */
|
||||
#if defined(__GNUC__)
|
||||
#define PACKED __attribute__((packed))
|
||||
#else
|
||||
#pragma pack(1)
|
||||
#define PACKED
|
||||
#endif
|
||||
|
||||
#define ARP_OPC_OFFSET 6 /* option code offset */
|
||||
#define ARP_SRC_ETH_OFFSET 8 /* src h/w address offset */
|
||||
#define ARP_SRC_IP_OFFSET 14 /* src IP address offset */
|
||||
#define ARP_TGT_ETH_OFFSET 18 /* target h/w address offset */
|
||||
#define ARP_TGT_IP_OFFSET 24 /* target IP address offset */
|
||||
|
||||
#define ARP_OPC_REQUEST 1 /* ARP request */
|
||||
#define ARP_OPC_REPLY 2 /* ARP reply */
|
||||
|
||||
#define ARP_DATA_LEN 28 /* ARP data length */
|
||||
|
||||
struct bcmarp {
|
||||
uint16 htype; /* Header type (1 = ethernet) */
|
||||
uint16 ptype; /* Protocol type (0x800 = IP) */
|
||||
uint8 hlen; /* Hardware address length (Eth = 6) */
|
||||
uint8 plen; /* Protocol address length (IP = 4) */
|
||||
uint16 oper; /* ARP_OPC_... */
|
||||
uint8 src_eth[ETHER_ADDR_LEN]; /* Source hardware address */
|
||||
uint8 src_ip[IPV4_ADDR_LEN]; /* Source protocol address (not aligned) */
|
||||
uint8 dst_eth[ETHER_ADDR_LEN]; /* Destination hardware address */
|
||||
uint8 dst_ip[IPV4_ADDR_LEN]; /* Destination protocol address */
|
||||
} PACKED;
|
||||
|
||||
/* Ethernet header + Arp message */
|
||||
struct bcmetharp {
|
||||
struct ether_header eh;
|
||||
struct bcmarp arp;
|
||||
} PACKED;
|
||||
|
||||
#undef PACKED
|
||||
#if !defined(__GNUC__)
|
||||
#pragma pack()
|
||||
#endif
|
||||
|
||||
#endif /* !defined(_bcmarp_h_) */
|
36
package/broadcom-wl/src/driver/proto/bcmdhcp.h
Normal file
36
package/broadcom-wl/src/driver/proto/bcmdhcp.h
Normal file
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
|
||||
* the contents of this file may not be disclosed to third parties, copied
|
||||
* or duplicated in any form, in whole or in part, without the prior
|
||||
* written permission of Broadcom Corporation.
|
||||
*
|
||||
* Fundamental constants relating to DHCP Protocol
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _bcmdhcp_h_
|
||||
#define _bcmdhcp_h_
|
||||
|
||||
/* DHCP params */
|
||||
#define DHCP_TYPE_OFFSET 0 /* DHCP type (request|reply) offset */
|
||||
#define DHCP_FLAGS_OFFSET 10 /* DHCP flags offset */
|
||||
#define DHCP_CIADDR_OFFSET 12 /* DHCP client IP address offset */
|
||||
#define DHCP_YIADDR_OFFSET 16 /* DHCP your IP address offset */
|
||||
#define DHCP_GIADDR_OFFSET 24 /* DHCP relay agent IP address offset */
|
||||
#define DHCP_CHADDR_OFFSET 28 /* DHCP client h/w address offset */
|
||||
|
||||
#define DHCP_TYPE_REQUEST 1 /* DHCP request (discover|request) */
|
||||
#define DHCP_TYPE_REPLY 2 /* DHCP reply (offset|ack) */
|
||||
|
||||
#define DHCP_PORT_SERVER 67 /* DHCP server UDP port */
|
||||
#define DHCP_PORT_CLIENT 68 /* DHCP client UDP port */
|
||||
|
||||
#define DHCP_FLAG_BCAST 0x8000 /* DHCP broadcast flag */
|
||||
|
||||
#define DHCP_FLAGS_LEN 2 /* DHCP flags field length */
|
||||
|
||||
#endif /* #ifndef _bcmdhcp_h_ */
|
101
package/broadcom-wl/src/driver/proto/bcmeth.h
Normal file
101
package/broadcom-wl/src/driver/proto/bcmeth.h
Normal file
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* Broadcom Ethernettype protocol definitions
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
/*
|
||||
* Broadcom Ethernet protocol defines
|
||||
*/
|
||||
|
||||
#ifndef _BCMETH_H_
|
||||
#define _BCMETH_H_
|
||||
|
||||
/* enable structure packing */
|
||||
#if defined(__GNUC__)
|
||||
#define PACKED __attribute__((packed))
|
||||
#else
|
||||
#pragma pack(1)
|
||||
#define PACKED
|
||||
#endif
|
||||
|
||||
/* ETHER_TYPE_BRCM is defined in ethernet.h */
|
||||
|
||||
/*
|
||||
* Following the 2byte BRCM ether_type is a 16bit BRCM subtype field
|
||||
* in one of two formats: (only subtypes 32768-65535 are in use now)
|
||||
*
|
||||
* subtypes 0-32767:
|
||||
* 8 bit subtype (0-127)
|
||||
* 8 bit length in bytes (0-255)
|
||||
*
|
||||
* subtypes 32768-65535:
|
||||
* 16 bit big-endian subtype
|
||||
* 16 bit big-endian length in bytes (0-65535)
|
||||
*
|
||||
* length is the number of additional bytes beyond the 4 or 6 byte header
|
||||
*
|
||||
* Reserved values:
|
||||
* 0 reserved
|
||||
* 5-15 reserved for iLine protocol assignments
|
||||
* 17-126 reserved, assignable
|
||||
* 127 reserved
|
||||
* 32768 reserved
|
||||
* 32769-65534 reserved, assignable
|
||||
* 65535 reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* While adding the subtypes and their specific processing code make sure
|
||||
* bcmeth_bcm_hdr_t is the first data structure in the user specific data structure definition
|
||||
*/
|
||||
|
||||
#define BCMILCP_SUBTYPE_RATE 1
|
||||
#define BCMILCP_SUBTYPE_LINK 2
|
||||
#define BCMILCP_SUBTYPE_CSA 3
|
||||
#define BCMILCP_SUBTYPE_LARQ 4
|
||||
#define BCMILCP_SUBTYPE_VENDOR 5
|
||||
#define BCMILCP_SUBTYPE_FLH 17
|
||||
|
||||
#define BCMILCP_SUBTYPE_VENDOR_LONG 32769
|
||||
#define BCMILCP_SUBTYPE_CERT 32770
|
||||
#define BCMILCP_SUBTYPE_SES 32771
|
||||
|
||||
|
||||
#define BCMILCP_BCM_SUBTYPE_RESERVED 0
|
||||
#define BCMILCP_BCM_SUBTYPE_EVENT 1
|
||||
#define BCMILCP_BCM_SUBTYPE_SES 2
|
||||
/*
|
||||
* The EAPOL type is not used anymore. Instead EAPOL messages are now embedded
|
||||
* within BCMILCP_BCM_SUBTYPE_EVENT type messages
|
||||
*/
|
||||
/* #define BCMILCP_BCM_SUBTYPE_EAPOL 3 */
|
||||
|
||||
#define BCMILCP_BCM_SUBTYPEHDR_MINLENGTH 8
|
||||
#define BCMILCP_BCM_SUBTYPEHDR_VERSION 0
|
||||
|
||||
/* These fields are stored in network order */
|
||||
typedef struct bcmeth_hdr
|
||||
{
|
||||
uint16 subtype; /* Vendor specific..32769 */
|
||||
uint16 length;
|
||||
uint8 version; /* Version is 0 */
|
||||
uint8 oui[3]; /* Broadcom OUI */
|
||||
/* user specific Data */
|
||||
uint16 usr_subtype;
|
||||
} PACKED bcmeth_hdr_t;
|
||||
|
||||
#undef PACKED
|
||||
#if !defined(__GNUC__)
|
||||
#pragma pack()
|
||||
#endif
|
||||
|
||||
#endif /* _BCMETH_H_ */
|
166
package/broadcom-wl/src/driver/proto/bcmevent.h
Normal file
166
package/broadcom-wl/src/driver/proto/bcmevent.h
Normal file
|
@ -0,0 +1,166 @@
|
|||
/*
|
||||
* Broadcom Event protocol definitions
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*
|
||||
* Dependencies: proto/bcmeth.h
|
||||
*
|
||||
* $Id$
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Broadcom Ethernet Events protocol defines
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _BCMEVENT_H_
|
||||
#define _BCMEVENT_H_
|
||||
|
||||
/* enable structure packing */
|
||||
#if defined(__GNUC__)
|
||||
#define PACKED __attribute__((packed))
|
||||
#else
|
||||
#pragma pack(1)
|
||||
#define PACKED
|
||||
#endif /* defined(__GNUC__) */
|
||||
|
||||
#define BCM_EVENT_MSG_VERSION 1 /* wl_event_msg_t struct version */
|
||||
#define BCM_MSG_IFNAME_MAX 16 /* max length of interface name */
|
||||
|
||||
/* flags */
|
||||
#define WLC_EVENT_MSG_LINK 0x01 /* link is up */
|
||||
#define WLC_EVENT_MSG_FLUSHTXQ 0x02 /* flush tx queue on MIC error */
|
||||
#define WLC_EVENT_MSG_GROUP 0x04 /* group MIC error */
|
||||
|
||||
/* these fields are stored in network order */
|
||||
typedef struct
|
||||
{
|
||||
uint16 version;
|
||||
uint16 flags; /* see flags below */
|
||||
uint32 event_type; /* Message (see below) */
|
||||
uint32 status; /* Status code (see below) */
|
||||
uint32 reason; /* Reason code (if applicable) */
|
||||
uint32 auth_type; /* WLC_E_AUTH */
|
||||
uint32 datalen; /* data buf */
|
||||
struct ether_addr addr; /* Station address (if applicable) */
|
||||
char ifname[BCM_MSG_IFNAME_MAX]; /* name of the packet incoming interface */
|
||||
} PACKED wl_event_msg_t;
|
||||
|
||||
/* used by driver msgs */
|
||||
typedef struct bcm_event {
|
||||
struct ether_header eth;
|
||||
bcmeth_hdr_t bcm_hdr;
|
||||
wl_event_msg_t event;
|
||||
/* data portion follows */
|
||||
} PACKED bcm_event_t;
|
||||
|
||||
#define BCM_MSG_LEN (sizeof(bcm_event_t) - sizeof(bcmeth_hdr_t) - sizeof(struct ether_header))
|
||||
|
||||
/* Event messages */
|
||||
#define WLC_E_SET_SSID 0 /* indicates status of set SSID */
|
||||
#define WLC_E_JOIN 1 /* differentiates join IBSS from found (WLC_E_START) IBSS */
|
||||
#define WLC_E_START 2 /* STA founded an IBSS or AP started a BSS */
|
||||
#define WLC_E_AUTH 3 /* 802.11 AUTH request */
|
||||
#define WLC_E_AUTH_IND 4 /* 802.11 AUTH indication */
|
||||
#define WLC_E_DEAUTH 5 /* 802.11 DEAUTH request */
|
||||
#define WLC_E_DEAUTH_IND 6 /* 802.11 DEAUTH indication */
|
||||
#define WLC_E_ASSOC 7 /* 802.11 ASSOC request */
|
||||
#define WLC_E_ASSOC_IND 8 /* 802.11 ASSOC indication */
|
||||
#define WLC_E_REASSOC 9 /* 802.11 REASSOC request */
|
||||
#define WLC_E_REASSOC_IND 10 /* 802.11 REASSOC indication */
|
||||
#define WLC_E_DISASSOC 11 /* 802.11 DISASSOC request */
|
||||
#define WLC_E_DISASSOC_IND 12 /* 802.11 DISASSOC indication */
|
||||
#define WLC_E_QUIET_START 13 /* 802.11h Quiet period started */
|
||||
#define WLC_E_QUIET_END 14 /* 802.11h Quiet period ended */
|
||||
#define WLC_E_BEACON_RX 15 /* BEACONS received/lost indication */
|
||||
#define WLC_E_LINK 16 /* generic link indication */
|
||||
#define WLC_E_MIC_ERROR 17 /* TKIP MIC error occurred */
|
||||
#define WLC_E_NDIS_LINK 18 /* NDIS style link indication */
|
||||
#define WLC_E_ROAM 19 /* roam attempt occurred: indicate status & reason */
|
||||
#define WLC_E_TXFAIL 20 /* change in dot11FailedCount (txfail) */
|
||||
#define WLC_E_PMKID_CACHE 21 /* WPA2 pmkid cache indication */
|
||||
#define WLC_E_RETROGRADE_TSF 22 /* current AP's TSF value went backward */
|
||||
#define WLC_E_PRUNE 23 /* AP was pruned from join list for reason */
|
||||
#define WLC_E_AUTOAUTH 24 /* report AutoAuth table entry match for join attempt */
|
||||
#define WLC_E_EAPOL_MSG 25 /* Event encapsulating an EAPOL message */
|
||||
#define WLC_E_SCAN_COMPLETE 26 /* Scan results are ready or scan was aborted */
|
||||
#define WLC_E_ADDTS_IND 27 /* indicate to host addts fail/success */
|
||||
#define WLC_E_DELTS_IND 28 /* indicate to host delts fail/success */
|
||||
#define WLC_E_BCNSENT_IND 29 /* indicate to host of beacon transmit */
|
||||
#define WLC_E_BCNRX_MSG 30 /* Send the received beacon up to the host */
|
||||
#define WLC_E_BCNLOST_MSG 31 /* indicate to host loss of beacon */
|
||||
#define WLC_E_ROAM_PREP 32 /* before attempting to roam */
|
||||
#define WLC_E_PFN_NET_FOUND 33 /* PFN network found event */
|
||||
#define WLC_E_PFN_NET_LOST 34 /* PFN network lost event */
|
||||
|
||||
#ifdef EXT_STA
|
||||
#define WLC_E_RESET_COMPLETE 35
|
||||
#define WLC_E_JOIN_START 36
|
||||
#define WLC_E_ROAM_START 37
|
||||
#define WLC_E_ASSOC_START 38
|
||||
#define WLC_E_IBSS_ASSOC 39
|
||||
#define WLC_E_RADIO 40
|
||||
#define WLC_E_LAST 41 /* highest val + 1 for range checking */
|
||||
#else /* EXT_STA */
|
||||
#define WLC_E_LAST 35 /* highest val + 1 for range checking */
|
||||
#endif /* EXT_STA */
|
||||
|
||||
/* Event status codes */
|
||||
#define WLC_E_STATUS_SUCCESS 0 /* operation was successful */
|
||||
#define WLC_E_STATUS_FAIL 1 /* operation failed */
|
||||
#define WLC_E_STATUS_TIMEOUT 2 /* operation timed out */
|
||||
#define WLC_E_STATUS_NO_NETWORKS 3 /* failed due to no matching network found */
|
||||
#define WLC_E_STATUS_ABORT 4 /* operation was aborted */
|
||||
#define WLC_E_STATUS_NO_ACK 5 /* protocol failure: packet not ack'd */
|
||||
#define WLC_E_STATUS_UNSOLICITED 6 /* AUTH or ASSOC packet was unsolicited */
|
||||
#define WLC_E_STATUS_ATTEMPT 7 /* attempt to assoc to an auto auth configuration */
|
||||
#define WLC_E_STATUS_PARTIAL 8 /* scan results are incomplete */
|
||||
#define WLC_E_STATUS_NEWSCAN 9 /* scan aborted by another scan */
|
||||
#define WLC_E_STATUS_NEWASSOC 10 /* scan aborted due to assoc in progress */
|
||||
#define WLC_E_STATUS_11HQUIET 11 /* 802.11h quiet period started */
|
||||
#define WLC_E_STATUS_SUPPRESS 12 /* user disabled scanning (WLC_SET_SCANSUPPRESS) */
|
||||
#define WLC_E_STATUS_NOCHANS 13 /* no allowable channels to scan */
|
||||
#define WLC_E_STATUS_CCXFASTRM 14 /* scan aborted due to CCX fast roam */
|
||||
|
||||
/* roam reason codes */
|
||||
#define WLC_E_REASON_INITIAL_ASSOC 0 /* initial assoc */
|
||||
#define WLC_E_REASON_LOW_RSSI 1 /* roamed due to low RSSI */
|
||||
#define WLC_E_REASON_DEAUTH 2 /* roamed due to DEAUTH indication */
|
||||
#define WLC_E_REASON_DISASSOC 3 /* roamed due to DISASSOC indication */
|
||||
#define WLC_E_REASON_BCNS_LOST 4 /* roamed due to lost beacons */
|
||||
#define WLC_E_REASON_FAST_ROAM_FAILED 5 /* roamed due to fast roam failure */
|
||||
#define WLC_E_REASON_DIRECTED_ROAM 6 /* roamed due to request by AP */
|
||||
#define WLC_E_REASON_TSPEC_REJECTED 7 /* roamed due to TSPEC rejection */
|
||||
#define WLC_E_REASON_BETTER_AP 8 /* roamed due to finding better AP */
|
||||
|
||||
/* prune reason codes */
|
||||
#define WLC_E_PRUNE_ENCR_MISMATCH 1 /* encryption mismatch */
|
||||
#define WLC_E_PRUNE_BCAST_BSSID 2 /* AP uses a broadcast BSSID */
|
||||
#define WLC_E_PRUNE_MAC_DENY 3 /* STA's MAC addr is in AP's MAC deny list */
|
||||
#define WLC_E_PRUNE_MAC_NA 4 /* STA's MAC addr is not in AP's MAC allow list */
|
||||
#define WLC_E_PRUNE_REG_PASSV 5 /* AP not allowed due to regulatory restriction */
|
||||
#define WLC_E_PRUNE_SPCT_MGMT 6 /* AP does not support STA locale spectrum mgmt */
|
||||
#define WLC_E_PRUNE_RADAR 7 /* AP is on a radar channel of STA locale */
|
||||
#define WLC_E_RSN_MISMATCH 8 /* STA does not support AP's RSN */
|
||||
#define WLC_E_PRUNE_NO_COMMON_RATES 9 /* No rates in common with AP */
|
||||
#define WLC_E_PRUNE_BASIC_RATES 10 /* STA does not support all basic rates of BSS */
|
||||
#define WLC_E_PRUNE_CIPHER_NA 12 /* BSS's cipher not supported */
|
||||
#define WLC_E_PRUNE_KNOWN_STA 13 /* AP is already known to us as a STA */
|
||||
#define WLC_E_PRUNE_WDS_PEER 15 /* AP is already known to us as a WDS peer */
|
||||
#define WLC_E_PRUNE_QBSS_LOAD 16 /* QBSS LOAD - AAC is too low */
|
||||
#define WLC_E_PRUNE_HOME_AP 17 /* prune home AP */
|
||||
|
||||
#undef PACKED
|
||||
#if !defined(__GNUC__)
|
||||
#pragma pack()
|
||||
#endif /* PACKED */
|
||||
|
||||
#endif /* _BCMEVENT_H_ */
|
152
package/broadcom-wl/src/driver/proto/bcmip.h
Normal file
152
package/broadcom-wl/src/driver/proto/bcmip.h
Normal file
|
@ -0,0 +1,152 @@
|
|||
/*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* Fundamental constants relating to IP Protocol
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _bcmip_h_
|
||||
#define _bcmip_h_
|
||||
|
||||
/* enable structure packing */
|
||||
#if defined(__GNUC__)
|
||||
#define PACKED __attribute__((packed))
|
||||
#else
|
||||
#pragma pack(1)
|
||||
#define PACKED
|
||||
#endif
|
||||
|
||||
|
||||
/* IPV4 and IPV6 common */
|
||||
#define IP_VER_OFFSET 0x0 /* offset to version field */
|
||||
#define IP_VER_MASK 0xf0 /* version mask */
|
||||
#define IP_VER_SHIFT 4 /* version shift */
|
||||
#define IP_VER_4 4 /* version number for IPV4 */
|
||||
#define IP_VER_6 6 /* version number for IPV6 */
|
||||
|
||||
#define IP_VER(ip_body) \
|
||||
((((uint8 *)(ip_body))[IP_VER_OFFSET] & IP_VER_MASK) >> IP_VER_SHIFT)
|
||||
|
||||
#define IP_PROT_ICMP 0x1 /* ICMP protocol */
|
||||
#define IP_PROT_TCP 0x6 /* TCP protocol */
|
||||
#define IP_PROT_UDP 0x11 /* UDP protocol type */
|
||||
|
||||
/* IPV4 field offsets */
|
||||
#define IPV4_VER_HL_OFFSET 0 /* version and ihl byte offset */
|
||||
#define IPV4_TOS_OFFSET 1 /* type of service offset */
|
||||
#define IPV4_PKTLEN_OFFSET 2 /* packet length offset */
|
||||
#define IPV4_PKTFLAG_OFFSET 6 /* more-frag,dont-frag flag offset */
|
||||
#define IPV4_PROT_OFFSET 9 /* protocol type offset */
|
||||
#define IPV4_CHKSUM_OFFSET 10 /* IP header checksum offset */
|
||||
#define IPV4_SRC_IP_OFFSET 12 /* src IP addr offset */
|
||||
#define IPV4_DEST_IP_OFFSET 16 /* dest IP addr offset */
|
||||
#define IPV4_OPTIONS_OFFSET 20 /* IP options offset */
|
||||
|
||||
/* IPV4 field decodes */
|
||||
#define IPV4_VER_MASK 0xf0 /* IPV4 version mask */
|
||||
#define IPV4_VER_SHIFT 4 /* IPV4 version shift */
|
||||
|
||||
#define IPV4_HLEN_MASK 0x0f /* IPV4 header length mask */
|
||||
#define IPV4_HLEN(ipv4_body) (4 * (((uint8 *)(ipv4_body))[IPV4_VER_HL_OFFSET] & IPV4_HLEN_MASK))
|
||||
|
||||
#define IPV4_ADDR_LEN 4 /* IPV4 address length */
|
||||
|
||||
#define IPV4_ADDR_NULL(a) ((((uint8 *)(a))[0] | ((uint8 *)(a))[1] | \
|
||||
((uint8 *)(a))[2] | ((uint8 *)(a))[3]) == 0)
|
||||
|
||||
#define IPV4_ADDR_BCAST(a) ((((uint8 *)(a))[0] & ((uint8 *)(a))[1] & \
|
||||
((uint8 *)(a))[2] & ((uint8 *)(a))[3]) == 0xff)
|
||||
|
||||
#define IPV4_TOS_DSCP_MASK 0xfc /* DiffServ codepoint mask */
|
||||
#define IPV4_TOS_DSCP_SHIFT 2 /* DiffServ codepoint shift */
|
||||
|
||||
#define IPV4_TOS(ipv4_body) (((uint8 *)(ipv4_body))[IPV4_TOS_OFFSET])
|
||||
|
||||
#define IPV4_TOS_PREC_MASK 0xe0 /* Historical precedence mask */
|
||||
#define IPV4_TOS_PREC_SHIFT 5 /* Historical precedence shift */
|
||||
|
||||
#define IPV4_TOS_LOWDELAY 0x10 /* Lowest delay requested */
|
||||
#define IPV4_TOS_THROUGHPUT 0x8 /* Best throughput requested */
|
||||
#define IPV4_TOS_RELIABILITY 0x4 /* Most reliable delivery requested */
|
||||
|
||||
#define IPV4_PROT(ipv4_body) (((uint8 *)(ipv4_body))[IPV4_PROT_OFFSET])
|
||||
|
||||
#define IPV4_FRAG_RESV 0x8000 /* Reserved */
|
||||
#define IPV4_FRAG_DONT 0x4000 /* Don't fragment */
|
||||
#define IPV4_FRAG_MORE 0x2000 /* More fragments */
|
||||
#define IPV4_FRAG_OFFSET_MASK 0x1fff /* Fragment offset */
|
||||
|
||||
#define IPV4_ADDR_STR_LEN 16 /* Max IP address length in string format */
|
||||
|
||||
/* IPv4, no options only. */
|
||||
#define IPV4_NO_OPTIONS_HDR_LEN 20
|
||||
#define IPV4_NO_OPTIONS_PAYLOAD(ip_hdr) (&(((uint8 *)(ip_hdr))[IPV4_NO_OPTIONS_HDR_LEN]))
|
||||
|
||||
#define IPV4_PAYLOAD_LEN(ip_body) \
|
||||
(((int)(((uint8 *)(ip_body))[IPV4_PKTLEN_OFFSET + 0]) << 8) | \
|
||||
((uint8 *)(ip_body))[IPV4_PKTLEN_OFFSET + 1])
|
||||
|
||||
/* IPV4 packet formats */
|
||||
struct ipv4_addr {
|
||||
uint8 addr[IPV4_ADDR_LEN];
|
||||
} PACKED;
|
||||
|
||||
struct ipv4_hdr {
|
||||
uint8 version_ihl; /* Version and Internet Header Length */
|
||||
uint8 tos; /* Type Of Service */
|
||||
uint16 tot_len; /* Number of bytes in packet (max 65535) */
|
||||
uint16 id;
|
||||
uint16 frag; /* 3 flag bits and fragment offset */
|
||||
uint8 ttl; /* Time To Live */
|
||||
uint8 prot; /* Protocol */
|
||||
uint16 hdr_chksum; /* IP header checksum */
|
||||
uint8 src_ip[IPV4_ADDR_LEN]; /* Source IP Address */
|
||||
uint8 dst_ip[IPV4_ADDR_LEN]; /* Destination IP Address */
|
||||
} PACKED;
|
||||
|
||||
/* IPV6 field offsets */
|
||||
#define IPV6_PAYLOAD_LEN_OFFSET 4 /* payload length offset */
|
||||
#define IPV6_NEXT_HDR_OFFSET 6 /* next header/protocol offset */
|
||||
#define IPV6_HOP_LIMIT_OFFSET 7 /* hop limit offset */
|
||||
#define IPV6_SRC_IP_OFFSET 8 /* src IP addr offset */
|
||||
#define IPV6_DEST_IP_OFFSET 24 /* dst IP addr offset */
|
||||
|
||||
/* IPV6 field decodes */
|
||||
#define IPV6_TRAFFIC_CLASS(ipv6_body) \
|
||||
(((((uint8 *)(ipv6_body))[0] & 0x0f) << 4) | \
|
||||
((((uint8 *)(ipv6_body))[1] & 0xf0) >> 4))
|
||||
|
||||
#define IPV6_FLOW_LABEL(ipv6_body) \
|
||||
(((((uint8 *)(ipv6_body))[1] & 0x0f) << 16) | \
|
||||
(((uint8 *)(ipv6_body))[2] << 8) | \
|
||||
(((uint8 *)(ipv6_body))[3]))
|
||||
|
||||
#define IPV6_PAYLOAD_LEN(ipv6_body) \
|
||||
((((uint8 *)(ipv6_body))[IPV6_PAYLOAD_LEN_OFFSET + 0] << 8) | \
|
||||
((uint8 *)(ipv6_body))[IPV6_PAYLOAD_LEN_OFFSET + 1])
|
||||
|
||||
#define IPV6_NEXT_HDR(ipv6_body) \
|
||||
(((uint8 *)(ipv6_body))[IPV6_NEXT_HDR_OFFSET])
|
||||
|
||||
#define IPV6_PROT(ipv6_body) IPV6_NEXT_HDR(ipv6_body)
|
||||
|
||||
#define IPV6_ADDR_LEN 16 /* IPV6 address length */
|
||||
|
||||
/* IPV4 TOS or IPV6 Traffic Classifier or 0 */
|
||||
#define IP_TOS(ip_body) \
|
||||
(IP_VER(ip_body) == IP_VER_4 ? IPV4_TOS(ip_body) : \
|
||||
IP_VER(ip_body) == IP_VER_6 ? IPV6_TRAFFIC_CLASS(ip_body) : 0)
|
||||
|
||||
#undef PACKED
|
||||
#if !defined(__GNUC__)
|
||||
#pragma pack()
|
||||
#endif
|
||||
|
||||
#endif /* _bcmip_h_ */
|
68
package/broadcom-wl/src/driver/proto/bcmtcp.h
Normal file
68
package/broadcom-wl/src/driver/proto/bcmtcp.h
Normal file
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* Fundamental constants relating to TCP Protocol
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _bcmtcp_h_
|
||||
#define _bcmtcp_h_
|
||||
|
||||
/* enable structure packing */
|
||||
#if defined(__GNUC__)
|
||||
#define PACKED __attribute__((packed))
|
||||
#else
|
||||
#pragma pack(1)
|
||||
#define PACKED
|
||||
#endif
|
||||
|
||||
#define TCP_SRC_PORT_OFFSET 0 /* TCP source port offset */
|
||||
#define TCP_DEST_PORT_OFFSET 2 /* TCP dest port offset */
|
||||
#define TCP_CHKSUM_OFFSET 16 /* TCP body checksum offset */
|
||||
|
||||
/* These fields are stored in network order */
|
||||
struct bcmtcp_hdr
|
||||
{
|
||||
uint16 src_port; /* Source Port Address */
|
||||
uint16 dst_port; /* Destination Port Address */
|
||||
uint32 seq_num; /* TCP Sequence Number */
|
||||
uint32 ack_num; /* TCP Sequence Number */
|
||||
uint16 hdrlen_rsvd_flags; /* Header length, reserved bits and flags */
|
||||
uint16 tcpwin; /* TCP window */
|
||||
uint16 chksum; /* Segment checksum with pseudoheader */
|
||||
uint16 urg_ptr; /* Points to seq-num of byte following urg data */
|
||||
} PACKED;
|
||||
|
||||
#undef PACKED
|
||||
#if !defined(__GNUC__)
|
||||
#pragma pack()
|
||||
#endif
|
||||
|
||||
/* Byte offset of flags in TCP header */
|
||||
#define TCP_FLAGS_OFFSET 13
|
||||
|
||||
#define TCP_FLAGS_FIN 0x01
|
||||
#define TCP_FLAGS_SYN 0x02
|
||||
#define TCP_FLAGS_RST 0x03
|
||||
#define TCP_FLAGS_PSH 0x04
|
||||
#define TCP_FLAGS_ACK 0x10
|
||||
#define TCP_FLAGS_URG 0x20
|
||||
#define TCP_FLAGS_ECN 0x40
|
||||
#define TCP_FLAGS_CWR 0x80
|
||||
|
||||
#define TCP_FLAGS(tcp_hdr) (((uint8 *)(tcp_hdr))[TCP_FLAGS_OFFSET])
|
||||
#define TCP_IS_ACK(tcp_hdr) (TCP_FLAGS(tcp_hdr) & TCP_FLAGS_ACK)
|
||||
|
||||
#define TCP_SRC_PORT(tcp_hdr) (ntoh16(((struct bcmtcp_hdr*)(tcp_hdr))->src_port))
|
||||
#define TCP_DST_PORT(tcp_hdr) (ntoh16(((struct bcmtcp_hdr*)(tcp_hdr))->dst_port))
|
||||
#define TCP_SEQ_NUM(tcp_hdr) (ntoh32(((struct bcmtcp_hdr*)(tcp_hdr))->seq_num))
|
||||
#define TCP_ACK_NUM(tcp_hdr) (ntoh32(((struct bcmtcp_hdr*)(tcp_hdr))->ack_num))
|
||||
|
||||
#endif /* #ifndef _bcmtcp_h_ */
|
48
package/broadcom-wl/src/driver/proto/bcmudp.h
Normal file
48
package/broadcom-wl/src/driver/proto/bcmudp.h
Normal file
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
|
||||
* the contents of this file may not be disclosed to third parties, copied
|
||||
* or duplicated in any form, in whole or in part, without the prior
|
||||
* written permission of Broadcom Corporation.
|
||||
*
|
||||
* Fundamental constants relating to UDP Protocol
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _bcmudp_h_
|
||||
#define _bcmudp_h_
|
||||
|
||||
/* enable structure packing */
|
||||
#if defined(__GNUC__)
|
||||
#define PACKED __attribute__((packed))
|
||||
#else
|
||||
#pragma pack(1)
|
||||
#define PACKED
|
||||
#endif
|
||||
|
||||
/* UDP header */
|
||||
#define UDP_DEST_PORT_OFFSET 2 /* UDP dest port offset */
|
||||
#define UDP_LEN_OFFSET 4 /* UDP length offset */
|
||||
#define UDP_CHKSUM_OFFSET 6 /* UDP body checksum offset */
|
||||
|
||||
#define UDP_HDR_LEN 8 /* UDP header length */
|
||||
#define UDP_PORT_LEN 2 /* UDP port length */
|
||||
|
||||
/* These fields are stored in network order */
|
||||
struct bcmudp_hdr
|
||||
{
|
||||
uint16 src_port; /* Source Port Address */
|
||||
uint16 dst_port; /* Destination Port Address */
|
||||
uint16 len; /* Number of bytes in datagram including header */
|
||||
uint16 chksum; /* entire datagram checksum with pseudoheader */
|
||||
} PACKED;
|
||||
|
||||
#undef PACKED
|
||||
#if !defined(__GNUC__)
|
||||
#pragma pack()
|
||||
#endif
|
||||
|
||||
#endif /* #ifndef _bcmudp_h_ */
|
45
package/broadcom-wl/src/driver/proto/eap.h
Normal file
45
package/broadcom-wl/src/driver/proto/eap.h
Normal file
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Extensible Authentication Protocol (EAP) definitions
|
||||
*
|
||||
* See
|
||||
* RFC 2284: PPP Extensible Authentication Protocol (EAP)
|
||||
*
|
||||
* Copyright (C) 2002 Broadcom Corporation
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _eap_h_
|
||||
#define _eap_h_
|
||||
|
||||
/* EAP packet format */
|
||||
typedef struct {
|
||||
unsigned char code; /* EAP code */
|
||||
unsigned char id; /* Current request ID */
|
||||
unsigned short length; /* Length including header */
|
||||
unsigned char type; /* EAP type (optional) */
|
||||
unsigned char data[1]; /* Type data (optional) */
|
||||
} eap_header_t;
|
||||
|
||||
#define EAP_HEADER_LEN 4
|
||||
|
||||
/* EAP codes */
|
||||
#define EAP_REQUEST 1
|
||||
#define EAP_RESPONSE 2
|
||||
#define EAP_SUCCESS 3
|
||||
#define EAP_FAILURE 4
|
||||
|
||||
/* EAP types */
|
||||
#define EAP_IDENTITY 1
|
||||
#define EAP_NOTIFICATION 2
|
||||
#define EAP_NAK 3
|
||||
#define EAP_MD5 4
|
||||
#define EAP_OTP 5
|
||||
#define EAP_GTC 6
|
||||
#define EAP_TLS 13
|
||||
#define EAP_EXPANDED 254
|
||||
#define BCM_EAP_SES 10
|
||||
#define BCM_EAP_EXP_LEN 12 /* EAP_LEN 5 + 3 bytes for SMI ID + 4 bytes for ven type */
|
||||
#define BCM_SMI_ID 0x113d
|
||||
|
||||
#endif /* _eap_h_ */
|
179
package/broadcom-wl/src/driver/proto/eapol.h
Normal file
179
package/broadcom-wl/src/driver/proto/eapol.h
Normal file
|
@ -0,0 +1,179 @@
|
|||
/*
|
||||
* 802.1x EAPOL definitions
|
||||
*
|
||||
* See
|
||||
* IEEE Std 802.1X-2001
|
||||
* IEEE 802.1X RADIUS Usage Guidelines
|
||||
*
|
||||
* Copyright (C) 2002 Broadcom Corporation
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _eapol_h_
|
||||
#define _eapol_h_
|
||||
|
||||
/* enable structure packing */
|
||||
#if defined(__GNUC__)
|
||||
#define PACKED __attribute__((packed))
|
||||
#else
|
||||
#pragma pack(1)
|
||||
#define PACKED
|
||||
#endif
|
||||
|
||||
#include <bcmcrypto/aeskeywrap.h>
|
||||
|
||||
/* EAPOL for 802.3/Ethernet */
|
||||
typedef struct {
|
||||
struct ether_header eth; /* 802.3/Ethernet header */
|
||||
unsigned char version; /* EAPOL protocol version */
|
||||
unsigned char type; /* EAPOL type */
|
||||
unsigned short length; /* Length of body */
|
||||
unsigned char body[1]; /* Body (optional) */
|
||||
} eapol_header_t;
|
||||
|
||||
#define EAPOL_HEADER_LEN 18
|
||||
|
||||
/* EAPOL version */
|
||||
#define WPA2_EAPOL_VERSION 2
|
||||
#define WPA_EAPOL_VERSION 1
|
||||
#define LEAP_EAPOL_VERSION 1
|
||||
#define SES_EAPOL_VERSION 1
|
||||
|
||||
/* EAPOL types */
|
||||
#define EAP_PACKET 0
|
||||
#define EAPOL_START 1
|
||||
#define EAPOL_LOGOFF 2
|
||||
#define EAPOL_KEY 3
|
||||
#define EAPOL_ASF 4
|
||||
|
||||
/* EAPOL-Key types */
|
||||
#define EAPOL_RC4_KEY 1
|
||||
#ifdef BCMWPA2
|
||||
#define EAPOL_WPA2_KEY 2 /* 802.11i/WPA2 */
|
||||
#endif
|
||||
#define EAPOL_WPA_KEY 254 /* WPA */
|
||||
|
||||
/* RC4 EAPOL-Key header field sizes */
|
||||
#define EAPOL_KEY_REPLAY_LEN 8
|
||||
#define EAPOL_KEY_IV_LEN 16
|
||||
#define EAPOL_KEY_SIG_LEN 16
|
||||
|
||||
/* RC4 EAPOL-Key */
|
||||
typedef struct {
|
||||
unsigned char type; /* Key Descriptor Type */
|
||||
unsigned short length; /* Key Length (unaligned) */
|
||||
unsigned char replay[EAPOL_KEY_REPLAY_LEN]; /* Replay Counter */
|
||||
unsigned char iv[EAPOL_KEY_IV_LEN]; /* Key IV */
|
||||
unsigned char index; /* Key Flags & Index */
|
||||
unsigned char signature[EAPOL_KEY_SIG_LEN]; /* Key Signature */
|
||||
unsigned char key[1]; /* Key (optional) */
|
||||
} PACKED eapol_key_header_t;
|
||||
|
||||
#define EAPOL_KEY_HEADER_LEN 44
|
||||
|
||||
/* RC4 EAPOL-Key flags */
|
||||
#define EAPOL_KEY_FLAGS_MASK 0x80
|
||||
#define EAPOL_KEY_BROADCAST 0
|
||||
#define EAPOL_KEY_UNICAST 0x80
|
||||
|
||||
/* RC4 EAPOL-Key index */
|
||||
#define EAPOL_KEY_INDEX_MASK 0x7f
|
||||
|
||||
/* WPA/802.11i/WPA2 EAPOL-Key header field sizes */
|
||||
#define EAPOL_WPA_KEY_REPLAY_LEN 8
|
||||
#define EAPOL_WPA_KEY_NONCE_LEN 32
|
||||
#define EAPOL_WPA_KEY_IV_LEN 16
|
||||
#define EAPOL_WPA_KEY_RSC_LEN 8
|
||||
#define EAPOL_WPA_KEY_ID_LEN 8
|
||||
#define EAPOL_WPA_KEY_MIC_LEN 16
|
||||
#define EAPOL_WPA_KEY_DATA_LEN (EAPOL_WPA_MAX_KEY_SIZE + AKW_BLOCK_LEN)
|
||||
#define EAPOL_WPA_MAX_KEY_SIZE 32
|
||||
|
||||
/* WPA EAPOL-Key */
|
||||
typedef struct {
|
||||
unsigned char type; /* Key Descriptor Type */
|
||||
unsigned short key_info; /* Key Information (unaligned) */
|
||||
unsigned short key_len; /* Key Length (unaligned) */
|
||||
unsigned char replay[EAPOL_WPA_KEY_REPLAY_LEN]; /* Replay Counter */
|
||||
unsigned char nonce[EAPOL_WPA_KEY_NONCE_LEN]; /* Nonce */
|
||||
unsigned char iv[EAPOL_WPA_KEY_IV_LEN]; /* Key IV */
|
||||
unsigned char rsc[EAPOL_WPA_KEY_RSC_LEN]; /* Key RSC */
|
||||
unsigned char id[EAPOL_WPA_KEY_ID_LEN]; /* WPA:Key ID, 802.11i/WPA2: Reserved */
|
||||
unsigned char mic[EAPOL_WPA_KEY_MIC_LEN]; /* Key MIC */
|
||||
unsigned short data_len; /* Key Data Length */
|
||||
unsigned char data[EAPOL_WPA_KEY_DATA_LEN]; /* Key data */
|
||||
} PACKED eapol_wpa_key_header_t;
|
||||
|
||||
#define EAPOL_WPA_KEY_LEN 95
|
||||
|
||||
/* WPA/802.11i/WPA2 KEY KEY_INFO bits */
|
||||
#define WPA_KEY_DESC_V1 0x01
|
||||
#define WPA_KEY_DESC_V2 0x02
|
||||
#define WPA_KEY_PAIRWISE 0x08
|
||||
#define WPA_KEY_INSTALL 0x40
|
||||
#define WPA_KEY_ACK 0x80
|
||||
#define WPA_KEY_MIC 0x100
|
||||
#define WPA_KEY_SECURE 0x200
|
||||
#define WPA_KEY_ERROR 0x400
|
||||
#define WPA_KEY_REQ 0x800
|
||||
|
||||
/* WPA-only KEY KEY_INFO bits */
|
||||
#define WPA_KEY_INDEX_0 0x00
|
||||
#define WPA_KEY_INDEX_1 0x10
|
||||
#define WPA_KEY_INDEX_2 0x20
|
||||
#define WPA_KEY_INDEX_3 0x30
|
||||
#define WPA_KEY_INDEX_MASK 0x30
|
||||
#define WPA_KEY_INDEX_SHIFT 0x04
|
||||
|
||||
#ifdef BCMWPA2
|
||||
/* 802.11i/WPA2-only KEY KEY_INFO bits */
|
||||
#define WPA_KEY_ENCRYPTED_DATA 0x1000
|
||||
|
||||
/* Key Data encapsulation */
|
||||
typedef struct {
|
||||
uint8 type;
|
||||
uint8 length;
|
||||
uint8 oui[3];
|
||||
uint8 subtype;
|
||||
uint8 data[1];
|
||||
} PACKED eapol_wpa2_encap_data_t;
|
||||
|
||||
#define EAPOL_WPA2_ENCAP_DATA_HDR_LEN 6
|
||||
|
||||
#define WPA2_KEY_DATA_SUBTYPE_GTK 1
|
||||
#define WPA2_KEY_DATA_SUBTYPE_STAKEY 2
|
||||
#define WPA2_KEY_DATA_SUBTYPE_MAC 3
|
||||
#define WPA2_KEY_DATA_SUBTYPE_PMKID 4
|
||||
|
||||
/* GTK encapsulation */
|
||||
typedef struct {
|
||||
uint8 flags;
|
||||
uint8 reserved;
|
||||
uint8 gtk[EAPOL_WPA_MAX_KEY_SIZE];
|
||||
} PACKED eapol_wpa2_key_gtk_encap_t;
|
||||
|
||||
#define EAPOL_WPA2_KEY_GTK_ENCAP_HDR_LEN 2
|
||||
|
||||
#define WPA2_GTK_INDEX_MASK 0x03
|
||||
#define WPA2_GTK_INDEX_SHIFT 0x00
|
||||
|
||||
#define WPA2_GTK_TRANSMIT 0x04
|
||||
|
||||
/* STAKey encapsulation */
|
||||
typedef struct {
|
||||
uint8 reserved[2];
|
||||
uint8 mac[ETHER_ADDR_LEN];
|
||||
uint8 stakey[EAPOL_WPA_MAX_KEY_SIZE];
|
||||
} PACKED eapol_wpa2_key_stakey_encap_t;
|
||||
|
||||
#define WPA2_KEY_DATA_PAD 0xdd
|
||||
|
||||
#endif /* BCMWPA2 */
|
||||
|
||||
#undef PACKED
|
||||
#if !defined(__GNUC__)
|
||||
#pragma pack()
|
||||
#endif
|
||||
|
||||
#endif /* _eapol_h_ */
|
175
package/broadcom-wl/src/driver/proto/ethernet.h
Normal file
175
package/broadcom-wl/src/driver/proto/ethernet.h
Normal file
|
@ -0,0 +1,175 @@
|
|||
/*
|
||||
* From FreeBSD 2.2.7: Fundamental constants relating to ethernet.
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _NET_ETHERNET_H_ /* use native BSD ethernet.h when available */
|
||||
#define _NET_ETHERNET_H_
|
||||
|
||||
#ifndef _TYPEDEFS_H_
|
||||
#include "typedefs.h"
|
||||
#endif
|
||||
|
||||
/* enable structure packing */
|
||||
#if defined(__GNUC__)
|
||||
#define PACKED __attribute__((packed))
|
||||
#else
|
||||
#pragma pack(1)
|
||||
#define PACKED
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The number of bytes in an ethernet (MAC) address.
|
||||
*/
|
||||
#define ETHER_ADDR_LEN 6
|
||||
|
||||
/*
|
||||
* The number of bytes in the type field.
|
||||
*/
|
||||
#define ETHER_TYPE_LEN 2
|
||||
|
||||
/*
|
||||
* The number of bytes in the trailing CRC field.
|
||||
*/
|
||||
#define ETHER_CRC_LEN 4
|
||||
|
||||
/*
|
||||
* The length of the combined header.
|
||||
*/
|
||||
#define ETHER_HDR_LEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN)
|
||||
|
||||
/*
|
||||
* The minimum packet length.
|
||||
*/
|
||||
#define ETHER_MIN_LEN 64
|
||||
|
||||
/*
|
||||
* The minimum packet user data length.
|
||||
*/
|
||||
#define ETHER_MIN_DATA 46
|
||||
|
||||
/*
|
||||
* The maximum packet length.
|
||||
*/
|
||||
#define ETHER_MAX_LEN 1518
|
||||
|
||||
/*
|
||||
* The maximum packet user data length.
|
||||
*/
|
||||
#define ETHER_MAX_DATA 1500
|
||||
|
||||
/* ether types */
|
||||
#define ETHER_TYPE_MIN 0x0600 /* Anything less than MIN is a length */
|
||||
#define ETHER_TYPE_IP 0x0800 /* IP */
|
||||
#define ETHER_TYPE_ARP 0x0806 /* ARP */
|
||||
#define ETHER_TYPE_8021Q 0x8100 /* 802.1Q */
|
||||
#define ETHER_TYPE_BRCM 0x886c /* Broadcom Corp. */
|
||||
#define ETHER_TYPE_802_1X 0x888e /* 802.1x */
|
||||
#ifdef BCMWPA2
|
||||
#define ETHER_TYPE_802_1X_PREAUTH 0x88c7 /* 802.1x preauthentication */
|
||||
#endif
|
||||
|
||||
/* Broadcom subtype follows ethertype; First 2 bytes are reserved; Next 2 are subtype; */
|
||||
#define ETHER_BRCM_SUBTYPE_LEN 4 /* Broadcom 4 byte subtype */
|
||||
#define ETHER_BRCM_CRAM 0x1 /* Broadcom subtype cram protocol */
|
||||
|
||||
/* ether header */
|
||||
#define ETHER_DEST_OFFSET (0 * ETHER_ADDR_LEN) /* dest address offset */
|
||||
#define ETHER_SRC_OFFSET (1 * ETHER_ADDR_LEN) /* src address offset */
|
||||
#define ETHER_TYPE_OFFSET (2 * ETHER_ADDR_LEN) /* ether type offset */
|
||||
|
||||
/*
|
||||
* A macro to validate a length with
|
||||
*/
|
||||
#define ETHER_IS_VALID_LEN(foo) \
|
||||
((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
|
||||
|
||||
|
||||
#ifndef __INCif_etherh /* Quick and ugly hack for VxWorks */
|
||||
/*
|
||||
* Structure of a 10Mb/s Ethernet header.
|
||||
*/
|
||||
struct ether_header {
|
||||
uint8 ether_dhost[ETHER_ADDR_LEN];
|
||||
uint8 ether_shost[ETHER_ADDR_LEN];
|
||||
uint16 ether_type;
|
||||
} PACKED;
|
||||
|
||||
/*
|
||||
* Structure of a 48-bit Ethernet address.
|
||||
*/
|
||||
#ifndef NOETHREQ /* Quick and ugly hack for VxWorks */
|
||||
struct ether_addr {
|
||||
uint8 octet[ETHER_ADDR_LEN];
|
||||
} PACKED;
|
||||
#endif
|
||||
#endif /* !__INCif_etherh Quick and ugly hack for VxWorks */
|
||||
|
||||
/*
|
||||
* Takes a pointer, set, test, clear, toggle locally admininistered
|
||||
* address bit in the 48-bit Ethernet address.
|
||||
*/
|
||||
#define ETHER_SET_LOCALADDR(ea) (((uint8 *)(ea))[0] = (((uint8 *)(ea))[0] | 2))
|
||||
#define ETHER_IS_LOCALADDR(ea) (((uint8 *)(ea))[0] & 2)
|
||||
#define ETHER_CLR_LOCALADDR(ea) (((uint8 *)(ea))[0] = (((uint8 *)(ea))[0] & 0xd))
|
||||
#define ETHER_TOGGLE_LOCALADDR(ea) (((uint8 *)(ea))[0] = (((uint8 *)(ea))[0] ^ 2))
|
||||
|
||||
/* Takes a pointer, marks unicast address bit in the MAC address */
|
||||
#define ETHER_SET_UNICAST(ea) (((uint8 *)(ea))[0] = (((uint8 *)(ea))[0] & ~1))
|
||||
|
||||
/*
|
||||
* Takes a pointer, returns true if a 48-bit multicast address
|
||||
* (including broadcast, since it is all ones)
|
||||
*/
|
||||
#define ETHER_ISMULTI(ea) (((const uint8 *)(ea))[0] & 1)
|
||||
|
||||
|
||||
/* compare two ethernet addresses - assumes the pointers can be referenced as shorts */
|
||||
#define ether_cmp(a, b) (!(((short*)a)[0] == ((short*)b)[0]) | \
|
||||
!(((short*)a)[1] == ((short*)b)[1]) | \
|
||||
!(((short*)a)[2] == ((short*)b)[2]))
|
||||
|
||||
/* copy an ethernet address - assumes the pointers can be referenced as shorts */
|
||||
#define ether_copy(s, d) { \
|
||||
((short*)d)[0] = ((short*)s)[0]; \
|
||||
((short*)d)[1] = ((short*)s)[1]; \
|
||||
((short*)d)[2] = ((short*)s)[2]; }
|
||||
|
||||
/*
|
||||
* Takes a pointer, returns true if a 48-bit broadcast (all ones)
|
||||
*/
|
||||
#define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \
|
||||
((uint8 *)(ea))[1] & \
|
||||
((uint8 *)(ea))[2] & \
|
||||
((uint8 *)(ea))[3] & \
|
||||
((uint8 *)(ea))[4] & \
|
||||
((uint8 *)(ea))[5]) == 0xff)
|
||||
|
||||
static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}};
|
||||
static const struct ether_addr ether_null = {{0, 0, 0, 0, 0, 0}};
|
||||
|
||||
/*
|
||||
* Takes a pointer, returns true if a 48-bit null address (all zeros)
|
||||
*/
|
||||
#define ETHER_ISNULLADDR(ea) ((((uint8 *)(ea))[0] | \
|
||||
((uint8 *)(ea))[1] | \
|
||||
((uint8 *)(ea))[2] | \
|
||||
((uint8 *)(ea))[3] | \
|
||||
((uint8 *)(ea))[4] | \
|
||||
((uint8 *)(ea))[5]) == 0)
|
||||
|
||||
#undef PACKED
|
||||
#if !defined(__GNUC__)
|
||||
#pragma pack()
|
||||
#endif
|
||||
|
||||
#endif /* _NET_ETHERNET_H_ */
|
52
package/broadcom-wl/src/driver/proto/vlan.h
Normal file
52
package/broadcom-wl/src/driver/proto/vlan.h
Normal file
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* 802.1Q VLAN protocol definitions
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _vlan_h_
|
||||
#define _vlan_h_
|
||||
|
||||
/* enable structure packing */
|
||||
#if defined(__GNUC__)
|
||||
#define PACKED __attribute__((packed))
|
||||
#else
|
||||
#pragma pack(1)
|
||||
#define PACKED
|
||||
#endif
|
||||
|
||||
#define VLAN_VID_MASK 0xfff /* low 12 bits are vlan id */
|
||||
#define VLAN_CFI_SHIFT 12 /* canonical format indicator bit */
|
||||
#define VLAN_PRI_SHIFT 13 /* user priority */
|
||||
|
||||
#define VLAN_PRI_MASK 7 /* 3 bits of priority */
|
||||
|
||||
#define VLAN_TAG_LEN 4
|
||||
#define VLAN_TAG_OFFSET (2 * ETHER_ADDR_LEN) /* offset in Ethernet II packet only */
|
||||
|
||||
#define VLAN_TPID 0x8100 /* VLAN ethertype/Tag Protocol ID */
|
||||
|
||||
struct ethervlan_header {
|
||||
uint8 ether_dhost[ETHER_ADDR_LEN];
|
||||
uint8 ether_shost[ETHER_ADDR_LEN];
|
||||
uint16 vlan_type; /* 0x8100 */
|
||||
uint16 vlan_tag; /* priority, cfi and vid */
|
||||
uint16 ether_type;
|
||||
};
|
||||
|
||||
#define ETHERVLAN_HDR_LEN (ETHER_HDR_LEN + VLAN_TAG_LEN)
|
||||
|
||||
#undef PACKED
|
||||
#if !defined(__GNUC__)
|
||||
#pragma pack()
|
||||
#endif
|
||||
|
||||
#endif /* _vlan_h_ */
|
158
package/broadcom-wl/src/driver/proto/wpa.h
Normal file
158
package/broadcom-wl/src/driver/proto/wpa.h
Normal file
|
@ -0,0 +1,158 @@
|
|||
/*
|
||||
* Fundamental types and constants relating to WPA
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _proto_wpa_h_
|
||||
#define _proto_wpa_h_
|
||||
|
||||
#include <typedefs.h>
|
||||
#include <proto/ethernet.h>
|
||||
|
||||
/* enable structure packing */
|
||||
#if defined(__GNUC__)
|
||||
#define PACKED __attribute__((packed))
|
||||
#else
|
||||
#pragma pack(1)
|
||||
#define PACKED
|
||||
#endif
|
||||
|
||||
/* Reason Codes */
|
||||
|
||||
/* 13 through 23 taken from IEEE Std 802.11i-2004 */
|
||||
#define DOT11_RC_INVALID_WPA_IE 13 /* Invalid info. element */
|
||||
#define DOT11_RC_MIC_FAILURE 14 /* Michael failure */
|
||||
#define DOT11_RC_4WH_TIMEOUT 15 /* 4-way handshake timeout */
|
||||
#define DOT11_RC_GTK_UPDATE_TIMEOUT 16 /* Group key update timeout */
|
||||
#define DOT11_RC_WPA_IE_MISMATCH 17 /* WPA IE in 4-way handshake differs from
|
||||
* (re-)assoc. request/probe response
|
||||
*/
|
||||
#define DOT11_RC_INVALID_MC_CIPHER 18 /* Invalid multicast cipher */
|
||||
#define DOT11_RC_INVALID_UC_CIPHER 19 /* Invalid unicast cipher */
|
||||
#define DOT11_RC_INVALID_AKMP 20 /* Invalid authenticated key management protocol */
|
||||
#define DOT11_RC_BAD_WPA_VERSION 21 /* Unsupported WPA version */
|
||||
#define DOT11_RC_INVALID_WPA_CAP 22 /* Invalid WPA IE capabilities */
|
||||
#define DOT11_RC_8021X_AUTH_FAIL 23 /* 802.1X authentication failure */
|
||||
|
||||
#define WPA2_PMKID_LEN 16
|
||||
|
||||
/* WPA IE fixed portion */
|
||||
typedef struct
|
||||
{
|
||||
uint8 tag; /* TAG */
|
||||
uint8 length; /* TAG length */
|
||||
uint8 oui[3]; /* IE OUI */
|
||||
uint8 oui_type; /* OUI type */
|
||||
struct {
|
||||
uint8 low;
|
||||
uint8 high;
|
||||
} PACKED version; /* IE version */
|
||||
} PACKED wpa_ie_fixed_t;
|
||||
#define WPA_IE_OUITYPE_LEN 4
|
||||
#define WPA_IE_FIXED_LEN 8
|
||||
#define WPA_IE_TAG_FIXED_LEN 6
|
||||
|
||||
#ifdef BCMWPA2
|
||||
typedef struct {
|
||||
uint8 tag; /* TAG */
|
||||
uint8 length; /* TAG length */
|
||||
struct {
|
||||
uint8 low;
|
||||
uint8 high;
|
||||
} PACKED version; /* IE version */
|
||||
} PACKED wpa_rsn_ie_fixed_t;
|
||||
#define WPA_RSN_IE_FIXED_LEN 4
|
||||
#define WPA_RSN_IE_TAG_FIXED_LEN 2
|
||||
typedef uint8 wpa_pmkid_t[WPA2_PMKID_LEN];
|
||||
#endif
|
||||
|
||||
/* WPA suite/multicast suite */
|
||||
typedef struct
|
||||
{
|
||||
uint8 oui[3];
|
||||
uint8 type;
|
||||
} PACKED wpa_suite_t, wpa_suite_mcast_t;
|
||||
#define WPA_SUITE_LEN 4
|
||||
|
||||
/* WPA unicast suite list/key management suite list */
|
||||
typedef struct
|
||||
{
|
||||
struct {
|
||||
uint8 low;
|
||||
uint8 high;
|
||||
} PACKED count;
|
||||
wpa_suite_t list[1];
|
||||
} PACKED wpa_suite_ucast_t, wpa_suite_auth_key_mgmt_t;
|
||||
#define WPA_IE_SUITE_COUNT_LEN 2
|
||||
#ifdef BCMWPA2
|
||||
typedef struct
|
||||
{
|
||||
struct {
|
||||
uint8 low;
|
||||
uint8 high;
|
||||
} PACKED count;
|
||||
wpa_pmkid_t list[1];
|
||||
} PACKED wpa_pmkid_list_t;
|
||||
#endif
|
||||
|
||||
/* WPA cipher suites */
|
||||
#define WPA_CIPHER_NONE 0 /* None */
|
||||
#define WPA_CIPHER_WEP_40 1 /* WEP (40-bit) */
|
||||
#define WPA_CIPHER_TKIP 2 /* TKIP: default for WPA */
|
||||
#define WPA_CIPHER_AES_OCB 3 /* AES (OCB) */
|
||||
#define WPA_CIPHER_AES_CCM 4 /* AES (CCM) */
|
||||
#define WPA_CIPHER_WEP_104 5 /* WEP (104-bit) */
|
||||
|
||||
#define IS_WPA_CIPHER(cipher) ((cipher) == WPA_CIPHER_NONE || \
|
||||
(cipher) == WPA_CIPHER_WEP_40 || \
|
||||
(cipher) == WPA_CIPHER_WEP_104 || \
|
||||
(cipher) == WPA_CIPHER_TKIP || \
|
||||
(cipher) == WPA_CIPHER_AES_OCB || \
|
||||
(cipher) == WPA_CIPHER_AES_CCM)
|
||||
|
||||
/* WPA TKIP countermeasures parameters */
|
||||
#define WPA_TKIP_CM_DETECT 60 /* multiple MIC failure window (seconds) */
|
||||
#define WPA_TKIP_CM_BLOCK 60 /* countermeasures active window (seconds) */
|
||||
|
||||
/* RSN IE defines */
|
||||
#define RSN_CAP_LEN 2 /* Length of RSN capabilities field (2 octets) */
|
||||
|
||||
/* RSN Capabilities defined in 802.11i */
|
||||
#define RSN_CAP_PREAUTH 0x0001
|
||||
#define RSN_CAP_NOPAIRWISE 0x0002
|
||||
#define RSN_CAP_PTK_REPLAY_CNTR_MASK 0x000C
|
||||
#define RSN_CAP_PTK_REPLAY_CNTR_SHIFT 2
|
||||
#define RSN_CAP_GTK_REPLAY_CNTR_MASK 0x0030
|
||||
#define RSN_CAP_GTK_REPLAY_CNTR_SHIFT 4
|
||||
#define RSN_CAP_1_REPLAY_CNTR 0
|
||||
#define RSN_CAP_2_REPLAY_CNTRS 1
|
||||
#define RSN_CAP_4_REPLAY_CNTRS 2
|
||||
#define RSN_CAP_16_REPLAY_CNTRS 3
|
||||
|
||||
/* WPA capabilities defined in 802.11i */
|
||||
#define WPA_CAP_4_REPLAY_CNTRS RSN_CAP_4_REPLAY_CNTRS
|
||||
#define WPA_CAP_16_REPLAY_CNTRS RSN_CAP_16_REPLAY_CNTRS
|
||||
#define WPA_CAP_REPLAY_CNTR_SHIFT RSN_CAP_PTK_REPLAY_CNTR_SHIFT
|
||||
#define WPA_CAP_REPLAY_CNTR_MASK RSN_CAP_PTK_REPLAY_CNTR_MASK
|
||||
|
||||
/* WPA Specific defines */
|
||||
#define WPA_CAP_LEN RSN_CAP_LEN /* Length of RSN capabilities in RSN IE (2 octets) */
|
||||
|
||||
#define WPA_CAP_WPA2_PREAUTH RSN_CAP_PREAUTH
|
||||
|
||||
|
||||
#undef PACKED
|
||||
#if !defined(__GNUC__)
|
||||
#pragma pack()
|
||||
#endif
|
||||
|
||||
#endif /* _proto_wpa_h_ */
|
|
@ -2,7 +2,7 @@
|
|||
* Generic Broadcom Home Networking Division (HND) DMA engine HW interface
|
||||
* This supports the following chips: BCM42xx, 44xx, 47xx .
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -10,7 +10,7 @@
|
|||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id: sbhnddma.h,v 1.1.1.2 2006/02/27 03:43:16 honor Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _sbhnddma_h_
|
||||
|
|
|
@ -56,7 +56,6 @@
|
|||
|
||||
static char wlbuf[8192];
|
||||
static char interface[16] = "wl0";
|
||||
static unsigned long ptable[128];
|
||||
static unsigned long kmem_offset = 0;
|
||||
static int vif = 0, debug = 1, fromstdin = 0;
|
||||
|
||||
|
@ -98,205 +97,6 @@ static inline int my_ether_ntoa(unsigned char *ea, char *buf)
|
|||
ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]);
|
||||
}
|
||||
|
||||
/*
|
||||
* find the starting point of wl.o in memory
|
||||
* by reading /proc/ksyms
|
||||
*/
|
||||
static inline void wlc_get_mem_offset(void)
|
||||
{
|
||||
FILE *f;
|
||||
char s[64];
|
||||
|
||||
/* yes, i'm lazy ;) */
|
||||
f = popen("grep '\\[wl]' /proc/ksyms | sort", "r");
|
||||
if (fgets(s, 64, f) == 0)
|
||||
return;
|
||||
|
||||
pclose(f);
|
||||
|
||||
s[8] = 0;
|
||||
kmem_offset = strtoul(s, NULL, 16);
|
||||
|
||||
/* sanity check */
|
||||
if (kmem_offset < 0xc0000000)
|
||||
kmem_offset = 0;
|
||||
}
|
||||
|
||||
|
||||
static int ptable_init(void)
|
||||
{
|
||||
glob_t globbuf;
|
||||
struct stat statbuf;
|
||||
int fd;
|
||||
|
||||
if (ptable[0] == PTABLE_MAGIC)
|
||||
return 0;
|
||||
|
||||
glob("/lib/modules/2.4.*/wl.o.patch", 0, NULL, &globbuf);
|
||||
|
||||
if (globbuf.gl_pathv[0] == NULL)
|
||||
return -1;
|
||||
|
||||
if ((fd = open(globbuf.gl_pathv[0], O_RDONLY)) < 0)
|
||||
return -1;
|
||||
|
||||
if (fstat(fd, &statbuf) < 0)
|
||||
goto failed;
|
||||
|
||||
if (statbuf.st_size < 512)
|
||||
goto failed;
|
||||
|
||||
if (read(fd, ptable, 512) < 512)
|
||||
goto failed;
|
||||
|
||||
if (ptable[0] != PTABLE_MAGIC)
|
||||
goto failed;
|
||||
|
||||
close(fd);
|
||||
|
||||
wlc_get_mem_offset();
|
||||
if (kmem_offset == 0)
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
|
||||
failed:
|
||||
close(fd);
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
static inline unsigned long wlc_kmem_read(unsigned long offset)
|
||||
{
|
||||
int fd;
|
||||
unsigned long ret;
|
||||
|
||||
if ((fd = open("/dev/kmem", O_RDONLY )) < 0)
|
||||
return -1;
|
||||
|
||||
lseek(fd, 0x70000000, SEEK_SET);
|
||||
lseek(fd, (kmem_offset - 0x70000000) + offset, SEEK_CUR);
|
||||
read(fd, &ret, 4);
|
||||
close(fd);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline void wlc_kmem_write(unsigned long offset, unsigned long value)
|
||||
{
|
||||
int fd;
|
||||
|
||||
if ((fd = open("/dev/kmem", O_WRONLY )) < 0)
|
||||
return;
|
||||
|
||||
lseek(fd, 0x70000000, SEEK_SET);
|
||||
lseek(fd, (kmem_offset - 0x70000000) + offset, SEEK_CUR);
|
||||
write(fd, &value, 4);
|
||||
close(fd);
|
||||
}
|
||||
|
||||
static int wlc_patcher_getval(unsigned long key, unsigned long *val)
|
||||
{
|
||||
unsigned long *pt = &ptable[1];
|
||||
unsigned long tmp;
|
||||
|
||||
if (ptable_init() < 0) {
|
||||
fprintf(stderr, "Could not load the ptable\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
while (*pt != PTABLE_END) {
|
||||
if (*pt == key) {
|
||||
tmp = wlc_kmem_read(pt[1]);
|
||||
|
||||
if (tmp == pt[2])
|
||||
*val = 0xffffffff;
|
||||
else
|
||||
*val = tmp;
|
||||
|
||||
return 0;
|
||||
}
|
||||
pt += 3;
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int wlc_patcher_setval(unsigned long key, unsigned long val)
|
||||
{
|
||||
unsigned long *pt = &ptable[1];
|
||||
|
||||
if (ptable_init() < 0) {
|
||||
fprintf(stderr, "Could not load the ptable\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (val != 0xffffffff)
|
||||
val = (pt[2] & ~(0xffff)) | (val & 0xffff);
|
||||
|
||||
while (*pt != PTABLE_END) {
|
||||
if (*pt == key) {
|
||||
if (val == 0xffffffff) /* default */
|
||||
val = pt[2];
|
||||
|
||||
wlc_kmem_write(pt[1], val);
|
||||
}
|
||||
pt += 3;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int wlc_slottime(wlc_param param, void *data, void *value)
|
||||
{
|
||||
int *val = (int *) value;
|
||||
int ret = 0;
|
||||
|
||||
if ((param & PARAM_MODE) == SET) {
|
||||
wlc_patcher_setval(PTABLE_SLT1, *val);
|
||||
wlc_patcher_setval(PTABLE_SLT2, ((*val == -1) ? *val : *val + 510));
|
||||
} else if ((param & PARAM_MODE) == GET) {
|
||||
ret = wlc_patcher_getval(PTABLE_SLT1, (unsigned long *) val);
|
||||
if (*val != 0xffffffff)
|
||||
*val &= 0xffff;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int wlc_noack(wlc_param param, void *data, void *value)
|
||||
{
|
||||
int *val = (int *) value;
|
||||
int ret = 0;
|
||||
|
||||
if ((param & PARAM_MODE) == SET) {
|
||||
wlc_patcher_setval(PTABLE_ACKW, ((*val) ? 1 : 0));
|
||||
} else if ((param & PARAM_MODE) == GET) {
|
||||
ret = wlc_patcher_getval(PTABLE_ACKW, (unsigned long *) val);
|
||||
*val &= 0xffff;
|
||||
*val = (*val ? 1 : 0);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int wlc_ibss_merge(wlc_param param, void *data, void *value)
|
||||
{
|
||||
int *val = (int *) value;
|
||||
int ret = 0;
|
||||
|
||||
if ((param & PARAM_MODE) == SET) {
|
||||
/* overwrite the instruction with 'lui v0,0x0' - fake a return
|
||||
* status of 0 for wlc_bcn_tsf_later */
|
||||
wlc_patcher_setval(PTABLE_ACKW, ((*val) ? -1 : 0x3c020000));
|
||||
} else if ((param & PARAM_MODE) == GET) {
|
||||
ret = wlc_patcher_getval(PTABLE_ACKW, (unsigned long *) val);
|
||||
*val = ((*val == -1) ? 1 : 0);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int wlc_ioctl(wlc_param param, void *data, void *value)
|
||||
{
|
||||
unsigned int *var = ((unsigned int *) data);
|
||||
|
@ -956,6 +756,13 @@ static const struct wlc_call wlc_calls[] = {
|
|||
.data.str = "rtsthresh",
|
||||
.desc = "RTS threshold"
|
||||
},
|
||||
{
|
||||
.name = "slottime",
|
||||
.param = INT,
|
||||
.handler = wlc_iovar,
|
||||
.data.str = "acktiming",
|
||||
.desc = "Slot time"
|
||||
},
|
||||
{
|
||||
.name = "rxant",
|
||||
.param = INT,
|
||||
|
@ -1052,24 +859,6 @@ static const struct wlc_call wlc_calls[] = {
|
|||
.handler = wlc_afterburner,
|
||||
.desc = "Broadcom Afterburner"
|
||||
},
|
||||
{
|
||||
.name = "slottime",
|
||||
.param = INT,
|
||||
.handler = wlc_slottime,
|
||||
.desc = "Slot time (-1 = auto)"
|
||||
},
|
||||
{
|
||||
.name = "txack",
|
||||
.param = INT,
|
||||
.handler = wlc_noack,
|
||||
.desc = "Tx ACK enabled flag"
|
||||
},
|
||||
{
|
||||
.name = "ibss_merge",
|
||||
.param = INT,
|
||||
.handler = wlc_ibss_merge,
|
||||
.desc = "Allow IBSS merge in Ad-Hoc mode"
|
||||
}
|
||||
};
|
||||
#define wlc_calls_size (sizeof(wlc_calls) / sizeof(struct wlc_call))
|
||||
|
||||
|
|
|
@ -15,6 +15,9 @@ ifneq ($(DEBUG),)
|
|||
EXTRA_CFLAGS += -DDEBUG=1
|
||||
_D=-debug
|
||||
endif
|
||||
ifneq ($(WL_WEXT),)
|
||||
EXTRA_CFLAGS += -DWL_WEXT=1
|
||||
endif
|
||||
|
||||
obj-m := wlcompat$(_D).o
|
||||
modules: wlcompat$(_D).o
|
||||
|
|
|
@ -30,6 +30,7 @@
|
|||
#include <linux/wireless.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/random.h>
|
||||
#include <net/iw_handler.h>
|
||||
#include <asm/uaccess.h>
|
||||
|
||||
|
@ -37,14 +38,15 @@
|
|||
#include <bcmutils.h>
|
||||
#include <wlioctl.h>
|
||||
|
||||
char buf[WLC_IOCTL_MAXLEN];
|
||||
static struct net_device *dev;
|
||||
static struct iw_statistics wstats;
|
||||
#ifndef DEBUG
|
||||
static int random = 1;
|
||||
#endif
|
||||
#ifndef WL_WEXT
|
||||
static struct iw_statistics wstats;
|
||||
static int last_mode = -1;
|
||||
static int scan_cur = 0;
|
||||
char buf[WLC_IOCTL_MAXLEN];
|
||||
|
||||
/* The frequency of each channel in MHz */
|
||||
const long channel_frequency[] = {
|
||||
|
@ -52,6 +54,7 @@ const long channel_frequency[] = {
|
|||
2447, 2452, 2457, 2462, 2467, 2472, 2484
|
||||
};
|
||||
#define NUM_CHANNELS ( sizeof(channel_frequency) / sizeof(channel_frequency[0]) )
|
||||
#endif
|
||||
|
||||
#define SCAN_RETRY_MAX 5
|
||||
#define RNG_POLL_FREQ 1
|
||||
|
@ -88,6 +91,7 @@ static int wl_ioctl(struct net_device *dev, int cmd, void *buf, int len)
|
|||
return ret;
|
||||
}
|
||||
|
||||
#if !defined(DEBUG) || !defined(WL_WEXT)
|
||||
static int
|
||||
wl_iovar_getbuf(struct net_device *dev, char *iovar, void *param, int paramlen, void *bufptr, int buflen)
|
||||
{
|
||||
|
@ -268,6 +272,9 @@ wl_bssiovar_get(struct net_device *dev, char *iovar, int bssidx, void *outbuf, i
|
|||
return err;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef WL_WEXT
|
||||
|
||||
int get_primary_key(struct net_device *dev)
|
||||
{
|
||||
|
@ -903,6 +910,7 @@ static const struct iw_handler_def wlcompat_handler_def =
|
|||
.num_standard = sizeof(wlcompat_handler)/sizeof(iw_handler),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef DEBUG
|
||||
void print_buffer(int len, unsigned char *buf) {
|
||||
|
@ -923,8 +931,6 @@ void print_buffer(int len, unsigned char *buf) {
|
|||
static int (*old_ioctl)(struct net_device *dev, struct ifreq *ifr, int cmd);
|
||||
static int new_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) {
|
||||
int ret = 0;
|
||||
struct iwreq *iwr = (struct iwreq *) ifr;
|
||||
struct iw_request_info info;
|
||||
|
||||
#ifdef DEBUG
|
||||
printk("dev: %s ioctl: 0x%04x\n",dev->name,cmd);
|
||||
|
@ -975,23 +981,25 @@ static int __init wlcompat_init()
|
|||
{
|
||||
int found = 0, i;
|
||||
char devname[4] = "wl0";
|
||||
|
||||
|
||||
while (!found && (dev = dev_get_by_name(devname))) {
|
||||
if ((dev->wireless_handlers == NULL) && ((wl_ioctl(dev, WLC_GET_MAGIC, &i, sizeof(i)) == 0) && i == WLC_IOCTL_MAGIC))
|
||||
if ((wl_ioctl(dev, WLC_GET_MAGIC, &i, sizeof(i)) == 0) && (i == WLC_IOCTL_MAGIC))
|
||||
found = 1;
|
||||
devname[2]++;
|
||||
}
|
||||
|
||||
|
||||
|
||||
if (!found) {
|
||||
printk("No Broadcom devices found.\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
|
||||
old_ioctl = dev->do_ioctl;
|
||||
dev->do_ioctl = new_ioctl;
|
||||
#ifndef WL_WEXT
|
||||
dev->wireless_handlers = (struct iw_handler_def *)&wlcompat_handler_def;
|
||||
dev->get_wireless_stats = wlcompat_get_wireless_stats;
|
||||
#endif
|
||||
|
||||
#ifndef DEBUG
|
||||
if (random) {
|
||||
|
@ -1014,8 +1022,10 @@ static void __exit wlcompat_exit()
|
|||
if (random)
|
||||
del_timer(&rng_timer);
|
||||
#endif
|
||||
#ifndef WL_WEXT
|
||||
dev->get_wireless_stats = NULL;
|
||||
dev->wireless_handlers = NULL;
|
||||
#endif
|
||||
dev->do_ioctl = old_ioctl;
|
||||
return;
|
||||
}
|
||||
|
|
|
@ -100,6 +100,25 @@ CONFIG_BLUEZ_RFCOMM=m
|
|||
CONFIG_BLUEZ_RFCOMM_TTY=y
|
||||
CONFIG_BLUEZ_SCO=m
|
||||
# CONFIG_BPQETHER is not set
|
||||
# CONFIG_BRIDGE_EBT_802_3 is not set
|
||||
# CONFIG_BRIDGE_EBT_AMONG is not set
|
||||
# CONFIG_BRIDGE_EBT_ARPF is not set
|
||||
# CONFIG_BRIDGE_EBT_ARPREPLY is not set
|
||||
# CONFIG_BRIDGE_EBT_BROUTE is not set
|
||||
# CONFIG_BRIDGE_EBT_DNAT is not set
|
||||
# CONFIG_BRIDGE_EBT_IPF is not set
|
||||
# CONFIG_BRIDGE_EBT_LIMIT is not set
|
||||
# CONFIG_BRIDGE_EBT_LOG is not set
|
||||
# CONFIG_BRIDGE_EBT_MARKF is not set
|
||||
# CONFIG_BRIDGE_EBT_MARK_T is not set
|
||||
# CONFIG_BRIDGE_EBT_PKTTYPE is not set
|
||||
# CONFIG_BRIDGE_EBT_REDIRECT is not set
|
||||
# CONFIG_BRIDGE_EBT_SNAT is not set
|
||||
# CONFIG_BRIDGE_EBT_STP is not set
|
||||
# CONFIG_BRIDGE_EBT_T_FILTER is not set
|
||||
# CONFIG_BRIDGE_EBT_T_NAT is not set
|
||||
# CONFIG_BRIDGE_EBT_VLANF is not set
|
||||
# CONFIG_BRIDGE_NF_EBTABLES is not set
|
||||
CONFIG_CARDBUS=y
|
||||
CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 init=/etc/preinit noinitrd console=ttyS0,115200"
|
||||
# CONFIG_CMDLINE_BOOL is not set
|
||||
|
@ -146,6 +165,7 @@ CONFIG_IDEDMA_PCI_AUTO=y
|
|||
# CONFIG_IDE_TASK_IOCTL is not set
|
||||
# CONFIG_IEEE1394 is not set
|
||||
CONFIG_IP6_NF_MATCH_LIMIT=m
|
||||
# CONFIG_IP_NF_MATCH_PHYSDEV is not set
|
||||
CONFIG_IP_VS=m
|
||||
# CONFIG_IP_VS_DEBUG is not set
|
||||
CONFIG_IP_VS_DH=m
|
||||
|
@ -387,4 +407,3 @@ CONFIG_VIDEO_PROC_FS=y
|
|||
# CONFIG_WDTPCI is not set
|
||||
# CONFIG_WINBOND_840 is not set
|
||||
# CONFIG_YAM is not set
|
||||
CONFIG_USB_BLUETOOTH=n
|
|
@ -9,8 +9,8 @@ O_TARGET := bcm947xx.o
|
|||
|
||||
export-objs := export.o
|
||||
obj-y := prom.o setup.o time.o sbmips.o gpio.o
|
||||
obj-y += nvram.o nvram_linux.o sflash.o
|
||||
obj-y += sbutils.o bcmutils.o bcmsrom.o hndchipc.o
|
||||
obj-y += nvram.o nvram_linux.o cfe_env.o hndpmu.o
|
||||
obj-y += sbutils.o utils.o bcmsrom.o hndchipc.o
|
||||
obj-$(CONFIG_PCI) += sbpci.o pcibios.o
|
||||
obj-y += export.o
|
||||
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -1,247 +0,0 @@
|
|||
/*
|
||||
* Misc useful OS-independent routines.
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
* $Id: bcmutils.c,v 1.1.1.12 2006/02/27 03:43:16 honor Exp $
|
||||
*/
|
||||
|
||||
#include <typedefs.h>
|
||||
#include <bcmdefs.h>
|
||||
#include <stdarg.h>
|
||||
#include <bcmutils.h>
|
||||
#include <osl.h>
|
||||
#include <sbutils.h>
|
||||
#include <bcmnvram.h>
|
||||
#include <bcmendian.h>
|
||||
#include <bcmdevs.h>
|
||||
|
||||
unsigned char bcm_ctype[] = {
|
||||
_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
|
||||
_BCM_C, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C,
|
||||
_BCM_C, /* 8-15 */
|
||||
_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
|
||||
_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
|
||||
_BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
|
||||
_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
|
||||
_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
|
||||
_BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
|
||||
_BCM_P, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X,
|
||||
_BCM_U|_BCM_X, _BCM_U, /* 64-71 */
|
||||
_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
|
||||
_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
|
||||
_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
|
||||
_BCM_P, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X,
|
||||
_BCM_L|_BCM_X, _BCM_L, /* 96-103 */
|
||||
_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
|
||||
_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
|
||||
_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 128-143 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 144-159 */
|
||||
_BCM_S|_BCM_SP, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
|
||||
_BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 160-175 */
|
||||
_BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
|
||||
_BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 176-191 */
|
||||
_BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U,
|
||||
_BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, /* 192-207 */
|
||||
_BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_P, _BCM_U, _BCM_U, _BCM_U,
|
||||
_BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_L, /* 208-223 */
|
||||
_BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L,
|
||||
_BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, /* 224-239 */
|
||||
_BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_P, _BCM_L, _BCM_L, _BCM_L,
|
||||
_BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L /* 240-255 */
|
||||
};
|
||||
|
||||
|
||||
ulong
|
||||
bcm_strtoul(char *cp, char **endp, uint base)
|
||||
{
|
||||
ulong result, value;
|
||||
bool minus;
|
||||
|
||||
minus = FALSE;
|
||||
|
||||
while (bcm_isspace(*cp))
|
||||
cp++;
|
||||
|
||||
if (cp[0] == '+')
|
||||
cp++;
|
||||
else if (cp[0] == '-') {
|
||||
minus = TRUE;
|
||||
cp++;
|
||||
}
|
||||
|
||||
if (base == 0) {
|
||||
if (cp[0] == '0') {
|
||||
if ((cp[1] == 'x') || (cp[1] == 'X')) {
|
||||
base = 16;
|
||||
cp = &cp[2];
|
||||
} else {
|
||||
base = 8;
|
||||
cp = &cp[1];
|
||||
}
|
||||
} else
|
||||
base = 10;
|
||||
} else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
|
||||
cp = &cp[2];
|
||||
}
|
||||
|
||||
result = 0;
|
||||
|
||||
while (bcm_isxdigit(*cp) &&
|
||||
(value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
|
||||
result = result*base + value;
|
||||
cp++;
|
||||
}
|
||||
|
||||
if (minus)
|
||||
result = (ulong)(result * -1);
|
||||
|
||||
if (endp)
|
||||
*endp = (char *)cp;
|
||||
|
||||
return (result);
|
||||
}
|
||||
|
||||
uchar
|
||||
bcm_toupper(uchar c)
|
||||
{
|
||||
if (bcm_islower(c))
|
||||
c -= 'a'-'A';
|
||||
return (c);
|
||||
}
|
||||
|
||||
char*
|
||||
bcm_ether_ntoa(struct ether_addr *ea, char *buf)
|
||||
{
|
||||
sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
|
||||
ea->octet[0]&0xff, ea->octet[1]&0xff, ea->octet[2]&0xff,
|
||||
ea->octet[3]&0xff, ea->octet[4]&0xff, ea->octet[5]&0xff);
|
||||
return (buf);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Search the name=value vars for a specific one and return its value.
|
||||
* Returns NULL if not found.
|
||||
*/
|
||||
char*
|
||||
getvar(char *vars, char *name)
|
||||
{
|
||||
char *s;
|
||||
int len;
|
||||
|
||||
len = strlen(name);
|
||||
|
||||
/* first look in vars[] */
|
||||
for (s = vars; s && *s;) {
|
||||
/* CSTYLED */
|
||||
if ((memcmp(s, name, len) == 0) && (s[len] == '='))
|
||||
return (&s[len+1]);
|
||||
|
||||
while (*s++)
|
||||
;
|
||||
}
|
||||
|
||||
/* then query nvram */
|
||||
return (nvram_get(name));
|
||||
}
|
||||
|
||||
/*
|
||||
* Search the vars for a specific one and return its value as
|
||||
* an integer. Returns 0 if not found.
|
||||
*/
|
||||
int
|
||||
getintvar(char *vars, char *name)
|
||||
{
|
||||
char *val;
|
||||
|
||||
if ((val = getvar(vars, name)) == NULL)
|
||||
return (0);
|
||||
|
||||
return (bcm_strtoul(val, NULL, 0));
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* crc8
|
||||
*
|
||||
* Computes a crc8 over the input data using the polynomial:
|
||||
*
|
||||
* x^8 + x^7 +x^6 + x^4 + x^2 + 1
|
||||
*
|
||||
* The caller provides the initial value (either CRC8_INIT_VALUE
|
||||
* or the previous returned value) to allow for processing of
|
||||
* discontiguous blocks of data. When generating the CRC the
|
||||
* caller is responsible for complementing the final return value
|
||||
* and inserting it into the byte stream. When checking, a final
|
||||
* return value of CRC8_GOOD_VALUE indicates a valid CRC.
|
||||
*
|
||||
* Reference: Dallas Semiconductor Application Note 27
|
||||
* Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
|
||||
* ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
|
||||
* ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
|
||||
*
|
||||
* ****************************************************************************
|
||||
*/
|
||||
|
||||
static uint8 crc8_table[256] = {
|
||||
0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
|
||||
0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
|
||||
0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
|
||||
0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
|
||||
0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
|
||||
0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
|
||||
0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
|
||||
0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
|
||||
0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
|
||||
0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
|
||||
0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
|
||||
0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
|
||||
0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
|
||||
0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
|
||||
0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
|
||||
0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
|
||||
0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
|
||||
0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
|
||||
0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
|
||||
0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
|
||||
0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
|
||||
0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
|
||||
0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
|
||||
0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
|
||||
0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
|
||||
0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
|
||||
0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
|
||||
0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
|
||||
0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
|
||||
0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
|
||||
0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
|
||||
0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
|
||||
};
|
||||
|
||||
#define CRC_INNER_LOOP(n, c, x) \
|
||||
(c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
|
||||
|
||||
uint8
|
||||
hndcrc8(
|
||||
uint8 *pdata, /* pointer to array of data to process */
|
||||
uint nbytes, /* number of input data bytes to process */
|
||||
uint8 crc /* either CRC8_INIT_VALUE or previous return value */
|
||||
)
|
||||
{
|
||||
/* hard code the crc loop instead of using CRC_INNER_LOOP macro
|
||||
* to avoid the undefined and unnecessary (uint8 >> 8) operation.
|
||||
*/
|
||||
while (nbytes-- > 0)
|
||||
crc = crc8_table[(crc ^ *pdata++) & 0xff];
|
||||
|
||||
return crc;
|
||||
}
|
||||
|
||||
|
233
target/linux/brcm-2.4/files/arch/mips/bcm947xx/cfe_env.c
Normal file
233
target/linux/brcm-2.4/files/arch/mips/bcm947xx/cfe_env.c
Normal file
|
@ -0,0 +1,233 @@
|
|||
/*
|
||||
* NVRAM variable manipulation (Linux kernel half)
|
||||
*
|
||||
* Copyright 2001-2003, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/string.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/uaccess.h>
|
||||
|
||||
#include <typedefs.h>
|
||||
#include <osl.h>
|
||||
#include <bcmendian.h>
|
||||
|
||||
#define NVRAM_SIZE (0x1ff0)
|
||||
static char _nvdata[NVRAM_SIZE] __initdata;
|
||||
static char _valuestr[256] __initdata;
|
||||
|
||||
/*
|
||||
* TLV types. These codes are used in the "type-length-value"
|
||||
* encoding of the items stored in the NVRAM device (flash or EEPROM)
|
||||
*
|
||||
* The layout of the flash/nvram is as follows:
|
||||
*
|
||||
* <type> <length> <data ...> <type> <length> <data ...> <type_end>
|
||||
*
|
||||
* The type code of "ENV_TLV_TYPE_END" marks the end of the list.
|
||||
* The "length" field marks the length of the data section, not
|
||||
* including the type and length fields.
|
||||
*
|
||||
* Environment variables are stored as follows:
|
||||
*
|
||||
* <type_env> <length> <flags> <name> = <value>
|
||||
*
|
||||
* If bit 0 (low bit) is set, the length is an 8-bit value.
|
||||
* If bit 0 (low bit) is clear, the length is a 16-bit value
|
||||
*
|
||||
* Bit 7 set indicates "user" TLVs. In this case, bit 0 still
|
||||
* indicates the size of the length field.
|
||||
*
|
||||
* Flags are from the constants below:
|
||||
*
|
||||
*/
|
||||
#define ENV_LENGTH_16BITS 0x00 /* for low bit */
|
||||
#define ENV_LENGTH_8BITS 0x01
|
||||
|
||||
#define ENV_TYPE_USER 0x80
|
||||
|
||||
#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
|
||||
#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
|
||||
|
||||
/*
|
||||
* The actual TLV types we support
|
||||
*/
|
||||
|
||||
#define ENV_TLV_TYPE_END 0x00
|
||||
#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
|
||||
|
||||
/*
|
||||
* Environment variable flags
|
||||
*/
|
||||
|
||||
#define ENV_FLG_NORMAL 0x00 /* normal read/write */
|
||||
#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
|
||||
#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
|
||||
|
||||
#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
|
||||
#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
|
||||
|
||||
|
||||
/* *********************************************************************
|
||||
* _nvram_read(buffer,offset,length)
|
||||
*
|
||||
* Read data from the NVRAM device
|
||||
*
|
||||
* Input parameters:
|
||||
* buffer - destination buffer
|
||||
* offset - offset of data to read
|
||||
* length - number of bytes to read
|
||||
*
|
||||
* Return value:
|
||||
* number of bytes read, or <0 if error occured
|
||||
********************************************************************* */
|
||||
static int
|
||||
_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
|
||||
{
|
||||
int i;
|
||||
if (offset > NVRAM_SIZE)
|
||||
return -1;
|
||||
|
||||
for ( i = 0; i < length; i++) {
|
||||
buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
|
||||
}
|
||||
return length;
|
||||
}
|
||||
|
||||
|
||||
static char*
|
||||
_strnchr(const char *dest,int c,size_t cnt)
|
||||
{
|
||||
while (*dest && (cnt > 0)) {
|
||||
if (*dest == c) return (char *) dest;
|
||||
dest++;
|
||||
cnt--;
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Core support API: Externally visible.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Get the value of an NVRAM variable
|
||||
* @param name name of variable to get
|
||||
* @return value of variable or NULL if undefined
|
||||
*/
|
||||
|
||||
char*
|
||||
cfe_env_get(unsigned char *nv_buf, char* name)
|
||||
{
|
||||
int size;
|
||||
unsigned char *buffer;
|
||||
unsigned char *ptr;
|
||||
unsigned char *envval;
|
||||
unsigned int reclen;
|
||||
unsigned int rectype;
|
||||
int offset;
|
||||
int flg;
|
||||
|
||||
size = NVRAM_SIZE;
|
||||
buffer = &_nvdata[0];
|
||||
|
||||
ptr = buffer;
|
||||
offset = 0;
|
||||
|
||||
/* Read the record type and length */
|
||||
if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
|
||||
goto error;
|
||||
}
|
||||
|
||||
while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
|
||||
|
||||
/* Adjust pointer for TLV type */
|
||||
rectype = *(ptr);
|
||||
offset++;
|
||||
size--;
|
||||
|
||||
/*
|
||||
* Read the length. It can be either 1 or 2 bytes
|
||||
* depending on the code
|
||||
*/
|
||||
if (rectype & ENV_LENGTH_8BITS) {
|
||||
/* Read the record type and length - 8 bits */
|
||||
if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
|
||||
goto error;
|
||||
}
|
||||
reclen = *(ptr);
|
||||
size--;
|
||||
offset++;
|
||||
}
|
||||
else {
|
||||
/* Read the record type and length - 16 bits, MSB first */
|
||||
if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
|
||||
goto error;
|
||||
}
|
||||
reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
|
||||
size -= 2;
|
||||
offset += 2;
|
||||
}
|
||||
|
||||
if (reclen > size)
|
||||
break; /* should not happen, bad NVRAM */
|
||||
|
||||
switch (rectype) {
|
||||
case ENV_TLV_TYPE_ENV:
|
||||
/* Read the TLV data */
|
||||
if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
|
||||
goto error;
|
||||
flg = *ptr++;
|
||||
envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
|
||||
if (envval) {
|
||||
*envval++ = '\0';
|
||||
memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
|
||||
_valuestr[(reclen-1)-(envval-ptr)] = '\0';
|
||||
#if 0
|
||||
printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
|
||||
#endif
|
||||
if(!strcmp(ptr, name)){
|
||||
return _valuestr;
|
||||
}
|
||||
if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
|
||||
return _valuestr;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
/* Unknown TLV type, skip it. */
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* Advance to next TLV
|
||||
*/
|
||||
|
||||
size -= (int)reclen;
|
||||
offset += reclen;
|
||||
|
||||
/* Read the next record type */
|
||||
ptr = buffer;
|
||||
if (_nvram_read(nv_buf, ptr,offset,1) != 1)
|
||||
goto error;
|
||||
}
|
||||
|
||||
error:
|
||||
return NULL;
|
||||
|
||||
}
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
#
|
||||
# Makefile for Broadcom BCM947XX boards
|
||||
#
|
||||
# Copyright 2001-2003, Broadcom Corporation
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
#
|
||||
# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
|
||||
#
|
||||
|
||||
OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
|
||||
SYSTEM ?= $(TOPDIR)/vmlinux
|
||||
|
||||
all: vmlinuz
|
||||
|
||||
# Don't build dependencies, this may die if $(CC) isn't gcc
|
||||
dep:
|
||||
|
||||
# Create a gzipped version named vmlinuz for compatibility
|
||||
vmlinuz: piggy
|
||||
gzip -c9 $< > $@
|
||||
|
||||
piggy: $(SYSTEM)
|
||||
$(OBJCOPY) $(OBJCOPY_ARGS) $< $@
|
||||
|
||||
mrproper: clean
|
||||
|
||||
clean:
|
||||
rm -f vmlinuz piggy
|
|
@ -6,8 +6,10 @@
|
|||
|
||||
_export(bcm947xx_sbh)
|
||||
|
||||
_export(sb_alp_clock)
|
||||
_export(sb_attach)
|
||||
_export(sb_kattach)
|
||||
_export(sb_backplane64)
|
||||
_export(sb_boardtype)
|
||||
_export(sb_boardvendor)
|
||||
_export(sb_btcgpiowar)
|
||||
|
@ -24,6 +26,7 @@ _export(sb_core_disable)
|
|||
_export(sb_core_reset)
|
||||
_export(sb_core_tofixup)
|
||||
_export(sb_coreflags)
|
||||
_export(sb_coreflags_wo)
|
||||
_export(sb_coreflagshi)
|
||||
_export(sb_coreidx)
|
||||
_export(sb_coreregs)
|
||||
|
@ -39,26 +42,30 @@ _export(sb_gpioled)
|
|||
_export(sb_gpioin)
|
||||
_export(sb_gpioout)
|
||||
_export(sb_gpioouten)
|
||||
_export(sb_gpiopull)
|
||||
_export(sb_gpiotimerval)
|
||||
_export(sb_irq)
|
||||
_export(sb_iscoreup)
|
||||
_export(sb_pci_setup)
|
||||
_export(sb_pci_sleep)
|
||||
_export(sb_pci_down)
|
||||
_export(sb_pci_up)
|
||||
_export(sb_pcirev)
|
||||
_export(sb_pcmcia_init)
|
||||
_export(sb_pcmciarev)
|
||||
_export(sb_pmu_paref_ldo_enable)
|
||||
_export(sb_pmu_rcal)
|
||||
_export(sb_pmu_set_ldo_voltage)
|
||||
_export(sb_deregister_intr_callback)
|
||||
_export(sb_register_intr_callback)
|
||||
_export(sb_setcore)
|
||||
_export(sb_setcoreidx)
|
||||
_export(sb_war16165)
|
||||
_export(sb_war32414_forceHT)
|
||||
_export(sb_war42780_clkreq)
|
||||
_export(sb_osh)
|
||||
|
||||
|
||||
_export(getvar)
|
||||
_export(getintvar)
|
||||
_export(bcm_strtoul)
|
||||
_export(bcm_ctype)
|
||||
_export(bcm_toupper)
|
||||
_export(bcm_ether_ntoa)
|
||||
|
||||
_export(nvram_get)
|
||||
_export(nvram_getall)
|
||||
|
|
|
@ -20,7 +20,6 @@
|
|||
|
||||
#include <typedefs.h>
|
||||
#include <osl.h>
|
||||
#include <bcmutils.h>
|
||||
#include <sbutils.h>
|
||||
#include <bcmdevs.h>
|
||||
|
||||
|
@ -122,7 +121,7 @@ gpio_init(void)
|
|||
{
|
||||
int i;
|
||||
|
||||
if (!(gpio_sbh = sb_kattach()))
|
||||
if (!(gpio_sbh = sb_kattach(SB_OSH)))
|
||||
return -ENODEV;
|
||||
|
||||
sb_gpiosetcore(gpio_sbh);
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* BCM47XX support code for some chipcommon (old extif) facilities (uart)
|
||||
* BCM47XX support code for some chipcommon facilities (uart, jtagm)
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -9,28 +9,52 @@
|
|||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id: hndchipc.c,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <typedefs.h>
|
||||
#include <bcmdefs.h>
|
||||
#include <osl.h>
|
||||
#include <bcmutils.h>
|
||||
#include <sbutils.h>
|
||||
#include <bcmdevs.h>
|
||||
#include <bcmnvram.h>
|
||||
#include <sbconfig.h>
|
||||
#include <sbextif.h>
|
||||
#include <sbchipc.h>
|
||||
#include <sbextif.h>
|
||||
#include <hndchipc.h>
|
||||
#include <hndcpu.h>
|
||||
|
||||
/*
|
||||
* Returns TRUE if an external UART exists at the given base
|
||||
* register.
|
||||
/* debug/trace */
|
||||
#define CC_ERROR(args)
|
||||
|
||||
#ifdef BCMDBG
|
||||
#define CC_MSG(args) printf args
|
||||
#else
|
||||
#define CC_MSG(args)
|
||||
#endif /* BCMDBG */
|
||||
|
||||
/* interested chipcommon interrupt source
|
||||
* - GPIO
|
||||
* - EXTIF
|
||||
* - ECI
|
||||
* - PMU
|
||||
* - UART
|
||||
*/
|
||||
static bool
|
||||
BCMINITFN(serial_exists)(osl_t *osh, uint8 *regs)
|
||||
{
|
||||
#define MAX_CC_INT_SOURCE 5
|
||||
|
||||
/* chipc secondary isr info */
|
||||
typedef struct {
|
||||
uint intmask; /* int mask */
|
||||
cc_isr_fn isr; /* secondary isr handler */
|
||||
void *cbdata; /* pointer to private data */
|
||||
} cc_isr_info_t;
|
||||
|
||||
static cc_isr_info_t cc_isr_desc[MAX_CC_INT_SOURCE];
|
||||
|
||||
/* chip common intmask */
|
||||
static uint32 cc_intmask = 0;
|
||||
|
||||
static bool BCMINITFN(serial_exists) (osl_t * osh, uint8 * regs) {
|
||||
uint8 save_mcr, status1;
|
||||
|
||||
save_mcr = R_REG(osh, ®s[UART_MCR]);
|
||||
|
@ -41,118 +65,276 @@ BCMINITFN(serial_exists)(osl_t *osh, uint8 *regs)
|
|||
return (status1 == 0x90);
|
||||
}
|
||||
|
||||
static void __init sb_extif_serial_init(sb_t * sbh, void *regs,
|
||||
sb_serial_init_fn add)
|
||||
{
|
||||
osl_t *osh = sb_osh(sbh);
|
||||
extifregs_t *eir = (extifregs_t *) regs;
|
||||
sbconfig_t *sb;
|
||||
ulong base;
|
||||
uint irq;
|
||||
int i, n;
|
||||
|
||||
/* Determine external UART register base */
|
||||
sb = (sbconfig_t *) ((ulong) eir + SBCONFIGOFF);
|
||||
base = EXTIF_CFGIF_BASE(sb_base(R_REG(osh, &sb->sbadmatch1)));
|
||||
|
||||
/* Determine IRQ */
|
||||
irq = sb_irq(sbh);
|
||||
|
||||
/* Disable GPIO interrupt initially */
|
||||
W_REG(osh, &eir->gpiointpolarity, 0);
|
||||
W_REG(osh, &eir->gpiointmask, 0);
|
||||
|
||||
/* Search for external UARTs */
|
||||
n = 2;
|
||||
for (i = 0; i < 2; i++) {
|
||||
regs = (void *)REG_MAP(base + (i * 8), 8);
|
||||
if (serial_exists(osh, regs)) {
|
||||
/* Set GPIO 1 to be the external UART IRQ */
|
||||
W_REG(osh, &eir->gpiointmask, 2);
|
||||
/* XXXDetermine external UART clock */
|
||||
if (add)
|
||||
add(regs, irq, 13500000, 0);
|
||||
}
|
||||
}
|
||||
|
||||
/* Add internal UART if enabled */
|
||||
if (R_REG(osh, &eir->corecontrol) & CC_UE)
|
||||
if (add)
|
||||
add((void *)&eir->uartdata, irq, sb_clock(sbh), 2);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initializes UART access. The callback function will be called once
|
||||
* per found UART.
|
||||
*/
|
||||
void
|
||||
BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base,
|
||||
uint reg_shift))
|
||||
{
|
||||
void BCMINITFN(sb_serial_init) (sb_t * sbh, sb_serial_init_fn add) {
|
||||
osl_t *osh;
|
||||
void *regs;
|
||||
ulong base;
|
||||
chipcregs_t *cc;
|
||||
uint32 rev, cap, pll, baud_base, div;
|
||||
uint irq;
|
||||
int i, n;
|
||||
|
||||
osh = sb_osh(sbh);
|
||||
|
||||
if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
|
||||
extifregs_t *eir = (extifregs_t *) regs;
|
||||
sbconfig_t *sb;
|
||||
regs = sb_setcore(sbh, SB_EXTIF, 0);
|
||||
if (regs) {
|
||||
sb_extif_serial_init(sbh, regs, add);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Determine external UART register base */
|
||||
sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
|
||||
base = EXTIF_CFGIF_BASE(sb_base(R_REG(osh, &sb->sbadmatch1)));
|
||||
cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0);
|
||||
ASSERT(cc);
|
||||
|
||||
/* Determine IRQ */
|
||||
irq = sb_irq(sbh);
|
||||
/* Determine core revision and capabilities */
|
||||
rev = sbh->ccrev;
|
||||
cap = sbh->cccaps;
|
||||
pll = cap & CC_CAP_PLL_MASK;
|
||||
|
||||
/* Disable GPIO interrupt initially */
|
||||
W_REG(osh, &eir->gpiointpolarity, 0);
|
||||
W_REG(osh, &eir->gpiointmask, 0);
|
||||
/* Determine IRQ */
|
||||
irq = sb_irq(sbh);
|
||||
|
||||
/* Search for external UARTs */
|
||||
n = 2;
|
||||
for (i = 0; i < 2; i++) {
|
||||
regs = (void *) REG_MAP(base + (i * 8), 8);
|
||||
if (serial_exists(osh, regs)) {
|
||||
/* Set GPIO 1 to be the external UART IRQ */
|
||||
W_REG(osh, &eir->gpiointmask, 2);
|
||||
/* XXXDetermine external UART clock */
|
||||
if (add)
|
||||
add(regs, irq, 13500000, 0);
|
||||
}
|
||||
}
|
||||
|
||||
/* Add internal UART if enabled */
|
||||
if (R_REG(osh, &eir->corecontrol) & CC_UE)
|
||||
if (add)
|
||||
add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
|
||||
} else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
|
||||
chipcregs_t *cc = (chipcregs_t *) regs;
|
||||
uint32 rev, cap, pll, baud_base, div;
|
||||
|
||||
/* Determine core revision and capabilities */
|
||||
rev = sb_corerev(sbh);
|
||||
cap = R_REG(osh, &cc->capabilities);
|
||||
pll = cap & CAP_PLL_MASK;
|
||||
|
||||
/* Determine IRQ */
|
||||
irq = sb_irq(sbh);
|
||||
|
||||
if (pll == PLL_TYPE1) {
|
||||
/* PLL clock */
|
||||
baud_base = sb_clock_rate(pll,
|
||||
R_REG(osh, &cc->clockcontrol_n),
|
||||
R_REG(osh, &cc->clockcontrol_m2));
|
||||
div = 1;
|
||||
} else {
|
||||
if (pll == PLL_TYPE1) {
|
||||
/* PLL clock */
|
||||
baud_base = sb_clock_rate(pll,
|
||||
R_REG(osh, &cc->clockcontrol_n),
|
||||
R_REG(osh, &cc->clockcontrol_m2));
|
||||
div = 1;
|
||||
} else {
|
||||
/* 5354 chip common uart uses a constant clock
|
||||
* frequency of 25MHz */
|
||||
if (sb_corerev(sbh) == 20) {
|
||||
/* Set the override bit so we don't divide it */
|
||||
W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
|
||||
baud_base = 25000000;
|
||||
} else if (rev >= 11 && rev != 15) {
|
||||
/* Fixed ALP clock */
|
||||
if (rev >= 11 && rev != 15) {
|
||||
baud_base = 20000000;
|
||||
div = 1;
|
||||
/* Set the override bit so we don't divide it */
|
||||
W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
|
||||
}
|
||||
baud_base = sb_alp_clock(sbh);
|
||||
div = 1;
|
||||
/* Turn off UART clock before switching clock source */
|
||||
if (rev >= 21)
|
||||
AND_REG(osh, &cc->corecontrol, ~CC_UARTCLKEN);
|
||||
/* Set the override bit so we don't divide it */
|
||||
OR_REG(osh, &cc->corecontrol, CC_UARTCLKO);
|
||||
if (rev >= 21)
|
||||
OR_REG(osh, &cc->corecontrol, CC_UARTCLKEN);
|
||||
} else if (rev >= 3) {
|
||||
/* Internal backplane clock */
|
||||
else if (rev >= 3) {
|
||||
baud_base = sb_clock(sbh);
|
||||
div = 2; /* Minimum divisor */
|
||||
W_REG(osh, &cc->clkdiv,
|
||||
((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
|
||||
}
|
||||
baud_base = sb_clock(sbh);
|
||||
div = 2; /* Minimum divisor */
|
||||
W_REG(osh, &cc->clkdiv,
|
||||
((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
|
||||
} else {
|
||||
/* Fixed internal backplane clock */
|
||||
else {
|
||||
baud_base = 88000000;
|
||||
div = 48;
|
||||
}
|
||||
|
||||
/* Clock source depends on strapping if UartClkOverride is unset */
|
||||
if ((rev > 0) &&
|
||||
((R_REG(osh, &cc->corecontrol) & CC_UARTCLKO) == 0)) {
|
||||
if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
|
||||
/* Internal divided backplane clock */
|
||||
baud_base /= div;
|
||||
} else {
|
||||
/* Assume external clock of 1.8432 MHz */
|
||||
baud_base = 1843200;
|
||||
}
|
||||
}
|
||||
baud_base = 88000000;
|
||||
div = 48;
|
||||
}
|
||||
|
||||
/* Add internal UARTs */
|
||||
n = cap & CAP_UARTS_MASK;
|
||||
for (i = 0; i < n; i++) {
|
||||
/* Register offset changed after revision 0 */
|
||||
if (rev)
|
||||
regs = (void *)((ulong) &cc->uart0data + (i * 256));
|
||||
else
|
||||
regs = (void *)((ulong) &cc->uart0data + (i * 8));
|
||||
|
||||
if (add)
|
||||
add(regs, irq, baud_base, 0);
|
||||
/* Clock source depends on strapping if UartClkOverride is unset */
|
||||
if ((rev > 0)
|
||||
&& ((R_REG(osh, &cc->corecontrol) & CC_UARTCLKO) == 0)) {
|
||||
if ((cap & CC_CAP_UCLKSEL) == CC_CAP_UINTCLK) {
|
||||
/* Internal divided backplane clock */
|
||||
baud_base /= div;
|
||||
} else {
|
||||
/* Assume external clock of 1.8432 MHz */
|
||||
baud_base = 1843200;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Add internal UARTs */
|
||||
n = cap & CC_CAP_UARTS_MASK;
|
||||
for (i = 0; i < n; i++) {
|
||||
/* Register offset changed after revision 0 */
|
||||
if (rev)
|
||||
regs = (void *)((ulong) & cc->uart0data + (i * 256));
|
||||
else
|
||||
regs = (void *)((ulong) & cc->uart0data + (i * 8));
|
||||
|
||||
if (add)
|
||||
add(regs, irq, baud_base, 0);
|
||||
}
|
||||
}
|
||||
|
||||
#if 0
|
||||
/*
|
||||
* Initialize jtag master and return handle for
|
||||
* jtag_rwreg. Returns NULL on failure.
|
||||
*/
|
||||
void *sb_jtagm_init(sb_t * sbh, uint clkd, bool exttap)
|
||||
{
|
||||
void *regs;
|
||||
|
||||
if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) {
|
||||
chipcregs_t *cc = (chipcregs_t *) regs;
|
||||
uint32 tmp;
|
||||
|
||||
/*
|
||||
* Determine jtagm availability from
|
||||
* core revision and capabilities.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Corerev 10 has jtagm, but the only chip
|
||||
* with it does not have a mips, and
|
||||
* the layout of the jtagcmd register is
|
||||
* different. We'll only accept >= 11.
|
||||
*/
|
||||
if (sbh->ccrev < 11)
|
||||
return (NULL);
|
||||
|
||||
if ((sbh->cccaps & CC_CAP_JTAGP) == 0)
|
||||
return (NULL);
|
||||
|
||||
/* Set clock divider if requested */
|
||||
if (clkd != 0) {
|
||||
tmp = R_REG(osh, &cc->clkdiv);
|
||||
tmp =
|
||||
(tmp & ~CLKD_JTAG) | ((clkd << CLKD_JTAG_SHIFT) &
|
||||
CLKD_JTAG);
|
||||
W_REG(osh, &cc->clkdiv, tmp);
|
||||
}
|
||||
|
||||
/* Enable jtagm */
|
||||
tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0);
|
||||
W_REG(osh, &cc->jtagctrl, tmp);
|
||||
}
|
||||
|
||||
return (regs);
|
||||
}
|
||||
|
||||
void sb_jtagm_disable(osl_t * osh, void *h)
|
||||
{
|
||||
chipcregs_t *cc = (chipcregs_t *) h;
|
||||
|
||||
W_REG(osh, &cc->jtagctrl, R_REG(osh, &cc->jtagctrl) & ~JCTRL_EN);
|
||||
}
|
||||
|
||||
/*
|
||||
* Read/write a jtag register. Assumes a target with
|
||||
* 8 bit IR and 32 bit DR.
|
||||
*/
|
||||
#define IRWIDTH 8 /* Default Instruction Register width */
|
||||
#define DRWIDTH 32 /* Default Data Register width */
|
||||
|
||||
uint32 jtag_rwreg(osl_t * osh, void *h, uint32 ir, uint32 dr)
|
||||
{
|
||||
chipcregs_t *cc = (chipcregs_t *) h;
|
||||
uint32 tmp;
|
||||
|
||||
W_REG(osh, &cc->jtagir, ir);
|
||||
W_REG(osh, &cc->jtagdr, dr);
|
||||
tmp = JCMD_START | JCMD_ACC_IRDR |
|
||||
((IRWIDTH - 1) << JCMD_IRW_SHIFT) | (DRWIDTH - 1);
|
||||
W_REG(osh, &cc->jtagcmd, tmp);
|
||||
while (((tmp = R_REG(osh, &cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) {
|
||||
/* OSL_DELAY(1); */
|
||||
}
|
||||
|
||||
tmp = R_REG(osh, &cc->jtagdr);
|
||||
return (tmp);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Interface to register chipc secondary isr
|
||||
*/
|
||||
bool
|
||||
BCMINITFN(sb_cc_register_isr) (sb_t * sbh, cc_isr_fn isr, uint32 ccintmask,
|
||||
void *cbdata) {
|
||||
bool done = FALSE;
|
||||
chipcregs_t *regs;
|
||||
uint origidx;
|
||||
uint i;
|
||||
|
||||
/* Save the current core index */
|
||||
origidx = sb_coreidx(sbh);
|
||||
regs = sb_setcore(sbh, SB_CC, 0);
|
||||
ASSERT(regs);
|
||||
|
||||
for (i = 0; i < MAX_CC_INT_SOURCE; i++) {
|
||||
if (cc_isr_desc[i].isr == NULL) {
|
||||
cc_isr_desc[i].isr = isr;
|
||||
cc_isr_desc[i].cbdata = cbdata;
|
||||
cc_isr_desc[i].intmask = ccintmask;
|
||||
done = TRUE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (done) {
|
||||
cc_intmask = R_REG(sb_osh(sbh), ®s->intmask);
|
||||
cc_intmask |= ccintmask;
|
||||
W_REG(sb_osh(sbh), ®s->intmask, cc_intmask);
|
||||
}
|
||||
|
||||
/* restore original coreidx */
|
||||
sb_setcoreidx(sbh, origidx);
|
||||
return done;
|
||||
}
|
||||
|
||||
/*
|
||||
* chipc primary interrupt handler
|
||||
*/
|
||||
void sb_cc_isr(sb_t * sbh, chipcregs_t * regs)
|
||||
{
|
||||
uint32 ccintstatus;
|
||||
uint32 intstatus;
|
||||
uint32 i;
|
||||
|
||||
/* prior to rev 21 chipc interrupt means uart and gpio */
|
||||
if (sbh->ccrev >= 21)
|
||||
ccintstatus = R_REG(sb_osh(sbh), ®s->intstatus) & cc_intmask;
|
||||
else
|
||||
ccintstatus = (CI_UART | CI_GPIO);
|
||||
|
||||
for (i = 0; i < MAX_CC_INT_SOURCE; i++) {
|
||||
if ((cc_isr_desc[i].isr != NULL) &&
|
||||
(intstatus = (cc_isr_desc[i].intmask & ccintstatus))) {
|
||||
(cc_isr_desc[i].isr) (cc_isr_desc[i].cbdata, intstatus);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
1257
target/linux/brcm-2.4/files/arch/mips/bcm947xx/hndpmu.c
Normal file
1257
target/linux/brcm-2.4/files/arch/mips/bcm947xx/hndpmu.c
Normal file
File diff suppressed because it is too large
Load diff
|
@ -101,6 +101,8 @@ extern bool bcmreclaimed;
|
|||
*/
|
||||
#define BCMDONGLEHDRSZ 8
|
||||
|
||||
/* Max. nvram variable table size */
|
||||
#define MAXSZ_NVRAM_VARS 4096
|
||||
|
||||
|
||||
#endif /* _bcmdefs_h_ */
|
||||
|
|
|
@ -1,22 +1,20 @@
|
|||
/*
|
||||
* Broadcom device-specific manifest constants.
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
* $Id: bcmdevs.h,v 1.1.1.17 2006/04/15 01:29:08 michael Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _BCMDEVS_H
|
||||
#define _BCMDEVS_H
|
||||
|
||||
#include "bcm4710.h"
|
||||
|
||||
/* Known PCI vendor Id's */
|
||||
/* PCI vendor IDs */
|
||||
#define VENDOR_EPIGRAM 0xfeda
|
||||
#define VENDOR_BROADCOM 0x14e4
|
||||
#define VENDOR_3COM 0x10b7
|
||||
|
@ -25,24 +23,63 @@
|
|||
#define VENDOR_DELL 0x1028
|
||||
#define VENDOR_HP 0x0e11
|
||||
#define VENDOR_APPLE 0x106b
|
||||
#define VENDOR_SI_IMAGE 0x1095 /* Silicon Image, used by Arasan SDIO Host */
|
||||
#define VENDOR_BUFFALO 0x1154 /* Buffalo vendor id */
|
||||
#define VENDOR_TI 0x104c /* Texas Instruments */
|
||||
|
||||
/* PCI Device Id's */
|
||||
/* PCMCIA vendor IDs */
|
||||
#define VENDOR_BROADCOM_PCMCIA 0x02d0
|
||||
|
||||
/* SDIO vendor IDs */
|
||||
#define VENDOR_BROADCOM_SDIO 0x00BF
|
||||
|
||||
/* PCI Device IDs */
|
||||
#define BCM4210_DEVICE_ID 0x1072 /* never used */
|
||||
#define BCM4211_DEVICE_ID 0x4211
|
||||
#define BCM4230_DEVICE_ID 0x1086 /* never used */
|
||||
#define BCM4231_DEVICE_ID 0x4231
|
||||
|
||||
#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
|
||||
#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
|
||||
#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
|
||||
#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
|
||||
|
||||
#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
|
||||
#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
|
||||
#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
|
||||
|
||||
#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
|
||||
#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
|
||||
|
||||
#define BCM4211_DEVICE_ID 0x4211
|
||||
#define BCM4231_DEVICE_ID 0x4231
|
||||
#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
|
||||
#define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */
|
||||
#define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */
|
||||
#define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */
|
||||
#define BCM4328_D11DUAL_ID 0x4314 /* 4328 802.11a/g id */
|
||||
#define BCM4328_D11G_ID 0x4315 /* 4328 802.11g 2.4Ghz band id */
|
||||
#define BCM4328_D11A_ID 0x4316 /* 4328 802.11a 5Ghz band id */
|
||||
#define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */
|
||||
#define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */
|
||||
#define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */
|
||||
#define BCM4325_D11DUAL_ID 0x431b /* 4325 802.11a/g id */
|
||||
#define BCM4325_D11G_ID 0x431c /* 4325 802.11g 2.4Ghz band id */
|
||||
#define BCM4325_D11A_ID 0x431d /* 4325 802.11a 5Ghz band id */
|
||||
#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
|
||||
#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
|
||||
#define BCM4306_UART_ID 0x4322 /* 4306 uart */
|
||||
#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
|
||||
#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
|
||||
#define BCM4306_D11G_ID2 0x4325
|
||||
#define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */
|
||||
#define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Ghz band id */
|
||||
#define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */
|
||||
#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
|
||||
#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
|
||||
#define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */
|
||||
#define BCM_JTAGM_ID 0x43f1 /* BCM jtagm device id */
|
||||
#define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */
|
||||
#define BCM_SDIOH_ID 0x43f3 /* BCM sdio host id */
|
||||
#define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */
|
||||
#define SPIH_FPGA_ID 0x43f5 /* PCI SPI Host Controller FPGA */
|
||||
#define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */
|
||||
#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
|
||||
#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
|
||||
#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
|
||||
#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
|
||||
#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
|
||||
#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
|
||||
#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
|
||||
#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
|
||||
#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
|
||||
#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
|
||||
#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
|
||||
|
@ -57,114 +94,83 @@
|
|||
#define BCM47XX_ATA100_ID 0x471d /* 47xx parallel ATA */
|
||||
#define BCM47XX_SATAXOR_ID 0x471e /* 47xx serial ATA & XOR DMA */
|
||||
#define BCM47XX_GIGETH_ID 0x471f /* 47xx GbE (5700) */
|
||||
|
||||
#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
|
||||
#define BCM47XX_SMBUS_EMU_ID 0x47fe /* 47xx emulated SMBus device */
|
||||
#define BCM47XX_XOR_EMU_ID 0x47ff /* 47xx emulated XOR engine */
|
||||
#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
|
||||
#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
|
||||
#define JINVANI_SDIOH_ID 0x4743 /* Jinvani SDIO Gold Host */
|
||||
#define BCM27XX_SDIOH_ID 0x2702 /* BCM27xx Standard SDIO Host */
|
||||
#define PCIXX21_FLASHMEDIA_ID 0x803b /* TI PCI xx21 Standard Host Controller */
|
||||
#define PCIXX21_SDIOH_ID 0x803c /* TI PCI xx21 Standard Host Controller */
|
||||
|
||||
/* Chip IDs */
|
||||
#define BCM4710_CHIP_ID 0x4710 /* 4710 chipid returned by sb_chip() */
|
||||
#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
|
||||
|
||||
#define BCM4402_CHIP_ID 0x4402 /* 4402 chipid */
|
||||
#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
|
||||
#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
|
||||
#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
|
||||
|
||||
#define BCM4306_CHIP_ID 0x4306 /* 4306 chipcommon chipid */
|
||||
#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
|
||||
#define BCM4306_D11G_ID2 0x4325
|
||||
#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
|
||||
#define BCM4306_UART_ID 0x4322 /* 4306 uart */
|
||||
#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
|
||||
#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
|
||||
|
||||
#define BCM4309_PKG_ID 1 /* 4309 package id */
|
||||
|
||||
#define BCM4311_CHIP_ID 0x4311 /* 4311 PCIe 802.11a/b/g */
|
||||
#define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */
|
||||
#define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */
|
||||
#define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */
|
||||
|
||||
#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
|
||||
#define BCM4303_PKG_ID 2 /* 4303 package id */
|
||||
|
||||
#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
|
||||
#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
|
||||
|
||||
#define BCM4704_CHIP_ID 0x4704 /* 4704 chipcommon chipid */
|
||||
#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
|
||||
|
||||
#define BCM4312_CHIP_ID 0x4312 /* 4312 chip common chipid */
|
||||
#define BCM4318_CHIP_ID 0x4318 /* 4318 chip common chipid */
|
||||
#define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */
|
||||
#define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */
|
||||
#define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */
|
||||
|
||||
#define BCM4321_CHIP_ID 0x4321 /* 4321 chip common chipid */
|
||||
#define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */
|
||||
#define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Hgz band id */
|
||||
#define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */
|
||||
|
||||
#define BCM4331_CHIP_ID 0x4331 /* 4331 chip common chipid */
|
||||
#define BCM4331_D11N2G_ID 0x4330 /* 4331 802.11n 2.4Ghz band id */
|
||||
#define BCM4331_D11N_ID 0x4331 /* 4331 802.11n dualband id */
|
||||
#define BCM4331_D11N5G_ID 0x4332 /* 4331 802.11n 5Ghz band id */
|
||||
#define BCM4328_CHIP_ID 0x4328 /* 4328 chip common chipid */
|
||||
#define BCM4325_CHIP_ID 0x4325 /* 4325 chip common chipid */
|
||||
#define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */
|
||||
#define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */
|
||||
#define BCM5350_CHIP_ID 0x5350 /* bcm5350 chipcommon chipid */
|
||||
#define BCM5352_CHIP_ID 0x5352 /* bcm5352 chipcommon chipid */
|
||||
#define BCM5354_CHIP_ID 0x5354 /* bcm5354 chipcommon chipid */
|
||||
#define BCM4320_CHIP_ID 0x4320 /* bcm4320 chipcommon chipid */
|
||||
#define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */
|
||||
|
||||
/* Package IDs */
|
||||
#define BCM4303_PKG_ID 2 /* 4303 package id */
|
||||
#define BCM4309_PKG_ID 1 /* 4309 package id */
|
||||
#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
|
||||
#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
|
||||
#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
|
||||
#define BCM4328USBD11G_PKG_ID 2 /* 4328 802.11g USB package id */
|
||||
#define BCM4328USBDUAL_PKG_ID 3 /* 4328 802.11a/g USB package id */
|
||||
#define BCM4328SDIOD11G_PKG_ID 4 /* 4328 802.11g SDIO package id */
|
||||
#define BCM4328SDIODUAL_PKG_ID 5 /* 4328 802.11a/g SDIO package id */
|
||||
#define BCM5354E_PKG_ID 1 /* 5354E package id */
|
||||
#define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */
|
||||
#define HDLSIM_PKG_ID 14 /* HDL simulator package id */
|
||||
#define HWSIM_PKG_ID 15 /* Hardware simulator package id */
|
||||
|
||||
#define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */
|
||||
#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
|
||||
#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
|
||||
#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
|
||||
#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
|
||||
|
||||
#define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */
|
||||
#define BCM5350_CHIP_ID 0x5350 /* bcm5350 chipcommon chipid */
|
||||
#define BCM5352_CHIP_ID 0x5352 /* bcm5352 chipcommon chipid */
|
||||
|
||||
#define BCM4320_CHIP_ID 0x4320 /* bcm4320 chipcommon chipid */
|
||||
|
||||
#define BCM4328_CHIP_ID 0x4328 /* bcm4328 chipcommon chipid */
|
||||
|
||||
#define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */
|
||||
#define BCM43XX_JTAGM_ID 0x43f1 /* 43xx jtagm device id */
|
||||
#define BCM43XXOLD_JTAGM_ID 0x4331 /* 43xx old jtagm device id */
|
||||
|
||||
#define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */
|
||||
#define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */
|
||||
|
||||
#define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */
|
||||
|
||||
#define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */
|
||||
|
||||
/* PCMCIA vendor Id's */
|
||||
|
||||
#define VENDOR_BROADCOM_PCMCIA 0x02d0
|
||||
|
||||
/* SDIO vendor Id's */
|
||||
#define VENDOR_BROADCOM_SDIO 0x00BF
|
||||
|
||||
|
||||
#define PCIXX21_FLASHMEDIA0_ID 0x8033 /* TI PCI xx21 Standard Host Controller */
|
||||
#define PCIXX21_SDIOH0_ID 0x8034 /* TI PCI xx21 Standard Host Controller */
|
||||
/* boardflags */
|
||||
#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
|
||||
#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
|
||||
#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
|
||||
#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
|
||||
#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
|
||||
#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
|
||||
#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
|
||||
#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
|
||||
#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
|
||||
#define BFL_FEM 0x0800 /* This board supports the Front End Module */
|
||||
#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
|
||||
#define BFL_HGPA 0x2000 /* This board has a high gain PA */
|
||||
#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
|
||||
#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
|
||||
|
||||
#define BFL_BTCOEXIST 0x00000001 /* This board implements Bluetooth coexistance */
|
||||
#define BFL_PACTRL 0x00000002 /* This board has gpio 9 controlling the PA */
|
||||
#define BFL_AIRLINEMODE 0x00000004 /* This board implements gpio13 radio disable indication */
|
||||
#define BFL_ADCDIV 0x00000008 /* This board has the rssi ADC divider */
|
||||
#define BFL_ENETROBO 0x00000010 /* This board has robo switch or core */
|
||||
#define BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */
|
||||
#define BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */
|
||||
#define BFL_ENETADM 0x00000080 /* This board has ADMtek switch */
|
||||
#define BFL_ENETVLAN 0x00000100 /* This board has vlan capability */
|
||||
#define BFL_AFTERBURNER 0x00000200 /* This board supports Afterburner mode */
|
||||
#define BFL_NOPCI 0x00000400 /* This board leaves PCI floating */
|
||||
#define BFL_FEM 0x00000800 /* This board supports the Front End Module */
|
||||
#define BFL_EXTLNA 0x00001000 /* This board has an external LNA */
|
||||
#define BFL_HGPA 0x00002000 /* This board has a high gain PA */
|
||||
#define BFL_BTCMOD 0x00004000 /* This board' BTCOEXIST is in the alternate gpios */
|
||||
#define BFL_ALTIQ 0x00008000 /* Alternate I/Q settings */
|
||||
#define BFL_NOPA 0x00010000 /* This board has no PA */
|
||||
#define BFL_RSSIINV 0x00020000 /* This board's RSSI uses positive slope */
|
||||
#define BFL_PAREF 0x00040000 /* This board uses the PARef LDO */
|
||||
#define BFL_3TSWITCH 0x00080000 /* This board uses a triple throw switch shared with BT */
|
||||
#define BFL_PHASESHIFTER 0x00100000 /* This board can support phase shifter */
|
||||
#define BFL_BUCKBOOST 0x00200000 /* This board has buck/booster */
|
||||
/* boardflags2 */
|
||||
#define BFL2_RXBB_INT_REG_DIS 0x00000001 /* This board has an external rxbb regulator */
|
||||
#define BFL2_SSWITCH_AVAIL 0x00000002 /* This board has a superswitch for > 2 antennas */
|
||||
#define BFL2_TXPWRCTRL_EN 0x00000004 /* This board permits TX Power Control to be enabled */
|
||||
#define BFL2_DEPRECIATED_STUB 0x00000002 /* This board flag is depreciated */
|
||||
#define BFL2_TXPWRCTRL_EN 0x00000004 /* This board permits enabling TX Power Control */
|
||||
#define BFL2_2X4_DIV 0x00000008 /* This board supports the 2X4 diversity switch */
|
||||
#define BFL2_5G_PWRGAIN 0x00000010 /* This board supports 5G band power gain */
|
||||
#define BFL2_PCIEWAR_OVR 0x00000020 /* This board overrides ASPM and Clkreq settings */
|
||||
#define BFL2_CAESERS_BRD 0x00000040 /* This board is Dell Caeser's brd (unused by sw) */
|
||||
|
||||
/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
|
||||
#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
|
||||
|
@ -172,6 +178,9 @@
|
|||
#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
|
||||
#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
|
||||
#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
|
||||
#define BOARD_GPIO_ANT0_SEL 0x100 /* With BFL2_2X4_DIV */
|
||||
#define BOARD_GPIO_ANT1_SEL 0x200 /* With BFL2_2X4_DIV */
|
||||
|
||||
#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
|
||||
#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
|
||||
#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
|
||||
|
@ -184,7 +193,6 @@
|
|||
#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
|
||||
|
||||
/* Reference Board Types */
|
||||
|
||||
#define BU4710_BOARD 0x0400
|
||||
#define VSIM4710_BOARD 0x0401
|
||||
#define QT4710_BOARD 0x0402
|
||||
|
@ -259,6 +267,7 @@
|
|||
/* BCM63XX boards */
|
||||
#define BCM96338_BOARD 0x6338
|
||||
#define BCM96348_BOARD 0x6348
|
||||
#define BCM96358_BOARD 0x6358
|
||||
|
||||
/* Another mp4306 with SiGe */
|
||||
#define BCM94306P_BOARD 0x044c
|
||||
|
@ -333,6 +342,18 @@
|
|||
#define CB2_4321_BOARD 0x046d
|
||||
#define MC4321_BOARD 0x046e
|
||||
|
||||
/* 4328 boards */
|
||||
#define BU4328_BOARD 0x0481
|
||||
#define BCM4328SDG_BOARD 0x0482
|
||||
#define BCM4328SDAG_BOARD 0x0483
|
||||
#define BCM4328UG_BOARD 0x0484
|
||||
#define BCM4328UAG_BOARD 0x0485
|
||||
#define BCM4328PC_BOARD 0x0486
|
||||
#define BCM4328CF_BOARD 0x0487
|
||||
|
||||
/* 4325 boards */
|
||||
#define BU4325_BOARD 0x0490
|
||||
|
||||
/* # of GPIO pins */
|
||||
#define GPIO_NUMPINS 16
|
||||
|
||||
|
@ -358,6 +379,10 @@
|
|||
#define BCM2062_IDCODE 0x02062000
|
||||
#define BCM2062A0_IDCODE 0x0206217f
|
||||
|
||||
#define BCM2063_ID 0x2063
|
||||
#define BCM2063_IDCODE 0x02063000
|
||||
#define BCM2063A0_IDCODE 0x0206317f
|
||||
|
||||
/* parts of an idcode: */
|
||||
#define IDCODE_MFG_MASK 0x00000fff
|
||||
#define IDCODE_MFG_SHIFT 0
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* local version of endian.h - byte order defines
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -9,7 +9,7 @@
|
|||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id: bcmendian.h,v 1.1.1.10 2006/02/27 03:43:16 honor Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _BCMENDIAN_H_
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* NVRAM variable manipulation
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -9,7 +9,7 @@
|
|||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id: bcmnvram.h,v 1.17 2006/03/02 12:33:44 honor Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _bcmnvram_h_
|
||||
|
@ -35,10 +35,19 @@ struct nvram_tuple {
|
|||
};
|
||||
|
||||
/*
|
||||
* Initialize NVRAM access. May be unnecessary or undefined on certain
|
||||
* platforms.
|
||||
* Get default value for an NVRAM variable
|
||||
*/
|
||||
extern int nvram_init(void *sbh);
|
||||
extern char *nvram_default_get(const char *name);
|
||||
|
||||
/*
|
||||
* Append a chunk of nvram variables to the global list
|
||||
*/
|
||||
extern int nvram_append(void *sb, char *vars, uint varsz);
|
||||
|
||||
/*
|
||||
* Check for reset button press for restoring factory defaults.
|
||||
*/
|
||||
extern bool nvram_reset(void *sbh);
|
||||
|
||||
/*
|
||||
* Disable NVRAM access. May be unnecessary or undefined on certain
|
||||
|
@ -59,8 +68,6 @@ extern char * nvram_get(const char *name);
|
|||
* as input
|
||||
*/
|
||||
extern int BCMINITFN(nvram_resetgpio_init)(void *sbh);
|
||||
extern int BCMINITFN(nvram_gpio_init)(const char *name, void *sbh);
|
||||
extern int BCMINITFN(nvram_gpio_set)(const char *name, void *sbh, int type);
|
||||
|
||||
/*
|
||||
* Get the value of an NVRAM variable.
|
||||
|
@ -69,16 +76,6 @@ extern int BCMINITFN(nvram_gpio_set)(const char *name, void *sbh, int type);
|
|||
*/
|
||||
#define nvram_safe_get(name) (nvram_get(name) ? : "")
|
||||
|
||||
#define nvram_safe_unset(name) ({ \
|
||||
if(nvram_get(name)) \
|
||||
nvram_unset(name); \
|
||||
})
|
||||
|
||||
#define nvram_safe_set(name, value) ({ \
|
||||
if(!nvram_get(name) || strcmp(nvram_get(name), value)) \
|
||||
nvram_set(name, value); \
|
||||
})
|
||||
|
||||
/*
|
||||
* Match an NVRAM variable.
|
||||
* @param name name of variable to match
|
||||
|
@ -139,15 +136,24 @@ extern int nvram_commit(void);
|
|||
* @param count size of buffer in bytes
|
||||
* @return 0 on success and errno on failure
|
||||
*/
|
||||
extern int nvram_getall(char *buf, int count);
|
||||
extern int nvram_getall(char *nvram_buf, int count);
|
||||
|
||||
extern int file2nvram(char *filename, char *varname);
|
||||
extern int nvram2file(char *varname, char *filename);
|
||||
/*
|
||||
* returns the crc value of the nvram
|
||||
* @param nvh nvram header pointer
|
||||
*/
|
||||
extern uint8 nvram_calc_crc(struct nvram_header * nvh);
|
||||
|
||||
extern char* getvar(char *vars, const char *name);
|
||||
extern int getintvar(char *vars, const char *name);
|
||||
|
||||
#endif /* _LANGUAGE_ASSEMBLY */
|
||||
|
||||
/* The NVRAM version number stored as an NVRAM variable */
|
||||
#define NVRAM_SOFTWARE_VERSION "1"
|
||||
|
||||
#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
|
||||
#define NVRAM_CLEAR_MAGIC 0x0
|
||||
#define NVRAM_CLEAR_MAGIC 0x0
|
||||
#define NVRAM_INVALID_MAGIC 0xFFFFFFFF
|
||||
#define NVRAM_VERSION 1
|
||||
#define NVRAM_HEADER_SIZE 20
|
||||
|
@ -156,4 +162,7 @@ extern int nvram2file(char *varname, char *filename);
|
|||
#define NVRAM_MAX_VALUE_LEN 255
|
||||
#define NVRAM_MAX_PARAM_LEN 64
|
||||
|
||||
#define NVRAM_CRC_START_POSITION 9 /* magic, len, crc8 to be skipped */
|
||||
#define NVRAM_CRC_VER_MASK 0xffffff00 /* for crc_ver_init */
|
||||
|
||||
#endif /* _bcmnvram_h_ */
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Misc useful routines to access NIC local SROM/OTP .
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -9,14 +9,93 @@
|
|||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id: bcmsrom.h,v 1.1.1.13 2006/04/15 01:29:08 michael Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _bcmsrom_h_
|
||||
#define _bcmsrom_h_
|
||||
|
||||
/* Maximum srom: 4 Kilobits == 512 bytes */
|
||||
#define SROM_MAX 512
|
||||
#define SROM_MAX 512
|
||||
|
||||
|
||||
#define SROM_WORDS 64
|
||||
|
||||
#define SROM3_SWRGN_OFF 28 /* s/w region offset in words */
|
||||
|
||||
#define SROM_SSID 2
|
||||
|
||||
#define SROM_WL1LHMAXP 29
|
||||
|
||||
#define SROM_WL1LPAB0 30
|
||||
#define SROM_WL1LPAB1 31
|
||||
#define SROM_WL1LPAB2 32
|
||||
|
||||
#define SROM_WL1HPAB0 33
|
||||
#define SROM_WL1HPAB1 34
|
||||
#define SROM_WL1HPAB2 35
|
||||
|
||||
#define SROM_MACHI_IL0 36
|
||||
#define SROM_MACMID_IL0 37
|
||||
#define SROM_MACLO_IL0 38
|
||||
#define SROM_MACHI_ET0 39
|
||||
#define SROM_MACMID_ET0 40
|
||||
#define SROM_MACLO_ET0 41
|
||||
#define SROM_MACHI_ET1 42
|
||||
#define SROM_MACMID_ET1 43
|
||||
#define SROM_MACLO_ET1 44
|
||||
#define SROM3_MACHI 37
|
||||
#define SROM3_MACMID 38
|
||||
#define SROM3_MACLO 39
|
||||
|
||||
#define SROM_BXARSSI2G 40
|
||||
#define SROM_BXARSSI5G 41
|
||||
|
||||
#define SROM_TRI52G 42
|
||||
#define SROM_TRI5GHL 43
|
||||
|
||||
#define SROM_RXPO52G 45
|
||||
|
||||
#define SROM2_ENETPHY 45
|
||||
|
||||
#define SROM_AABREV 46
|
||||
/* Fields in AABREV */
|
||||
#define SROM_BR_MASK 0x00ff
|
||||
#define SROM_CC_MASK 0x0f00
|
||||
#define SROM_CC_SHIFT 8
|
||||
#define SROM_AA0_MASK 0x3000
|
||||
#define SROM_AA0_SHIFT 12
|
||||
#define SROM_AA1_MASK 0xc000
|
||||
#define SROM_AA1_SHIFT 14
|
||||
|
||||
#define SROM_WL0PAB0 47
|
||||
#define SROM_WL0PAB1 48
|
||||
#define SROM_WL0PAB2 49
|
||||
|
||||
#define SROM_LEDBH10 50
|
||||
#define SROM_LEDBH32 51
|
||||
|
||||
#define SROM_WL10MAXP 52
|
||||
|
||||
#define SROM_WL1PAB0 53
|
||||
#define SROM_WL1PAB1 54
|
||||
#define SROM_WL1PAB2 55
|
||||
|
||||
#define SROM_ITT 56
|
||||
|
||||
#define SROM_BFL 57
|
||||
#define SROM_BFL2 28
|
||||
#define SROM3_BFL2 61
|
||||
|
||||
#define SROM_AG10 58
|
||||
|
||||
#define SROM_CCODE 59
|
||||
|
||||
#define SROM_OPO 60
|
||||
|
||||
#define SROM3_LEDDC 62
|
||||
|
||||
#define SROM_CRCREV 63
|
||||
|
||||
/* SROM Rev 4: Reallocate the software part of the srom to accomodate
|
||||
* MIMO features. It assumes up to two PCIE functions and 440 bytes
|
||||
|
@ -35,18 +114,30 @@
|
|||
#define SROM4_BFL1 35
|
||||
#define SROM4_BFL2 36
|
||||
#define SROM4_BFL3 37
|
||||
#define SROM5_BFL0 37
|
||||
#define SROM5_BFL1 38
|
||||
#define SROM5_BFL2 39
|
||||
#define SROM5_BFL3 40
|
||||
|
||||
#define SROM4_MACHI 38
|
||||
#define SROM4_MACMID 39
|
||||
#define SROM4_MACLO 40
|
||||
#define SROM5_MACHI 41
|
||||
#define SROM5_MACMID 42
|
||||
#define SROM5_MACLO 43
|
||||
|
||||
#define SROM4_CCODE 41
|
||||
#define SROM4_REGREV 42
|
||||
#define SROM5_CCODE 34
|
||||
#define SROM5_REGREV 35
|
||||
|
||||
#define SROM4_LEDBH10 43
|
||||
#define SROM4_LEDBH32 44
|
||||
#define SROM5_LEDBH10 59
|
||||
#define SROM5_LEDBH32 60
|
||||
|
||||
#define SROM4_LEDDC 45
|
||||
#define SROM5_LEDDC 45
|
||||
|
||||
#define SROM4_AA 46
|
||||
#define SROM4_AA2G_MASK 0x00ff
|
||||
|
@ -62,6 +153,14 @@
|
|||
#define SROM4_TXPID5GL 53
|
||||
#define SROM4_TXPID5GH 55
|
||||
|
||||
#define SROM4_TXRXC 61
|
||||
#define SROM4_TXCHAIN_MASK 0x000f
|
||||
#define SROM4_TXCHAIN_SHIFT 0
|
||||
#define SROM4_RXCHAIN_MASK 0x00f0
|
||||
#define SROM4_RXCHAIN_SHIFT 4
|
||||
#define SROM4_SWITCH_MASK 0xff00
|
||||
#define SROM4_SWITCH_SHIFT 8
|
||||
|
||||
/* Per-path fields */
|
||||
#define MAX_PATH 4
|
||||
#define SROM4_PATH0 64
|
||||
|
@ -95,14 +194,117 @@
|
|||
#define SROM4_5G_MCSPO 173
|
||||
#define SROM4_5GL_MCSPO 181
|
||||
#define SROM4_5GH_MCSPO 189
|
||||
#define SROM4_CCDPO 197
|
||||
#define SROM4_CDDPO 197
|
||||
#define SROM4_STBCPO 198
|
||||
#define SROM4_BW40PO 199
|
||||
#define SROM4_BWDUPPO 200
|
||||
|
||||
extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, uint *count);
|
||||
#define SROM4_CRCREV 219
|
||||
|
||||
extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
|
||||
extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
|
||||
|
||||
/*SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6.
|
||||
* This is acombined srom for both MIMO and SISO boards, usable in
|
||||
* the .130 4Kilobit OTP with hardware redundancy.
|
||||
*/
|
||||
|
||||
#define SROM8_SIGN 64
|
||||
|
||||
#define SROM8_BREV 65
|
||||
|
||||
#define SROM8_BFL0 66
|
||||
#define SROM8_BFL1 67
|
||||
#define SROM8_BFL2 68
|
||||
#define SROM8_BFL3 69
|
||||
|
||||
#define SROM8_MACHI 70
|
||||
#define SROM8_MACMID 71
|
||||
#define SROM8_MACLO 72
|
||||
|
||||
#define SROM8_CCODE 73
|
||||
#define SROM8_REGREV 74
|
||||
|
||||
#define SROM8_LEDBH10 75
|
||||
#define SROM8_LEDBH32 76
|
||||
|
||||
#define SROM8_LEDDC 77
|
||||
|
||||
#define SROM8_AA 78
|
||||
|
||||
#define SROM8_AG10 79
|
||||
#define SROM8_AG32 80
|
||||
|
||||
#define SROM8_TXRXC 81
|
||||
|
||||
#define SROM8_BXARSSI2G 82
|
||||
#define SROM8_BXARSSI5G 83
|
||||
#define SROM8_TRI52G 84
|
||||
#define SROM8_TRI5GHL 85
|
||||
#define SROM8_RXPO52G 86
|
||||
|
||||
/* Per-path offsets & fields */
|
||||
#define SROM8_PATH0 96
|
||||
#define SROM8_PATH1 112
|
||||
#define SROM8_PATH2 128
|
||||
#define SROM8_PATH3 144
|
||||
|
||||
#define SROM8_2G_ITT_MAXP 0
|
||||
#define SROM8_2G_PA 1
|
||||
#define SROM8_5G_ITT_MAXP 4
|
||||
#define SROM8_5GLH_MAXP 5
|
||||
#define SROM8_5G_PA 6
|
||||
#define SROM8_5GL_PA 9
|
||||
#define SROM8_5GH_PA 12
|
||||
|
||||
/* All the miriad power offsets */
|
||||
#define SROM8_2G_CCKPO 160
|
||||
|
||||
#define SROM8_2G_OFDMPO 161
|
||||
#define SROM8_5G_OFDMPO 163
|
||||
#define SROM8_5GL_OFDMPO 165
|
||||
#define SROM8_5GH_OFDMPO 167
|
||||
|
||||
#define SROM8_2G_MCSPO 169
|
||||
#define SROM8_5G_MCSPO 177
|
||||
#define SROM8_5GL_MCSPO 185
|
||||
#define SROM8_5GH_MCSPO 193
|
||||
|
||||
#define SROM8_CDDPO 201
|
||||
#define SROM8_STBCPO 202
|
||||
#define SROM8_BW40PO 203
|
||||
#define SROM8_BWDUPPO 204
|
||||
|
||||
/* SISO PA parameters are in the path0 spaces */
|
||||
#define SROM8_SISO 96
|
||||
|
||||
/* Legacy names for SISO PA paramters */
|
||||
#define SROM8_W0_ITTMAXP (SROM8_SISO + SROM8_2G_ITT_MAXP)
|
||||
#define SROM8_W0_PAB0 (SROM8_SISO + SROM8_2G_PA)
|
||||
#define SROM8_W0_PAB1 (SROM8_SISO + SROM8_2G_PA + 1)
|
||||
#define SROM8_W0_PAB2 (SROM8_SISO + SROM8_2G_PA + 2)
|
||||
#define SROM8_W1_ITTMAXP (SROM8_SISO + SROM8_5G_ITT_MAXP)
|
||||
#define SROM8_W1_MAXP_LCHC (SROM8_SISO + SROM8_5GLH_MAXP)
|
||||
#define SROM8_W1_PAB0 (SROM8_SISO + SROM8_5G_PA)
|
||||
#define SROM8_W1_PAB1 (SROM8_SISO + SROM8_5G_PA + 1)
|
||||
#define SROM8_W1_PAB2 (SROM8_SISO + SROM8_5G_PA + 2)
|
||||
#define SROM8_W1_PAB0_LC (SROM8_SISO + SROM8_5GL_PA)
|
||||
#define SROM8_W1_PAB1_LC (SROM8_SISO + SROM8_5GL_PA + 1)
|
||||
#define SROM8_W1_PAB2_LC (SROM8_SISO + SROM8_5GL_PA + 2)
|
||||
#define SROM8_W1_PAB0_HC (SROM8_SISO + SROM8_5GH_PA)
|
||||
#define SROM8_W1_PAB1_HC (SROM8_SISO + SROM8_5GH_PA + 1)
|
||||
#define SROM8_W1_PAB2_HC (SROM8_SISO + SROM8_5GH_PA + 2)
|
||||
|
||||
#define SROM8_CRCREV 219
|
||||
|
||||
/* Prototypes */
|
||||
extern int srom_var_init(sb_t *sbh, uint bus, void *curmap, osl_t *osh,
|
||||
char **vars, uint *count);
|
||||
|
||||
extern int srom_read(sb_t *sbh, uint bus, void *curmap, osl_t *osh,
|
||||
uint byteoff, uint nbytes, uint16 *buf);
|
||||
extern int srom_write(sb_t *sbh, uint bus, void *curmap, osl_t *osh,
|
||||
uint byteoff, uint nbytes, uint16 *buf);
|
||||
|
||||
extern int srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt,
|
||||
char **vars, uint *count);
|
||||
|
||||
#endif /* _bcmsrom_h_ */
|
||||
|
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* HND SiliconBackplane chipcommon support.
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _hndchipc_h_
|
||||
#define _hndchipc_h_
|
||||
|
||||
typedef void (*sb_serial_init_fn)(void *regs, uint irq, uint baud_base, uint reg_shift);
|
||||
|
||||
extern void sb_serial_init(sb_t *sbh, sb_serial_init_fn add);
|
||||
|
||||
extern void *sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap);
|
||||
extern void sb_jtagm_disable(osl_t *osh, void *h);
|
||||
extern uint32 jtag_rwreg(osl_t *osh, void *h, uint32 ir, uint32 dr);
|
||||
|
||||
typedef void (*cc_isr_fn)(void* cbdata, uint32 ccintst);
|
||||
|
||||
extern bool sb_cc_register_isr(sb_t *sbh, cc_isr_fn isr, uint32 ccintmask, void *cbdata);
|
||||
extern void sb_cc_isr(sb_t *sbh, chipcregs_t *regs);
|
||||
|
||||
#endif /* _hndchipc_h_ */
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* HND SiliconBackplane MIPS/ARM cores software interface.
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -9,7 +9,7 @@
|
|||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id: hndcpu.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _hndcpu_h_
|
||||
|
@ -17,12 +17,14 @@
|
|||
|
||||
#if defined(mips)
|
||||
#include <hndmips.h>
|
||||
#elif defined(__ARM_ARCH_4T__)
|
||||
#elif defined(__arm__) || defined(__thumb__) || defined(__thumb2__)
|
||||
#include <hndarm.h>
|
||||
#endif
|
||||
|
||||
extern uint sb_irq(sb_t *sbh);
|
||||
extern uint32 sb_cpu_clock(sb_t *sbh);
|
||||
extern void sb_cpu_wait(void);
|
||||
extern void hnd_cpu_wait(sb_t *sbh);
|
||||
extern void hnd_cpu_jumpto(void *addr);
|
||||
extern void hnd_cpu_reset(sb_t *sbh);
|
||||
|
||||
#endif /* _hndcpu_h_ */
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* HND SiliconBackplane MIPS core software interface.
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -9,7 +9,7 @@
|
|||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id: hndmips.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _hndmips_h_
|
||||
|
@ -22,6 +22,7 @@ extern uint32 sb_memc_get_ncdl(sb_t *sbh);
|
|||
|
||||
#if defined(BCMPERFSTATS)
|
||||
/* enable counting - exclusive version. Only one set of counters allowed at a time */
|
||||
extern void hndmips_perf_cyclecount_enable(void);
|
||||
extern void hndmips_perf_instrcount_enable(void);
|
||||
extern void hndmips_perf_icachecount_enable(void);
|
||||
extern void hndmips_perf_dcachecount_enable(void);
|
||||
|
@ -40,6 +41,6 @@ extern void hndmips_perf_icache_miss_enable(void);
|
|||
extern uint32 hndmips_perf_read_instrcount(void);
|
||||
extern uint32 hndmips_perf_read_cache_miss(void);
|
||||
extern uint32 hndmips_perf_read_cache_hit(void);
|
||||
#endif /* defined(BCMINTERNAL) || defined (BCMPERFSTATS) */
|
||||
#endif
|
||||
|
||||
#endif /* _hndmips_h_ */
|
||||
|
|
|
@ -1,8 +1,8 @@
|
|||
/*
|
||||
* HND SiliconBackplane PCI core software interface.
|
||||
*
|
||||
* $Id: hndpci.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* $Id$
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -25,6 +25,9 @@ extern int extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint of
|
|||
extern void sbpci_ban(uint16 core);
|
||||
extern int sbpci_init(sb_t *sbh);
|
||||
extern int sbpci_init_pci(sb_t *sbh);
|
||||
extern void sbpci_check(sb_t *sbh);
|
||||
extern void sbpci_init_cores(sb_t *sbh);
|
||||
extern void sbpci_arb_park(sb_t *sbh, uint parkid);
|
||||
|
||||
#define PCI_PARK_NVRAM 0xff
|
||||
|
||||
#endif /* _hndpci_h_ */
|
||||
|
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* HND SiliconBackplane PMU support.
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _hndpmu_h_
|
||||
#define _hndpmu_h_
|
||||
|
||||
#define SET_LDO_VOLTAGE_LDO1 1
|
||||
#define SET_LDO_VOLTAGE_LDO2 2
|
||||
#define SET_LDO_VOLTAGE_LDO3 3
|
||||
#define SET_LDO_VOLTAGE_PAREF 4
|
||||
|
||||
extern void sb_pmu_init(sb_t *sbh, osl_t *osh);
|
||||
extern void sb_pmu_pll_init(sb_t *sbh, osl_t *osh, uint32 xtalfreq);
|
||||
extern void sb_pmu_res_init(sb_t *sbh, osl_t *osh);
|
||||
extern uint32 sb_pmu_force_ilp(sb_t *sbh, osl_t *osh, bool force);
|
||||
extern uint32 sb_pmu_cpu_clock(sb_t *sbh, osl_t *osh);
|
||||
extern uint32 sb_pmu_alp_clock(sb_t *sbh, osl_t *osh);
|
||||
|
||||
extern void sb_pmu_set_switcher_voltage(sb_t *sbh, osl_t *osh, uint8 bb_voltage, uint8 rf_voltage);
|
||||
extern void sb_pmu_set_ldo_voltage(sb_t *sbh, osl_t *osh, uint8 ldo, uint8 voltage);
|
||||
extern void sb_pmu_paref_ldo_enable(sb_t *sbh, osl_t *osh, bool enable);
|
||||
extern uint16 sb_pmu_fast_pwrup_delay(sb_t *sbh, osl_t *osh);
|
||||
extern void sb_pmu_otp_power(sb_t *sbh, osl_t *osh, bool on);
|
||||
extern void sb_pmu_rcal(sb_t *sbh, osl_t *osh);
|
||||
|
||||
#endif /* _hndpmu_h_ */
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* Linux Broadcom BCM47xx GPIO char driver
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _linux_gpio_h_
|
||||
#define _linux_gpio_h_
|
||||
|
||||
struct gpio_ioctl {
|
||||
uint32 mask;
|
||||
uint32 val;
|
||||
};
|
||||
|
||||
#define GPIO_IOC_MAGIC 'G'
|
||||
|
||||
/* reserve/release a gpio to the caller */
|
||||
#define GPIO_IOC_RESERVE _IOWR(GPIO_IOC_MAGIC, 1, struct gpio_ioctl)
|
||||
#define GPIO_IOC_RELEASE _IOWR(GPIO_IOC_MAGIC, 2, struct gpio_ioctl)
|
||||
/* ioctls to read/write the gpio registers */
|
||||
#define GPIO_IOC_OUT _IOWR(GPIO_IOC_MAGIC, 3, struct gpio_ioctl)
|
||||
#define GPIO_IOC_IN _IOWR(GPIO_IOC_MAGIC, 4, struct gpio_ioctl)
|
||||
#define GPIO_IOC_OUTEN _IOWR(GPIO_IOC_MAGIC, 5, struct gpio_ioctl)
|
||||
|
||||
#endif /* _linux_gpio_h_ */
|
|
@ -2,7 +2,7 @@
|
|||
* Linux-specific abstractions to gain some independence from linux kernel versions.
|
||||
* Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -10,14 +10,19 @@
|
|||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id: linuxver.h,v 1.1.1.10 2006/02/27 03:43:16 honor Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _linuxver_h_
|
||||
#define _linuxver_h_
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/version.h>
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
|
||||
#include <linux/config.h>
|
||||
#else
|
||||
#include <linux/autoconf.h>
|
||||
#endif
|
||||
#include <linux/module.h>
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0))
|
||||
/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
|
||||
|
@ -28,15 +33,6 @@
|
|||
#endif
|
||||
#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0) */
|
||||
|
||||
#if defined(MODULE) && defined(MODVERSIONS)
|
||||
#include <linux/modversions.h>
|
||||
#endif
|
||||
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 0)
|
||||
#include <linux/moduleparam.h>
|
||||
#endif
|
||||
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)
|
||||
#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
|
||||
#define module_param_string(_name_, _string_, _size_, _perm_) \
|
||||
|
@ -77,6 +73,13 @@
|
|||
#endif
|
||||
#endif /* LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41) */
|
||||
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20)
|
||||
#define MY_INIT_WORK(_work, _func, _data) INIT_WORK(_work, _func)
|
||||
#else
|
||||
#define MY_INIT_WORK(_work, _func, _data) INIT_WORK(_work, _func, _data)
|
||||
typedef void (*work_func_t)(void *work);
|
||||
#endif /* < 2.6.20 */
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
|
||||
/* Some distributions have their own 2.6.x compatibility layers */
|
||||
#ifndef IRQ_NONE
|
||||
|
@ -110,6 +113,12 @@ cs_error(client_handle_t handle, int func, int ret)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 15))
|
||||
|
||||
typedef struct pcmcia_device dev_link_t;
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_PCMCIA */
|
||||
|
||||
#ifndef __exit
|
||||
|
@ -414,4 +423,11 @@ pci_restore_state(struct pci_dev *dev, u32 *buffer)
|
|||
#define af_packet_priv data
|
||||
#endif
|
||||
|
||||
/* suspend args */
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 11)
|
||||
#define DRV_SUSPEND_STATE_TYPE pm_message_t
|
||||
#else
|
||||
#define DRV_SUSPEND_STATE_TYPE uint32
|
||||
#endif
|
||||
|
||||
#endif /* _linuxver_h_ */
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* HND Run Time Environment for standalone MIPS programs.
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -9,7 +9,7 @@
|
|||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id: mipsinc.h,v 1.1.1.5 2006/02/27 03:43:16 honor Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _MISPINC_H
|
||||
|
@ -69,6 +69,7 @@
|
|||
#define C0_CTEXT $4
|
||||
#define C0_PGMASK $5
|
||||
#define C0_WIRED $6
|
||||
#define C0_INFO $7
|
||||
#define C0_BADVADDR $8
|
||||
#define C0_COUNT $9
|
||||
#define C0_TLBHI $10
|
||||
|
@ -145,6 +146,7 @@ symbol: .frame sp, 0, ra
|
|||
#define C0_CTEXT 4 /* CP0: Context */
|
||||
#define C0_PGMASK 5 /* CP0: TLB PageMask */
|
||||
#define C0_WIRED 6 /* CP0: TLB Wired */
|
||||
#define C0_INFO 7 /* CP0: Info */
|
||||
#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
|
||||
#define C0_COUNT 9 /* CP0: Count */
|
||||
#define C0_TLBHI 10 /* CP0: TLB EntryHi */
|
||||
|
|
|
@ -4,26 +4,66 @@
|
|||
#include <linux/delay.h>
|
||||
#include <typedefs.h>
|
||||
#include <linuxver.h>
|
||||
#include <bcmutils.h>
|
||||
#include <pcicfg.h>
|
||||
|
||||
#define ASSERT(n)
|
||||
|
||||
#ifndef ABS
|
||||
#define ABS(a) (((a) < 0)?-(a):(a))
|
||||
#endif /* ABS */
|
||||
|
||||
#ifndef MIN
|
||||
#define MIN(a, b) (((a) < (b))?(a):(b))
|
||||
#endif /* MIN */
|
||||
|
||||
#ifndef MAX
|
||||
#define MAX(a, b) (((a) > (b))?(a):(b))
|
||||
#endif /* MAX */
|
||||
|
||||
#define CEIL(x, y) (((x) + ((y)-1)) / (y))
|
||||
#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
|
||||
#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
|
||||
#define ISPOWEROF2(x) ((((x)-1)&(x)) == 0)
|
||||
#define VALID_MASK(mask) !((mask) & ((mask) + 1))
|
||||
#ifndef OFFSETOF
|
||||
#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
|
||||
#endif /* OFFSETOF */
|
||||
#ifndef ARRAYSIZE
|
||||
#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Spin at most 'us' microseconds while 'exp' is true.
|
||||
* Caller should explicitly test 'exp' when this completes
|
||||
* and take appropriate error action if 'exp' is still true.
|
||||
*/
|
||||
#define SPINWAIT(exp, us) { \
|
||||
uint countdown = (us) + 9; \
|
||||
while ((exp) && (countdown >= 10)) {\
|
||||
OSL_DELAY(10); \
|
||||
countdown -= 10; \
|
||||
} \
|
||||
}
|
||||
|
||||
|
||||
typedef void (*pktfree_cb_fn_t)(void *ctx, void *pkt, unsigned int status);
|
||||
/* Pkttag flag should be part of public information */
|
||||
typedef struct {
|
||||
bool pkttag;
|
||||
uint pktalloced; /* Number of allocated packet buffers */
|
||||
void *tx_fn;
|
||||
void *tx_ctx;
|
||||
uint pktalloced; /* Number of allocated packet buffers */
|
||||
bool mmbus; /* Bus supports memory-mapped register accesses */
|
||||
pktfree_cb_fn_t tx_fn; /* Callback function for PKTFREE */
|
||||
void *tx_ctx; /* Context to the callback function */
|
||||
} osl_pubinfo_t;
|
||||
|
||||
struct osl_info {
|
||||
osl_pubinfo_t pub;
|
||||
uint magic;
|
||||
void *pdev;
|
||||
uint malloced;
|
||||
uint failed;
|
||||
void *dbgmem_list;
|
||||
osl_pubinfo_t pub;
|
||||
uint magic;
|
||||
void *pdev;
|
||||
uint malloced;
|
||||
uint failed;
|
||||
uint bustype;
|
||||
void *dbgmem_list;
|
||||
};
|
||||
|
||||
typedef struct osl_info osl_t;
|
||||
|
@ -101,8 +141,8 @@ typedef struct osl_info osl_t;
|
|||
#define MFREE(osh, addr, size) kfree((addr))
|
||||
#define MALLOCED(osh) (0)
|
||||
|
||||
#define osl_delay OSL_DELAY
|
||||
static inline void OSL_DELAY(uint usec)
|
||||
#define OSL_DELAY _osl_delay
|
||||
static inline void _osl_delay(uint usec)
|
||||
{
|
||||
uint d;
|
||||
|
||||
|
@ -128,10 +168,10 @@ bcm_mdelay(uint ms)
|
|||
#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size)
|
||||
|
||||
#define OSL_PCI_READ_CONFIG(osh, offset, size) \
|
||||
osl_pci_read_config((osh), (offset), (size))
|
||||
_osl_pci_read_config((osh), (offset), (size))
|
||||
|
||||
static inline uint32
|
||||
osl_pci_read_config(osl_t *osh, uint offset, uint size)
|
||||
_osl_pci_read_config(osl_t *osh, uint offset, uint size)
|
||||
{
|
||||
uint val;
|
||||
uint retry = PCI_CFG_RETRY;
|
||||
|
@ -146,9 +186,9 @@ osl_pci_read_config(osl_t *osh, uint offset, uint size)
|
|||
}
|
||||
|
||||
#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
|
||||
osl_pci_write_config((osh), (offset), (size), (val))
|
||||
_osl_pci_write_config((osh), (offset), (size), (val))
|
||||
static inline void
|
||||
osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
|
||||
_osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
|
||||
{
|
||||
uint retry = PCI_CFG_RETRY;
|
||||
|
||||
|
@ -156,24 +196,24 @@ osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
|
|||
pci_write_config_dword(osh->pdev, offset, val);
|
||||
if (offset != PCI_BAR0_WIN)
|
||||
break;
|
||||
if (osl_pci_read_config(osh, offset, size) == val)
|
||||
if (_osl_pci_read_config(osh, offset, size) == val)
|
||||
break;
|
||||
} while (retry--);
|
||||
}
|
||||
|
||||
|
||||
/* return bus # for the pci device pointed by osh->pdev */
|
||||
#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
|
||||
#define OSL_PCI_BUS(osh) _osl_pci_bus(osh)
|
||||
static inline uint
|
||||
osl_pci_bus(osl_t *osh)
|
||||
_osl_pci_bus(osl_t *osh)
|
||||
{
|
||||
return ((struct pci_dev *)osh->pdev)->bus->number;
|
||||
}
|
||||
|
||||
/* return slot # for the pci device pointed by osh->pdev */
|
||||
#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
|
||||
#define OSL_PCI_SLOT(osh) _osl_pci_slot(osh)
|
||||
static inline uint
|
||||
osl_pci_slot(osl_t *osh)
|
||||
_osl_pci_slot(osl_t *osh)
|
||||
{
|
||||
return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn);
|
||||
}
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* pcicfg.h: PCI configuration constants and structures.
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -9,7 +9,7 @@
|
|||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id: pcicfg.h,v 1.1.1.11 2006/04/08 06:13:40 honor Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _h_pcicfg_
|
||||
|
@ -170,6 +170,14 @@ typedef struct _pci_config_regs {
|
|||
#undef PCI_CLASS_DOCK
|
||||
#endif /* __NetBSD__ */
|
||||
|
||||
#ifdef EFI
|
||||
#undef PCI_CLASS_BRIDGE
|
||||
#undef PCI_CLASS_OLD
|
||||
#undef PCI_CLASS_DISPLAY
|
||||
#undef PCI_CLASS_SERIAL
|
||||
#undef PCI_CLASS_SATELLITE
|
||||
#endif /* EFI */
|
||||
|
||||
/* Classes and subclasses */
|
||||
|
||||
typedef enum {
|
||||
|
@ -406,6 +414,11 @@ typedef struct _pciconfig_cap_pwrmgmt {
|
|||
unsigned char data;
|
||||
} pciconfig_cap_pwrmgmt;
|
||||
|
||||
#define PME_CAP_PM_STATES (0x1f << 27) /* Bits 31:27 states that can generate PME */
|
||||
#define PME_CSR_OFFSET 0x4 /* 4-bytes offset */
|
||||
#define PME_CSR_PME_EN (1 << 8) /* Bit 8 Enable generating of PME */
|
||||
#define PME_CSR_PME_STAT (1 << 15) /* Bit 15 PME got asserted */
|
||||
|
||||
/* Data structure to define the PCIE capability */
|
||||
typedef struct _pciconfig_cap_pcie {
|
||||
unsigned char capID;
|
||||
|
@ -463,7 +476,7 @@ typedef struct _pcie_enhanced_caphdr {
|
|||
* 8KB window, so their address is the "regular"
|
||||
* address plus 4K
|
||||
*/
|
||||
#define PCI_BAR0_WINSZ 8192 /* bar0 window size */
|
||||
#define PCI_BAR0_WINSZ (16 * 1024) /* bar0 window size Match with corerev 13 */
|
||||
|
||||
/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
|
||||
#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */
|
||||
|
|
|
@ -5,8 +5,8 @@
|
|||
* jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
|
||||
* gpio interface, extbus, and support for serial and parallel flashes.
|
||||
*
|
||||
* $Id: sbchipc.h,v 1.1.1.14 2006/04/15 01:29:08 michael Exp $
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* $Id$
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -19,7 +19,6 @@
|
|||
#ifndef _SBCHIPC_H
|
||||
#define _SBCHIPC_H
|
||||
|
||||
|
||||
#ifndef _LANGUAGE_ASSEMBLY
|
||||
|
||||
/* cpp contortions to concatenate w/arg prescan */
|
||||
|
@ -29,6 +28,7 @@
|
|||
#define PAD _XSTR(__LINE__)
|
||||
#endif /* PAD */
|
||||
|
||||
|
||||
typedef volatile struct {
|
||||
uint32 chipid; /* 0x0 */
|
||||
uint32 capabilities;
|
||||
|
@ -62,20 +62,26 @@ typedef volatile struct {
|
|||
/* Silicon backplane configuration broadcast control */
|
||||
uint32 broadcastaddress; /* 0x50 */
|
||||
uint32 broadcastdata;
|
||||
uint32 PAD[2];
|
||||
|
||||
/* gpio - cleared only by power-on-reset */
|
||||
uint32 gpiopullup; /* 0x58, corerev >= 20 */
|
||||
uint32 gpiopulldown; /* 0x5c, corerev >= 20 */
|
||||
uint32 gpioin; /* 0x60 */
|
||||
uint32 gpioout;
|
||||
uint32 gpioouten;
|
||||
uint32 gpiocontrol;
|
||||
uint32 gpiointpolarity;
|
||||
uint32 gpiointmask;
|
||||
uint32 PAD[2];
|
||||
|
||||
/* GPIO events corerev >= 11 */
|
||||
uint32 gpioevent;
|
||||
uint32 gpioeventintmask;
|
||||
|
||||
/* Watchdog timer */
|
||||
uint32 watchdog; /* 0x80 */
|
||||
uint32 PAD[1];
|
||||
|
||||
/* GPIO events corerev >= 11 */
|
||||
uint32 gpioeventintpolarity;
|
||||
|
||||
/* GPIO based LED powersave registers corerev >= 16 */
|
||||
uint32 gpiotimerval; /* 0x88 */
|
||||
|
@ -114,10 +120,31 @@ typedef volatile struct {
|
|||
uint32 prog_waitcount;
|
||||
uint32 flash_config;
|
||||
uint32 flash_waitcount;
|
||||
uint32 PAD[44];
|
||||
uint32 PAD[4];
|
||||
|
||||
/* Clock control and hardware workarounds */
|
||||
uint32 clk_ctl_st;
|
||||
/* Enhanced Coexistance Interface (ECI) registers (corerev >= 21) */
|
||||
uint32 eci_output; /* 0x140 */
|
||||
uint32 eci_control;
|
||||
uint32 eci_inputlo;
|
||||
uint32 eci_inputmi;
|
||||
uint32 eci_inputhi;
|
||||
uint32 eci_inputintpolaritylo;
|
||||
uint32 eci_inputintpolaritymi;
|
||||
uint32 eci_inputintpolarityhi;
|
||||
uint32 eci_intmasklo;
|
||||
uint32 eci_intmaskmi;
|
||||
uint32 eci_intmaskhi;
|
||||
uint32 eci_eventlo;
|
||||
uint32 eci_eventmi;
|
||||
uint32 eci_eventhi;
|
||||
uint32 eci_eventmasklo;
|
||||
uint32 eci_eventmaskmi;
|
||||
uint32 eci_eventmaskhi;
|
||||
uint32 PAD[23];
|
||||
|
||||
|
||||
/* Clock control and hardware workarounds (corerev >= 20) */
|
||||
uint32 clk_ctl_st; /* 0x1e0 */
|
||||
uint32 hw_war;
|
||||
uint32 PAD[70];
|
||||
|
||||
|
@ -140,12 +167,47 @@ typedef volatile struct {
|
|||
uint8 uart1lsr;
|
||||
uint8 uart1msr;
|
||||
uint8 uart1scratch;
|
||||
uint32 PAD[126];
|
||||
|
||||
/* PMU registers (corerev >= 20) */
|
||||
uint32 pmucontrol; /* 0x600 */
|
||||
uint32 pmucapabilities;
|
||||
uint32 pmustatus;
|
||||
uint32 res_state;
|
||||
uint32 res_pending;
|
||||
uint32 pmutimer;
|
||||
uint32 min_res_mask;
|
||||
uint32 max_res_mask;
|
||||
uint32 res_table_sel;
|
||||
uint32 res_dep_mask;
|
||||
uint32 res_updn_timer;
|
||||
uint32 res_timer;
|
||||
uint32 clkstretch;
|
||||
uint32 pmuwatchdog;
|
||||
uint32 PAD[2];
|
||||
uint32 res_req_timer_sel;
|
||||
uint32 res_req_timer;
|
||||
uint32 res_req_mask;
|
||||
uint32 PAD;
|
||||
uint32 chipcontrol_addr;
|
||||
uint32 chipcontrol_data;
|
||||
uint32 regcontrol_addr;
|
||||
uint32 regcontrol_data;
|
||||
uint32 pllcontrol_addr;
|
||||
uint32 pllcontrol_data;
|
||||
uint32 PAD[102];
|
||||
uint16 otp[512];
|
||||
} chipcregs_t;
|
||||
|
||||
#endif /* _LANGUAGE_ASSEMBLY */
|
||||
|
||||
/* corecontrol */
|
||||
#define CC_UE (1 << 0) /* uart enable */
|
||||
|
||||
#define CC_CHIPID 0
|
||||
#define CC_CAPABILITIES 4
|
||||
#define CC_OTPST 0x10
|
||||
#define CC_CHIPST 0x2c
|
||||
#define CC_JTAGCMD 0x30
|
||||
#define CC_JTAGIR 0x34
|
||||
#define CC_JTAGDR 0x38
|
||||
|
@ -158,7 +220,18 @@ typedef volatile struct {
|
|||
#define CC_CLKC_M3 0xa0
|
||||
#define CC_CLKDIV 0xa4
|
||||
#define CC_SYS_CLK_CTL 0xc0
|
||||
#define CC_OTP 0x800
|
||||
#define CC_CLK_CTL_ST SB_CLK_CTL_ST
|
||||
#define PMU_CTL 0x600
|
||||
#define PMU_CAP 0x604
|
||||
#define PMU_ST 0x608
|
||||
#define PMU_TIMER 0x614
|
||||
#define PMU_MIN_RES_MASK 0x618
|
||||
#define PMU_MAX_RES_MASK 0x61c
|
||||
#define PMU_REG_CONTROL_ADDR 0x658
|
||||
#define PMU_REG_CONTROL_DATA 0x65C
|
||||
#define PMU_PLL_CONTROL_ADDR 0x660
|
||||
#define PMU_PLL_CONTROL_DATA 0x664
|
||||
#define CC_OTP 0x800 /* OTP address space */
|
||||
|
||||
/* chipid */
|
||||
#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
|
||||
|
@ -170,24 +243,26 @@ typedef volatile struct {
|
|||
#define CID_CC_SHIFT 24
|
||||
|
||||
/* capabilities */
|
||||
#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
|
||||
#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
|
||||
#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
|
||||
#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
|
||||
#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
|
||||
#define CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
|
||||
#define CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
|
||||
#define CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
|
||||
#define CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
|
||||
#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
|
||||
#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
|
||||
#define CAP_PWR_CTL 0x00040000 /* Power control */
|
||||
#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
|
||||
#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
|
||||
#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
|
||||
#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
|
||||
#define CAP_ROM 0x00800000 /* Internal boot rom active */
|
||||
#define CAP_BKPLN64 0x08000000 /* 64-bit backplane */
|
||||
#define CC_CAP_UARTS_MASK 0x00000003 /* Number of uarts */
|
||||
#define CC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
|
||||
#define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */
|
||||
#define CC_CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
|
||||
#define CC_CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
|
||||
#define CC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
|
||||
#define CC_CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
|
||||
#define CC_CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
|
||||
#define CC_CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
|
||||
#define CC_CAP_FLASH_MASK 0x00000700 /* Type of flash */
|
||||
#define CC_CAP_PLL_MASK 0x00038000 /* Type of PLL */
|
||||
#define CC_CAP_PWR_CTL 0x00040000 /* Power control */
|
||||
#define CC_CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
|
||||
#define CC_CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
|
||||
#define CC_CAP_OTPSIZE_BASE 5 /* OTP Size base */
|
||||
#define CC_CAP_JTAGP 0x00400000 /* JTAG Master Present */
|
||||
#define CC_CAP_ROM 0x00800000 /* Internal boot rom active */
|
||||
#define CC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */
|
||||
#define CC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */
|
||||
#define CC_CAP_ECI 0x20000000 /* ECI Present, rev >= 21 */
|
||||
|
||||
/* PLL type */
|
||||
#define PLL_NONE 0x00000000
|
||||
|
@ -199,39 +274,72 @@ typedef volatile struct {
|
|||
#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
|
||||
#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
|
||||
|
||||
/* ALP clock on pre-PMU chips */
|
||||
#define ALP_CLOCK 20000000
|
||||
|
||||
/* HT clock */
|
||||
#define HT_CLOCK 80000000
|
||||
|
||||
/* watchdog clock */
|
||||
#define WATCHDOG_CLOCK_5354 32000 /* Hz */
|
||||
|
||||
/* corecontrol */
|
||||
#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
|
||||
#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
|
||||
#define CC_UARTCLKEN 0x00000008 /* enable UART Clock (corerev > = 21 */
|
||||
|
||||
/* chipcontrol */
|
||||
#define CHIPCTRL_4321A0_DEFAULT 0x3a4
|
||||
#define CHIPCTRL_4321A1_DEFAULT 0x0a4
|
||||
|
||||
/* Fields in the otpstatus register */
|
||||
#define OTPS_PROGFAIL 0x80000000
|
||||
#define OTPS_PROTECT 0x00000007
|
||||
#define OTPS_HW_PROTECT 0x00000001
|
||||
#define OTPS_SW_PROTECT 0x00000002
|
||||
#define OTPS_CID_PROTECT 0x00000004
|
||||
/* Fields in the otpstatus register in rev >= 21 */
|
||||
#define OTPS_OL_MASK 0x000000ff
|
||||
#define OTPS_OL_MFG 0x00000001 /* manuf row is locked */
|
||||
#define OTPS_OL_OR1 0x00000002 /* otp redundancy row 1 is locked */
|
||||
#define OTPS_OL_OR2 0x00000004 /* otp redundancy row 2 is locked */
|
||||
#define OTPS_OL_GU 0x00000008 /* general use region is locked */
|
||||
#define OTPS_GUP_MASK 0x00000f00
|
||||
#define OTPS_GUP_SHIFT 8
|
||||
#define OTPS_GUP_HW 0x00000100 /* h/w subregion is programmed */
|
||||
#define OTPS_GUP_SW 0x00000200 /* s/w subregion is programmed */
|
||||
#define OTPS_GUP_CI 0x00000400 /* chipid/pkgopt subregion is programmed */
|
||||
#define OTPS_GUP_FUSE 0x00000800 /* fuse subregion is programmed */
|
||||
#define OTPS_READY 0x00001000
|
||||
#define OTPS_RV(x) (1 << (16 + (x)))
|
||||
|
||||
/* Fields in the otpcontrol register */
|
||||
#define OTPC_RECWAIT 0xff000000
|
||||
#define OTPC_PROGWAIT 0x00ffff00
|
||||
#define OTPC_PRW_SHIFT 8
|
||||
#define OTPC_MAXFAIL 0x00000038
|
||||
#define OTPC_VSEL 0x00000006
|
||||
#define OTPC_SELVL 0x00000001
|
||||
/* Fields in the otpcontrol register in rev >= 21 */
|
||||
#define OTPC_PROGSEL 0x00000001
|
||||
#define OTPC_PCOUNT_MASK 0x0000000e
|
||||
#define OTPC_PCOUNT_SHIFT 1
|
||||
#define OTPC_VSEL_MASK 0x000000f0
|
||||
#define OTPC_VSEL_SHIFT 4
|
||||
#define OTPC_TMM_MASK 0x00000700
|
||||
#define OTPC_TMM_SHIFT 8
|
||||
#define OTPC_ODM 0x00000800
|
||||
#define OTPC_PROGEN 0x80000000
|
||||
|
||||
/* Fields in otpprog */
|
||||
#define OTPP_COL_MASK 0x000000ff
|
||||
#define OTPP_ROW_MASK 0x0000ff00
|
||||
#define OTPP_ROW_SHIFT 8
|
||||
#define OTPP_READERR 0x10000000
|
||||
#define OTPP_VALUE 0x20000000
|
||||
#define OTPP_VALUE_SHIFT 29
|
||||
#define OTPP_READ 0x40000000
|
||||
#define OTPP_START 0x80000000
|
||||
#define OTPP_BUSY 0x80000000
|
||||
/* Fields in otpprog in rev >= 21 */
|
||||
#define OTPP_COL_MASK 0x000000ff
|
||||
#define OTPP_COL_SHIFT 0
|
||||
#define OTPP_ROW_MASK 0x0000ff00
|
||||
#define OTPP_ROW_SHIFT 8
|
||||
#define OTPP_OC_MASK 0x0f000000
|
||||
#define OTPP_OC_SHIFT 24
|
||||
#define OTPP_READERR 0x10000000
|
||||
#define OTPP_VALUE_MASK 0x20000000
|
||||
#define OTPP_VALUE_SHIFT 29
|
||||
#define OTPP_START_BUSY 0x80000000
|
||||
|
||||
/* Opcodes for OTPP_OC field */
|
||||
#define OTPPOC_READ 0
|
||||
#define OTPPOC_BIT_PROG 1
|
||||
#define OTPPOC_VERIFY 3
|
||||
#define OTPPOC_INIT 4
|
||||
#define OTPPOC_SET 5
|
||||
#define OTPPOC_RESET 6
|
||||
#define OTPPOC_OCST 7
|
||||
#define OTPPOC_ROW_LOCK 8
|
||||
#define OTPPOC_PRESCN_TEST 9
|
||||
|
||||
/* jtagcmd */
|
||||
#define JCMD_START 0x80000000
|
||||
|
@ -272,7 +380,12 @@ typedef volatile struct {
|
|||
|
||||
/* intstatus/intmask */
|
||||
#define CI_GPIO 0x00000001 /* gpio intr */
|
||||
#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
|
||||
#define CI_EI 0x00000002 /* extif intr (corerev >= 3) */
|
||||
#define CI_TEMP 0x00000004 /* temp. ctrl intr (corerev >= 15) */
|
||||
#define CI_SIRQ 0x00000008 /* serial IRQ intr (corerev >= 15) */
|
||||
#define CI_ECI 0x00000010 /* eci intr (corerev >= 21) */
|
||||
#define CI_PMU 0x00000020 /* pmu intr (corerev >= 21) */
|
||||
#define CI_UART 0x00000040 /* uart intr (corerev >= 21) */
|
||||
#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
|
||||
|
||||
/* slow_clk_ctl */
|
||||
|
@ -306,6 +419,43 @@ typedef volatile struct {
|
|||
#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
|
||||
#define SYCC_CD_SHIFT 16
|
||||
|
||||
/* pcmcia_iowait */
|
||||
#define PI_W0_MASK 0x0000003f /* waitcount0 */
|
||||
#define PI_W1_MASK 0x00001f00 /* waitcount1 */
|
||||
#define PI_W1_SHIFT 8
|
||||
#define PI_W2_MASK 0x001f0000 /* waitcount2 */
|
||||
#define PI_W2_SHIFT 16
|
||||
#define PI_W3_MASK 0x1f000000 /* waitcount3 */
|
||||
#define PI_W3_SHIFT 24
|
||||
|
||||
/* prog_waitcount */
|
||||
#define PW_W0_MASK 0x0000001f /* waitcount0 */
|
||||
#define PW_W1_MASK 0x00001f00 /* waitcount1 */
|
||||
#define PW_W1_SHIFT 8
|
||||
#define PW_W2_MASK 0x001f0000 /* waitcount2 */
|
||||
#define PW_W2_SHIFT 16
|
||||
#define PW_W3_MASK 0x1f000000 /* waitcount3 */
|
||||
#define PW_W3_SHIFT 24
|
||||
|
||||
#define PW_W0 0x0000000c
|
||||
#define PW_W1 0x00000a00
|
||||
#define PW_W2 0x00020000
|
||||
#define PW_W3 0x01000000
|
||||
|
||||
/* watchdog */
|
||||
#define WATCHDOG_CLOCK 48000000 /* Hz */
|
||||
|
||||
/* Fields in pmucontrol */
|
||||
#define PCTL_ILP_DIV_MASK 0xffff0000
|
||||
#define PCTL_ILP_DIV_SHIFT 16
|
||||
#define PCTL_NOILP_ON_WAIT 0x00000200
|
||||
#define PCTL_HT_REQ_EN 0x00000100
|
||||
#define PCTL_ALP_REQ_EN 0x00000080
|
||||
#define PCTL_XTALFREQ_MASK 0x0000007c
|
||||
#define PCTL_XTALFREQ_SHIFT 2
|
||||
#define PCTL_ILP_DIV_EN 0x00000002
|
||||
#define PCTL_LPO_SEL 0x00000001
|
||||
|
||||
/* gpiotimerval */
|
||||
#define GPIO_ONTIME_SHIFT 16
|
||||
|
||||
|
@ -377,9 +527,10 @@ typedef volatile struct {
|
|||
#define CC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */
|
||||
#define CC_CFG_EM_IDE 0x0006 /* IDE */
|
||||
#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
|
||||
#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
|
||||
#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
|
||||
#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
|
||||
#define CC_CFG_CD_MASK 0x00e0 /* Sync: Clock divisor, rev >= 20 */
|
||||
#define CC_CFG_CE 0x0100 /* Sync: Clock enable, rev >= 20 */
|
||||
#define CC_CFG_SB 0x0200 /* Sync: Size/Bytestrobe, rev >= 20 */
|
||||
#define CC_CFG_IS 0x0400 /* Extif Sync Clk Select, rev >= 20 */
|
||||
|
||||
/* ExtBus address space */
|
||||
#define CC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */
|
||||
|
@ -396,6 +547,7 @@ typedef volatile struct {
|
|||
/* Start/busy bit in flashcontrol */
|
||||
#define SFLASH_OPCODE 0x000000ff
|
||||
#define SFLASH_ACTION 0x00000700
|
||||
#define SFLASH_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */
|
||||
#define SFLASH_START 0x80000000
|
||||
#define SFLASH_BUSY SFLASH_START
|
||||
|
||||
|
@ -419,6 +571,7 @@ typedef volatile struct {
|
|||
#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
|
||||
#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
|
||||
#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
|
||||
#define SFLASH_ST_CSA 0x1000 /* Keep chip select asserted */
|
||||
|
||||
/* Status register bits for ST flashes */
|
||||
#define SFLASH_ST_WIP 0x01 /* Write In Progress */
|
||||
|
@ -456,31 +609,6 @@ typedef volatile struct {
|
|||
#define SFLASH_AT_ID_MASK 0x38
|
||||
#define SFLASH_AT_ID_SHIFT 3
|
||||
|
||||
/* OTP regions */
|
||||
#define OTP_HW_REGION OTPS_HW_PROTECT
|
||||
#define OTP_SW_REGION OTPS_SW_PROTECT
|
||||
#define OTP_CID_REGION OTPS_CID_PROTECT
|
||||
|
||||
/* OTP regions (Byte offsets from otp size) */
|
||||
#define OTP_SWLIM_OFF (-8)
|
||||
#define OTP_CIDBASE_OFF 0
|
||||
#define OTP_CIDLIM_OFF 8
|
||||
|
||||
/* Predefined OTP words (Word offset from otp size) */
|
||||
#define OTP_BOUNDARY_OFF (-4)
|
||||
#define OTP_HWSIGN_OFF (-3)
|
||||
#define OTP_SWSIGN_OFF (-2)
|
||||
#define OTP_CIDSIGN_OFF (-1)
|
||||
|
||||
#define OTP_CID_OFF 0
|
||||
#define OTP_PKG_OFF 1
|
||||
#define OTP_FID_OFF 2
|
||||
#define OTP_RSV_OFF 3
|
||||
#define OTP_LIM_OFF 4
|
||||
|
||||
#define OTP_SIGNATURE 0x578a
|
||||
#define OTP_MAGIC 0x4e56
|
||||
|
||||
/*
|
||||
* These are the UART port assignments, expressed as offsets from the base
|
||||
* register. These assignments should hold for any serial port based on
|
||||
|
@ -507,10 +635,223 @@ typedef volatile struct {
|
|||
#define UART_LSR_RXRDY 0x01 /* Receiver ready */
|
||||
#define UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */
|
||||
|
||||
/* Interrupt Identity Register (IIR) bits */
|
||||
#define UART_IIR_FIFO_MASK 0xc0 /* IIR FIFO disable/enabled mask */
|
||||
#define UART_IIR_INT_MASK 0xf /* IIR interrupt ID source */
|
||||
#define UART_IIR_MDM_CHG 0x0 /* Modem status changed */
|
||||
#define UART_IIR_NOINT 0x1 /* No interrupt pending */
|
||||
#define UART_IIR_THRE 0x2 /* THR empty */
|
||||
#define UART_IIR_RCVD_DATA 0x4 /* Received data available */
|
||||
#define UART_IIR_RCVR_STATUS 0x6 /* Receiver status */
|
||||
#define UART_IIR_CHAR_TIME 0xc /* Character time */
|
||||
|
||||
/* Interrupt Enable Register (IER) bits */
|
||||
#define UART_IER_EDSSI 8 /* enable modem status interrupt */
|
||||
#define UART_IER_ELSI 4 /* enable receiver line status interrupt */
|
||||
#define UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */
|
||||
#define UART_IER_ERBFI 1 /* enable data available interrupt */
|
||||
|
||||
/* pmustatus */
|
||||
#define PST_INTPEND 0x0040
|
||||
#define PST_SBCLKST 0x0030
|
||||
#define PST_ALPAVAIL 0x0008
|
||||
#define PST_HTAVAIL 0x0004
|
||||
#define PST_RESINIT 0x0003
|
||||
|
||||
/* pmucapabilities */
|
||||
#define PCAP_REV_MASK 0x000000ff
|
||||
|
||||
/* PMU Resource Request Timer registers */
|
||||
/* This is based on PmuRev0 */
|
||||
#define PRRT_TIME_MASK 0x03ff
|
||||
#define PRRT_INTEN 0x0400
|
||||
#define PRRT_REQ_ACTIVE 0x0800
|
||||
#define PRRT_ALP_REQ 0x1000
|
||||
#define PRRT_HT_REQ 0x2000
|
||||
|
||||
/* PMU resource bit position */
|
||||
#define PMURES_BIT(bit) (1 << (bit))
|
||||
|
||||
/* PMU corerev and chip specific PLL controls.
|
||||
* PMU<rev>_PLL<num>_XXXX where <rev> is PMU corerev and <num> is an arbitary number
|
||||
* to differentiate different PLLs controlled by the same PMU rev.
|
||||
*/
|
||||
/* pllcontrol registers */
|
||||
/* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */
|
||||
#define PMU0_PLL0_PLLCTL0 0
|
||||
#define PMU0_PLL0_PC0_PDIV_MASK 1
|
||||
#define PMU0_PLL0_PC0_PDIV_FREQ 25000
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_SHIFT 3
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_BASE 8
|
||||
|
||||
/* PC0_DIV_ARM for PLLOUT_ARM */
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_88MHZ 2
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7
|
||||
|
||||
/* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */
|
||||
#define PMU0_PLL0_PLLCTL1 1
|
||||
#define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000
|
||||
#define PMU0_PLL0_PC1_WILD_INT_SHIFT 28
|
||||
#define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00
|
||||
#define PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8
|
||||
#define PMU0_PLL0_PC1_STOP_MOD 0x00000040
|
||||
|
||||
/* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */
|
||||
#define PMU0_PLL0_PLLCTL2 2
|
||||
#define PMU0_PLL0_PC2_WILD_INT_MASK 0xf
|
||||
#define PMU0_PLL0_PC2_WILD_INT_SHIFT 4
|
||||
|
||||
/* Chip specific PMU resources. */
|
||||
#define RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */
|
||||
#define RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */
|
||||
#define RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */
|
||||
#define RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */
|
||||
#define RES4328_ILP_REQUEST 4 /* 0x00010 */
|
||||
#define RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */
|
||||
#define RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */
|
||||
#define RES4328_ROM_SWITCH 7 /* 0x00080 */
|
||||
#define RES4328_PA_REF_LDO 8 /* 0x00100 */
|
||||
#define RES4328_RADIO_LDO 9 /* 0x00200 */
|
||||
#define RES4328_AFE_LDO 10 /* 0x00400 */
|
||||
#define RES4328_PLL_LDO 11 /* 0x00800 */
|
||||
#define RES4328_BG_FILTBYP 12 /* 0x01000 */
|
||||
#define RES4328_TX_FILTBYP 13 /* 0x02000 */
|
||||
#define RES4328_RX_FILTBYP 14 /* 0x04000 */
|
||||
#define RES4328_XTAL_PU 15 /* 0x08000 */
|
||||
#define RES4328_XTAL_EN 16 /* 0x10000 */
|
||||
#define RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */
|
||||
#define RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */
|
||||
#define RES4328_BB_PLL_PU 19 /* 0x80000 */
|
||||
|
||||
#define RES5354_EXT_SWITCHER_PWM 0 /* 0x00001 */
|
||||
#define RES5354_BB_SWITCHER_PWM 1 /* 0x00002 */
|
||||
#define RES5354_BB_SWITCHER_BURST 2 /* 0x00004 */
|
||||
#define RES5354_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */
|
||||
#define RES5354_ILP_REQUEST 4 /* 0x00010 */
|
||||
#define RES5354_RADIO_SWITCHER_PWM 5 /* 0x00020 */
|
||||
#define RES5354_RADIO_SWITCHER_BURST 6 /* 0x00040 */
|
||||
#define RES5354_ROM_SWITCH 7 /* 0x00080 */
|
||||
#define RES5354_PA_REF_LDO 8 /* 0x00100 */
|
||||
#define RES5354_RADIO_LDO 9 /* 0x00200 */
|
||||
#define RES5354_AFE_LDO 10 /* 0x00400 */
|
||||
#define RES5354_PLL_LDO 11 /* 0x00800 */
|
||||
#define RES5354_BG_FILTBYP 12 /* 0x01000 */
|
||||
#define RES5354_TX_FILTBYP 13 /* 0x02000 */
|
||||
#define RES5354_RX_FILTBYP 14 /* 0x04000 */
|
||||
#define RES5354_XTAL_PU 15 /* 0x08000 */
|
||||
#define RES5354_XTAL_EN 16 /* 0x10000 */
|
||||
#define RES5354_BB_PLL_FILTBYP 17 /* 0x20000 */
|
||||
#define RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */
|
||||
#define RES5354_BB_PLL_PU 19 /* 0x80000 */
|
||||
|
||||
/* pllcontrol registers */
|
||||
/* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypsss_sdmod */
|
||||
#define PMU1_PLL0_PLLCTL0 0
|
||||
#define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
|
||||
#define PMU1_PLL0_PC0_P1DIV_SHIFT 20
|
||||
#define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000
|
||||
#define PMU1_PLL0_PC0_P2DIV_SHIFT 24
|
||||
|
||||
/* m<x>div */
|
||||
#define PMU1_PLL0_PLLCTL1 1
|
||||
#define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff
|
||||
#define PMU1_PLL0_PC1_M1DIV_SHIFT 0
|
||||
#define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00
|
||||
#define PMU1_PLL0_PC1_M2DIV_SHIFT 8
|
||||
#define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000
|
||||
#define PMU1_PLL0_PC1_M3DIV_SHIFT 16
|
||||
#define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000
|
||||
#define PMU1_PLL0_PC1_M4DIV_SHIFT 24
|
||||
|
||||
/* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */
|
||||
#define PMU1_PLL0_PLLCTL2 2
|
||||
#define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff
|
||||
#define PMU1_PLL0_PC2_M5DIV_SHIFT 0
|
||||
#define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00
|
||||
#define PMU1_PLL0_PC2_M6DIV_SHIFT 8
|
||||
#define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000
|
||||
#define PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17
|
||||
#define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
|
||||
#define PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
|
||||
|
||||
/* ndiv_frac */
|
||||
#define PMU1_PLL0_PLLCTL3 3
|
||||
#define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff
|
||||
#define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0
|
||||
|
||||
/* pll_ctrl */
|
||||
#define PMU1_PLL0_PLLCTL4 4
|
||||
|
||||
/* pll_ctrl, vco_rng, clkdrive_ch<x> */
|
||||
#define PMU1_PLL0_PLLCTL5 5
|
||||
#define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00
|
||||
#define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8
|
||||
|
||||
#define RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */
|
||||
#define RES4325_CBUCK_BURST 1 /* 0x00000002 */
|
||||
#define RES4325_CBUCK_PWM 2 /* 0x00000004 */
|
||||
#define RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */
|
||||
#define RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */
|
||||
#define RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */
|
||||
#define RES4325_ILP_REQUEST 6 /* 0x00000040 */
|
||||
#define RES4325_ABUCK_BURST 7 /* 0x00000080 */
|
||||
#define RES4325_ABUCK_PWM 8 /* 0x00000100 */
|
||||
#define RES4325_LNLDO1_PU 9 /* 0x00000200 */
|
||||
#define RES4325_LNLDO2_PU 10 /* 0x00000400 */
|
||||
#define RES4325_LNLDO3_PU 11 /* 0x00000800 */
|
||||
#define RES4325_LNLDO4_PU 12 /* 0x00001000 */
|
||||
#define RES4325_XTAL_PU 13 /* 0x00002000 */
|
||||
#define RES4325_ALP_AVAIL 14 /* 0x00004000 */
|
||||
#define RES4325_RX_PWRSW_PU 15 /* 0x00008000 */
|
||||
#define RES4325_TX_PWRSW_PU 16 /* 0x00010000 */
|
||||
#define RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */
|
||||
#define RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */
|
||||
#define RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */
|
||||
#define RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */
|
||||
#define RES4325_HT_AVAIL 21 /* 0x00200000 */
|
||||
|
||||
/* Chip specific ChipStatus register bits */
|
||||
#define CST4325_SPROM_OTP_SEL_MASK 0x00000003
|
||||
#define CST4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
|
||||
#define CST4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
|
||||
#define CST4325_OTP_SEL 2 /* OTP is powered up, no SPROM */
|
||||
#define CST4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
|
||||
#define CST4325_SDIO_USB_MODE_MASK 0x00000004
|
||||
#define CST4325_SDIO_USB_MODE_SHIFT 2
|
||||
#define CST4325_RCAL_VALID_MASK 0x00000008
|
||||
#define CST4325_RCAL_VALID_SHIFT 3
|
||||
#define CST4325_RCAL_VALUE_MASK 0x000001f0
|
||||
#define CST4325_RCAL_VALUE_SHIFT 4
|
||||
#define CST4325_PMUTOP_2B_MASK 0x00000200 /* 1 for 2b, 0 for to 2a */
|
||||
#define CST4325_PMUTOP_2B_SHIFT 9
|
||||
|
||||
#define RES4312_SWITCHER_BURST 0 /* 0x00000001 */
|
||||
#define RES4312_SWITCHER_PWM 1 /* 0x00000002 */
|
||||
#define RES4312_PA_REF_LDO 2 /* 0x00000004 */
|
||||
#define RES4312_CORE_LDO_BURST 3 /* 0x00000008 */
|
||||
#define RES4312_CORE_LDO_PWM 4 /* 0x00000010 */
|
||||
#define RES4312_RADIO_LDO 5 /* 0x00000020 */
|
||||
#define RES4312_ILP_REQUEST 6 /* 0x00000040 */
|
||||
#define RES4312_BG_FILTBYP 7 /* 0x00000080 */
|
||||
#define RES4312_TX_FILTBYP 8 /* 0x00000100 */
|
||||
#define RES4312_RX_FILTBYP 9 /* 0x00000200 */
|
||||
#define RES4312_XTAL_PU 10 /* 0x00000400 */
|
||||
#define RES4312_ALP_AVAIL 11 /* 0x00000800 */
|
||||
#define RES4312_BB_PLL_FILTBYP 12 /* 0x00001000 */
|
||||
#define RES4312_RF_PLL_FILTBYP 13 /* 0x00002000 */
|
||||
#define RES4312_HT_AVAIL 14 /* 0x00004000 */
|
||||
|
||||
/*
|
||||
* Maximum delay for the PMU state transition.
|
||||
* This is an upper bound intended for spinwaits etc.
|
||||
*/
|
||||
#define PMU_MAX_TRANSITION_DLY 15000
|
||||
|
||||
#endif /* _SBCHIPC_H */
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Broadcom SiliconBackplane hardware register definitions.
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -9,11 +9,12 @@
|
|||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id: sbconfig.h,v 1.1.1.11 2006/02/27 03:43:16 honor Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _SBCONFIG_H
|
||||
#define _SBCONFIG_H
|
||||
#include "linuxver.h"
|
||||
|
||||
/* cpp contortions to concatenate w/arg prescan */
|
||||
#ifndef PAD
|
||||
|
@ -36,13 +37,13 @@
|
|||
|
||||
#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
|
||||
#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
|
||||
|
||||
#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
|
||||
#define SB_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */
|
||||
#define SB_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
|
||||
#define SB_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
|
||||
|
||||
#define SB_ROM 0x20000000 /* ARM ROM */
|
||||
#define SB_SRAM2 0x80000000 /* ARM SRAM Region 2 */
|
||||
#define SB_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */
|
||||
#define SB_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */
|
||||
#define SB_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */
|
||||
#define SB_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */
|
||||
#define SB_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */
|
||||
|
||||
|
@ -196,7 +197,7 @@ typedef volatile struct _sbconfig {
|
|||
#define SBTMH_INT 0x2 /* interrupt */
|
||||
#define SBTMH_BUSY 0x4 /* busy */
|
||||
#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
|
||||
#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
|
||||
#define SBTMH_FL_MASK 0x0fff0000 /* core-specific flags */
|
||||
#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
|
||||
#define SBTMH_GCR 0x20000000 /* gated clock request */
|
||||
#define SBTMH_BISTF 0x40000000 /* bist failed */
|
||||
|
@ -323,7 +324,6 @@ typedef volatile struct _sbconfig {
|
|||
#define SB_ILINE100 0x80a /* iline100 core */
|
||||
#define SB_IPSEC 0x80b /* ipsec core */
|
||||
#define SB_PCMCIA 0x80d /* pcmcia core */
|
||||
#define SB_SDIOD SB_PCMCIA /* pcmcia core has sdio device */
|
||||
#define SB_SOCRAM 0x80e /* internal memory core */
|
||||
#define SB_MEMC 0x80f /* memc sdram core */
|
||||
#define SB_EXTIF 0x811 /* external interface core */
|
||||
|
@ -342,11 +342,32 @@ typedef volatile struct _sbconfig {
|
|||
#define SB_MIMO 0x821 /* MIMO phy core */
|
||||
#define SB_SRAMC 0x822 /* SRAM controller core */
|
||||
#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
|
||||
#define SB_ARM11 0x824 /* ARM 1176 core */
|
||||
#define SB_ARM7 0x825 /* ARM 7tdmi core */
|
||||
#define SB_ARM7S 0x825 /* ARM7tdmi-s core */
|
||||
#define SB_SDIOD 0x829 /* SDIO device core */
|
||||
#define SB_ARMCM3 0x82a /* ARM Cortex M3 core */
|
||||
#define SB_OCP 0x830 /* OCP2OCP bridge core */
|
||||
#define SB_SC 0x831 /* shared common core */
|
||||
#define SB_AHB 0x832 /* OCP2AHB bridge core */
|
||||
|
||||
#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
|
||||
|
||||
/* Not an enumeration space register, but common to all cores to
|
||||
* communicate w/PMU regarding Silicon Backplane clocking.
|
||||
*/
|
||||
#define SB_CLK_CTL_ST 0x1e0 /* clock control and status */
|
||||
|
||||
/* clk_ctl_st register */
|
||||
#define CCS_FORCEALP 0x00000001 /* force ALP request */
|
||||
#define CCS_FORCEHT 0x00000002 /* force HT request */
|
||||
#define CCS_FORCEILP 0x00000004 /* force ILP request */
|
||||
#define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
|
||||
#define CCS_HTAREQ 0x00000010 /* HT Avail Request */
|
||||
#define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
|
||||
#define CCS_ALPAVAIL 0x00010000 /* ALP is available */
|
||||
#define CCS_HTAVAIL 0x00020000 /* HT is available */
|
||||
#define CCS0_HTAVAIL 0x00010000 /* HT avail in chipc and pcmcia on 4328a0 */
|
||||
#define CCS0_ALPAVAIL 0x00020000 /* ALP avail in chipc and pcmcia on 4328a0 */
|
||||
|
||||
/* Not really related to Silicon Backplane, but a couple of software
|
||||
* conventions for the use the flash space:
|
||||
*/
|
||||
|
@ -359,11 +380,11 @@ typedef volatile struct _sbconfig {
|
|||
#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
|
||||
#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
|
||||
#define BISZ_TXTST_IDX 1 /* 1: text start */
|
||||
#define BISZ_TXTEND_IDX 2 /* 2: text start */
|
||||
#define BISZ_DATAST_IDX 3 /* 3: text start */
|
||||
#define BISZ_DATAEND_IDX 4 /* 4: text start */
|
||||
#define BISZ_BSSST_IDX 5 /* 5: text start */
|
||||
#define BISZ_BSSEND_IDX 6 /* 6: text start */
|
||||
#define BISZ_TXTEND_IDX 2 /* 2: text end */
|
||||
#define BISZ_DATAST_IDX 3 /* 3: data start */
|
||||
#define BISZ_DATAEND_IDX 4 /* 4: data end */
|
||||
#define BISZ_BSSST_IDX 5 /* 5: bss start */
|
||||
#define BISZ_BSSEND_IDX 6 /* 6: bss end */
|
||||
#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
|
||||
|
||||
#endif /* _SBCONFIG_H */
|
||||
|
|
|
@ -161,15 +161,6 @@ typedef volatile struct {
|
|||
#define PA_W3_MASK 0x1f000000 /* waitcount3 */
|
||||
#define PA_W3_SHIFT 24
|
||||
|
||||
/* pcmcia_iowait */
|
||||
#define PI_W0_MASK 0x3f /* waitcount0 */
|
||||
#define PI_W1_MASK 0x1f00 /* waitcount1 */
|
||||
#define PI_W1_SHIFT 8
|
||||
#define PI_W2_MASK 0x1f0000 /* waitcount2 */
|
||||
#define PI_W2_SHIFT 16
|
||||
#define PI_W3_MASK 0x1f000000 /* waitcount3 */
|
||||
#define PI_W3_SHIFT 24
|
||||
|
||||
/* prog_waitcount */
|
||||
#define PW_W0_MASK 0x0000001f /* waitcount0 */
|
||||
#define PW_W1_MASK 0x00001f00 /* waitcount1 */
|
||||
|
|
|
@ -7,7 +7,7 @@
|
|||
* interface. The core revision is stored in the SB ID register in SB
|
||||
* configuration space.
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -15,7 +15,7 @@
|
|||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id: sbhndmips.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _sbhndmips_h_
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -9,7 +9,7 @@
|
|||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id: sbmemc.h,v 1.6 2006/03/02 12:33:44 honor Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _SBMEMC_H
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* HND SiliconBackplane PCI core hardware definitions.
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -9,7 +9,7 @@
|
|||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id: sbpci.h,v 1.1.1.11 2006/02/27 03:43:16 honor Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _sbpci_h_
|
||||
|
@ -68,8 +68,11 @@ typedef struct sbpciregs {
|
|||
#define PCI_PARKID_EXT0 0 /* External master 0 */
|
||||
#define PCI_PARKID_EXT1 1 /* External master 1 */
|
||||
#define PCI_PARKID_EXT2 2 /* External master 2 */
|
||||
#define PCI_PARKID_INT 3 /* Internal master */
|
||||
#define PCI_PARKID_LAST 4 /* Last active master */
|
||||
#define PCI_PARKID_EXT3 3 /* External master 3 (rev >= 11) */
|
||||
#define PCI_PARKID_INT 3 /* Internal master (rev < 11) */
|
||||
#define PCI11_PARKID_INT 4 /* Internal master (rev >= 11) */
|
||||
#define PCI_PARKID_LAST 4 /* Last active master (rev < 11) */
|
||||
#define PCI11_PARKID_LAST 5 /* Last active master (rev >= 11) */
|
||||
|
||||
/* Interrupt status/mask */
|
||||
#define PCI_INTA 0x01 /* PCI INTA# is asserted */
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* BCM43XX SiliconBackplane PCIE core hardware definitions.
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -9,7 +9,7 @@
|
|||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id: sbpcie.h,v 1.1.1.2 2006/02/27 03:43:16 honor Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _SBPCIE_H
|
||||
|
@ -38,11 +38,17 @@
|
|||
#define PCIE_BAR0_PCIECORE_OFFSET 0x2000
|
||||
#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000
|
||||
|
||||
/* different register spaces to access thr'u pcie indirect access */
|
||||
#define PCIE_CONFIGREGS 1 /* Access to config space */
|
||||
#define PCIE_PCIEREGS 2 /* Access to pcie registers */
|
||||
|
||||
/* SB side: PCIE core and host control registers */
|
||||
typedef struct sbpcieregs {
|
||||
uint32 PAD[3];
|
||||
uint32 biststatus; /* bist Status: 0x00C */
|
||||
uint32 PAD[6];
|
||||
uint32 gpiosel; /* PCIE gpio sel: 0x010 */
|
||||
uint32 gpioouten; /* PCIE gpio outen: 0x14 */
|
||||
uint32 PAD[4];
|
||||
uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */
|
||||
uint32 PAD[54];
|
||||
uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
|
||||
|
@ -58,11 +64,12 @@ typedef struct sbpcieregs {
|
|||
uint32 mdiocontrol; /* controls the mdio access: 0x128 */
|
||||
uint32 mdiodata; /* Data to the mdio access: 0x12c */
|
||||
|
||||
/* pcie protocol phy/dllp/tlp register access mechanism */
|
||||
uint32 pcieaddr; /* address of the internal registeru: 0x130 */
|
||||
uint32 pciedata; /* Data to/from the internal regsiter: 0x134 */
|
||||
/* pcie protocol phy/dllp/tlp register indirect access mechanism */
|
||||
uint32 pcieindaddr; /* indirect access to the internal register: 0x130 */
|
||||
uint32 pcieinddata; /* Data to/from the internal regsiter: 0x134 */
|
||||
|
||||
uint32 PAD[434];
|
||||
uint32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */
|
||||
uint32 PAD[433];
|
||||
uint16 sprom[36]; /* SPROM shadow Area */
|
||||
} sbpcieregs_t;
|
||||
|
||||
|
@ -136,6 +143,7 @@ typedef struct sbpcieregs {
|
|||
#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
|
||||
#define PCIE_DLLP_TESTREG 0x14C /* Test */
|
||||
#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST */
|
||||
#define PCIE_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */
|
||||
|
||||
/* PCIE protocol TLP diagnostic registers */
|
||||
#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */
|
||||
|
@ -192,9 +200,38 @@ typedef struct sbpcieregs {
|
|||
#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
|
||||
#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
|
||||
|
||||
/* SERDES registers */
|
||||
/* SERDES RX registers */
|
||||
#define SERDES_RX_CTRL 1 /* Rx cntrl */
|
||||
#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
|
||||
#define SERDES_RX_CDR 6 /* CDR */
|
||||
#define SERDES_RX_CDRBW 7 /* CDR BW */
|
||||
|
||||
/* SERDES RX control register */
|
||||
#define SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
|
||||
#define SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
|
||||
|
||||
/* SERDES PLL registers */
|
||||
#define SERDES_PLL_CTRL 1 /* PLL control reg */
|
||||
#define PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
|
||||
|
||||
#define PCIE_L1THRESHOLDTIME_MASK 0xFF00 /* bits 8 - 15 */
|
||||
#define PCIE_L1THRESHOLDTIME_SHIFT 8 /* PCIE_L1THRESHOLDTIME_SHIFT */
|
||||
#define PCIE_L1THRESHOLD_WARVAL 0x72 /* WAR value */
|
||||
|
||||
/* SPROM offsets */
|
||||
#define SRSH_ASPM_OFFSET 4 /* word 4 */
|
||||
#define SRSH_ASPM_ENB 0x18 /* bit 3, 4 */
|
||||
#define SRSH_CLKREQ_OFFSET 20 /* word 20 */
|
||||
#define SRSH_CLKREQ_ENB 0x0800 /* bit 11 */
|
||||
|
||||
/* Linkcontrol reg offset in PCIE Cap */
|
||||
#define PCIE_CAP_LINKCTRL_OFFSET 16 /* linkctrl offset in pcie cap */
|
||||
#define PCIE_CAP_LCREG_ASPML0s 0x01 /* ASPM L0s in linkctrl */
|
||||
#define PCIE_CAP_LCREG_ASPML1 0x02 /* ASPM L1 in linkctrl */
|
||||
#define PCIE_ASPM_ENAB 0x03 /* ASPM L0s & L1 in linkctrl */
|
||||
#define PCIE_CLKREQ_ENAB 0x100 /* CLKREQ Enab in linkctrl */
|
||||
|
||||
/* Status reg PCIE_PLP_STATUSREG */
|
||||
#define PCIE_PLP_POLARITYINV_STAT 0x10
|
||||
|
||||
#endif /* _SBPCIE_H */
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -9,7 +9,7 @@
|
|||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id: sbpcmcia.h,v 1.1.1.9 2006/02/27 03:43:16 honor Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _SBPCMCIA_H
|
||||
|
@ -75,6 +75,8 @@
|
|||
#define SROM_DATAH (0x073a / 2)
|
||||
#define SROM_ADDRL (0x073c / 2)
|
||||
#define SROM_ADDRH (0x073e / 2)
|
||||
#define SROM_INFO2 (0x0772 / 2) /* Corerev >= 2 && <= 5 */
|
||||
#define SROM_INFO (0x07be / 2) /* Corerev >= 6 */
|
||||
|
||||
/* Values for srom_cs: */
|
||||
#define SROM_IDLE 0
|
||||
|
@ -84,16 +86,30 @@
|
|||
#define SROM_WDS 7
|
||||
#define SROM_DONE 8
|
||||
|
||||
/* Fields in srom_info: */
|
||||
#define SRI_SZ_MASK 0x03
|
||||
#define SRI_BLANK 0x04
|
||||
#define SRI_OTP 0x80
|
||||
|
||||
/* CIS stuff */
|
||||
|
||||
/* The CIS stops where the FCRs start */
|
||||
#define CIS_SIZE PCMCIA_FCR
|
||||
|
||||
/* CIS tuple length field max */
|
||||
#define CIS_TUPLE_LEN_MAX 0xff
|
||||
|
||||
/* Standard tuples we know about */
|
||||
|
||||
#define CISTPL_VERS_1 0x15 /* CIS ver, manf, dev & ver strings */
|
||||
#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
|
||||
#define CISTPL_FUNCID 0x21 /* Function identification */
|
||||
#define CISTPL_FUNCE 0x22 /* Function extensions */
|
||||
#define CISTPL_CFTABLE 0x1b /* Config table entry */
|
||||
#define CISTPL_END 0xff /* End of the CIS tuple chain */
|
||||
|
||||
/* Function identifier provides context for the function extentions tuple */
|
||||
|
||||
|
||||
/* Function extensions for LANs */
|
||||
|
||||
|
@ -135,7 +151,29 @@
|
|||
#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */
|
||||
#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */
|
||||
#define HNBU_GPIOTIMER 0x0d /* 2 bytes with on/off values in rev 3 */
|
||||
|
||||
#define HNBU_PAPARMS5G 0x0e /* 5G PA params */
|
||||
#define HNBU_ANT5G 0x0f /* 4328 5G antennas available/gain */
|
||||
#define HNBU_RDLID 0x10 /* 2 byte USB remote downloader (RDL) product Id */
|
||||
#define HNBU_RSSISMBXA2G 0x11 /* 4328 2G RSSI mid pt sel & board switch arch,
|
||||
* 2 bytes, rev 3.
|
||||
*/
|
||||
#define HNBU_RSSISMBXA5G 0x12 /* 4328 5G RSSI mid pt sel & board switch arch,
|
||||
* 2 bytes, rev 3.
|
||||
*/
|
||||
#define HNBU_XTALFREQ 0x13 /* 4 byte Crystal frequency in kilohertz */
|
||||
#define HNBU_TRI2G 0x14 /* 4328 2G TR isolation, 1 byte */
|
||||
#define HNBU_TRI5G 0x15 /* 4328 5G TR isolation, 3 bytes */
|
||||
#define HNBU_RXPO2G 0x16 /* 4328 2G RX power offset, 1 byte */
|
||||
#define HNBU_RXPO5G 0x17 /* 4328 5G RX power offset, 1 byte */
|
||||
#define HNBU_BOARDNUM 0x18 /* board serial number, independent of mac addr */
|
||||
#define HNBU_MACADDR 0x19 /* mac addr override for the standard CIS LAN_NID */
|
||||
#define HNBU_RDLSN 0x1a /* 2 bytes; serial # advertised in USB descriptor */
|
||||
#define HNBU_BOARDTYPE 0x1b /* 2 bytes; boardtype */
|
||||
#define HNBU_RDLRNDIS 0x20 /* 1 byte; 1 = RDL advertises RNDIS config */
|
||||
#define HNBU_RDLRWU 0x30 /* 1 byte; 1 = RDL advertises Remote Wake-up */
|
||||
#define HNBU_SROM3SWRGN 0x80 /* 78 bytes; srom rev 3 s/w region without crc8
|
||||
* plus extra info appended.
|
||||
*/
|
||||
|
||||
/* sbtmstatelow */
|
||||
#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -9,7 +9,7 @@
|
|||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id: sbsdram.h,v 1.1.1.9 2006/03/02 13:03:52 honor Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _SBSDRAM_H
|
||||
|
@ -26,16 +26,7 @@ typedef volatile struct sbsdramregs {
|
|||
uint32 pad2;
|
||||
} sbsdramregs_t;
|
||||
|
||||
/* SDRAM simulation */
|
||||
#ifdef RAMSZ
|
||||
#define SDRAMSZ RAMSZ
|
||||
#else
|
||||
#define SDRAMSZ (4 * 1024 * 1024)
|
||||
#endif
|
||||
|
||||
extern uchar sdrambuf[SDRAMSZ];
|
||||
|
||||
#endif /* _LANGUAGE_ASSEMBLY */
|
||||
#endif /* !_LANGUAGE_ASSEMBLY */
|
||||
|
||||
/* SDRAM initialization control (initcontrol) register bits */
|
||||
#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* BCM47XX Sonics SiliconBackplane embedded ram core
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -9,21 +9,21 @@
|
|||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id: sbsocram.h,v 1.1.1.3 2006/02/27 03:43:16 honor Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _SBSOCRAM_H
|
||||
#define _SBSOCRAM_H
|
||||
|
||||
#define SR_COREINFO 0x00
|
||||
#define SR_BWALLOC 0x04
|
||||
#define SR_BISTSTAT 0x0c
|
||||
#define SR_BANKINDEX 0x10
|
||||
#define SR_BANKSTBYCTL 0x14
|
||||
|
||||
|
||||
#ifndef _LANGUAGE_ASSEMBLY
|
||||
|
||||
/* cpp contortions to concatenate w/arg prescan */
|
||||
#ifndef PAD
|
||||
#define _PADLINE(line) pad ## line
|
||||
#define _XSTR(line) _PADLINE(line)
|
||||
#define PAD _XSTR(__LINE__)
|
||||
#endif /* PAD */
|
||||
|
||||
/* Memcsocram core registers */
|
||||
typedef volatile struct sbsocramregs {
|
||||
uint32 coreinfo;
|
||||
|
@ -32,13 +32,28 @@ typedef volatile struct sbsocramregs {
|
|||
uint32 biststat;
|
||||
uint32 bankidx;
|
||||
uint32 standbyctrl;
|
||||
uint32 PAD[116];
|
||||
uint32 pwrctl; /* corerev >= 2 */
|
||||
} sbsocramregs_t;
|
||||
|
||||
#endif
|
||||
#endif /* _LANGUAGE_ASSEMBLY */
|
||||
|
||||
/* Register offsets */
|
||||
#define SR_COREINFO 0x00
|
||||
#define SR_BWALLOC 0x04
|
||||
#define SR_BISTSTAT 0x0c
|
||||
#define SR_BANKINDEX 0x10
|
||||
#define SR_BANKSTBYCTL 0x14
|
||||
#define SR_PWRCTL 0x1e8
|
||||
|
||||
/* Coreinfo register */
|
||||
#define SRCI_PT_MASK 0x30000
|
||||
#define SRCI_PT_MASK 0x00030000
|
||||
#define SRCI_PT_SHIFT 16
|
||||
/* corerev >= 3 */
|
||||
#define SRCI_LSS_MASK 0x00f00000
|
||||
#define SRCI_LSS_SHIFT 20
|
||||
#define SRCI_LRS_MASK 0x0f000000
|
||||
#define SRCI_LRS_SHIFT 24
|
||||
|
||||
/* In corerev 0, the memory size is 2 to the power of the
|
||||
* base plus 16 plus to the contents of the memsize field plus 1.
|
||||
|
@ -61,4 +76,11 @@ typedef volatile struct sbsocramregs {
|
|||
#define SRCI_SRBSZ_SHIFT 0
|
||||
|
||||
#define SR_BSZ_BASE 14
|
||||
|
||||
/* Standby control register */
|
||||
#define SRSC_SBYOVR_MASK 0x80000000
|
||||
#define SRSC_SBYOVR_SHIFT 31
|
||||
#define SRSC_SBYOVRVAL_MASK 0x60000000
|
||||
#define SRSC_SBYOVRVAL_SHIFT 29
|
||||
|
||||
#endif /* _SBSOCRAM_H */
|
||||
|
|
277
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsprom.h
Normal file
277
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsprom.h
Normal file
|
@ -0,0 +1,277 @@
|
|||
/*
|
||||
* SPROM format definitions for the Broadcom 47xx and 43xx chip family.
|
||||
*
|
||||
* $Id$
|
||||
* Copyright(c) 2002 Broadcom Corporation
|
||||
*/
|
||||
|
||||
#ifndef _SBSPROM_H
|
||||
#define _SBSPROM_H
|
||||
|
||||
#include "typedefs.h"
|
||||
#include "bcmdevs.h"
|
||||
|
||||
/* A word is this many bytes */
|
||||
#define SRW 2
|
||||
|
||||
/* offset into PCI config space for write enable bit */
|
||||
#define CFG_SROM_WRITABLE_OFFSET 0x88
|
||||
#define SROM_WRITEABLE 0x10
|
||||
|
||||
/* enumeration space consists of N contiguous 4Kbyte core register sets */
|
||||
#define SBCORES_BASE 0x18000000
|
||||
#define SBCORES_EACH 0x1000
|
||||
|
||||
/* offset from BAR0 for srom space */
|
||||
#define SROM_BASE 4096
|
||||
|
||||
/* number of 2-byte words in srom */
|
||||
#define SROM_SIZE 64
|
||||
|
||||
#define SROM_BYTES (SROM_SIZE * SRW)
|
||||
|
||||
#define MAX_FN 4
|
||||
|
||||
/* Word 0, Hardware control */
|
||||
#define SROM_HWCTL 0
|
||||
#define HW_FUNMSK 0x000f
|
||||
#define HW_FCLK 0x0200
|
||||
#define HW_CBM 0x0400
|
||||
#define HW_PIMSK 0xf000
|
||||
#define HW_PISHIFT 12
|
||||
#define HW_4301PISHIFT 13
|
||||
#define HW_PI4402 0x2
|
||||
#define HW_FUN4401 0x0001
|
||||
#define HW_FCLK4402 0x0000
|
||||
|
||||
/* Word 1, common-power/boot-rom */
|
||||
#define SROM_COMMPW 1
|
||||
/* boot rom present bit */
|
||||
#define BR_PRESSHIFT 8
|
||||
/* 15:9 for n; boot rom size is 2^(14 + n) bytes */
|
||||
#define BR_SIZESHIFT 9
|
||||
|
||||
/* Word 2, SubsystemId */
|
||||
#define SROM_SSID 2
|
||||
|
||||
/* Word 3, VendorId */
|
||||
#define SROM_VID 3
|
||||
|
||||
/* Function 0 info, function info length */
|
||||
#define SROM_FN0 4
|
||||
#define SROM_FNSZ 8
|
||||
|
||||
/* Within each function: */
|
||||
/* Word 0, deviceID */
|
||||
#define SRFN_DID 0
|
||||
|
||||
/* Words 1-2, ClassCode */
|
||||
#define SRFN_CCL 1
|
||||
/* Word 2, D0 Power */
|
||||
#define SRFN_CCHD0 2
|
||||
|
||||
/* Word 3, PME and D1D2D3 power */
|
||||
#define SRFN_PMED123 3
|
||||
|
||||
#define PME_IL 0
|
||||
#define PME_ENET0 1
|
||||
#define PME_ENET1 2
|
||||
#define PME_CODEC 3
|
||||
|
||||
#define PME_4402_ENET 0
|
||||
#define PME_4402_CODEC 1
|
||||
#define PME_4301_WL 2
|
||||
#define PMEREP_4402_ENET (PMERD3CV | PMERD3CA | PMERD3H | PMERD2 | PMERD1 | PMERD0 | PME)
|
||||
|
||||
/* Word 4, Bar1 enable, pme reports */
|
||||
#define SRFN_B1PMER 4
|
||||
#define B1E 1
|
||||
#define B1SZMSK 0xe
|
||||
#define B1SZSH 1
|
||||
#define PMERMSK 0x0ff0
|
||||
#define PME 0x0010
|
||||
#define PMERD0 0x0020
|
||||
#define PMERD1 0x0040
|
||||
#define PMERD2 0x0080
|
||||
#define PMERD3H 0x0100
|
||||
#define PMERD3CA 0x0200
|
||||
#define PMERD3CV 0x0400
|
||||
#define IGNCLKRR 0x0800
|
||||
#define B0LMSK 0xf000
|
||||
|
||||
/* Words 4-5, Bar0 Sonics value */
|
||||
#define SRFN_B0H 5
|
||||
/* Words 6-7, CIS Pointer */
|
||||
#define SRFN_CISL 6
|
||||
#define SRFN_CISH 7
|
||||
|
||||
/* Words 36-38: iLine MAC address */
|
||||
#define SROM_I_MACHI 36
|
||||
#define SROM_I_MACMID 37
|
||||
#define SROM_I_MACLO 38
|
||||
|
||||
/* Words 36-38: wireless0 MAC address on 43xx */
|
||||
#define SROM_W0_MACHI 36
|
||||
#define SROM_W0_MACMID 37
|
||||
#define SROM_W0_MACLO 38
|
||||
|
||||
/* Words 39-41: enet0 MAC address */
|
||||
#define SROM_E0_MACHI 39
|
||||
#define SROM_E0_MACMID 40
|
||||
#define SROM_E0_MACLO 41
|
||||
|
||||
/* Words 42-44: enet1 MAC address */
|
||||
#define SROM_E1_MACHI 42
|
||||
#define SROM_E1_MACMID 43
|
||||
#define SROM_E1_MACLO 44
|
||||
|
||||
/* Words 42-44: wireless1 MAC address on 4309 */
|
||||
#define SROM_W1_MACHI 42
|
||||
#define SROM_W1_MACMID 43
|
||||
#define SROM_W1_MACLO 44
|
||||
|
||||
#define SROM_EPHY 45
|
||||
|
||||
/* Word 46: BdRev & Antennas0/1 & ccLock for 430x */
|
||||
#define SROM_REV_AA_LOCK 46
|
||||
|
||||
/* Words 47-51 wl0 PA bx */
|
||||
#define SROM_WL0_PAB0 47
|
||||
#define SROM_WL0_PAB1 48
|
||||
#define SROM_WL0_PAB2 49
|
||||
#define SROM_WL0_PAB3 50
|
||||
#define SROM_WL0_PAB4 51
|
||||
|
||||
/* Word 52: wl0/wl1 MaxPower */
|
||||
#define SROM_WL_MAXPWR 52
|
||||
|
||||
/* Words 53-55 wl1 PA bx */
|
||||
#define SROM_WL1_PAB0 53
|
||||
#define SROM_WL1_PAB1 54
|
||||
#define SROM_WL1_PAB2 55
|
||||
|
||||
/* Woprd 56: itt */
|
||||
#define SROM_ITT 56
|
||||
|
||||
/* Words 59-62: OEM Space */
|
||||
#define SROM_WL_OEM 59
|
||||
#define SROM_OEM_SIZE 4
|
||||
|
||||
/* Contents for the srom */
|
||||
|
||||
#define BU4710_SSID 0x0400
|
||||
#define VSIM4710_SSID 0x0401
|
||||
#define QT4710_SSID 0x0402
|
||||
|
||||
#define BU4610_SSID 0x0403
|
||||
#define VSIM4610_SSID 0x0404
|
||||
|
||||
#define BU4307_SSID 0x0405
|
||||
#define BCM94301CB_SSID 0x0406
|
||||
#define BCM94301MP_SSID 0x0407
|
||||
#define BCM94307MP_SSID 0x0408
|
||||
#define AP4307_SSID 0x0409
|
||||
|
||||
#define BU4309_SSID 0x040a
|
||||
#define BCM94309CB_SSID 0x040b
|
||||
#define BCM94309MP_SSID 0x040c
|
||||
#define AP4309_SSID 0x040d
|
||||
|
||||
#define BU4402_SSID 0x4402
|
||||
|
||||
#define CLASS_OTHER 0x8000
|
||||
#define CLASS_ETHER 0x0000
|
||||
#define CLASS_NET 0x0002
|
||||
#define CLASS_COMM 0x0007
|
||||
#define CLASS_MODEM 0x0300
|
||||
#define CLASS_MIPS 0x3000
|
||||
#define CLASS_PROC 0x000b
|
||||
#define CLASS_FLASH 0x0100
|
||||
#define CLASS_MEM 0x0005
|
||||
#define CLASS_SERIALBUS 0x000c
|
||||
#define CLASS_OHCI 0x0310
|
||||
|
||||
/* Broadcom IEEE MAC addresses are 00:90:4c:xx:xx:xx */
|
||||
#define MACHI 0x90
|
||||
|
||||
#define MACMID_BU4710I 0x4c17
|
||||
#define MACMID_BU4710E0 0x4c18
|
||||
#define MACMID_BU4710E1 0x4c19
|
||||
|
||||
#define MACMID_94710R1I 0x4c1a
|
||||
#define MACMID_94710R1E0 0x4c1b
|
||||
#define MACMID_94710R1E1 0x4c1c
|
||||
|
||||
#define MACMID_94710R4I 0x4c1d
|
||||
#define MACMID_94710R4E0 0x4c1e
|
||||
#define MACMID_94710R4E1 0x4c1f
|
||||
|
||||
#define MACMID_94710DEVI 0x4c20
|
||||
#define MACMID_94710DEVE0 0x4c21
|
||||
#define MACMID_94710DEVE1 0x4c22
|
||||
|
||||
#define MACMID_BU4402 0x4c23
|
||||
|
||||
#define MACMID_BU4610I 0x4c24
|
||||
#define MACMID_BU4610E0 0x4c25
|
||||
#define MACMID_BU4610E1 0x4c26
|
||||
|
||||
#define MACMID_BU4307W 0x4c27
|
||||
#define MACMID_BU4307E 0x4c28
|
||||
|
||||
#define MACMID_94301CB 0x4c29
|
||||
|
||||
#define MACMID_94301MP 0x4c2a
|
||||
|
||||
#define MACMID_94307MPW 0x4c2b
|
||||
#define MACMID_94307MPE 0x4c2c
|
||||
|
||||
#define MACMID_AP4307W 0x4c2d
|
||||
#define MACMID_AP4307E 0x4c2e
|
||||
|
||||
#define MACMID_BU4309W0 0x4c2f
|
||||
#define MACMID_BU4309W1 0x4c30
|
||||
#define MACMID_BU4309E 0x4c31
|
||||
|
||||
#define MACMID_94309CBW0 0x4c32
|
||||
#define MACMID_94309CBW1 0x4c33
|
||||
|
||||
#define MACMID_94309MPW0 0x4c34
|
||||
#define MACMID_94309MPW1 0x4c35
|
||||
#define MACMID_94309MPE 0x4c36
|
||||
|
||||
#define MACMID_BU4401 0x4c37
|
||||
|
||||
/* Enet phy settings one or two singles or a dual */
|
||||
/* Bits 4-0 : MII address for enet0 (0x1f for not there */
|
||||
/* Bits 9-5 : MII address for enet1 (0x1f for not there */
|
||||
/* Bit 14 : Mdio for enet0 */
|
||||
/* Bit 15 : Mdio for enet1 */
|
||||
|
||||
/* bu4710 with only one phy on enet1 with address 7: */
|
||||
#define SROM_EPHY_ONE 0x80ff
|
||||
|
||||
/* bu4710 with two individual phys, at 6 and 7, */
|
||||
/* each mdio connected to its own mac: */
|
||||
#define SROM_EPHY_TWO 0x80e6
|
||||
|
||||
/* bu4710 with a dual phy addresses 0 & 1, mdio-connected to enet0 */
|
||||
#define SROM_EPHY_DUAL 0x0001
|
||||
|
||||
/* r1 board with a dual phy at 0, 1 (NOT swapped and mdc0 */
|
||||
#define SROM_EPHY_R1 0x0010
|
||||
|
||||
/* r4 board with a single phy on enet0 at address 5 and a switch */
|
||||
/* chip on enet1 (speciall case: 0x1e */
|
||||
#define SROM_EPHY_R4 0x83e5
|
||||
|
||||
/* 4402 uses an internal phy at phyaddr 1; want mdcport == coreunit == 0 */
|
||||
#define SROM_EPHY_INTERNAL 0x0001
|
||||
|
||||
/* 4307 uses an external phy at phyaddr 0; want mdcport == coreunit == 0 */
|
||||
#define SROM_EPHY_ZERO 0x0000
|
||||
|
||||
#define SROM_VERS 0x0001
|
||||
|
||||
|
||||
#endif /* _SBSPROM_H */
|
|
@ -2,7 +2,7 @@
|
|||
* Misc utility routines for accessing chip-specific features
|
||||
* of Broadcom HNBU SiliconBackplane-based chips.
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -10,14 +10,14 @@
|
|||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id: sbutils.h,v 1.4 2006/04/08 07:12:42 honor Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _sbutils_h_
|
||||
#define _sbutils_h_
|
||||
|
||||
/*
|
||||
* Datastructure to export all chip specific common variables
|
||||
* Data structure to export all chip specific common variables
|
||||
* public (read-only) portion of sbutils handle returned by
|
||||
* sb_attach()/sb_kattach()
|
||||
*/
|
||||
|
@ -29,15 +29,22 @@ struct sb_pub {
|
|||
uint buscorerev; /* buscore rev */
|
||||
uint buscoreidx; /* buscore index */
|
||||
int ccrev; /* chip common core rev */
|
||||
uint32 cccaps; /* chip common capabilities */
|
||||
int pmurev; /* pmu core rev */
|
||||
uint32 pmucaps; /* pmu capabilities */
|
||||
uint boardtype; /* board type */
|
||||
uint boardvendor; /* board vendor */
|
||||
uint boardflags; /* board flags */
|
||||
uint chip; /* chip number */
|
||||
uint chiprev; /* chip revision */
|
||||
uint chippkg; /* chip package option */
|
||||
uint32 chipst; /* chip status */
|
||||
uint sonicsrev; /* sonics backplane rev */
|
||||
bool pr42780; /* whether PCIE 42780 WAR applies to this chip */
|
||||
bool pr32414; /* whether 432414 WAR applis to the chip */
|
||||
};
|
||||
|
||||
typedef const struct sb_pub sb_t;
|
||||
typedef const struct sb_pub sb_t;
|
||||
|
||||
/*
|
||||
* Many of the routines below take an 'sbh' handle as their first arg.
|
||||
|
@ -48,10 +55,11 @@ typedef const struct sb_pub sb_t;
|
|||
*/
|
||||
|
||||
#define SB_OSH NULL /* Use for sb_kattach when no osh is available */
|
||||
|
||||
/* exported externs */
|
||||
extern sb_t *sb_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
|
||||
void *sdh, char **vars, uint *varsz);
|
||||
extern sb_t *sb_kattach(void);
|
||||
extern sb_t *sb_kattach(osl_t *osh);
|
||||
extern void sb_detach(sb_t *sbh);
|
||||
extern uint sb_chip(sb_t *sbh);
|
||||
extern uint sb_chiprev(sb_t *sbh);
|
||||
|
@ -67,16 +75,20 @@ extern uint sb_buscoretype(sb_t *sbh);
|
|||
extern uint sb_buscorerev(sb_t *sbh);
|
||||
extern uint sb_corelist(sb_t *sbh, uint coreid[]);
|
||||
extern uint sb_coreid(sb_t *sbh);
|
||||
extern uint sb_flag(sb_t *sbh);
|
||||
extern uint sb_coreidx(sb_t *sbh);
|
||||
extern uint sb_coreunit(sb_t *sbh);
|
||||
extern uint sb_corevendor(sb_t *sbh);
|
||||
extern uint sb_corerev(sb_t *sbh);
|
||||
extern void *sb_osh(sb_t *sbh);
|
||||
extern void sb_setosh(sb_t *sbh, osl_t *osh);
|
||||
extern uint sb_corereg(sb_t *sbh, uint coreidx, uint regoff, uint mask, uint val);
|
||||
extern void *sb_coreregs(sb_t *sbh);
|
||||
extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
|
||||
extern void sb_coreflags_wo(sb_t *sbh, uint32 mask, uint32 val);
|
||||
extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
|
||||
extern bool sb_iscoreup(sb_t *sbh);
|
||||
extern uint sb_findcoreidx(sb_t *sbh, uint coreid, uint coreunit);
|
||||
extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
|
||||
extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
|
||||
extern int sb_corebist(sb_t *sbh);
|
||||
|
@ -88,6 +100,7 @@ extern void sb_core_tofixup(sb_t *sbh);
|
|||
extern void sb_core_disable(sb_t *sbh, uint32 bits);
|
||||
extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
|
||||
extern uint32 sb_clock(sb_t *sbh);
|
||||
extern uint32 sb_alp_clock(sb_t *sbh);
|
||||
extern void sb_pci_setup(sb_t *sbh, uint coremask);
|
||||
extern void sb_pcmcia_init(sb_t *sbh);
|
||||
extern void sb_watchdog(sb_t *sbh, uint ticks);
|
||||
|
@ -101,6 +114,17 @@ extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
|
|||
extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
|
||||
extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
|
||||
extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
|
||||
extern uint32 sb_gpiopull(sb_t *sbh, bool updown, uint32 mask, uint32 val);
|
||||
extern uint32 sb_gpioevent(sb_t *sbh, uint regtype, uint32 mask, uint32 val);
|
||||
extern uint32 sb_gpio_int_enable(sb_t *sbh, bool enable);
|
||||
|
||||
/* GPIO event handlers */
|
||||
typedef void (*gpio_handler_t)(uint32 stat, void *arg);
|
||||
|
||||
extern void *sb_gpio_handler_register(sb_t *sbh, uint32 event,
|
||||
bool level, gpio_handler_t cb, void *arg);
|
||||
extern void sb_gpio_handler_unregister(sb_t *sbh, void* gpioh);
|
||||
extern void sb_gpio_handler_process(sb_t *sbh);
|
||||
|
||||
extern void sb_clkctl_init(sb_t *sbh);
|
||||
extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
|
||||
|
@ -108,7 +132,9 @@ extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
|
|||
extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
|
||||
extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn,
|
||||
void *intrsenabled_fn, void *intr_arg);
|
||||
extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
|
||||
extern void sb_deregister_intr_callback(sb_t *sbh);
|
||||
extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to, uint idx);
|
||||
extern uint16 sb_d11_devid(sb_t *sbh);
|
||||
extern int sb_corepciid(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice,
|
||||
uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif,
|
||||
uint8 *pciheader);
|
||||
|
@ -119,7 +145,19 @@ extern bool sb_backplane64(sb_t *sbh);
|
|||
extern void sb_btcgpiowar(sb_t *sbh);
|
||||
|
||||
|
||||
#if defined(BCMDBG_ASSERT)
|
||||
extern bool sb_taclear(sb_t *sbh);
|
||||
#endif
|
||||
|
||||
#ifdef BCMDBG
|
||||
extern void sb_dump(sb_t *sbh, struct bcmstrbuf *b);
|
||||
extern void sb_dumpregs(sb_t *sbh, struct bcmstrbuf *b);
|
||||
extern void sb_view(sb_t *sbh);
|
||||
extern void sb_viewall(sb_t *sbh);
|
||||
extern void sb_clkctl_dump(sb_t *sbh, struct bcmstrbuf *b);
|
||||
extern uint8 sb_pcieL1plldown(sb_t *sbh);
|
||||
extern uint32 sb_pcielcreg(sb_t *sbh, uint32 mask, uint32 val);
|
||||
#endif
|
||||
|
||||
extern bool sb_deviceremoved(sb_t *sbh);
|
||||
extern uint32 sb_socram_size(sb_t *sbh);
|
||||
|
@ -130,6 +168,20 @@ extern uint32 sb_socram_size(sb_t *sbh);
|
|||
* Return 0 on success, nonzero otherwise.
|
||||
*/
|
||||
extern int sb_devpath(sb_t *sbh, char *path, int size);
|
||||
/* Read variable with prepending the devpath to the name */
|
||||
extern char *sb_getdevpathvar(sb_t *sbh, const char *name);
|
||||
extern int sb_getdevpathintvar(sb_t *sbh, const char *name);
|
||||
|
||||
extern uint8 sb_pcieclkreq(sb_t *sbh, uint32 mask, uint32 val);
|
||||
extern void sb_war42780_clkreq(sb_t *sbh, bool clkreq);
|
||||
extern void sb_pci_sleep(sb_t *sbh);
|
||||
extern void sb_pci_down(sb_t *sbh);
|
||||
extern void sb_pci_up(sb_t *sbh);
|
||||
|
||||
/* Wake-on-wireless-LAN (WOWL) */
|
||||
extern bool sb_pci_pmecap(sb_t *sbh);
|
||||
extern bool sb_pci_pmeclr(sb_t *sbh);
|
||||
extern void sb_pci_pmeen(sb_t *sbh);
|
||||
|
||||
/* clkctl xtal what flags */
|
||||
#define XTAL 0x1 /* primary crystal oscillator (2050) */
|
||||
|
@ -143,7 +195,16 @@ extern int sb_devpath(sb_t *sbh, char *path, int size);
|
|||
/* GPIO usage priorities */
|
||||
#define GPIO_DRV_PRIORITY 0 /* Driver */
|
||||
#define GPIO_APP_PRIORITY 1 /* Application */
|
||||
#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO reservation */
|
||||
#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO reservation */
|
||||
|
||||
/* GPIO pull up/down */
|
||||
#define GPIO_PULLUP 0
|
||||
#define GPIO_PULLDN 1
|
||||
|
||||
/* GPIO event regtype */
|
||||
#define GPIO_REGEVT 0 /* GPIO register event */
|
||||
#define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
|
||||
#define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
|
||||
|
||||
/* device path */
|
||||
#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Broadcom SiliconBackplane chipcommon serial flash interface
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -9,7 +9,7 @@
|
|||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id: sflash.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _sflash_h_
|
||||
|
@ -17,6 +17,7 @@
|
|||
|
||||
#include <typedefs.h>
|
||||
#include <sbchipc.h>
|
||||
#include <sbutils.h>
|
||||
|
||||
struct sflash {
|
||||
uint blocksize; /* Block size */
|
||||
|
@ -26,11 +27,14 @@ struct sflash {
|
|||
};
|
||||
|
||||
/* Utility functions */
|
||||
extern int sflash_poll(chipcregs_t *cc, uint offset);
|
||||
extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
|
||||
extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
|
||||
extern int sflash_erase(chipcregs_t *cc, uint offset);
|
||||
extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
|
||||
extern struct sflash * sflash_init(chipcregs_t *cc);
|
||||
extern int sflash_poll(sb_t *sbh, chipcregs_t *cc, uint offset);
|
||||
extern int sflash_read(sb_t *sbh, chipcregs_t *cc,
|
||||
uint offset, uint len, uchar *buf);
|
||||
extern int sflash_write(sb_t *sbh, chipcregs_t *cc,
|
||||
uint offset, uint len, const uchar *buf);
|
||||
extern int sflash_erase(sb_t *sbh, chipcregs_t *cc, uint offset);
|
||||
extern int sflash_commit(sb_t *sbh, chipcregs_t *cc,
|
||||
uint offset, uint len, const uchar *buf);
|
||||
extern struct sflash *sflash_init(sb_t *sbh, chipcregs_t *cc);
|
||||
|
||||
#endif /* _sflash_h_ */
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* TRX image file header format.
|
||||
*
|
||||
* Copyright 2005, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
|
@ -10,16 +10,16 @@
|
|||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
*/
|
||||
|
||||
#include <typedefs.h>
|
||||
|
||||
#define TRX_MAGIC 0x30524448 /* "HDR0" */
|
||||
#define TRX_VERSION 1
|
||||
#define TRX_MAX_LEN 0x3A0000
|
||||
#define TRX_NO_HEADER 1 /* Do not write TRX header */
|
||||
#define TRX_VERSION 1 /* Version 1 */
|
||||
#define TRX_MAX_LEN 0x7A0000 /* Max length */
|
||||
#define TRX_NO_HEADER 1 /* Do not write TRX header */
|
||||
#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
|
||||
#define TRX_MAX_OFFSET 3
|
||||
#define TRX_MAX_OFFSET 3 /* Max number of individual files */
|
||||
|
||||
struct trx_header {
|
||||
uint32 magic; /* "HDR0" */
|
||||
|
|
|
@ -1,12 +1,12 @@
|
|||
/*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
* $Id: typedefs.h,v 1.1.1.12 2006/04/08 06:13:40 honor Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _TYPEDEFS_H_
|
||||
|
@ -69,10 +69,13 @@ typedef unsigned char bool; /* consistent w/BOOL */
|
|||
#endif /* ! __cplusplus */
|
||||
|
||||
/* use the Windows ULONG_PTR type when compiling for 64 bit */
|
||||
#if defined(_WIN64)
|
||||
#if defined(_WIN64) && !defined(EFI)
|
||||
#include <basetsd.h>
|
||||
#define TYPEDEF_UINTPTR
|
||||
typedef ULONG_PTR uintptr;
|
||||
typedef ULONG_PTR uintptr;
|
||||
#elif defined(__x86_64__)
|
||||
#define TYPEDEF_UINTPTR
|
||||
typedef unsigned long long int uintptr;
|
||||
#endif
|
||||
|
||||
|
||||
|
@ -80,6 +83,10 @@ typedef ULONG_PTR uintptr;
|
|||
#define _NEED_SIZE_T_
|
||||
#endif
|
||||
|
||||
#if defined(EFI) && !defined(_WIN64)
|
||||
#define _NEED_SIZE_T_
|
||||
#endif
|
||||
|
||||
#if defined(_NEED_SIZE_T_)
|
||||
typedef long unsigned int size_t;
|
||||
#endif
|
||||
|
@ -104,14 +111,20 @@ typedef unsigned __int64 uint64;
|
|||
#endif
|
||||
|
||||
|
||||
#if defined(linux)
|
||||
#ifdef linux
|
||||
#define TYPEDEF_UINT
|
||||
#define TYPEDEF_USHORT
|
||||
#define TYPEDEF_ULONG
|
||||
#endif
|
||||
#ifdef __KERNEL__
|
||||
#include <linux/version.h>
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19))
|
||||
#define TYPEDEF_BOOL
|
||||
#endif /* >= 2.6.19 */
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* linux */
|
||||
|
||||
#if !defined(linux) && !defined(_WIN32) && !defined(_CFE_) && \
|
||||
!defined(_HNDRTE_) && !defined(_MINOSL_) && !defined(__DJGPP__)
|
||||
!defined(_HNDRTE_) && !defined(_MINOSL_) && !defined(__DJGPP__) && !defined(__IOPOS__)
|
||||
#define TYPEDEF_UINT
|
||||
#define TYPEDEF_USHORT
|
||||
#endif
|
||||
|
@ -137,7 +150,7 @@ typedef unsigned __int64 uint64;
|
|||
#endif /* __ICL */
|
||||
|
||||
#if !defined(_WIN32) && !defined(_CFE_) && !defined(_MINOSL_) && \
|
||||
!defined(__DJGPP__)
|
||||
!defined(__DJGPP__) && !defined(__IOPOS__)
|
||||
|
||||
/* pick up ushort & uint from standard types.h */
|
||||
#if defined(linux) && defined(__KERNEL__)
|
||||
|
@ -150,7 +163,7 @@ typedef unsigned __int64 uint64;
|
|||
|
||||
#endif
|
||||
|
||||
#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ && !__DJGPP__ */
|
||||
#endif
|
||||
|
||||
#if defined(MACOSX)
|
||||
|
||||
|
@ -320,7 +333,7 @@ typedef float64 float_t;
|
|||
|
||||
#define INLINE __inline
|
||||
|
||||
#elif __GNUC__
|
||||
#elif defined(__GNUC__)
|
||||
|
||||
#define INLINE __inline__
|
||||
|
||||
|
@ -353,8 +366,8 @@ typedef float64 float_t;
|
|||
#endif /* USE_TYPEDEF_DEFAULTS */
|
||||
|
||||
/*
|
||||
* Including the bcmdefs.h here, to make sure everyone including typedefs.h
|
||||
* gets this automatically
|
||||
* Including the bcmdefs.h here, to make sure everyone including typedefs.h
|
||||
* gets this automatically
|
||||
*/
|
||||
#include "bcmdefs.h"
|
||||
|
||||
|
|
|
@ -15,7 +15,6 @@
|
|||
#include <osl.h>
|
||||
#include <bcmendian.h>
|
||||
#include <bcmnvram.h>
|
||||
#include <bcmutils.h>
|
||||
#include <sbsdram.h>
|
||||
|
||||
extern struct nvram_tuple * BCMINIT(_nvram_realloc)(struct nvram_tuple *t, const char *name, const char *value);
|
||||
|
@ -244,10 +243,10 @@ BCMINITFN(_nvram_commit)(struct nvram_header *header)
|
|||
header->config_refresh |= SDRAM_REFRESH << 16;
|
||||
header->config_ncdl = 0;
|
||||
} else {
|
||||
header->crc_ver_init |= (bcm_strtoul(init, NULL, 0) & 0xffff) << 16;
|
||||
header->config_refresh = bcm_strtoul(config, NULL, 0) & 0xffff;
|
||||
header->config_refresh |= (bcm_strtoul(refresh, NULL, 0) & 0xffff) << 16;
|
||||
header->config_ncdl = bcm_strtoul(ncdl, NULL, 0);
|
||||
header->crc_ver_init |= (simple_strtoul(init, NULL, 0) & 0xffff) << 16;
|
||||
header->config_refresh = simple_strtoul(config, NULL, 0) & 0xffff;
|
||||
header->config_refresh |= (simple_strtoul(refresh, NULL, 0) & 0xffff) << 16;
|
||||
header->config_ncdl = simple_strtoul(ncdl, NULL, 0);
|
||||
}
|
||||
|
||||
/* Clear data area */
|
||||
|
@ -276,7 +275,7 @@ BCMINITFN(_nvram_commit)(struct nvram_header *header)
|
|||
tmp.crc_ver_init = htol32(header->crc_ver_init);
|
||||
tmp.config_refresh = htol32(header->config_refresh);
|
||||
tmp.config_ncdl = htol32(header->config_ncdl);
|
||||
crc = hndcrc8((char *) &tmp + 9, sizeof(struct nvram_header) - 9, CRC8_INIT_VALUE);
|
||||
crc = hndcrc8((char *) &tmp + 9, sizeof(struct nvram_header) - 9, 0xff);
|
||||
|
||||
/* Continue CRC8 over data bytes */
|
||||
crc = hndcrc8((char *) &header[1], header->len - sizeof(struct nvram_header), crc);
|
||||
|
@ -313,3 +312,46 @@ BCMINITFN(_nvram_exit)(void)
|
|||
{
|
||||
BCMINIT(nvram_free)();
|
||||
}
|
||||
|
||||
/*
|
||||
* Search the name=value vars for a specific one and return its value.
|
||||
* Returns NULL if not found.
|
||||
*/
|
||||
char*
|
||||
getvar(char *vars, const char *name)
|
||||
{
|
||||
char *s;
|
||||
int len;
|
||||
|
||||
len = strlen(name);
|
||||
|
||||
/* first look in vars[] */
|
||||
for (s = vars; s && *s;) {
|
||||
/* CSTYLED */
|
||||
if ((memcmp(s, name, len) == 0) && (s[len] == '='))
|
||||
return (&s[len+1]);
|
||||
|
||||
while (*s++)
|
||||
;
|
||||
}
|
||||
|
||||
/* then query nvram */
|
||||
return (nvram_get(name));
|
||||
}
|
||||
|
||||
/*
|
||||
* Search the vars for a specific one and return its value as
|
||||
* an integer. Returns 0 if not found.
|
||||
*/
|
||||
int
|
||||
getintvar(char *vars, const char *name)
|
||||
{
|
||||
char *val;
|
||||
|
||||
if ((val = getvar(vars, name)) == NULL)
|
||||
return (0);
|
||||
|
||||
return (simple_strtoul(val, NULL, 0));
|
||||
}
|
||||
|
||||
|
||||
|
|
|
@ -33,7 +33,6 @@
|
|||
#include <osl.h>
|
||||
#include <bcmendian.h>
|
||||
#include <bcmnvram.h>
|
||||
#include <bcmutils.h>
|
||||
#include <sbconfig.h>
|
||||
#include <sbchipc.h>
|
||||
#include <sbutils.h>
|
||||
|
@ -53,6 +52,9 @@ static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
|
|||
extern void *bcm947xx_sbh;
|
||||
extern spinlock_t bcm947xx_sbh_lock;
|
||||
|
||||
static int cfe_env;
|
||||
extern char *cfe_env_get(char *nv_buf, const char *name);
|
||||
|
||||
/* Convenience */
|
||||
#define sbh bcm947xx_sbh
|
||||
#define sbh_lock bcm947xx_sbh_lock
|
||||
|
@ -72,14 +74,14 @@ early_nvram_init(void)
|
|||
|
||||
if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
|
||||
base = KSEG1ADDR(SB_FLASH2);
|
||||
switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
|
||||
switch (readl(&cc->capabilities) & CC_CAP_FLASH_MASK) {
|
||||
case PFLASH:
|
||||
lim = SB_FLASH2_SZ;
|
||||
break;
|
||||
|
||||
case SFLASH_ST:
|
||||
case SFLASH_AT:
|
||||
if ((info = sflash_init(cc)) == NULL)
|
||||
if ((info = sflash_init(sbh,cc)) == NULL)
|
||||
return;
|
||||
lim = info->size;
|
||||
break;
|
||||
|
@ -105,6 +107,7 @@ early_nvram_init(void)
|
|||
break;
|
||||
*dst++ = *src++;
|
||||
}
|
||||
cfe_env = 1;
|
||||
return;
|
||||
}
|
||||
|
||||
|
@ -154,6 +157,9 @@ early_nvram_get(const char *name)
|
|||
if (!nvram_buf[0])
|
||||
early_nvram_init();
|
||||
|
||||
if (cfe_env)
|
||||
return cfe_env_get(nvram_buf, name);
|
||||
|
||||
/* Look for name=value and return value */
|
||||
var = &nvram_buf[sizeof(struct nvram_header)];
|
||||
end = nvram_buf + sizeof(nvram_buf) - 2;
|
||||
|
|
|
@ -25,7 +25,6 @@
|
|||
|
||||
#include <typedefs.h>
|
||||
#include <osl.h>
|
||||
#include <bcmutils.h>
|
||||
#include <sbconfig.h>
|
||||
#include <sbutils.h>
|
||||
#include <hndpci.h>
|
||||
|
@ -134,7 +133,7 @@ pcibios_init(void)
|
|||
{
|
||||
ulong flags;
|
||||
|
||||
if (!(sbh = sb_kattach()))
|
||||
if (!(sbh = sb_kattach(SB_OSH)))
|
||||
panic("sb_kattach failed");
|
||||
spin_lock_init(&sbh_lock);
|
||||
|
||||
|
@ -312,6 +311,25 @@ pcibios_enable_device(struct pci_dev *dev, int mask)
|
|||
writel(0x7FF, (ulong)regs + 0x200);
|
||||
udelay(1);
|
||||
}
|
||||
/* PRxxxx: War for 5354 failures. */
|
||||
if (sb_corerev(sbh) == 1) {
|
||||
uint32 tmp;
|
||||
|
||||
/* Change Flush control reg */
|
||||
tmp = readl((uintptr)regs + 0x400);
|
||||
tmp &= ~8;
|
||||
writel(tmp, (uintptr)regs + 0x400);
|
||||
tmp = readl((uintptr)regs + 0x400);
|
||||
printk("USB20H fcr: 0x%x\n", tmp);
|
||||
|
||||
/* Change Shim control reg */
|
||||
tmp = readl((uintptr)regs + 0x304);
|
||||
tmp &= ~0x100;
|
||||
writel(tmp, (uintptr)regs + 0x304);
|
||||
tmp = readl((uintptr)regs + 0x304);
|
||||
printk("USB20H shim cr: 0x%x\n", tmp);
|
||||
}
|
||||
|
||||
} else
|
||||
sb_core_reset(sbh, 0, 0);
|
||||
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -17,7 +17,6 @@
|
|||
#include <pcicfg.h>
|
||||
#include <bcmdevs.h>
|
||||
#include <sbconfig.h>
|
||||
#include <bcmutils.h>
|
||||
#include <sbutils.h>
|
||||
#include <sbpci.h>
|
||||
#include <bcmendian.h>
|
||||
|
@ -31,7 +30,7 @@
|
|||
#define PCI_MSG(args) printf args
|
||||
#else
|
||||
#define PCI_MSG(args)
|
||||
#endif /* BCMDBG_PCI */
|
||||
#endif /* BCMDBG_PCI */
|
||||
|
||||
/* Can free sbpci_init() memory after boot */
|
||||
#ifndef linux
|
||||
|
@ -40,11 +39,11 @@
|
|||
|
||||
/* Emulated configuration space */
|
||||
typedef struct {
|
||||
int n;
|
||||
uint size0;
|
||||
uint size1;
|
||||
uint size2;
|
||||
uint size3;
|
||||
int n;
|
||||
uint size0;
|
||||
uint size1;
|
||||
uint size2;
|
||||
uint size3;
|
||||
} sb_bar_cfg_t;
|
||||
static pci_config_regs sb_config_regs[SB_MAXCORES];
|
||||
static sb_bar_cfg_t sb_bar_cfg[SB_MAXCORES];
|
||||
|
@ -86,10 +85,9 @@ static uint8 pci_hbslot = 0;
|
|||
*/
|
||||
|
||||
/* Assume one-hot slot wiring */
|
||||
#define PCI_SLOT_MAX 16 /* Max. PCI Slots */
|
||||
#define PCI_SLOT_MAX 16 /* Max. PCI Slots */
|
||||
|
||||
static uint32
|
||||
config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
|
||||
static uint32 config_cmd(sb_t * sbh, uint bus, uint dev, uint func, uint off)
|
||||
{
|
||||
uint coreidx;
|
||||
sbpciregs_t *regs;
|
||||
|
@ -112,21 +110,21 @@ config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
|
|||
uint32 win;
|
||||
|
||||
/* Slide the PCI window to the appropriate slot */
|
||||
win = (SBTOPCI_CFG0 | ((1 << (dev + PCI_SLOTAD_MAP)) & SBTOPCI1_MASK));
|
||||
win =
|
||||
(SBTOPCI_CFG0 |
|
||||
((1 << (dev + PCI_SLOTAD_MAP)) & SBTOPCI1_MASK));
|
||||
W_REG(osh, ®s->sbtopci1, win);
|
||||
addr = SB_PCI_CFG |
|
||||
((1 << (dev + PCI_SLOTAD_MAP)) & ~SBTOPCI1_MASK) |
|
||||
(func << PCICFG_FUN_SHIFT) |
|
||||
(off & ~3);
|
||||
((1 << (dev + PCI_SLOTAD_MAP)) & ~SBTOPCI1_MASK) |
|
||||
(func << PCICFG_FUN_SHIFT) | (off & ~3);
|
||||
}
|
||||
} else {
|
||||
/* Type 1 transaction */
|
||||
W_REG(osh, ®s->sbtopci1, SBTOPCI_CFG1);
|
||||
addr = SB_PCI_CFG |
|
||||
(bus << PCICFG_BUS_SHIFT) |
|
||||
(dev << PCICFG_SLOT_SHIFT) |
|
||||
(func << PCICFG_FUN_SHIFT) |
|
||||
(off & ~3);
|
||||
(bus << PCICFG_BUS_SHIFT) |
|
||||
(dev << PCICFG_SLOT_SHIFT) |
|
||||
(func << PCICFG_FUN_SHIFT) | (off & ~3);
|
||||
}
|
||||
|
||||
sb_setcoreidx(sbh, coreidx);
|
||||
|
@ -145,8 +143,8 @@ config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
|
|||
* the register address where value in 'val' is read.
|
||||
*/
|
||||
static bool
|
||||
sb_pcihb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off,
|
||||
uint32 **addr, uint32 *val)
|
||||
sb_pcihb_read_config(sb_t * sbh, uint bus, uint dev, uint func, uint off,
|
||||
uint32 ** addr, uint32 * val)
|
||||
{
|
||||
sbpciregs_t *regs;
|
||||
osl_t *osh;
|
||||
|
@ -162,9 +160,9 @@ sb_pcihb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off,
|
|||
|
||||
/* read pci config when core rev >= 8 */
|
||||
coreidx = sb_coreidx(sbh);
|
||||
regs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
|
||||
regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
|
||||
if (regs && sb_corerev(sbh) >= PCI_HBSBCFG_REV) {
|
||||
*addr = (uint32 *)®s->pcicfg[func][off >> 2];
|
||||
*addr = (uint32 *) & regs->pcicfg[func][off >> 2];
|
||||
*val = R_REG(osh, *addr);
|
||||
ret = TRUE;
|
||||
}
|
||||
|
@ -174,30 +172,30 @@ sb_pcihb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off,
|
|||
}
|
||||
|
||||
int
|
||||
extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
|
||||
extpci_read_config(sb_t * sbh, uint bus, uint dev, uint func, uint off,
|
||||
void *buf, int len)
|
||||
{
|
||||
uint32 addr = 0, *reg = NULL, val;
|
||||
int ret = 0;
|
||||
|
||||
/*
|
||||
* Set value to -1 when:
|
||||
* flag 'pci_disabled' is true;
|
||||
* value of 'addr' is zero;
|
||||
* REG_MAP() fails;
|
||||
* BUSPROBE() fails;
|
||||
* flag 'pci_disabled' is true;
|
||||
* value of 'addr' is zero;
|
||||
* REG_MAP() fails;
|
||||
* BUSPROBE() fails;
|
||||
*/
|
||||
if (pci_disabled)
|
||||
val = 0xffffffff;
|
||||
else if (bus == 1 && dev == pci_hbslot && func == 0 &&
|
||||
sb_pcihb_read_config(sbh, bus, dev, func, off, ®, &val))
|
||||
;
|
||||
sb_pcihb_read_config(sbh, bus, dev, func, off, ®, &val)) ;
|
||||
else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
|
||||
((reg = (uint32 *)REG_MAP(addr, len)) == 0) ||
|
||||
(BUSPROBE(val, reg) != 0))
|
||||
((reg = (uint32 *) REG_MAP(addr, len)) == 0) ||
|
||||
(BUSPROBE(val, reg) != 0))
|
||||
val = 0xffffffff;
|
||||
|
||||
PCI_MSG(("%s: 0x%x <= 0x%p(0x%x), len %d, off 0x%x, buf 0x%p\n",
|
||||
__FUNCTION__, val, reg, addr, len, off, buf));
|
||||
__FUNCTION__, val, reg, addr, len, off, buf));
|
||||
|
||||
val >>= 8 * (off & 3);
|
||||
if (len == 4)
|
||||
|
@ -216,7 +214,8 @@ extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf
|
|||
}
|
||||
|
||||
int
|
||||
extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
|
||||
extpci_write_config(sb_t * sbh, uint bus, uint dev, uint func, uint off,
|
||||
void *buf, int len)
|
||||
{
|
||||
osl_t *osh;
|
||||
uint32 addr = 0, *reg = NULL, val;
|
||||
|
@ -226,19 +225,18 @@ extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *bu
|
|||
|
||||
/*
|
||||
* Ignore write attempt when:
|
||||
* flag 'pci_disabled' is true;
|
||||
* value of 'addr' is zero;
|
||||
* REG_MAP() fails;
|
||||
* BUSPROBE() fails;
|
||||
* flag 'pci_disabled' is true;
|
||||
* value of 'addr' is zero;
|
||||
* REG_MAP() fails;
|
||||
* BUSPROBE() fails;
|
||||
*/
|
||||
if (pci_disabled)
|
||||
return 0;
|
||||
else if (bus == 1 && dev == pci_hbslot && func == 0 &&
|
||||
sb_pcihb_read_config(sbh, bus, dev, func, off, ®, &val))
|
||||
;
|
||||
sb_pcihb_read_config(sbh, bus, dev, func, off, ®, &val)) ;
|
||||
else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
|
||||
((reg = (uint32 *) REG_MAP(addr, len)) == 0) ||
|
||||
(BUSPROBE(val, reg) != 0))
|
||||
((reg = (uint32 *) REG_MAP(addr, len)) == 0) ||
|
||||
(BUSPROBE(val, reg) != 0))
|
||||
goto done;
|
||||
|
||||
if (len == 4)
|
||||
|
@ -258,7 +256,7 @@ extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *bu
|
|||
|
||||
W_REG(osh, reg, val);
|
||||
|
||||
done:
|
||||
done:
|
||||
if (reg && addr)
|
||||
REG_UNMAP(reg);
|
||||
|
||||
|
@ -287,8 +285,8 @@ done:
|
|||
|
||||
/* Sync the emulation registers and the real PCI config registers. */
|
||||
static void
|
||||
sb_pcid_read_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
|
||||
uint off, uint len)
|
||||
sb_pcid_read_config(sb_t * sbh, uint coreidx, sb_pci_cfg_t * cfg,
|
||||
uint off, uint len)
|
||||
{
|
||||
osl_t *osh;
|
||||
uint oldidx;
|
||||
|
@ -308,21 +306,23 @@ sb_pcid_read_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
|
|||
sb_setcoreidx(sbh, coreidx);
|
||||
if (sb_iscoreup(sbh)) {
|
||||
if (len == 4)
|
||||
*(uint32 *)((ulong)cfg->emu + off) =
|
||||
htol32(R_REG(osh, (uint32 *)((ulong)cfg->pci + off)));
|
||||
*(uint32 *) ((ulong) cfg->emu + off) =
|
||||
htol32(R_REG
|
||||
(osh, (uint32 *) ((ulong) cfg->pci + off)));
|
||||
else if (len == 2)
|
||||
*(uint16 *)((ulong)cfg->emu + off) =
|
||||
htol16(R_REG(osh, (uint16 *)((ulong)cfg->pci + off)));
|
||||
*(uint16 *) ((ulong) cfg->emu + off) =
|
||||
htol16(R_REG
|
||||
(osh, (uint16 *) ((ulong) cfg->pci + off)));
|
||||
else if (len == 1)
|
||||
*(uint8 *)((ulong)cfg->emu + off) =
|
||||
R_REG(osh, (uint8 *)((ulong)cfg->pci + off));
|
||||
*(uint8 *) ((ulong) cfg->emu + off) =
|
||||
R_REG(osh, (uint8 *) ((ulong) cfg->pci + off));
|
||||
}
|
||||
sb_setcoreidx(sbh, oldidx);
|
||||
}
|
||||
|
||||
static void
|
||||
sb_pcid_write_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
|
||||
uint off, uint len)
|
||||
sb_pcid_write_config(sb_t * sbh, uint coreidx, sb_pci_cfg_t * cfg,
|
||||
uint off, uint len)
|
||||
{
|
||||
osl_t *osh;
|
||||
uint oldidx;
|
||||
|
@ -342,14 +342,14 @@ sb_pcid_write_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
|
|||
sb_setcoreidx(sbh, coreidx);
|
||||
if (sb_iscoreup(sbh)) {
|
||||
if (len == 4)
|
||||
W_REG(osh, (uint32 *)((ulong)cfg->pci + off),
|
||||
ltoh32(*(uint32 *)((ulong)cfg->emu + off)));
|
||||
W_REG(osh, (uint32 *) ((ulong) cfg->pci + off),
|
||||
ltoh32(*(uint32 *) ((ulong) cfg->emu + off)));
|
||||
else if (len == 2)
|
||||
W_REG(osh, (uint16 *)((ulong)cfg->pci + off),
|
||||
ltoh16(*(uint16 *)((ulong)cfg->emu + off)));
|
||||
W_REG(osh, (uint16 *) ((ulong) cfg->pci + off),
|
||||
ltoh16(*(uint16 *) ((ulong) cfg->emu + off)));
|
||||
else if (len == 1)
|
||||
W_REG(osh, (uint8 *)((ulong)cfg->pci + off),
|
||||
*(uint8 *)((ulong)cfg->emu + off));
|
||||
W_REG(osh, (uint8 *) ((ulong) cfg->pci + off),
|
||||
*(uint8 *) ((ulong) cfg->emu + off));
|
||||
}
|
||||
sb_setcoreidx(sbh, oldidx);
|
||||
}
|
||||
|
@ -358,16 +358,18 @@ sb_pcid_write_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
|
|||
* Functions for accessing translated SB configuration space
|
||||
*/
|
||||
static int
|
||||
sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
|
||||
sb_read_config(sb_t * sbh, uint bus, uint dev, uint func, uint off, void *buf,
|
||||
int len)
|
||||
{
|
||||
pci_config_regs *cfg;
|
||||
|
||||
if (dev >= SB_MAXCORES || func >= MAXFUNCS || (off + len) > sizeof(pci_config_regs))
|
||||
if (dev >= SB_MAXCORES || func >= MAXFUNCS
|
||||
|| (off + len) > sizeof(pci_config_regs))
|
||||
return -1;
|
||||
cfg = sb_pci_cfg[dev][func].emu;
|
||||
|
||||
ASSERT(ISALIGNED(off, len));
|
||||
ASSERT(ISALIGNED((uintptr)buf, len));
|
||||
ASSERT(ISALIGNED((uintptr) buf, len));
|
||||
|
||||
/* use special config space if the device does not exist */
|
||||
if (!cfg)
|
||||
|
@ -377,11 +379,11 @@ sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, in
|
|||
sb_pcid_read_config(sbh, dev, &sb_pci_cfg[dev][func], off, len);
|
||||
|
||||
if (len == 4)
|
||||
*((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
|
||||
*((uint32 *) buf) = ltoh32(*((uint32 *) ((ulong) cfg + off)));
|
||||
else if (len == 2)
|
||||
*((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
|
||||
*((uint16 *) buf) = ltoh16(*((uint16 *) ((ulong) cfg + off)));
|
||||
else if (len == 1)
|
||||
*((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
|
||||
*((uint8 *) buf) = *((uint8 *) ((ulong) cfg + off));
|
||||
else
|
||||
return -1;
|
||||
|
||||
|
@ -389,7 +391,8 @@ sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, in
|
|||
}
|
||||
|
||||
static int
|
||||
sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
|
||||
sb_write_config(sb_t * sbh, uint bus, uint dev, uint func, uint off, void *buf,
|
||||
int len)
|
||||
{
|
||||
uint coreidx;
|
||||
void *regs;
|
||||
|
@ -397,14 +400,15 @@ sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, i
|
|||
osl_t *osh;
|
||||
sb_bar_cfg_t *bar;
|
||||
|
||||
if (dev >= SB_MAXCORES || func >= MAXFUNCS || (off + len) > sizeof(pci_config_regs))
|
||||
if (dev >= SB_MAXCORES || func >= MAXFUNCS
|
||||
|| (off + len) > sizeof(pci_config_regs))
|
||||
return -1;
|
||||
cfg = sb_pci_cfg[dev][func].emu;
|
||||
if (!cfg)
|
||||
return -1;
|
||||
|
||||
ASSERT(ISALIGNED(off, len));
|
||||
ASSERT(ISALIGNED((uintptr)buf, len));
|
||||
ASSERT(ISALIGNED((uintptr) buf, len));
|
||||
|
||||
osh = sb_osh(sbh);
|
||||
|
||||
|
@ -418,33 +422,37 @@ sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, i
|
|||
/* Highest numbered address match register */
|
||||
if (off == OFFSETOF(pci_config_regs, base[0]))
|
||||
cfg->base[0] = ~(bar->size0 - 1);
|
||||
else if (off == OFFSETOF(pci_config_regs, base[1]) && bar->n >= 1)
|
||||
else if (off == OFFSETOF(pci_config_regs, base[1])
|
||||
&& bar->n >= 1)
|
||||
cfg->base[1] = ~(bar->size1 - 1);
|
||||
else if (off == OFFSETOF(pci_config_regs, base[2]) && bar->n >= 2)
|
||||
else if (off == OFFSETOF(pci_config_regs, base[2])
|
||||
&& bar->n >= 2)
|
||||
cfg->base[2] = ~(bar->size2 - 1);
|
||||
else if (off == OFFSETOF(pci_config_regs, base[3]) && bar->n >= 3)
|
||||
else if (off == OFFSETOF(pci_config_regs, base[3])
|
||||
&& bar->n >= 3)
|
||||
cfg->base[3] = ~(bar->size3 - 1);
|
||||
}
|
||||
sb_setcoreidx(sbh, coreidx);
|
||||
}
|
||||
else if (len == 4)
|
||||
*((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
|
||||
} else if (len == 4)
|
||||
*((uint32 *) ((ulong) cfg + off)) = htol32(*((uint32 *) buf));
|
||||
else if (len == 2)
|
||||
*((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
|
||||
*((uint16 *) ((ulong) cfg + off)) = htol16(*((uint16 *) buf));
|
||||
else if (len == 1)
|
||||
*((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
|
||||
*((uint8 *) ((ulong) cfg + off)) = *((uint8 *) buf);
|
||||
else
|
||||
return -1;
|
||||
|
||||
/* sync emulation with real PCI config if necessary */
|
||||
if (sb_pci_cfg[dev][func].pci)
|
||||
sb_pcid_write_config(sbh, dev, &sb_pci_cfg[dev][func], off, len);
|
||||
sb_pcid_write_config(sbh, dev, &sb_pci_cfg[dev][func], off,
|
||||
len);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
|
||||
sbpci_read_config(sb_t * sbh, uint bus, uint dev, uint func, uint off,
|
||||
void *buf, int len)
|
||||
{
|
||||
if (bus == 0)
|
||||
return sb_read_config(sbh, bus, dev, func, off, buf, len);
|
||||
|
@ -453,7 +461,8 @@ sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
|
|||
}
|
||||
|
||||
int
|
||||
sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
|
||||
sbpci_write_config(sb_t * sbh, uint bus, uint dev, uint func, uint off,
|
||||
void *buf, int len)
|
||||
{
|
||||
if (bus == 0)
|
||||
return sb_write_config(sbh, bus, dev, func, off, buf, len);
|
||||
|
@ -461,8 +470,7 @@ sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf
|
|||
return extpci_write_config(sbh, bus, dev, func, off, buf, len);
|
||||
}
|
||||
|
||||
void
|
||||
sbpci_ban(uint16 core)
|
||||
void sbpci_ban(uint16 core)
|
||||
{
|
||||
if (pci_banned < ARRAYSIZE(pci_ban))
|
||||
pci_ban[pci_banned++] = core;
|
||||
|
@ -473,8 +481,7 @@ sbpci_ban(uint16 core)
|
|||
* Otherwise return -1 to indicate there is no PCI core and return 1
|
||||
* to indicate PCI core is disabled.
|
||||
*/
|
||||
int __init
|
||||
sbpci_init_pci(sb_t *sbh)
|
||||
int __init sbpci_init_pci(sb_t * sbh)
|
||||
{
|
||||
uint chip, chiprev, chippkg, host;
|
||||
uint32 boardflags;
|
||||
|
@ -499,8 +506,8 @@ sbpci_init_pci(sb_t *sbh)
|
|||
|
||||
if ((chip == 0x4310) && (chiprev == 0))
|
||||
pci_disabled = TRUE;
|
||||
|
||||
sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
|
||||
|
||||
sb = (sbconfig_t *) ((ulong) pci + SBCONFIGOFF);
|
||||
|
||||
boardflags = (uint32) getintvar(NULL, "boardflags");
|
||||
|
||||
|
@ -511,8 +518,7 @@ sbpci_init_pci(sb_t *sbh)
|
|||
*/
|
||||
if (((chip == BCM4712_CHIP_ID) &&
|
||||
((chippkg == BCM4712SMALL_PKG_ID) ||
|
||||
(chippkg == BCM4712MID_PKG_ID))) ||
|
||||
(boardflags & BFL_NOPCI))
|
||||
(chippkg == BCM4712MID_PKG_ID))) || (boardflags & BFL_NOPCI))
|
||||
pci_disabled = TRUE;
|
||||
|
||||
/* Enable the core */
|
||||
|
@ -550,13 +556,13 @@ sbpci_init_pci(sb_t *sbh)
|
|||
}
|
||||
|
||||
/* Reset the external PCI bus and enable the clock */
|
||||
W_REG(osh, &pci->control, 0x5); /* enable the tristate drivers */
|
||||
W_REG(osh, &pci->control, 0xd); /* enable the PCI clock */
|
||||
OSL_DELAY(150); /* delay > 100 us */
|
||||
W_REG(osh, &pci->control, 0xf); /* deassert PCI reset */
|
||||
W_REG(osh, &pci->control, 0x5); /* enable the tristate drivers */
|
||||
W_REG(osh, &pci->control, 0xd); /* enable the PCI clock */
|
||||
OSL_DELAY(150); /* delay > 100 us */
|
||||
W_REG(osh, &pci->control, 0xf); /* deassert PCI reset */
|
||||
/* Use internal arbiter and park REQ/GRNT at external master 0 */
|
||||
W_REG(osh, &pci->arbcontrol, PCI_INT_ARB);
|
||||
OSL_DELAY(1); /* delay 1 us */
|
||||
OSL_DELAY(1); /* delay 1 us */
|
||||
if (sb_corerev(sbh) >= 8) {
|
||||
val = getintvar(NULL, "parkid");
|
||||
ASSERT(val <= PCI_PARKID_LAST);
|
||||
|
@ -571,7 +577,8 @@ sbpci_init_pci(sb_t *sbh)
|
|||
/* GPIO 1 resets the CardBus device on bcm94710ap */
|
||||
sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
|
||||
sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
|
||||
W_REG(osh, &pci->sprom[0], R_REG(osh, &pci->sprom[0]) | 0x400);
|
||||
W_REG(osh, &pci->sprom[0],
|
||||
R_REG(osh, &pci->sprom[0]) | 0x400);
|
||||
}
|
||||
|
||||
/* 64 MB I/O access window */
|
||||
|
@ -583,13 +590,14 @@ sbpci_init_pci(sb_t *sbh)
|
|||
|
||||
/* Host bridge slot # nvram overwrite */
|
||||
if ((hbslot = nvram_get("pcihbslot"))) {
|
||||
pci_hbslot = bcm_strtoul(hbslot, NULL, 0);
|
||||
pci_hbslot = simple_strtoul(hbslot, NULL, 0);
|
||||
ASSERT(pci_hbslot < PCI_MAX_DEVICES);
|
||||
}
|
||||
|
||||
/* Enable PCI bridge BAR0 prefetch and burst */
|
||||
val = 6;
|
||||
sbpci_write_config(sbh, 1, pci_hbslot, 0, PCI_CFG_CMD, &val, sizeof(val));
|
||||
sbpci_write_config(sbh, 1, pci_hbslot, 0, PCI_CFG_CMD, &val,
|
||||
sizeof(val));
|
||||
|
||||
/* Enable PCI interrupts */
|
||||
W_REG(osh, &pci->intmask, PCI_INTA);
|
||||
|
@ -602,7 +610,8 @@ sbpci_init_pci(sb_t *sbh)
|
|||
* Get the PCI region address and size information.
|
||||
*/
|
||||
static void __init
|
||||
sbpci_init_regions(sb_t *sbh, uint func, pci_config_regs *cfg, sb_bar_cfg_t *bar)
|
||||
sbpci_init_regions(sb_t * sbh, uint func, pci_config_regs * cfg,
|
||||
sb_bar_cfg_t * bar)
|
||||
{
|
||||
osl_t *osh;
|
||||
uint16 coreid;
|
||||
|
@ -610,26 +619,26 @@ sbpci_init_regions(sb_t *sbh, uint func, pci_config_regs *cfg, sb_bar_cfg_t *bar
|
|||
sbconfig_t *sb;
|
||||
uint32 base;
|
||||
|
||||
osh = sb_osh(sbh);
|
||||
coreid = sb_coreid(sbh);
|
||||
regs = sb_coreregs(sbh);
|
||||
sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
|
||||
osh = sb_osh(sbh);
|
||||
coreid = sb_coreid(sbh);
|
||||
regs = sb_coreregs(sbh);
|
||||
sb = (sbconfig_t *) ((ulong) regs + SBCONFIGOFF);
|
||||
|
||||
switch (coreid) {
|
||||
case SB_USB20H:
|
||||
base = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
|
||||
|
||||
cfg->base[0] = func == 0 ? base : base + 0x800; /* OHCI/EHCI */
|
||||
cfg->base[0] = func == 0 ? base : base + 0x800; /* OHCI/EHCI */
|
||||
cfg->base[1] = 0;
|
||||
cfg->base[2] = 0;
|
||||
cfg->base[3] = 0;
|
||||
cfg->base[4] = 0;
|
||||
cfg->base[5] = 0;
|
||||
bar->n = 1;
|
||||
bar->size0 = func == 0 ? 0x200 : 0x100; /* OHCI/EHCI */
|
||||
bar->size1 = 0;
|
||||
bar->size2 = 0;
|
||||
bar->size3 = 0;
|
||||
bar->n = 1;
|
||||
bar->size0 = func == 0 ? 0x200 : 0x100; /* OHCI/EHCI */
|
||||
bar->size1 = 0;
|
||||
bar->size2 = 0;
|
||||
bar->size3 = 0;
|
||||
break;
|
||||
default:
|
||||
cfg->base[0] = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
|
||||
|
@ -638,11 +647,13 @@ sbpci_init_regions(sb_t *sbh, uint func, pci_config_regs *cfg, sb_bar_cfg_t *bar
|
|||
cfg->base[3] = htol32(sb_base(R_REG(osh, &sb->sbadmatch3)));
|
||||
cfg->base[4] = 0;
|
||||
cfg->base[5] = 0;
|
||||
bar->n = (R_REG(osh, &sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
|
||||
bar->size0 = sb_size(R_REG(osh, &sb->sbadmatch0));
|
||||
bar->size1 = sb_size(R_REG(osh, &sb->sbadmatch1));
|
||||
bar->size2 = sb_size(R_REG(osh, &sb->sbadmatch2));
|
||||
bar->size3 = sb_size(R_REG(osh, &sb->sbadmatch3));
|
||||
bar->n =
|
||||
(R_REG(osh, &sb->sbidlow) & SBIDL_AR_MASK) >>
|
||||
SBIDL_AR_SHIFT;
|
||||
bar->size0 = sb_size(R_REG(osh, &sb->sbadmatch0));
|
||||
bar->size1 = sb_size(R_REG(osh, &sb->sbadmatch1));
|
||||
bar->size2 = sb_size(R_REG(osh, &sb->sbadmatch2));
|
||||
bar->size3 = sb_size(R_REG(osh, &sb->sbadmatch3));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
@ -651,8 +662,7 @@ sbpci_init_regions(sb_t *sbh, uint func, pci_config_regs *cfg, sb_bar_cfg_t *bar
|
|||
* Construct PCI config spaces for SB cores so that they
|
||||
* can be accessed as if they were PCI devices.
|
||||
*/
|
||||
static void __init
|
||||
sbpci_init_cores(sb_t *sbh)
|
||||
static void __init sbpci_init_cores(sb_t * sbh)
|
||||
{
|
||||
uint chiprev, coreidx, i;
|
||||
sbconfig_t *sb;
|
||||
|
@ -679,11 +689,11 @@ sbpci_init_cores(sb_t *sbh)
|
|||
memset(&sb_pci_null, -1, sizeof(sb_pci_null));
|
||||
cfg = sb_config_regs;
|
||||
bar = sb_bar_cfg;
|
||||
for (dev = 0; dev < SB_MAXCORES; dev ++) {
|
||||
for (dev = 0; dev < SB_MAXCORES; dev++) {
|
||||
/* Check if the core exists */
|
||||
if (!(regs = sb_setcoreidx(sbh, dev)))
|
||||
continue;
|
||||
sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
|
||||
sb = (sbconfig_t *) ((ulong) regs + SBCONFIGOFF);
|
||||
|
||||
/* Check if this core is banned */
|
||||
coreid = sb_coreid(sbh);
|
||||
|
@ -701,8 +711,9 @@ sbpci_init_cores(sb_t *sbh)
|
|||
}
|
||||
|
||||
/* Convert core id to pci id */
|
||||
if (sb_corepciid(sbh, func, &vendor, &device, &class, &subclass,
|
||||
&progif, &header))
|
||||
if (sb_corepciid
|
||||
(sbh, func, &vendor, &device, &class, &subclass,
|
||||
&progif, &header))
|
||||
continue;
|
||||
|
||||
/*
|
||||
|
@ -712,13 +723,16 @@ sbpci_init_cores(sb_t *sbh)
|
|||
*/
|
||||
switch (device) {
|
||||
case BCM47XX_GIGETH_ID:
|
||||
pci = (pci_config_regs *)((uint32)regs + 0x800);
|
||||
pci =
|
||||
(pci_config_regs *) ((uint32) regs + 0x800);
|
||||
break;
|
||||
case BCM47XX_SATAXOR_ID:
|
||||
pci = (pci_config_regs *)((uint32)regs + 0x400);
|
||||
pci =
|
||||
(pci_config_regs *) ((uint32) regs + 0x400);
|
||||
break;
|
||||
case BCM47XX_ATA100_ID:
|
||||
pci = (pci_config_regs *)((uint32)regs + 0x800);
|
||||
pci =
|
||||
(pci_config_regs *) ((uint32) regs + 0x800);
|
||||
break;
|
||||
default:
|
||||
pci = NULL;
|
||||
|
@ -734,22 +748,23 @@ sbpci_init_cores(sb_t *sbh)
|
|||
cfg->header_type = header;
|
||||
sbpci_init_regions(sbh, func, cfg, bar);
|
||||
/* Save core interrupt flag */
|
||||
cfg->int_pin = R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
|
||||
cfg->int_pin =
|
||||
R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
|
||||
/* Save core interrupt assignment */
|
||||
cfg->int_line = sb_irq(sbh);
|
||||
/* Indicate there is no SROM */
|
||||
*((uint32 *) &cfg->sprom_control) = 0xffffffff;
|
||||
*((uint32 *) & cfg->sprom_control) = 0xffffffff;
|
||||
|
||||
/* Point to the PCI config spaces */
|
||||
sb_pci_cfg[dev][func].emu = cfg;
|
||||
sb_pci_cfg[dev][func].pci = pci;
|
||||
sb_pci_cfg[dev][func].bar = bar;
|
||||
cfg ++;
|
||||
bar ++;
|
||||
cfg++;
|
||||
bar++;
|
||||
}
|
||||
}
|
||||
|
||||
done:
|
||||
done:
|
||||
sb_setcoreidx(sbh, coreidx);
|
||||
}
|
||||
|
||||
|
@ -758,11 +773,9 @@ done:
|
|||
* Must propagate sbpci_init_pci() return value to the caller to let
|
||||
* them know the PCI core initialization status.
|
||||
*/
|
||||
int __init
|
||||
sbpci_init(sb_t *sbh)
|
||||
int __init sbpci_init(sb_t * sbh)
|
||||
{
|
||||
int status = sbpci_init_pci(sbh);
|
||||
sbpci_init_cores(sbh);
|
||||
return status;
|
||||
}
|
||||
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -48,7 +48,6 @@
|
|||
#include <typedefs.h>
|
||||
#include <osl.h>
|
||||
#include <sbutils.h>
|
||||
#include <bcmutils.h>
|
||||
#include <bcmnvram.h>
|
||||
#include <sbhndmips.h>
|
||||
#include <hndmips.h>
|
||||
|
@ -170,7 +169,7 @@ brcm_setup(void)
|
|||
char *value;
|
||||
|
||||
/* Get global SB handle */
|
||||
sbh = sb_kattach();
|
||||
sbh = sb_kattach(SB_OSH);
|
||||
|
||||
/* Initialize clocks and interrupts */
|
||||
sb_mips_init(sbh, SBMIPS_VIRTIRQ_BASE);
|
||||
|
|
|
@ -1,422 +0,0 @@
|
|||
/*
|
||||
* Broadcom SiliconBackplane chipcommon serial flash interface
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id: sflash.c,v 1.1.1.13 2006/02/27 03:43:16 honor Exp $
|
||||
*/
|
||||
|
||||
#include <osl.h>
|
||||
#include <typedefs.h>
|
||||
#include <sbconfig.h>
|
||||
#include <sbchipc.h>
|
||||
#include <mipsinc.h>
|
||||
#include <bcmutils.h>
|
||||
#include <bcmdevs.h>
|
||||
#include <sflash.h>
|
||||
|
||||
/* Private global state */
|
||||
static struct sflash sflash;
|
||||
|
||||
/* Issue a serial flash command */
|
||||
static INLINE void
|
||||
sflash_cmd(chipcregs_t *cc, uint opcode)
|
||||
{
|
||||
W_REG(NULL, &cc->flashcontrol, SFLASH_START | opcode);
|
||||
while (R_REG(NULL, &cc->flashcontrol) & SFLASH_BUSY);
|
||||
}
|
||||
|
||||
/* Initialize serial flash access */
|
||||
struct sflash *
|
||||
sflash_init(chipcregs_t *cc)
|
||||
{
|
||||
uint32 id, id2;
|
||||
|
||||
bzero(&sflash, sizeof(sflash));
|
||||
|
||||
sflash.type = R_REG(NULL, &cc->capabilities) & CAP_FLASH_MASK;
|
||||
|
||||
switch (sflash.type) {
|
||||
case SFLASH_ST:
|
||||
/* Probe for ST chips */
|
||||
sflash_cmd(cc, SFLASH_ST_DP);
|
||||
sflash_cmd(cc, SFLASH_ST_RES);
|
||||
id = R_REG(NULL, &cc->flashdata);
|
||||
switch (id) {
|
||||
case 0x11:
|
||||
/* ST M25P20 2 Mbit Serial Flash */
|
||||
sflash.blocksize = 64 * 1024;
|
||||
sflash.numblocks = 4;
|
||||
break;
|
||||
case 0x12:
|
||||
/* ST M25P40 4 Mbit Serial Flash */
|
||||
sflash.blocksize = 64 * 1024;
|
||||
sflash.numblocks = 8;
|
||||
break;
|
||||
case 0x13:
|
||||
/* ST M25P80 8 Mbit Serial Flash */
|
||||
sflash.blocksize = 64 * 1024;
|
||||
sflash.numblocks = 16;
|
||||
break;
|
||||
case 0x14:
|
||||
/* ST M25P16 16 Mbit Serial Flash */
|
||||
sflash.blocksize = 64 * 1024;
|
||||
sflash.numblocks = 32;
|
||||
break;
|
||||
case 0x15:
|
||||
/* ST M25P32 32 Mbit Serial Flash */
|
||||
sflash.blocksize = 64 * 1024;
|
||||
sflash.numblocks = 64;
|
||||
break;
|
||||
case 0x16:
|
||||
/* ST M25P64 64 Mbit Serial Flash */
|
||||
sflash.blocksize = 64 * 1024;
|
||||
sflash.numblocks = 128;
|
||||
break;
|
||||
case 0xbf:
|
||||
W_REG(NULL, &cc->flashaddress, 1);
|
||||
sflash_cmd(cc, SFLASH_ST_RES);
|
||||
id2 = R_REG(NULL, &cc->flashdata);
|
||||
if (id2 == 0x44) {
|
||||
/* SST M25VF80 4 Mbit Serial Flash */
|
||||
sflash.blocksize = 64 * 1024;
|
||||
sflash.numblocks = 8;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case SFLASH_AT:
|
||||
/* Probe for Atmel chips */
|
||||
sflash_cmd(cc, SFLASH_AT_STATUS);
|
||||
id = R_REG(NULL, &cc->flashdata) & 0x3c;
|
||||
switch (id) {
|
||||
case 0xc:
|
||||
/* Atmel AT45DB011 1Mbit Serial Flash */
|
||||
sflash.blocksize = 256;
|
||||
sflash.numblocks = 512;
|
||||
break;
|
||||
case 0x14:
|
||||
/* Atmel AT45DB021 2Mbit Serial Flash */
|
||||
sflash.blocksize = 256;
|
||||
sflash.numblocks = 1024;
|
||||
break;
|
||||
case 0x1c:
|
||||
/* Atmel AT45DB041 4Mbit Serial Flash */
|
||||
sflash.blocksize = 256;
|
||||
sflash.numblocks = 2048;
|
||||
break;
|
||||
case 0x24:
|
||||
/* Atmel AT45DB081 8Mbit Serial Flash */
|
||||
sflash.blocksize = 256;
|
||||
sflash.numblocks = 4096;
|
||||
break;
|
||||
case 0x2c:
|
||||
/* Atmel AT45DB161 16Mbit Serial Flash */
|
||||
sflash.blocksize = 512;
|
||||
sflash.numblocks = 4096;
|
||||
break;
|
||||
case 0x34:
|
||||
/* Atmel AT45DB321 32Mbit Serial Flash */
|
||||
sflash.blocksize = 512;
|
||||
sflash.numblocks = 8192;
|
||||
break;
|
||||
case 0x3c:
|
||||
/* Atmel AT45DB642 64Mbit Serial Flash */
|
||||
sflash.blocksize = 1024;
|
||||
sflash.numblocks = 8192;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
sflash.size = sflash.blocksize * sflash.numblocks;
|
||||
return sflash.size ? &sflash : NULL;
|
||||
}
|
||||
|
||||
/* Read len bytes starting at offset into buf. Returns number of bytes read. */
|
||||
int
|
||||
sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
|
||||
{
|
||||
int cnt;
|
||||
uint32 *from, *to;
|
||||
|
||||
if (!len)
|
||||
return 0;
|
||||
|
||||
if ((offset + len) > sflash.size)
|
||||
return -22;
|
||||
|
||||
if ((len >= 4) && (offset & 3))
|
||||
cnt = 4 - (offset & 3);
|
||||
else if ((len >= 4) && ((uint32)buf & 3))
|
||||
cnt = 4 - ((uint32)buf & 3);
|
||||
else
|
||||
cnt = len;
|
||||
|
||||
from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
|
||||
to = (uint32 *)buf;
|
||||
|
||||
if (cnt < 4) {
|
||||
bcopy(from, to, cnt);
|
||||
return cnt;
|
||||
}
|
||||
|
||||
while (cnt >= 4) {
|
||||
*to++ = *from++;
|
||||
cnt -= 4;
|
||||
}
|
||||
|
||||
return (len - cnt);
|
||||
}
|
||||
|
||||
/* Poll for command completion. Returns zero when complete. */
|
||||
int
|
||||
sflash_poll(chipcregs_t *cc, uint offset)
|
||||
{
|
||||
if (offset >= sflash.size)
|
||||
return -22;
|
||||
|
||||
switch (sflash.type) {
|
||||
case SFLASH_ST:
|
||||
/* Check for ST Write In Progress bit */
|
||||
sflash_cmd(cc, SFLASH_ST_RDSR);
|
||||
return R_REG(NULL, &cc->flashdata) & SFLASH_ST_WIP;
|
||||
case SFLASH_AT:
|
||||
/* Check for Atmel Ready bit */
|
||||
sflash_cmd(cc, SFLASH_AT_STATUS);
|
||||
return !(R_REG(NULL, &cc->flashdata) & SFLASH_AT_READY);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Write len bytes starting at offset into buf. Returns number of bytes
|
||||
* written. Caller should poll for completion.
|
||||
*/
|
||||
int
|
||||
sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
|
||||
{
|
||||
struct sflash *sfl;
|
||||
int ret = 0;
|
||||
bool is4712b0;
|
||||
uint32 page, byte, mask;
|
||||
|
||||
if (!len)
|
||||
return 0;
|
||||
|
||||
if ((offset + len) > sflash.size)
|
||||
return -22;
|
||||
|
||||
sfl = &sflash;
|
||||
switch (sfl->type) {
|
||||
case SFLASH_ST:
|
||||
mask = R_REG(NULL, &cc->chipid);
|
||||
is4712b0 = (((mask & CID_ID_MASK) == BCM4712_CHIP_ID) &&
|
||||
((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
|
||||
/* Enable writes */
|
||||
sflash_cmd(cc, SFLASH_ST_WREN);
|
||||
if (is4712b0) {
|
||||
mask = 1 << 14;
|
||||
W_REG(NULL, &cc->flashaddress, offset);
|
||||
W_REG(NULL, &cc->flashdata, *buf++);
|
||||
/* Set chip select */
|
||||
OR_REG(NULL, &cc->gpioout, mask);
|
||||
/* Issue a page program with the first byte */
|
||||
sflash_cmd(cc, SFLASH_ST_PP);
|
||||
ret = 1;
|
||||
offset++;
|
||||
len--;
|
||||
while (len > 0) {
|
||||
if ((offset & 255) == 0) {
|
||||
/* Page boundary, drop cs and return */
|
||||
AND_REG(NULL, &cc->gpioout, ~mask);
|
||||
if (!sflash_poll(cc, offset)) {
|
||||
/* Flash rejected command */
|
||||
return -11;
|
||||
}
|
||||
return ret;
|
||||
} else {
|
||||
/* Write single byte */
|
||||
sflash_cmd(cc, *buf++);
|
||||
}
|
||||
ret++;
|
||||
offset++;
|
||||
len--;
|
||||
}
|
||||
/* All done, drop cs if needed */
|
||||
if ((offset & 255) != 1) {
|
||||
/* Drop cs */
|
||||
AND_REG(NULL, &cc->gpioout, ~mask);
|
||||
if (!sflash_poll(cc, offset)) {
|
||||
/* Flash rejected command */
|
||||
return -12;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
ret = 1;
|
||||
W_REG(NULL, &cc->flashaddress, offset);
|
||||
W_REG(NULL, &cc->flashdata, *buf);
|
||||
/* Page program */
|
||||
sflash_cmd(cc, SFLASH_ST_PP);
|
||||
}
|
||||
break;
|
||||
case SFLASH_AT:
|
||||
mask = sfl->blocksize - 1;
|
||||
page = (offset & ~mask) << 1;
|
||||
byte = offset & mask;
|
||||
/* Read main memory page into buffer 1 */
|
||||
if (byte || (len < sfl->blocksize)) {
|
||||
W_REG(NULL, &cc->flashaddress, page);
|
||||
sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
|
||||
/* 250 us for AT45DB321B */
|
||||
SPINWAIT(sflash_poll(cc, offset), 1000);
|
||||
ASSERT(!sflash_poll(cc, offset));
|
||||
}
|
||||
/* Write into buffer 1 */
|
||||
for (ret = 0; (ret < (int)len) && (byte < sfl->blocksize); ret++) {
|
||||
W_REG(NULL, &cc->flashaddress, byte++);
|
||||
W_REG(NULL, &cc->flashdata, *buf++);
|
||||
sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
|
||||
}
|
||||
/* Write buffer 1 into main memory page */
|
||||
W_REG(NULL, &cc->flashaddress, page);
|
||||
sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Erase a region. Returns number of bytes scheduled for erasure.
|
||||
* Caller should poll for completion.
|
||||
*/
|
||||
int
|
||||
sflash_erase(chipcregs_t *cc, uint offset)
|
||||
{
|
||||
struct sflash *sfl;
|
||||
|
||||
if (offset >= sflash.size)
|
||||
return -22;
|
||||
|
||||
sfl = &sflash;
|
||||
switch (sfl->type) {
|
||||
case SFLASH_ST:
|
||||
sflash_cmd(cc, SFLASH_ST_WREN);
|
||||
W_REG(NULL, &cc->flashaddress, offset);
|
||||
sflash_cmd(cc, SFLASH_ST_SE);
|
||||
return sfl->blocksize;
|
||||
case SFLASH_AT:
|
||||
W_REG(NULL, &cc->flashaddress, offset << 1);
|
||||
sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
|
||||
return sfl->blocksize;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* writes the appropriate range of flash, a NULL buf simply erases
|
||||
* the region of flash
|
||||
*/
|
||||
int
|
||||
sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
|
||||
{
|
||||
struct sflash *sfl;
|
||||
uchar *block = NULL, *cur_ptr, *blk_ptr;
|
||||
uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
|
||||
uint blk_offset, blk_len, copied;
|
||||
int bytes, ret = 0;
|
||||
|
||||
/* Check address range */
|
||||
if (len <= 0)
|
||||
return 0;
|
||||
|
||||
sfl = &sflash;
|
||||
if ((offset + len) > sfl->size)
|
||||
return -1;
|
||||
|
||||
blocksize = sfl->blocksize;
|
||||
mask = blocksize - 1;
|
||||
|
||||
/* Allocate a block of mem */
|
||||
if (!(block = MALLOC(NULL, blocksize)))
|
||||
return -1;
|
||||
|
||||
while (len) {
|
||||
/* Align offset */
|
||||
cur_offset = offset & ~mask;
|
||||
cur_length = blocksize;
|
||||
cur_ptr = block;
|
||||
|
||||
remainder = blocksize - (offset & mask);
|
||||
if (len < remainder)
|
||||
cur_retlen = len;
|
||||
else
|
||||
cur_retlen = remainder;
|
||||
|
||||
/* buf == NULL means erase only */
|
||||
if (buf) {
|
||||
/* Copy existing data into holding block if necessary */
|
||||
if ((offset & mask) || (len < blocksize)) {
|
||||
blk_offset = cur_offset;
|
||||
blk_len = cur_length;
|
||||
blk_ptr = cur_ptr;
|
||||
|
||||
/* Copy entire block */
|
||||
while (blk_len) {
|
||||
copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
|
||||
blk_offset += copied;
|
||||
blk_len -= copied;
|
||||
blk_ptr += copied;
|
||||
}
|
||||
}
|
||||
|
||||
/* Copy input data into holding block */
|
||||
memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
|
||||
}
|
||||
|
||||
/* Erase block */
|
||||
if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
|
||||
goto done;
|
||||
while (sflash_poll(cc, (uint) cur_offset));
|
||||
|
||||
/* buf == NULL means erase only */
|
||||
if (!buf) {
|
||||
offset += cur_retlen;
|
||||
len -= cur_retlen;
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Write holding block */
|
||||
while (cur_length > 0) {
|
||||
if ((bytes = sflash_write(cc,
|
||||
(uint) cur_offset,
|
||||
(uint) cur_length,
|
||||
(uchar *) cur_ptr)) < 0) {
|
||||
ret = bytes;
|
||||
goto done;
|
||||
}
|
||||
while (sflash_poll(cc, (uint) cur_offset));
|
||||
cur_offset += bytes;
|
||||
cur_length -= bytes;
|
||||
cur_ptr += bytes;
|
||||
}
|
||||
|
||||
offset += cur_retlen;
|
||||
len -= cur_retlen;
|
||||
buf += cur_retlen;
|
||||
}
|
||||
|
||||
ret = len;
|
||||
done:
|
||||
if (block)
|
||||
MFREE(NULL, block, blocksize);
|
||||
return ret;
|
||||
}
|
|
@ -23,11 +23,12 @@
|
|||
#include <osl.h>
|
||||
#include <bcmnvram.h>
|
||||
#include <sbconfig.h>
|
||||
#include <sbextif.h>
|
||||
#include <sbutils.h>
|
||||
#include <sbchipc.h>
|
||||
#include <hndmips.h>
|
||||
#include <mipsinc.h>
|
||||
#include <hndcpu.h>
|
||||
#include <bcmdevs.h>
|
||||
|
||||
/* Global SB handle */
|
||||
extern void *bcm947xx_sbh;
|
||||
|
@ -39,13 +40,11 @@ extern spinlock_t bcm947xx_sbh_lock;
|
|||
|
||||
extern int panic_timeout;
|
||||
static int watchdog = 0;
|
||||
static u8 *mcr = NULL;
|
||||
|
||||
void __init
|
||||
bcm947xx_time_init(void)
|
||||
{
|
||||
unsigned int hz;
|
||||
extifregs_t *eir;
|
||||
|
||||
/*
|
||||
* Use deterministic values for initial counter interrupt
|
||||
|
@ -83,8 +82,13 @@ bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
|||
timer_interrupt(irq, dev_id, regs);
|
||||
|
||||
/* Set the watchdog timer to reset after the specified number of ms */
|
||||
if (watchdog > 0)
|
||||
sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
|
||||
if (watchdog > 0) {
|
||||
if (sb_chip(sbh) == BCM5354_CHIP_ID)
|
||||
sb_watchdog(sbh, WATCHDOG_CLOCK_5354 / 1000 * watchdog);
|
||||
else
|
||||
sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static struct irqaction bcm947xx_timer_irqaction = {
|
||||
|
|
105
target/linux/brcm-2.4/files/arch/mips/bcm947xx/utils.c
Normal file
105
target/linux/brcm-2.4/files/arch/mips/bcm947xx/utils.c
Normal file
|
@ -0,0 +1,105 @@
|
|||
/*
|
||||
* Driver O/S-independent utility routines
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <typedefs.h>
|
||||
#include <bcmdefs.h>
|
||||
#include <stdarg.h>
|
||||
#include <osl.h>
|
||||
#include <sbutils.h>
|
||||
#include <bcmendian.h>
|
||||
#include "utils.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* crc8
|
||||
*
|
||||
* Computes a crc8 over the input data using the polynomial:
|
||||
*
|
||||
* x^8 + x^7 +x^6 + x^4 + x^2 + 1
|
||||
*
|
||||
* The caller provides the initial value (either CRC8_INIT_VALUE
|
||||
* or the previous returned value) to allow for processing of
|
||||
* discontiguous blocks of data. When generating the CRC the
|
||||
* caller is responsible for complementing the final return value
|
||||
* and inserting it into the byte stream. When checking, a final
|
||||
* return value of CRC8_GOOD_VALUE indicates a valid CRC.
|
||||
*
|
||||
* Reference: Dallas Semiconductor Application Note 27
|
||||
* Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
|
||||
* ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
|
||||
* ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
|
||||
*
|
||||
* ****************************************************************************
|
||||
*/
|
||||
|
||||
static const uint8 crc8_table[256] = {
|
||||
0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
|
||||
0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
|
||||
0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
|
||||
0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
|
||||
0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
|
||||
0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
|
||||
0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
|
||||
0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
|
||||
0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
|
||||
0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
|
||||
0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
|
||||
0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
|
||||
0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
|
||||
0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
|
||||
0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
|
||||
0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
|
||||
0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
|
||||
0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
|
||||
0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
|
||||
0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
|
||||
0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
|
||||
0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
|
||||
0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
|
||||
0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
|
||||
0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
|
||||
0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
|
||||
0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
|
||||
0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
|
||||
0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
|
||||
0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
|
||||
0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
|
||||
0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
|
||||
};
|
||||
|
||||
#define CRC_INNER_LOOP(n, c, x) \
|
||||
(c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
|
||||
|
||||
|
||||
uint8 hndcrc8 (uint8 * pdata, /* pointer to array of data to process */
|
||||
uint nbytes, /* number of input data bytes to process */
|
||||
uint8 crc /* either CRC8_INIT_VALUE or previous return value */
|
||||
)
|
||||
{
|
||||
/* hard code the crc loop instead of using CRC_INNER_LOOP macro
|
||||
* to avoid the undefined and unnecessary (uint8 >> 8) operation.
|
||||
*/
|
||||
while (nbytes-- > 0)
|
||||
crc = crc8_table[(crc ^ *pdata++) & 0xff];
|
||||
|
||||
return crc;
|
||||
}
|
||||
|
||||
char *
|
||||
bcm_ether_ntoa (struct ether_addr *ea, char *buf)
|
||||
{
|
||||
snprintf (buf, 18, "%02x:%02x:%02x:%02x:%02x:%02x",
|
||||
ea->octet[0] & 0xff, ea->octet[1] & 0xff, ea->octet[2] & 0xff,
|
||||
ea->octet[3] & 0xff, ea->octet[4] & 0xff, ea->octet[5] & 0xff);
|
||||
return (buf);
|
||||
}
|
||||
|
65
target/linux/brcm-2.4/files/arch/mips/bcm947xx/utils.h
Normal file
65
target/linux/brcm-2.4/files/arch/mips/bcm947xx/utils.h
Normal file
|
@ -0,0 +1,65 @@
|
|||
#ifndef __bcm_utils_h
|
||||
#define __bcm_utils_h
|
||||
|
||||
#define BCME_STRLEN 64 /* Max string length for BCM errors */
|
||||
#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
|
||||
|
||||
/*
|
||||
* error codes could be added but the defined ones shouldn't be changed/deleted
|
||||
* these error codes are exposed to the user code
|
||||
* when ever a new error code is added to this list
|
||||
* please update errorstring table with the related error string and
|
||||
* update osl files with os specific errorcode map
|
||||
*/
|
||||
|
||||
#define BCME_OK 0 /* Success */
|
||||
#define BCME_ERROR -1 /* Error generic */
|
||||
#define BCME_BADARG -2 /* Bad Argument */
|
||||
#define BCME_BADOPTION -3 /* Bad option */
|
||||
#define BCME_NOTUP -4 /* Not up */
|
||||
#define BCME_NOTDOWN -5 /* Not down */
|
||||
#define BCME_NOTAP -6 /* Not AP */
|
||||
#define BCME_NOTSTA -7 /* Not STA */
|
||||
#define BCME_BADKEYIDX -8 /* BAD Key Index */
|
||||
#define BCME_RADIOOFF -9 /* Radio Off */
|
||||
#define BCME_NOTBANDLOCKED -10 /* Not band locked */
|
||||
#define BCME_NOCLK -11 /* No Clock */
|
||||
#define BCME_BADRATESET -12 /* BAD Rate valueset */
|
||||
#define BCME_BADBAND -13 /* BAD Band */
|
||||
#define BCME_BUFTOOSHORT -14 /* Buffer too short */
|
||||
#define BCME_BUFTOOLONG -15 /* Buffer too long */
|
||||
#define BCME_BUSY -16 /* Busy */
|
||||
#define BCME_NOTASSOCIATED -17 /* Not Associated */
|
||||
#define BCME_BADSSIDLEN -18 /* Bad SSID len */
|
||||
#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel */
|
||||
#define BCME_BADCHAN -20 /* Bad Channel */
|
||||
#define BCME_BADADDR -21 /* Bad Address */
|
||||
#define BCME_NORESOURCE -22 /* Not Enough Resources */
|
||||
#define BCME_UNSUPPORTED -23 /* Unsupported */
|
||||
#define BCME_BADLEN -24 /* Bad length */
|
||||
#define BCME_NOTREADY -25 /* Not Ready */
|
||||
#define BCME_EPERM -26 /* Not Permitted */
|
||||
#define BCME_NOMEM -27 /* No Memory */
|
||||
#define BCME_ASSOCIATED -28 /* Associated */
|
||||
#define BCME_RANGE -29 /* Not In Range */
|
||||
#define BCME_NOTFOUND -30 /* Not Found */
|
||||
#define BCME_WME_NOT_ENABLED -31 /* WME Not Enabled */
|
||||
#define BCME_TSPEC_NOTFOUND -32 /* TSPEC Not Found */
|
||||
#define BCME_ACM_NOTSUPPORTED -33 /* ACM Not Supported */
|
||||
#define BCME_NOT_WME_ASSOCIATION -34 /* Not WME Association */
|
||||
#define BCME_SDIO_ERROR -35 /* SDIO Bus Error */
|
||||
#define BCME_DONGLE_DOWN -36 /* Dongle Not Accessible */
|
||||
#define BCME_VERSION -37 /* Incorrect version */
|
||||
#define BCME_LAST BCME_VERSION
|
||||
|
||||
/* buffer length for ethernet address from bcm_ether_ntoa() */
|
||||
#define ETHER_ADDR_STR_LEN 18 /* 18-bytes of Ethernet address buffer length */
|
||||
|
||||
struct ether_addr {
|
||||
unsigned char octet[6];
|
||||
};
|
||||
|
||||
extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
|
||||
|
||||
#endif /* __bcm_utils_h */
|
||||
|
|
@ -1,298 +1,531 @@
|
|||
/*
|
||||
* Broadcom SiliconBackplane chipcommon serial flash interface
|
||||
*
|
||||
* Copyright 2001-2003, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id: sflash.c,v 1.1.1.3 2003/11/10 17:43:38 hyin Exp $
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/mtd/compatmac.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/delay.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/minix_fs.h>
|
||||
#include <linux/ext2_fs.h>
|
||||
#include <linux/romfs_fs.h>
|
||||
#include <linux/cramfs_fs.h>
|
||||
#include <linux/jffs2.h>
|
||||
#endif
|
||||
|
||||
#include <typedefs.h>
|
||||
#include <bcmdevs.h>
|
||||
#include <bcmutils.h>
|
||||
#include <osl.h>
|
||||
#include <bcmutils.h>
|
||||
#include <bcmnvram.h>
|
||||
#include <sbutils.h>
|
||||
#include <sbconfig.h>
|
||||
#include <sbchipc.h>
|
||||
#include <bcmdevs.h>
|
||||
#include <sflash.h>
|
||||
#include <trxhdr.h>
|
||||
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
extern struct mtd_partition * init_mtd_partitions(struct mtd_info *mtd, size_t size);
|
||||
#endif
|
||||
|
||||
struct sflash_mtd {
|
||||
chipcregs_t *cc;
|
||||
struct semaphore lock;
|
||||
struct mtd_info mtd;
|
||||
struct mtd_erase_region_info regions[1];
|
||||
};
|
||||
|
||||
/* Private global state */
|
||||
static struct sflash_mtd sflash;
|
||||
static struct sflash sflash;
|
||||
|
||||
static int
|
||||
sflash_mtd_poll(struct sflash_mtd *sflash, unsigned int offset, int timeout)
|
||||
/* Issue a serial flash command */
|
||||
static INLINE void
|
||||
sflash_cmd (osl_t * osh, chipcregs_t * cc, uint opcode)
|
||||
{
|
||||
int now = jiffies;
|
||||
int ret = 0;
|
||||
W_REG (osh, &cc->flashcontrol, SFLASH_START | opcode);
|
||||
while (R_REG (osh, &cc->flashcontrol) & SFLASH_BUSY);
|
||||
}
|
||||
|
||||
for (;;) {
|
||||
if (!sflash_poll(sflash->cc, offset)) {
|
||||
ret = 0;
|
||||
break;
|
||||
/* Initialize serial flash access */
|
||||
struct sflash *
|
||||
sflash_init (sb_t * sbh, chipcregs_t * cc)
|
||||
{
|
||||
uint32 id, id2;
|
||||
osl_t *osh;
|
||||
|
||||
ASSERT (sbh);
|
||||
|
||||
osh = sb_osh (sbh);
|
||||
|
||||
bzero (&sflash, sizeof (sflash));
|
||||
|
||||
sflash.type = sbh->cccaps & CC_CAP_FLASH_MASK;
|
||||
|
||||
switch (sflash.type)
|
||||
{
|
||||
case SFLASH_ST:
|
||||
/* Probe for ST chips */
|
||||
sflash_cmd (osh, cc, SFLASH_ST_DP);
|
||||
sflash_cmd (osh, cc, SFLASH_ST_RES);
|
||||
id = R_REG (osh, &cc->flashdata);
|
||||
switch (id)
|
||||
{
|
||||
case 0x11:
|
||||
/* ST M25P20 2 Mbit Serial Flash */
|
||||
sflash.blocksize = 64 * 1024;
|
||||
sflash.numblocks = 4;
|
||||
break;
|
||||
case 0x12:
|
||||
/* ST M25P40 4 Mbit Serial Flash */
|
||||
sflash.blocksize = 64 * 1024;
|
||||
sflash.numblocks = 8;
|
||||
break;
|
||||
case 0x13:
|
||||
/* ST M25P80 8 Mbit Serial Flash */
|
||||
sflash.blocksize = 64 * 1024;
|
||||
sflash.numblocks = 16;
|
||||
break;
|
||||
case 0x14:
|
||||
/* ST M25P16 16 Mbit Serial Flash */
|
||||
sflash.blocksize = 64 * 1024;
|
||||
sflash.numblocks = 32;
|
||||
break;
|
||||
case 0x15:
|
||||
/* ST M25P32 32 Mbit Serial Flash */
|
||||
sflash.blocksize = 64 * 1024;
|
||||
sflash.numblocks = 64;
|
||||
break;
|
||||
case 0x16:
|
||||
/* ST M25P64 64 Mbit Serial Flash */
|
||||
sflash.blocksize = 64 * 1024;
|
||||
sflash.numblocks = 128;
|
||||
break;
|
||||
case 0xbf:
|
||||
W_REG (osh, &cc->flashaddress, 1);
|
||||
sflash_cmd (osh, cc, SFLASH_ST_RES);
|
||||
id2 = R_REG (osh, &cc->flashdata);
|
||||
if (id2 == 0x44)
|
||||
{
|
||||
/* SST M25VF80 4 Mbit Serial Flash */
|
||||
sflash.blocksize = 64 * 1024;
|
||||
sflash.numblocks = 8;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case SFLASH_AT:
|
||||
/* Probe for Atmel chips */
|
||||
sflash_cmd (osh, cc, SFLASH_AT_STATUS);
|
||||
id = R_REG (osh, &cc->flashdata) & 0x3c;
|
||||
switch (id)
|
||||
{
|
||||
case 0xc:
|
||||
/* Atmel AT45DB011 1Mbit Serial Flash */
|
||||
sflash.blocksize = 256;
|
||||
sflash.numblocks = 512;
|
||||
break;
|
||||
case 0x14:
|
||||
/* Atmel AT45DB021 2Mbit Serial Flash */
|
||||
sflash.blocksize = 256;
|
||||
sflash.numblocks = 1024;
|
||||
break;
|
||||
case 0x1c:
|
||||
/* Atmel AT45DB041 4Mbit Serial Flash */
|
||||
sflash.blocksize = 256;
|
||||
sflash.numblocks = 2048;
|
||||
break;
|
||||
case 0x24:
|
||||
/* Atmel AT45DB081 8Mbit Serial Flash */
|
||||
sflash.blocksize = 256;
|
||||
sflash.numblocks = 4096;
|
||||
break;
|
||||
case 0x2c:
|
||||
/* Atmel AT45DB161 16Mbit Serial Flash */
|
||||
sflash.blocksize = 512;
|
||||
sflash.numblocks = 4096;
|
||||
break;
|
||||
case 0x34:
|
||||
/* Atmel AT45DB321 32Mbit Serial Flash */
|
||||
sflash.blocksize = 512;
|
||||
sflash.numblocks = 8192;
|
||||
break;
|
||||
case 0x3c:
|
||||
/* Atmel AT45DB642 64Mbit Serial Flash */
|
||||
sflash.blocksize = 1024;
|
||||
sflash.numblocks = 8192;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
sflash.size = sflash.blocksize * sflash.numblocks;
|
||||
return sflash.size ? &sflash : NULL;
|
||||
}
|
||||
|
||||
/* Read len bytes starting at offset into buf. Returns number of bytes read. */
|
||||
int
|
||||
sflash_read (sb_t * sbh, chipcregs_t * cc, uint offset, uint len, uchar * buf)
|
||||
{
|
||||
uint8 *from, *to;
|
||||
int cnt, i;
|
||||
osl_t *osh;
|
||||
|
||||
ASSERT (sbh);
|
||||
|
||||
if (!len)
|
||||
return 0;
|
||||
|
||||
if ((offset + len) > sflash.size)
|
||||
return -22;
|
||||
|
||||
if ((len >= 4) && (offset & 3))
|
||||
cnt = 4 - (offset & 3);
|
||||
else if ((len >= 4) && ((uintptr) buf & 3))
|
||||
cnt = 4 - ((uintptr) buf & 3);
|
||||
else
|
||||
cnt = len;
|
||||
|
||||
osh = sb_osh (sbh);
|
||||
|
||||
from = (uint8 *) (uintptr) OSL_UNCACHED (SB_FLASH2 + offset);
|
||||
to = (uint8 *) buf;
|
||||
|
||||
if (cnt < 4)
|
||||
{
|
||||
for (i = 0; i < cnt; i++)
|
||||
{
|
||||
*to = R_REG (osh, from);
|
||||
from++;
|
||||
to++;
|
||||
}
|
||||
return cnt;
|
||||
}
|
||||
|
||||
while (cnt >= 4)
|
||||
{
|
||||
*(uint32 *) to = R_REG (osh, (uint32 *) from);
|
||||
from += 4;
|
||||
to += 4;
|
||||
cnt -= 4;
|
||||
}
|
||||
|
||||
return (len - cnt);
|
||||
}
|
||||
|
||||
/* Poll for command completion. Returns zero when complete. */
|
||||
int
|
||||
sflash_poll (sb_t * sbh, chipcregs_t * cc, uint offset)
|
||||
{
|
||||
osl_t *osh;
|
||||
|
||||
ASSERT (sbh);
|
||||
|
||||
osh = sb_osh (sbh);
|
||||
|
||||
if (offset >= sflash.size)
|
||||
return -22;
|
||||
|
||||
switch (sflash.type)
|
||||
{
|
||||
case SFLASH_ST:
|
||||
/* Check for ST Write In Progress bit */
|
||||
sflash_cmd (osh, cc, SFLASH_ST_RDSR);
|
||||
return R_REG (osh, &cc->flashdata) & SFLASH_ST_WIP;
|
||||
case SFLASH_AT:
|
||||
/* Check for Atmel Ready bit */
|
||||
sflash_cmd (osh, cc, SFLASH_AT_STATUS);
|
||||
return !(R_REG (osh, &cc->flashdata) & SFLASH_AT_READY);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Write len bytes starting at offset into buf. Returns number of bytes
|
||||
* written. Caller should poll for completion.
|
||||
*/
|
||||
int
|
||||
sflash_write (sb_t * sbh, chipcregs_t * cc, uint offset, uint len,
|
||||
const uchar * buf)
|
||||
{
|
||||
struct sflash *sfl;
|
||||
int ret = 0;
|
||||
bool is4712b0;
|
||||
uint32 page, byte, mask;
|
||||
osl_t *osh;
|
||||
|
||||
ASSERT (sbh);
|
||||
|
||||
osh = sb_osh (sbh);
|
||||
|
||||
if (!len)
|
||||
return 0;
|
||||
|
||||
if ((offset + len) > sflash.size)
|
||||
return -22;
|
||||
|
||||
sfl = &sflash;
|
||||
switch (sfl->type)
|
||||
{
|
||||
case SFLASH_ST:
|
||||
is4712b0 = (sbh->chip == BCM4712_CHIP_ID) && (sbh->chiprev == 3);
|
||||
/* Enable writes */
|
||||
sflash_cmd (osh, cc, SFLASH_ST_WREN);
|
||||
if (is4712b0)
|
||||
{
|
||||
mask = 1 << 14;
|
||||
W_REG (osh, &cc->flashaddress, offset);
|
||||
W_REG (osh, &cc->flashdata, *buf++);
|
||||
/* Set chip select */
|
||||
OR_REG (osh, &cc->gpioout, mask);
|
||||
/* Issue a page program with the first byte */
|
||||
sflash_cmd (osh, cc, SFLASH_ST_PP);
|
||||
ret = 1;
|
||||
offset++;
|
||||
len--;
|
||||
while (len > 0)
|
||||
{
|
||||
if ((offset & 255) == 0)
|
||||
{
|
||||
/* Page boundary, drop cs and return */
|
||||
AND_REG (osh, &cc->gpioout, ~mask);
|
||||
if (!sflash_poll (sbh, cc, offset))
|
||||
{
|
||||
/* Flash rejected command */
|
||||
return -11;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
if (time_after(jiffies, now + timeout)) {
|
||||
printk(KERN_ERR "sflash: timeout\n");
|
||||
ret = -ETIMEDOUT;
|
||||
break;
|
||||
else
|
||||
{
|
||||
/* Write single byte */
|
||||
sflash_cmd (osh, cc, *buf++);
|
||||
}
|
||||
if (current->need_resched) {
|
||||
set_current_state(TASK_UNINTERRUPTIBLE);
|
||||
schedule_timeout(timeout / 10);
|
||||
} else
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
sflash_mtd_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
|
||||
{
|
||||
struct sflash_mtd *sflash = (struct sflash_mtd *) mtd->priv;
|
||||
int bytes, ret = 0;
|
||||
|
||||
/* Check address range */
|
||||
if (!len)
|
||||
return 0;
|
||||
if ((from + len) > mtd->size)
|
||||
return -EINVAL;
|
||||
|
||||
down(&sflash->lock);
|
||||
|
||||
*retlen = 0;
|
||||
while (len) {
|
||||
if ((bytes = sflash_read(sflash->cc, (uint) from, len, buf)) < 0) {
|
||||
ret = bytes;
|
||||
break;
|
||||
ret++;
|
||||
offset++;
|
||||
len--;
|
||||
}
|
||||
/* All done, drop cs if needed */
|
||||
if ((offset & 255) != 1)
|
||||
{
|
||||
/* Drop cs */
|
||||
AND_REG (osh, &cc->gpioout, ~mask);
|
||||
if (!sflash_poll (sbh, cc, offset))
|
||||
{
|
||||
/* Flash rejected command */
|
||||
return -12;
|
||||
}
|
||||
from += (loff_t) bytes;
|
||||
len -= bytes;
|
||||
buf += bytes;
|
||||
*retlen += bytes;
|
||||
}
|
||||
}
|
||||
|
||||
up(&sflash->lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
sflash_mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf)
|
||||
{
|
||||
struct sflash_mtd *sflash = (struct sflash_mtd *) mtd->priv;
|
||||
int bytes, ret = 0;
|
||||
|
||||
/* Check address range */
|
||||
if (!len)
|
||||
return 0;
|
||||
if ((to + len) > mtd->size)
|
||||
return -EINVAL;
|
||||
|
||||
down(&sflash->lock);
|
||||
|
||||
*retlen = 0;
|
||||
while (len) {
|
||||
if ((bytes = sflash_write(sflash->cc, (uint) to, len, buf)) < 0) {
|
||||
ret = bytes;
|
||||
break;
|
||||
else if (sbh->ccrev >= 20)
|
||||
{
|
||||
W_REG (NULL, &cc->flashaddress, offset);
|
||||
W_REG (NULL, &cc->flashdata, *buf++);
|
||||
/* Issue a page program with CSA bit set */
|
||||
sflash_cmd (osh, cc, SFLASH_ST_CSA | SFLASH_ST_PP);
|
||||
ret = 1;
|
||||
offset++;
|
||||
len--;
|
||||
while (len > 0)
|
||||
{
|
||||
if ((offset & 255) == 0)
|
||||
{
|
||||
/* Page boundary, poll droping cs and return */
|
||||
W_REG (NULL, &cc->flashcontrol, 0);
|
||||
if (!sflash_poll (sbh, cc, offset))
|
||||
{
|
||||
/* Flash rejected command */
|
||||
return -11;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
if ((ret = sflash_mtd_poll(sflash, (unsigned int) to, HZ / 10)))
|
||||
break;
|
||||
to += (loff_t) bytes;
|
||||
len -= bytes;
|
||||
buf += bytes;
|
||||
*retlen += bytes;
|
||||
}
|
||||
|
||||
up(&sflash->lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
sflash_mtd_erase(struct mtd_info *mtd, struct erase_info *erase)
|
||||
{
|
||||
struct sflash_mtd *sflash = (struct sflash_mtd *) mtd->priv;
|
||||
int i, j, ret = 0;
|
||||
unsigned int addr, len;
|
||||
|
||||
/* Check address range */
|
||||
if (!erase->len)
|
||||
return 0;
|
||||
if ((erase->addr + erase->len) > mtd->size)
|
||||
return -EINVAL;
|
||||
|
||||
addr = erase->addr;
|
||||
len = erase->len;
|
||||
|
||||
down(&sflash->lock);
|
||||
|
||||
/* Ensure that requested region is aligned */
|
||||
for (i = 0; i < mtd->numeraseregions; i++) {
|
||||
for (j = 0; j < mtd->eraseregions[i].numblocks; j++) {
|
||||
if (addr == mtd->eraseregions[i].offset + mtd->eraseregions[i].erasesize * j &&
|
||||
len >= mtd->eraseregions[i].erasesize) {
|
||||
if ((ret = sflash_erase(sflash->cc, addr)) < 0)
|
||||
break;
|
||||
if ((ret = sflash_mtd_poll(sflash, addr, 10 * HZ)))
|
||||
break;
|
||||
addr += mtd->eraseregions[i].erasesize;
|
||||
len -= mtd->eraseregions[i].erasesize;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Write single byte */
|
||||
sflash_cmd (osh, cc, SFLASH_ST_CSA | *buf++);
|
||||
}
|
||||
if (ret)
|
||||
break;
|
||||
ret++;
|
||||
offset++;
|
||||
len--;
|
||||
}
|
||||
/* All done, drop cs if needed */
|
||||
if ((offset & 255) != 1)
|
||||
{
|
||||
/* Drop cs, poll */
|
||||
W_REG (NULL, &cc->flashcontrol, 0);
|
||||
if (!sflash_poll (sbh, cc, offset))
|
||||
{
|
||||
/* Flash rejected command */
|
||||
return -12;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = 1;
|
||||
W_REG (osh, &cc->flashaddress, offset);
|
||||
W_REG (osh, &cc->flashdata, *buf);
|
||||
/* Page program */
|
||||
sflash_cmd (osh, cc, SFLASH_ST_PP);
|
||||
}
|
||||
break;
|
||||
case SFLASH_AT:
|
||||
mask = sfl->blocksize - 1;
|
||||
page = (offset & ~mask) << 1;
|
||||
byte = offset & mask;
|
||||
/* Read main memory page into buffer 1 */
|
||||
if (byte || (len < sfl->blocksize))
|
||||
{
|
||||
W_REG (osh, &cc->flashaddress, page);
|
||||
sflash_cmd (osh, cc, SFLASH_AT_BUF1_LOAD);
|
||||
/* 250 us for AT45DB321B */
|
||||
SPINWAIT (sflash_poll (sbh, cc, offset), 1000);
|
||||
ASSERT (!sflash_poll (sbh, cc, offset));
|
||||
}
|
||||
/* Write into buffer 1 */
|
||||
for (ret = 0; (ret < (int) len) && (byte < sfl->blocksize); ret++)
|
||||
{
|
||||
W_REG (osh, &cc->flashaddress, byte++);
|
||||
W_REG (osh, &cc->flashdata, *buf++);
|
||||
sflash_cmd (osh, cc, SFLASH_AT_BUF1_WRITE);
|
||||
}
|
||||
/* Write buffer 1 into main memory page */
|
||||
W_REG (osh, &cc->flashaddress, page);
|
||||
sflash_cmd (osh, cc, SFLASH_AT_BUF1_PROGRAM);
|
||||
break;
|
||||
}
|
||||
|
||||
up(&sflash->lock);
|
||||
|
||||
/* Set erase status */
|
||||
if (ret)
|
||||
erase->state = MTD_ERASE_FAILED;
|
||||
else
|
||||
erase->state = MTD_ERASE_DONE;
|
||||
|
||||
/* Call erase callback */
|
||||
if (erase->callback)
|
||||
erase->callback(erase);
|
||||
|
||||
return ret;
|
||||
return ret;
|
||||
}
|
||||
|
||||
#if LINUX_VERSION_CODE < 0x20212 && defined(MODULE)
|
||||
#define sflash_mtd_init init_module
|
||||
#define sflash_mtd_exit cleanup_module
|
||||
#endif
|
||||
|
||||
mod_init_t
|
||||
sflash_mtd_init(void)
|
||||
/* Erase a region. Returns number of bytes scheduled for erasure.
|
||||
* Caller should poll for completion.
|
||||
*/
|
||||
int
|
||||
sflash_erase (sb_t * sbh, chipcregs_t * cc, uint offset)
|
||||
{
|
||||
struct pci_dev *pdev;
|
||||
int ret = 0;
|
||||
struct sflash *info;
|
||||
uint bank, i;
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
struct mtd_partition *parts;
|
||||
#endif
|
||||
struct sflash *sfl;
|
||||
osl_t *osh;
|
||||
|
||||
if (!(pdev = pci_find_device(VENDOR_BROADCOM, SB_CC, NULL))) {
|
||||
printk(KERN_ERR "sflash: chipcommon not found\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
ASSERT (sbh);
|
||||
|
||||
memset(&sflash, 0, sizeof(struct sflash_mtd));
|
||||
init_MUTEX(&sflash.lock);
|
||||
osh = sb_osh (sbh);
|
||||
|
||||
/* Map registers and flash base */
|
||||
if (!(sflash.cc = ioremap_nocache(pci_resource_start(pdev, 0),
|
||||
pci_resource_len(pdev, 0)))) {
|
||||
printk(KERN_ERR "sflash: error mapping registers\n");
|
||||
ret = -EIO;
|
||||
goto fail;
|
||||
}
|
||||
if (offset >= sflash.size)
|
||||
return -22;
|
||||
|
||||
/* Initialize serial flash access */
|
||||
info = sflash_init(sflash.cc);
|
||||
sfl = &sflash;
|
||||
switch (sfl->type)
|
||||
{
|
||||
case SFLASH_ST:
|
||||
sflash_cmd (osh, cc, SFLASH_ST_WREN);
|
||||
W_REG (osh, &cc->flashaddress, offset);
|
||||
sflash_cmd (osh, cc, SFLASH_ST_SE);
|
||||
return sfl->blocksize;
|
||||
case SFLASH_AT:
|
||||
W_REG (osh, &cc->flashaddress, offset << 1);
|
||||
sflash_cmd (osh, cc, SFLASH_AT_PAGE_ERASE);
|
||||
return sfl->blocksize;
|
||||
}
|
||||
|
||||
if (!info) {
|
||||
printk(KERN_ERR "sflash: found no supported devices\n");
|
||||
ret = -ENODEV;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/* Setup banks */
|
||||
sflash.regions[0].offset = 0;
|
||||
sflash.regions[0].erasesize = info->blocksize;
|
||||
sflash.regions[0].numblocks = info->numblocks;
|
||||
if (sflash.regions[0].erasesize > sflash.mtd.erasesize)
|
||||
sflash.mtd.erasesize = sflash.regions[0].erasesize;
|
||||
if (sflash.regions[0].erasesize * sflash.regions[0].numblocks) {
|
||||
sflash.mtd.size += sflash.regions[0].erasesize * sflash.regions[0].numblocks;
|
||||
}
|
||||
sflash.mtd.numeraseregions = 1;
|
||||
ASSERT(sflash.mtd.size == info->size);
|
||||
|
||||
/* Register with MTD */
|
||||
sflash.mtd.name = "sflash";
|
||||
sflash.mtd.type = MTD_NORFLASH;
|
||||
sflash.mtd.flags = MTD_CAP_NORFLASH;
|
||||
sflash.mtd.eraseregions = sflash.regions;
|
||||
sflash.mtd.module = THIS_MODULE;
|
||||
sflash.mtd.erase = sflash_mtd_erase;
|
||||
sflash.mtd.read = sflash_mtd_read;
|
||||
sflash.mtd.write = sflash_mtd_write;
|
||||
sflash.mtd.priv = &sflash;
|
||||
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
parts = init_mtd_partitions(&sflash.mtd, sflash.mtd.size);
|
||||
for (i = 0; parts[i].name; i++);
|
||||
ret = add_mtd_partitions(&sflash.mtd, parts, i);
|
||||
#else
|
||||
ret = add_mtd_device(&sflash.mtd);
|
||||
#endif
|
||||
if (ret) {
|
||||
printk(KERN_ERR "sflash: add_mtd failed\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
if (sflash.cc)
|
||||
iounmap((void *) sflash.cc);
|
||||
return ret;
|
||||
return 0;
|
||||
}
|
||||
|
||||
mod_exit_t
|
||||
sflash_mtd_exit(void)
|
||||
/*
|
||||
* writes the appropriate range of flash, a NULL buf simply erases
|
||||
* the region of flash
|
||||
*/
|
||||
int
|
||||
sflash_commit (sb_t * sbh, chipcregs_t * cc, uint offset, uint len,
|
||||
const uchar * buf)
|
||||
{
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
del_mtd_partitions(&sflash.mtd);
|
||||
#else
|
||||
del_mtd_device(&sflash.mtd);
|
||||
#endif
|
||||
iounmap((void *) sflash.cc);
|
||||
}
|
||||
struct sflash *sfl;
|
||||
uchar *block = NULL, *cur_ptr, *blk_ptr;
|
||||
uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
|
||||
uint blk_offset, blk_len, copied;
|
||||
int bytes, ret = 0;
|
||||
osl_t *osh;
|
||||
|
||||
module_init(sflash_mtd_init);
|
||||
module_exit(sflash_mtd_exit);
|
||||
ASSERT (sbh);
|
||||
|
||||
osh = sb_osh (sbh);
|
||||
|
||||
/* Check address range */
|
||||
if (len <= 0)
|
||||
return 0;
|
||||
|
||||
sfl = &sflash;
|
||||
if ((offset + len) > sfl->size)
|
||||
return -1;
|
||||
|
||||
blocksize = sfl->blocksize;
|
||||
mask = blocksize - 1;
|
||||
|
||||
/* Allocate a block of mem */
|
||||
if (!(block = MALLOC (osh, blocksize)))
|
||||
return -1;
|
||||
|
||||
while (len)
|
||||
{
|
||||
/* Align offset */
|
||||
cur_offset = offset & ~mask;
|
||||
cur_length = blocksize;
|
||||
cur_ptr = block;
|
||||
|
||||
remainder = blocksize - (offset & mask);
|
||||
if (len < remainder)
|
||||
cur_retlen = len;
|
||||
else
|
||||
cur_retlen = remainder;
|
||||
|
||||
/* buf == NULL means erase only */
|
||||
if (buf)
|
||||
{
|
||||
/* Copy existing data into holding block if necessary */
|
||||
if ((offset & mask) || (len < blocksize))
|
||||
{
|
||||
blk_offset = cur_offset;
|
||||
blk_len = cur_length;
|
||||
blk_ptr = cur_ptr;
|
||||
|
||||
/* Copy entire block */
|
||||
while (blk_len)
|
||||
{
|
||||
copied =
|
||||
sflash_read (sbh, cc, blk_offset, blk_len, blk_ptr);
|
||||
blk_offset += copied;
|
||||
blk_len -= copied;
|
||||
blk_ptr += copied;
|
||||
}
|
||||
}
|
||||
|
||||
/* Copy input data into holding block */
|
||||
memcpy (cur_ptr + (offset & mask), buf, cur_retlen);
|
||||
}
|
||||
|
||||
/* Erase block */
|
||||
if ((ret = sflash_erase (sbh, cc, (uint) cur_offset)) < 0)
|
||||
goto done;
|
||||
while (sflash_poll (sbh, cc, (uint) cur_offset));
|
||||
|
||||
/* buf == NULL means erase only */
|
||||
if (!buf)
|
||||
{
|
||||
offset += cur_retlen;
|
||||
len -= cur_retlen;
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Write holding block */
|
||||
while (cur_length > 0)
|
||||
{
|
||||
if ((bytes = sflash_write (sbh, cc,
|
||||
(uint) cur_offset,
|
||||
(uint) cur_length,
|
||||
(uchar *) cur_ptr)) < 0)
|
||||
{
|
||||
ret = bytes;
|
||||
goto done;
|
||||
}
|
||||
while (sflash_poll (sbh, cc, (uint) cur_offset));
|
||||
cur_offset += bytes;
|
||||
cur_length -= bytes;
|
||||
cur_ptr += bytes;
|
||||
}
|
||||
|
||||
offset += cur_retlen;
|
||||
len -= cur_retlen;
|
||||
buf += cur_retlen;
|
||||
}
|
||||
|
||||
ret = len;
|
||||
done:
|
||||
if (block)
|
||||
MFREE (osh, block, blocksize);
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -56,7 +56,6 @@
|
|||
#include <typedefs.h>
|
||||
#include <osl.h>
|
||||
#include <bcmnvram.h>
|
||||
#include <bcmutils.h>
|
||||
#include <sbconfig.h>
|
||||
#include <sbchipc.h>
|
||||
#include <sbutils.h>
|
||||
|
@ -470,7 +469,7 @@ mod_init_t init_bcm947xx_map(void)
|
|||
|
||||
/* Check strapping option if chipcommon exists */
|
||||
if ((cc = sb_setcore(sbh, SB_CC, 0))) {
|
||||
fltype = readl(&cc->capabilities) & CAP_FLASH_MASK;
|
||||
fltype = readl(&cc->capabilities) & CC_CAP_FLASH_MASK;
|
||||
if (fltype == PFLASH) {
|
||||
bcm947xx_map.map_priv_2 = 1;
|
||||
window_addr = 0x1c000000;
|
||||
|
|
|
@ -1,6 +1,7 @@
|
|||
diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
|
||||
--- linux.old/arch/mips/config-shared.in 2006-10-02 21:23:10.000000000 +0200
|
||||
+++ linux.dev/arch/mips/config-shared.in 2006-10-02 21:19:59.000000000 +0200
|
||||
Index: linux-2.4.35.4/arch/mips/config-shared.in
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/arch/mips/config-shared.in 2007-12-15 05:19:53.151449966 +0100
|
||||
+++ linux-2.4.35.4/arch/mips/config-shared.in 2007-12-15 05:20:13.936634447 +0100
|
||||
@@ -208,6 +208,14 @@
|
||||
fi
|
||||
define_bool CONFIG_MIPS_RTC y
|
||||
|
@ -54,9 +55,10 @@ diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared
|
|||
dep_bool ' Console output to GDB' CONFIG_GDB_CONSOLE $CONFIG_KGDB
|
||||
if [ "$CONFIG_KGDB" = "y" ]; then
|
||||
define_bool CONFIG_DEBUG_INFO y
|
||||
diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
|
||||
--- linux.old/arch/mips/kernel/cpu-probe.c 2006-10-02 21:23:10.000000000 +0200
|
||||
+++ linux.dev/arch/mips/kernel/cpu-probe.c 2006-10-02 21:19:59.000000000 +0200
|
||||
Index: linux-2.4.35.4/arch/mips/kernel/cpu-probe.c
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/arch/mips/kernel/cpu-probe.c 2007-12-15 05:19:44.862977633 +0100
|
||||
+++ linux-2.4.35.4/arch/mips/kernel/cpu-probe.c 2007-12-15 05:20:13.944634901 +0100
|
||||
@@ -162,7 +162,7 @@
|
||||
|
||||
static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
|
||||
|
@ -176,9 +178,10 @@ diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-
|
|||
case PRID_COMP_SIBYTE:
|
||||
cpu_probe_sibyte(c);
|
||||
break;
|
||||
diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
|
||||
--- linux.old/arch/mips/kernel/head.S 2006-10-02 21:23:10.000000000 +0200
|
||||
+++ linux.dev/arch/mips/kernel/head.S 2006-10-02 21:19:59.000000000 +0200
|
||||
Index: linux-2.4.35.4/arch/mips/kernel/head.S
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/arch/mips/kernel/head.S 2007-12-15 05:19:44.866977862 +0100
|
||||
+++ linux-2.4.35.4/arch/mips/kernel/head.S 2007-12-15 05:20:13.944634901 +0100
|
||||
@@ -28,12 +28,20 @@
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/stackframe.h>
|
||||
|
@ -201,9 +204,10 @@ diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
|
|||
|
||||
/* The following two symbols are used for kernel profiling. */
|
||||
EXPORT(stext)
|
||||
diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
|
||||
--- linux.old/arch/mips/kernel/proc.c 2006-10-02 21:23:10.000000000 +0200
|
||||
+++ linux.dev/arch/mips/kernel/proc.c 2006-10-02 21:19:59.000000000 +0200
|
||||
Index: linux-2.4.35.4/arch/mips/kernel/proc.c
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/arch/mips/kernel/proc.c 2007-12-15 05:19:36.358492990 +0100
|
||||
+++ linux-2.4.35.4/arch/mips/kernel/proc.c 2007-12-15 05:20:13.944634901 +0100
|
||||
@@ -78,9 +78,10 @@
|
||||
[CPU_AU1550] "Au1550",
|
||||
[CPU_24K] "MIPS 24K",
|
||||
|
@ -216,9 +220,10 @@ diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
|
|||
static int show_cpuinfo(struct seq_file *m, void *v)
|
||||
{
|
||||
unsigned int version = current_cpu_data.processor_id;
|
||||
diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
|
||||
--- linux.old/arch/mips/kernel/setup.c 2006-10-02 21:23:10.000000000 +0200
|
||||
+++ linux.dev/arch/mips/kernel/setup.c 2006-10-02 21:19:59.000000000 +0200
|
||||
Index: linux-2.4.35.4/arch/mips/kernel/setup.c
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/arch/mips/kernel/setup.c 2007-12-15 05:19:44.866977862 +0100
|
||||
+++ linux-2.4.35.4/arch/mips/kernel/setup.c 2007-12-15 05:20:13.944634901 +0100
|
||||
@@ -493,6 +493,7 @@
|
||||
void swarm_setup(void);
|
||||
void hp_setup(void);
|
||||
|
@ -239,9 +244,10 @@ diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
|
|||
default:
|
||||
panic("Unsupported architecture");
|
||||
}
|
||||
diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
|
||||
--- linux.old/arch/mips/kernel/traps.c 2006-10-02 21:23:10.000000000 +0200
|
||||
+++ linux.dev/arch/mips/kernel/traps.c 2006-10-02 21:19:59.000000000 +0200
|
||||
Index: linux-2.4.35.4/arch/mips/kernel/traps.c
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/arch/mips/kernel/traps.c 2007-12-15 05:19:44.870978088 +0100
|
||||
+++ linux-2.4.35.4/arch/mips/kernel/traps.c 2007-12-15 05:20:13.944634901 +0100
|
||||
@@ -920,6 +920,7 @@
|
||||
void __init trap_init(void)
|
||||
{
|
||||
|
@ -271,9 +277,10 @@ diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
|
|||
if (cpu_has_fpu && !cpu_has_nofpuex)
|
||||
set_except_vector(15, handle_fpe);
|
||||
|
||||
diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
|
||||
--- linux.old/arch/mips/Makefile 2006-10-02 21:23:10.000000000 +0200
|
||||
+++ linux.dev/arch/mips/Makefile 2006-10-02 21:19:59.000000000 +0200
|
||||
Index: linux-2.4.35.4/arch/mips/Makefile
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/arch/mips/Makefile 2007-12-15 05:19:51.215339635 +0100
|
||||
+++ linux-2.4.35.4/arch/mips/Makefile 2007-12-15 05:20:13.948635130 +0100
|
||||
@@ -726,6 +726,19 @@
|
||||
endif
|
||||
|
||||
|
@ -294,7 +301,7 @@ diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
|
|||
# Choosing incompatible machines durings configuration will result in
|
||||
# error messages during linking. Select a default linkscript if
|
||||
# none has been choosen above.
|
||||
@@ -778,6 +791,7 @@
|
||||
@@ -779,6 +792,7 @@
|
||||
$(MAKE) -C arch/$(ARCH)/tools clean
|
||||
$(MAKE) -C arch/mips/baget clean
|
||||
$(MAKE) -C arch/mips/lasat clean
|
||||
|
@ -302,10 +309,11 @@ diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
|
|||
|
||||
archmrproper:
|
||||
@$(MAKEBOOT) mrproper
|
||||
diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
||||
--- linux.old/arch/mips/mm/c-r4k.c 2006-10-02 21:23:10.000000000 +0200
|
||||
+++ linux.dev/arch/mips/mm/c-r4k.c 2006-10-02 21:19:59.000000000 +0200
|
||||
@@ -1166,3 +1166,47 @@
|
||||
Index: linux-2.4.35.4/arch/mips/mm/c-r4k.c
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/arch/mips/mm/c-r4k.c 2007-12-15 05:19:44.874978317 +0100
|
||||
+++ linux-2.4.35.4/arch/mips/mm/c-r4k.c 2007-12-15 05:20:13.948635130 +0100
|
||||
@@ -1118,3 +1118,47 @@
|
||||
build_clear_page();
|
||||
build_copy_page();
|
||||
}
|
||||
|
@ -353,9 +361,10 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|||
+}
|
||||
+
|
||||
+
|
||||
diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
|
||||
--- linux.old/arch/mips/pci/Makefile 2006-10-02 21:23:10.000000000 +0200
|
||||
+++ linux.dev/arch/mips/pci/Makefile 2006-10-02 21:19:59.000000000 +0200
|
||||
Index: linux-2.4.35.4/arch/mips/pci/Makefile
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/arch/mips/pci/Makefile 2007-12-15 05:19:36.398495270 +0100
|
||||
+++ linux-2.4.35.4/arch/mips/pci/Makefile 2007-12-15 05:20:13.948635130 +0100
|
||||
@@ -13,7 +13,9 @@
|
||||
obj-$(CONFIG_MIPS_MSC) += ops-msc.o
|
||||
obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
|
||||
|
@ -366,9 +375,10 @@ diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
|
|||
obj-$(CONFIG_PCI_AUTO) += pci_auto.o
|
||||
|
||||
include $(TOPDIR)/Rules.make
|
||||
diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
|
||||
--- linux.old/drivers/char/serial.c 2006-10-02 21:23:10.000000000 +0200
|
||||
+++ linux.dev/drivers/char/serial.c 2006-10-02 21:19:59.000000000 +0200
|
||||
Index: linux-2.4.35.4/drivers/char/serial.c
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/drivers/char/serial.c 2007-12-15 05:20:00.539871010 +0100
|
||||
+++ linux-2.4.35.4/drivers/char/serial.c 2007-12-15 05:20:13.952635360 +0100
|
||||
@@ -444,6 +444,10 @@
|
||||
return inb(info->port+1);
|
||||
#endif
|
||||
|
@ -437,9 +447,10 @@ diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
|
|||
cval = cflag & (CSIZE | CSTOPB);
|
||||
#if defined(__powerpc__) || defined(__alpha__)
|
||||
cval >>= 8;
|
||||
diff -urN linux.old/drivers/net/Makefile linux.dev/drivers/net/Makefile
|
||||
--- linux.old/drivers/net/Makefile 2006-10-02 21:23:10.000000000 +0200
|
||||
+++ linux.dev/drivers/net/Makefile 2006-10-02 21:19:59.000000000 +0200
|
||||
Index: linux-2.4.35.4/drivers/net/Makefile
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/drivers/net/Makefile 2007-12-15 05:20:10.804455954 +0100
|
||||
+++ linux-2.4.35.4/drivers/net/Makefile 2007-12-15 05:20:13.952635360 +0100
|
||||
@@ -3,6 +3,8 @@
|
||||
# Makefile for the Linux network (ethercard) device drivers.
|
||||
#
|
||||
|
@ -449,9 +460,10 @@ diff -urN linux.old/drivers/net/Makefile linux.dev/drivers/net/Makefile
|
|||
obj-y :=
|
||||
obj-m :=
|
||||
obj-n :=
|
||||
diff -urN linux.old/drivers/parport/Config.in linux.dev/drivers/parport/Config.in
|
||||
--- linux.old/drivers/parport/Config.in 2006-10-02 21:23:10.000000000 +0200
|
||||
+++ linux.dev/drivers/parport/Config.in 2006-10-02 21:19:59.000000000 +0200
|
||||
Index: linux-2.4.35.4/drivers/parport/Config.in
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/drivers/parport/Config.in 2007-12-15 05:19:36.422496639 +0100
|
||||
+++ linux-2.4.35.4/drivers/parport/Config.in 2007-12-15 05:20:13.956635587 +0100
|
||||
@@ -11,6 +11,7 @@
|
||||
tristate 'Parallel port support' CONFIG_PARPORT
|
||||
if [ "$CONFIG_PARPORT" != "n" ]; then
|
||||
|
@ -460,9 +472,10 @@ diff -urN linux.old/drivers/parport/Config.in linux.dev/drivers/parport/Config.i
|
|||
if [ "$CONFIG_PARPORT_PC" != "n" -a "$CONFIG_SERIAL" != "n" ]; then
|
||||
if [ "$CONFIG_SERIAL" = "m" ]; then
|
||||
define_tristate CONFIG_PARPORT_PC_CML1 m
|
||||
diff -urN linux.old/drivers/parport/Makefile linux.dev/drivers/parport/Makefile
|
||||
--- linux.old/drivers/parport/Makefile 2006-10-02 21:23:10.000000000 +0200
|
||||
+++ linux.dev/drivers/parport/Makefile 2006-10-02 21:19:59.000000000 +0200
|
||||
Index: linux-2.4.35.4/drivers/parport/Makefile
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/drivers/parport/Makefile 2007-12-15 05:19:36.430497094 +0100
|
||||
+++ linux-2.4.35.4/drivers/parport/Makefile 2007-12-15 05:20:13.956635587 +0100
|
||||
@@ -22,6 +22,7 @@
|
||||
|
||||
obj-$(CONFIG_PARPORT) += parport.o
|
||||
|
@ -471,9 +484,10 @@ diff -urN linux.old/drivers/parport/Makefile linux.dev/drivers/parport/Makefile
|
|||
obj-$(CONFIG_PARPORT_PC_PCMCIA) += parport_cs.o
|
||||
obj-$(CONFIG_PARPORT_AMIGA) += parport_amiga.o
|
||||
obj-$(CONFIG_PARPORT_MFC3) += parport_mfc3.o
|
||||
diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
|
||||
--- linux.old/include/asm-mips/bootinfo.h 2006-10-02 21:23:10.000000000 +0200
|
||||
+++ linux.dev/include/asm-mips/bootinfo.h 2006-10-02 21:19:59.000000000 +0200
|
||||
Index: linux-2.4.35.4/include/asm-mips/bootinfo.h
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/include/asm-mips/bootinfo.h 2007-12-15 05:19:45.026986980 +0100
|
||||
+++ linux-2.4.35.4/include/asm-mips/bootinfo.h 2007-12-15 05:20:13.956635587 +0100
|
||||
@@ -37,6 +37,7 @@
|
||||
#define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */
|
||||
#define MACH_GROUP_LASAT 21
|
||||
|
@ -498,9 +512,10 @@ diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/booti
|
|||
* Valid machtype for group TITAN
|
||||
*/
|
||||
#define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
|
||||
diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
|
||||
--- linux.old/include/asm-mips/cpu.h 2006-10-02 21:23:10.000000000 +0200
|
||||
+++ linux.dev/include/asm-mips/cpu.h 2006-10-02 21:19:59.000000000 +0200
|
||||
Index: linux-2.4.35.4/include/asm-mips/cpu.h
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/include/asm-mips/cpu.h 2007-12-15 05:19:36.442497779 +0100
|
||||
+++ linux-2.4.35.4/include/asm-mips/cpu.h 2007-12-15 05:20:13.956635587 +0100
|
||||
@@ -22,6 +22,11 @@
|
||||
spec.
|
||||
*/
|
||||
|
@ -549,10 +564,11 @@ diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
|
|||
|
||||
/*
|
||||
* ISA Level encodings
|
||||
diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
|
||||
--- linux.old/include/asm-mips/r4kcache.h 2006-10-02 21:23:10.000000000 +0200
|
||||
+++ linux.dev/include/asm-mips/r4kcache.h 2006-10-02 21:19:59.000000000 +0200
|
||||
@@ -658,4 +658,17 @@
|
||||
Index: linux-2.4.35.4/include/asm-mips/r4kcache.h
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/include/asm-mips/r4kcache.h 2007-12-15 05:19:36.450498234 +0100
|
||||
+++ linux-2.4.35.4/include/asm-mips/r4kcache.h 2007-12-15 05:20:13.960635812 +0100
|
||||
@@ -567,4 +567,17 @@
|
||||
cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
|
||||
}
|
||||
|
||||
|
@ -570,9 +586,10 @@ diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kca
|
|||
+}
|
||||
+
|
||||
#endif /* __ASM_R4KCACHE_H */
|
||||
diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
|
||||
--- linux.old/include/asm-mips/serial.h 2006-10-02 21:23:10.000000000 +0200
|
||||
+++ linux.dev/include/asm-mips/serial.h 2006-10-02 21:19:59.000000000 +0200
|
||||
Index: linux-2.4.35.4/include/asm-mips/serial.h
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/include/asm-mips/serial.h 2007-12-15 05:19:36.458498689 +0100
|
||||
+++ linux-2.4.35.4/include/asm-mips/serial.h 2007-12-15 05:20:13.960635812 +0100
|
||||
@@ -223,6 +223,13 @@
|
||||
#define TXX927_SERIAL_PORT_DEFNS
|
||||
#endif
|
||||
|
@ -595,9 +612,10 @@ diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.
|
|||
COBALT_SERIAL_PORT_DEFNS \
|
||||
DDB5477_SERIAL_PORT_DEFNS \
|
||||
EV96100_SERIAL_PORT_DEFNS \
|
||||
diff -urN linux.old/init/do_mounts.c linux.dev/init/do_mounts.c
|
||||
--- linux.old/init/do_mounts.c 2006-10-02 21:23:10.000000000 +0200
|
||||
+++ linux.dev/init/do_mounts.c 2006-10-02 21:19:59.000000000 +0200
|
||||
Index: linux-2.4.35.4/init/do_mounts.c
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/init/do_mounts.c 2007-12-15 05:19:48.667194423 +0100
|
||||
+++ linux-2.4.35.4/init/do_mounts.c 2007-12-15 05:20:13.960635812 +0100
|
||||
@@ -254,7 +254,13 @@
|
||||
{ "ftlb", 0x2c08 },
|
||||
{ "ftlc", 0x2c10 },
|
||||
|
|
|
@ -1,348 +0,0 @@
|
|||
diff -urN linux.old/include/linux/netdevice.h linux.dev/include/linux/netdevice.h
|
||||
--- linux.old/include/linux/netdevice.h 2006-03-19 06:32:22.000000000 +0100
|
||||
+++ linux.dev/include/linux/netdevice.h 2006-03-19 06:33:21.000000000 +0100
|
||||
@@ -296,10 +296,7 @@
|
||||
/* List of functions to handle Wireless Extensions (instead of ioctl).
|
||||
* See <net/iw_handler.h> for details. Jean II */
|
||||
const struct iw_handler_def * wireless_handlers;
|
||||
- /* Instance data managed by the core of Wireless Extensions. */
|
||||
- struct iw_public_data * wireless_data;
|
||||
|
||||
- struct ethtool_ops *ethtool_ops;
|
||||
|
||||
/*
|
||||
* This marks the end of the "visible" part of the structure. All
|
||||
@@ -354,8 +351,8 @@
|
||||
|
||||
struct Qdisc *qdisc;
|
||||
struct Qdisc *qdisc_sleeping;
|
||||
+ struct Qdisc *qdisc_list;
|
||||
struct Qdisc *qdisc_ingress;
|
||||
- struct list_head qdisc_list;
|
||||
unsigned long tx_queue_len; /* Max frames per queue allowed */
|
||||
|
||||
/* hard_start_xmit synchronizer */
|
||||
@@ -455,6 +452,10 @@
|
||||
/* this will get initialized at each interface type init routine */
|
||||
struct divert_blk *divert;
|
||||
#endif /* CONFIG_NET_DIVERT */
|
||||
+ struct ethtool_ops *ethtool_ops;
|
||||
+
|
||||
+ /* Instance data managed by the core of Wireless Extensions. */
|
||||
+ struct iw_public_data * wireless_data;
|
||||
};
|
||||
|
||||
/* 2.6 compatibility */
|
||||
diff -urN linux.old/include/linux/skbuff.h linux.dev/include/linux/skbuff.h
|
||||
--- linux.old/include/linux/skbuff.h 2006-03-19 06:32:22.000000000 +0100
|
||||
+++ linux.dev/include/linux/skbuff.h 2006-03-19 06:29:41.000000000 +0100
|
||||
@@ -138,10 +138,6 @@
|
||||
struct sock *sk; /* Socket we are owned by */
|
||||
struct timeval stamp; /* Time we arrived */
|
||||
struct net_device *dev; /* Device we arrived on/are leaving by */
|
||||
- struct net_device *real_dev; /* For support of point to point protocols
|
||||
- (e.g. 802.3ad) over bonding, we must save the
|
||||
- physical device that got the packet before
|
||||
- replacing skb->dev with the virtual device. */
|
||||
|
||||
/* Transport layer header */
|
||||
union
|
||||
@@ -225,6 +221,10 @@
|
||||
#if defined(CONFIG_IMQ) || defined(CONFIG_IMQ_MODULE)
|
||||
struct nf_info *nf_info;
|
||||
#endif
|
||||
+ struct net_device *real_dev; /* For support of point to point protocols
|
||||
+ (e.g. 802.3ad) over bonding, we must save the
|
||||
+ physical device that got the packet before
|
||||
+ replacing skb->dev with the virtual device. */
|
||||
};
|
||||
|
||||
#ifdef __KERNEL__
|
||||
diff -urN linux.old/include/net/pkt_sched.h linux.dev/include/net/pkt_sched.h
|
||||
--- linux.old/include/net/pkt_sched.h 2006-03-19 06:32:22.000000000 +0100
|
||||
+++ linux.dev/include/net/pkt_sched.h 2006-03-19 06:29:41.000000000 +0100
|
||||
@@ -63,8 +63,11 @@
|
||||
int (*enqueue)(struct sk_buff *, struct Qdisc *);
|
||||
struct sk_buff * (*dequeue)(struct Qdisc *);
|
||||
int (*requeue)(struct sk_buff *, struct Qdisc *);
|
||||
- unsigned int (*drop)(struct Qdisc *);
|
||||
-
|
||||
+#ifdef CONFIG_BCM4710
|
||||
+ int (*drop)(struct Qdisc *);
|
||||
+#else
|
||||
+ unsigned int (*drop)(struct Qdisc *);
|
||||
+#endif
|
||||
int (*init)(struct Qdisc *, struct rtattr *arg);
|
||||
void (*reset)(struct Qdisc *);
|
||||
void (*destroy)(struct Qdisc *);
|
||||
@@ -84,12 +87,19 @@
|
||||
#define TCQ_F_THROTTLED 2
|
||||
#define TCQ_F_INGRESS 4
|
||||
struct Qdisc_ops *ops;
|
||||
+#ifdef CONFIG_BCM4710
|
||||
+ struct Qdisc *next;
|
||||
+#endif
|
||||
u32 handle;
|
||||
- u32 parent;
|
||||
+#ifndef CONFIG_BCM4710
|
||||
+ u32 parent;
|
||||
+#endif
|
||||
atomic_t refcnt;
|
||||
struct sk_buff_head q;
|
||||
struct net_device *dev;
|
||||
- struct list_head list;
|
||||
+#ifndef CONFIG_BCM4710
|
||||
+ struct list_head list;
|
||||
+#endif
|
||||
|
||||
struct tc_stats stats;
|
||||
int (*reshape_fail)(struct sk_buff *skb, struct Qdisc *q);
|
||||
diff -urN linux.old/net/core/Makefile linux.dev/net/core/Makefile
|
||||
--- linux.old/net/core/Makefile 2006-03-19 06:32:22.000000000 +0100
|
||||
+++ linux.dev/net/core/Makefile 2006-03-19 06:29:41.000000000 +0100
|
||||
@@ -9,7 +9,11 @@
|
||||
|
||||
O_TARGET := core.o
|
||||
|
||||
+ifeq ($(CONFIG_BCM4710),y)
|
||||
+export-objs := netfilter.o profile.o neighbour.o
|
||||
+else
|
||||
export-objs := netfilter.o profile.o ethtool.o neighbour.o
|
||||
+endif
|
||||
|
||||
obj-y := sock.o skbuff.o iovec.o datagram.o scm.o
|
||||
|
||||
@@ -21,8 +25,13 @@
|
||||
|
||||
obj-$(CONFIG_FILTER) += filter.o
|
||||
|
||||
+ifeq ($(CONFIG_BCM4710),y)
|
||||
+obj-$(CONFIG_NET) += dev.o dev_mcast.o dst.o neighbour.o \
|
||||
+ rtnetlink.o utils.o
|
||||
+else
|
||||
obj-$(CONFIG_NET) += dev.o ethtool.o dev_mcast.o dst.o neighbour.o \
|
||||
rtnetlink.o utils.o
|
||||
+endif
|
||||
|
||||
obj-$(CONFIG_NETFILTER) += netfilter.o
|
||||
obj-$(CONFIG_NET_DIVERT) += dv.o
|
||||
diff -urN linux.old/net/core/dev.c linux.dev/net/core/dev.c
|
||||
--- linux.old/net/core/dev.c 2006-03-19 06:32:22.000000000 +0100
|
||||
+++ linux.dev/net/core/dev.c 2006-03-19 06:29:41.000000000 +0100
|
||||
@@ -2232,6 +2232,7 @@
|
||||
cmd == SIOCGMIIPHY ||
|
||||
cmd == SIOCGMIIREG ||
|
||||
cmd == SIOCSMIIREG ||
|
||||
+ cmd == SIOCETHTOOL ||
|
||||
cmd == SIOCWANDEV) {
|
||||
if (dev->do_ioctl) {
|
||||
if (!netif_device_present(dev))
|
||||
@@ -2324,6 +2325,7 @@
|
||||
}
|
||||
return ret;
|
||||
|
||||
+#ifndef CONFIG_BCM4710
|
||||
case SIOCETHTOOL:
|
||||
dev_load(ifr.ifr_name);
|
||||
rtnl_lock();
|
||||
@@ -2337,6 +2339,7 @@
|
||||
ret = -EFAULT;
|
||||
}
|
||||
return ret;
|
||||
+#endif
|
||||
|
||||
/*
|
||||
* These ioctl calls:
|
||||
@@ -2412,6 +2415,7 @@
|
||||
|
||||
default:
|
||||
if (cmd == SIOCWANDEV ||
|
||||
+ (cmd == SIOCETHTOOL) ||
|
||||
(cmd >= SIOCDEVPRIVATE &&
|
||||
cmd <= SIOCDEVPRIVATE + 15)) {
|
||||
dev_load(ifr.ifr_name);
|
||||
diff -urN linux.old/net/sched/sch_api.c linux.dev/net/sched/sch_api.c
|
||||
--- linux.old/net/sched/sch_api.c 2006-03-19 06:32:22.000000000 +0100
|
||||
+++ linux.dev/net/sched/sch_api.c 2006-03-19 06:29:41.000000000 +0100
|
||||
@@ -194,11 +194,12 @@
|
||||
{
|
||||
struct Qdisc *q;
|
||||
|
||||
- list_for_each_entry(q, &dev->qdisc_list, list) {
|
||||
+ for (q = dev->qdisc_list; q; q = q->next) {
|
||||
if (q->handle == handle)
|
||||
return q;
|
||||
}
|
||||
return NULL;
|
||||
+
|
||||
}
|
||||
|
||||
struct Qdisc *qdisc_leaf(struct Qdisc *p, u32 classid)
|
||||
@@ -371,8 +372,6 @@
|
||||
unsigned long cl = cops->get(parent, classid);
|
||||
if (cl) {
|
||||
err = cops->graft(parent, cl, new, old);
|
||||
- if (new)
|
||||
- new->parent = classid;
|
||||
cops->put(parent, cl);
|
||||
}
|
||||
}
|
||||
@@ -427,7 +426,6 @@
|
||||
|
||||
memset(sch, 0, size);
|
||||
|
||||
- INIT_LIST_HEAD(&sch->list);
|
||||
skb_queue_head_init(&sch->q);
|
||||
|
||||
if (handle == TC_H_INGRESS)
|
||||
@@ -453,7 +451,8 @@
|
||||
|
||||
if (!ops->init || (err = ops->init(sch, tca[TCA_OPTIONS-1])) == 0) {
|
||||
write_lock(&qdisc_tree_lock);
|
||||
- list_add_tail(&sch->list, &dev->qdisc_list);
|
||||
+ sch->next = dev->qdisc_list;
|
||||
+ dev->qdisc_list = sch;
|
||||
write_unlock(&qdisc_tree_lock);
|
||||
#ifdef CONFIG_NET_ESTIMATOR
|
||||
if (tca[TCA_RATE-1])
|
||||
@@ -808,19 +807,16 @@
|
||||
if (idx > s_idx)
|
||||
s_q_idx = 0;
|
||||
read_lock(&qdisc_tree_lock);
|
||||
- q_idx = 0;
|
||||
- list_for_each_entry(q, &dev->qdisc_list, list) {
|
||||
- if (q_idx < s_q_idx) {
|
||||
- q_idx++;
|
||||
- continue;
|
||||
- }
|
||||
- if (tc_fill_qdisc(skb, q, q->parent, NETLINK_CB(cb->skb).pid,
|
||||
- cb->nlh->nlmsg_seq, NLM_F_MULTI, RTM_NEWQDISC) <= 0) {
|
||||
- read_unlock(&qdisc_tree_lock);
|
||||
- goto done;
|
||||
- }
|
||||
- q_idx++;
|
||||
- }
|
||||
+ for (q = dev->qdisc_list, q_idx = 0; q;
|
||||
+ q = q->next, q_idx++) {
|
||||
+ if (q_idx < s_q_idx)
|
||||
+ continue;
|
||||
+ if (tc_fill_qdisc(skb, q, 0, NETLINK_CB(cb->skb).pid,
|
||||
+ cb->nlh->nlmsg_seq, NLM_F_MULTI, RTM_NEWQDISC) <= 0) {
|
||||
+ read_unlock(&qdisc_tree_lock);
|
||||
+ goto done;
|
||||
+ }
|
||||
+ }
|
||||
read_unlock(&qdisc_tree_lock);
|
||||
}
|
||||
|
||||
@@ -1033,27 +1029,24 @@
|
||||
t = 0;
|
||||
|
||||
read_lock(&qdisc_tree_lock);
|
||||
- list_for_each_entry(q, &dev->qdisc_list, list) {
|
||||
- if (t < s_t || !q->ops->cl_ops ||
|
||||
- (tcm->tcm_parent &&
|
||||
- TC_H_MAJ(tcm->tcm_parent) != q->handle)) {
|
||||
- t++;
|
||||
- continue;
|
||||
- }
|
||||
- if (t > s_t)
|
||||
- memset(&cb->args[1], 0, sizeof(cb->args)-sizeof(cb->args[0]));
|
||||
- arg.w.fn = qdisc_class_dump;
|
||||
- arg.skb = skb;
|
||||
- arg.cb = cb;
|
||||
- arg.w.stop = 0;
|
||||
- arg.w.skip = cb->args[1];
|
||||
- arg.w.count = 0;
|
||||
- q->ops->cl_ops->walk(q, &arg.w);
|
||||
- cb->args[1] = arg.w.count;
|
||||
- if (arg.w.stop)
|
||||
- break;
|
||||
- t++;
|
||||
- }
|
||||
+ for (q=dev->qdisc_list, t=0; q; q = q->next, t++) {
|
||||
+ if (t < s_t) continue;
|
||||
+ if (!q->ops->cl_ops) continue;
|
||||
+ if (tcm->tcm_parent && TC_H_MAJ(tcm->tcm_parent) != q->handle)
|
||||
+ continue;
|
||||
+ if (t > s_t)
|
||||
+ memset(&cb->args[1], 0, sizeof(cb->args)-sizeof(cb->args[0]));
|
||||
+ arg.w.fn = qdisc_class_dump;
|
||||
+ arg.skb = skb;
|
||||
+ arg.cb = cb;
|
||||
+ arg.w.stop = 0;
|
||||
+ arg.w.skip = cb->args[1];
|
||||
+ arg.w.count = 0;
|
||||
+ q->ops->cl_ops->walk(q, &arg.w);
|
||||
+ cb->args[1] = arg.w.count;
|
||||
+ if (arg.w.stop)
|
||||
+ break;
|
||||
+ }
|
||||
read_unlock(&qdisc_tree_lock);
|
||||
|
||||
cb->args[0] = t;
|
||||
diff -urN linux.old/net/sched/sch_generic.c linux.dev/net/sched/sch_generic.c
|
||||
--- linux.old/net/sched/sch_generic.c 2006-03-19 06:32:22.000000000 +0100
|
||||
+++ linux.dev/net/sched/sch_generic.c 2006-03-19 06:29:41.000000000 +0100
|
||||
@@ -399,7 +399,6 @@
|
||||
return NULL;
|
||||
memset(sch, 0, size);
|
||||
|
||||
- INIT_LIST_HEAD(&sch->list);
|
||||
skb_queue_head_init(&sch->q);
|
||||
sch->ops = ops;
|
||||
sch->enqueue = ops->enqueue;
|
||||
@@ -429,11 +428,22 @@
|
||||
void qdisc_destroy(struct Qdisc *qdisc)
|
||||
{
|
||||
struct Qdisc_ops *ops = qdisc->ops;
|
||||
+ struct net_device *dev;
|
||||
|
||||
if (qdisc->flags&TCQ_F_BUILTIN ||
|
||||
!atomic_dec_and_test(&qdisc->refcnt))
|
||||
return;
|
||||
- list_del(&qdisc->list);
|
||||
+
|
||||
+ dev = qdisc->dev;
|
||||
+ if (dev) {
|
||||
+ struct Qdisc *q, **qp;
|
||||
+ for (qp = &qdisc->dev->qdisc_list; (q=*qp) != NULL; qp = &q->next) {
|
||||
+ if (q == qdisc) {
|
||||
+ *qp = q->next;
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+ }
|
||||
#ifdef CONFIG_NET_ESTIMATOR
|
||||
qdisc_kill_estimator(&qdisc->stats);
|
||||
#endif
|
||||
@@ -462,9 +472,9 @@
|
||||
return;
|
||||
}
|
||||
write_lock(&qdisc_tree_lock);
|
||||
- list_add_tail(&qdisc->list, &dev->qdisc_list);
|
||||
+ qdisc->next = dev->qdisc_list;
|
||||
+ dev->qdisc_list = qdisc;
|
||||
write_unlock(&qdisc_tree_lock);
|
||||
-
|
||||
} else {
|
||||
qdisc = &noqueue_qdisc;
|
||||
}
|
||||
@@ -508,7 +518,7 @@
|
||||
dev->qdisc = &noop_qdisc;
|
||||
spin_unlock_bh(&dev->queue_lock);
|
||||
dev->qdisc_sleeping = &noop_qdisc;
|
||||
- INIT_LIST_HEAD(&dev->qdisc_list);
|
||||
+ dev->qdisc_list = NULL;
|
||||
write_unlock(&qdisc_tree_lock);
|
||||
|
||||
dev_watchdog_init(dev);
|
||||
@@ -530,7 +540,7 @@
|
||||
qdisc_destroy(qdisc);
|
||||
}
|
||||
#endif
|
||||
- BUG_TRAP(list_empty(&dev->qdisc_list));
|
||||
+ BUG_TRAP(dev->qdisc_list == NULL);
|
||||
BUG_TRAP(!timer_pending(&dev->watchdog_timer));
|
||||
spin_unlock_bh(&dev->queue_lock);
|
||||
write_unlock(&qdisc_tree_lock);
|
|
@ -1,6 +1,7 @@
|
|||
diff -urN linux.old/arch/mips/kernel/entry.S linux.dev/arch/mips/kernel/entry.S
|
||||
--- linux.old/arch/mips/kernel/entry.S 2005-07-05 16:46:49.000000000 +0200
|
||||
+++ linux.dev/arch/mips/kernel/entry.S 2005-07-06 11:23:55.000000000 +0200
|
||||
Index: linux-2.4.35.4/arch/mips/kernel/entry.S
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/arch/mips/kernel/entry.S 2007-12-15 05:19:36.266487747 +0100
|
||||
+++ linux-2.4.35.4/arch/mips/kernel/entry.S 2007-12-15 05:20:14.372659296 +0100
|
||||
@@ -100,6 +100,10 @@
|
||||
* and R4400 SC and MC versions.
|
||||
*/
|
||||
|
@ -12,9 +13,10 @@ diff -urN linux.old/arch/mips/kernel/entry.S linux.dev/arch/mips/kernel/entry.S
|
|||
#if R5432_CP0_INTERRUPT_WAR
|
||||
mfc0 k0, CP0_INDEX
|
||||
#endif
|
||||
diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
||||
--- linux.old/arch/mips/mm/c-r4k.c 2005-07-05 16:46:49.000000000 +0200
|
||||
+++ linux.dev/arch/mips/mm/c-r4k.c 2005-07-06 11:23:55.000000000 +0200
|
||||
Index: linux-2.4.35.4/arch/mips/mm/c-r4k.c
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/arch/mips/mm/c-r4k.c 2007-12-15 05:20:13.948635130 +0100
|
||||
+++ linux-2.4.35.4/arch/mips/mm/c-r4k.c 2007-12-15 05:20:14.376659523 +0100
|
||||
@@ -14,6 +14,12 @@
|
||||
#include <linux/mm.h>
|
||||
#include <linux/bitops.h>
|
||||
|
@ -28,16 +30,15 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|||
#include <asm/bcache.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/cacheops.h>
|
||||
@@ -40,6 +46,8 @@
|
||||
@@ -40,6 +46,7 @@
|
||||
.bc_inv = (void *)no_sc_noop
|
||||
};
|
||||
|
||||
+int bcm4710 = 0;
|
||||
+EXPORT_SYMBOL(bcm4710);
|
||||
struct bcache_ops *bcops = &no_sc_ops;
|
||||
|
||||
#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x2010)
|
||||
@@ -64,8 +72,10 @@
|
||||
@@ -64,8 +71,10 @@
|
||||
static inline void r4k_blast_dcache_page_setup(void)
|
||||
{
|
||||
unsigned long dc_lsize = current_cpu_data.dcache.linesz;
|
||||
|
@ -50,7 +51,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|||
r4k_blast_dcache_page = blast_dcache16_page;
|
||||
else if (dc_lsize == 32)
|
||||
r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
|
||||
@@ -77,7 +87,9 @@
|
||||
@@ -77,7 +86,9 @@
|
||||
{
|
||||
unsigned long dc_lsize = current_cpu_data.dcache.linesz;
|
||||
|
||||
|
@ -61,7 +62,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|||
r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
|
||||
else if (dc_lsize == 32)
|
||||
r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
|
||||
@@ -89,7 +101,9 @@
|
||||
@@ -89,7 +100,9 @@
|
||||
{
|
||||
unsigned long dc_lsize = current_cpu_data.dcache.linesz;
|
||||
|
||||
|
@ -72,7 +73,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|||
r4k_blast_dcache = blast_dcache16;
|
||||
else if (dc_lsize == 32)
|
||||
r4k_blast_dcache = blast_dcache32;
|
||||
@@ -266,6 +280,7 @@
|
||||
@@ -266,6 +279,7 @@
|
||||
r4k_blast_dcache();
|
||||
r4k_blast_icache();
|
||||
|
||||
|
@ -80,7 +81,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|||
switch (current_cpu_data.cputype) {
|
||||
case CPU_R4000SC:
|
||||
case CPU_R4000MC:
|
||||
@@ -304,10 +319,10 @@
|
||||
@@ -304,10 +318,10 @@
|
||||
* Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
|
||||
* only flush the primary caches but R10000 and R12000 behave sane ...
|
||||
*/
|
||||
|
@ -93,7 +94,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|||
r4k_blast_scache();
|
||||
}
|
||||
|
||||
@@ -383,12 +398,15 @@
|
||||
@@ -383,12 +397,15 @@
|
||||
unsigned long ic_lsize = current_cpu_data.icache.linesz;
|
||||
unsigned long addr, aend;
|
||||
|
||||
|
@ -111,7 +112,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|||
|
||||
while (1) {
|
||||
/* Hit_Writeback_Inv_D */
|
||||
@@ -403,8 +421,6 @@
|
||||
@@ -403,8 +420,6 @@
|
||||
if (end - start > icache_size)
|
||||
r4k_blast_icache();
|
||||
else {
|
||||
|
@ -120,7 +121,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|||
while (1) {
|
||||
/* Hit_Invalidate_I */
|
||||
protected_flush_icache_line(addr);
|
||||
@@ -413,6 +429,9 @@
|
||||
@@ -413,6 +428,9 @@
|
||||
addr += ic_lsize;
|
||||
}
|
||||
}
|
||||
|
@ -130,7 +131,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|||
}
|
||||
|
||||
/*
|
||||
@@ -443,7 +462,8 @@
|
||||
@@ -443,7 +461,8 @@
|
||||
if (cpu_has_subset_pcaches) {
|
||||
unsigned long addr = (unsigned long) page_address(page);
|
||||
|
||||
|
@ -140,7 +141,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|||
ClearPageDcacheDirty(page);
|
||||
|
||||
return;
|
||||
@@ -451,6 +471,7 @@
|
||||
@@ -451,6 +470,7 @@
|
||||
|
||||
if (!cpu_has_ic_fills_f_dc) {
|
||||
unsigned long addr = (unsigned long) page_address(page);
|
||||
|
@ -148,7 +149,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|||
r4k_blast_dcache_page(addr);
|
||||
ClearPageDcacheDirty(page);
|
||||
}
|
||||
@@ -477,7 +498,7 @@
|
||||
@@ -477,7 +497,7 @@
|
||||
/* Catch bad driver code */
|
||||
BUG_ON(size == 0);
|
||||
|
||||
|
@ -157,7 +158,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|||
unsigned long sc_lsize = current_cpu_data.scache.linesz;
|
||||
|
||||
if (size >= scache_size) {
|
||||
@@ -509,6 +530,8 @@
|
||||
@@ -509,6 +529,8 @@
|
||||
R4600_HIT_CACHEOP_WAR_IMPL;
|
||||
a = addr & ~(dc_lsize - 1);
|
||||
end = (addr + size - 1) & ~(dc_lsize - 1);
|
||||
|
@ -166,7 +167,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|||
while (1) {
|
||||
flush_dcache_line(a); /* Hit_Writeback_Inv_D */
|
||||
if (a == end)
|
||||
@@ -527,7 +550,7 @@
|
||||
@@ -527,7 +549,7 @@
|
||||
/* Catch bad driver code */
|
||||
BUG_ON(size == 0);
|
||||
|
||||
|
@ -175,7 +176,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|||
unsigned long sc_lsize = current_cpu_data.scache.linesz;
|
||||
|
||||
if (size >= scache_size) {
|
||||
@@ -554,6 +577,8 @@
|
||||
@@ -554,6 +576,8 @@
|
||||
R4600_HIT_CACHEOP_WAR_IMPL;
|
||||
a = addr & ~(dc_lsize - 1);
|
||||
end = (addr + size - 1) & ~(dc_lsize - 1);
|
||||
|
@ -184,7 +185,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|||
while (1) {
|
||||
flush_dcache_line(a); /* Hit_Writeback_Inv_D */
|
||||
if (a == end)
|
||||
@@ -577,6 +602,8 @@
|
||||
@@ -577,6 +601,8 @@
|
||||
unsigned long dc_lsize = current_cpu_data.dcache.linesz;
|
||||
|
||||
R4600_HIT_CACHEOP_WAR_IMPL;
|
||||
|
@ -193,7 +194,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|||
protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
|
||||
protected_flush_icache_line(addr & ~(ic_lsize - 1));
|
||||
if (MIPS4K_ICACHE_REFILL_WAR) {
|
||||
@@ -986,10 +1013,12 @@
|
||||
@@ -986,10 +1012,12 @@
|
||||
case CPU_R4000MC:
|
||||
case CPU_R4400SC:
|
||||
case CPU_R4400MC:
|
||||
|
@ -210,7 +211,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|||
break;
|
||||
|
||||
case CPU_R10000:
|
||||
@@ -1041,6 +1070,19 @@
|
||||
@@ -1041,6 +1069,19 @@
|
||||
static inline void coherency_setup(void)
|
||||
{
|
||||
change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
|
||||
|
@ -230,7 +231,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|||
|
||||
/*
|
||||
* c0_status.cu=0 specifies that updates by the sc instruction use
|
||||
@@ -1073,6 +1115,12 @@
|
||||
@@ -1073,6 +1114,12 @@
|
||||
memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
|
||||
memcpy((void *)(KSEG1 + 0x100), &except_vec2_generic, 0x80);
|
||||
|
||||
|
@ -243,9 +244,10 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|||
probe_pcache();
|
||||
setup_scache();
|
||||
|
||||
diff -urN linux.old/arch/mips/mm/tlbex-mips32.S linux.dev/arch/mips/mm/tlbex-mips32.S
|
||||
--- linux.old/arch/mips/mm/tlbex-mips32.S 2005-07-05 16:46:49.000000000 +0200
|
||||
+++ linux.dev/arch/mips/mm/tlbex-mips32.S 2005-07-06 11:23:56.000000000 +0200
|
||||
Index: linux-2.4.35.4/arch/mips/mm/tlbex-mips32.S
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/arch/mips/mm/tlbex-mips32.S 2007-12-15 05:19:44.874978317 +0100
|
||||
+++ linux-2.4.35.4/arch/mips/mm/tlbex-mips32.S 2007-12-15 05:20:14.380659748 +0100
|
||||
@@ -90,6 +90,9 @@
|
||||
.set noat
|
||||
LEAF(except_vec0_r4000)
|
||||
|
@ -256,9 +258,10 @@ diff -urN linux.old/arch/mips/mm/tlbex-mips32.S linux.dev/arch/mips/mm/tlbex-mip
|
|||
#ifdef CONFIG_SMP
|
||||
mfc0 k1, CP0_CONTEXT
|
||||
la k0, pgd_current
|
||||
diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
|
||||
--- linux.old/include/asm-mips/r4kcache.h 2005-07-05 16:46:49.000000000 +0200
|
||||
+++ linux.dev/include/asm-mips/r4kcache.h 2005-07-06 12:52:57.000000000 +0200
|
||||
Index: linux-2.4.35.4/include/asm-mips/r4kcache.h
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/include/asm-mips/r4kcache.h 2007-12-15 05:20:13.960635812 +0100
|
||||
+++ linux-2.4.35.4/include/asm-mips/r4kcache.h 2007-12-15 05:20:14.384659977 +0100
|
||||
@@ -15,6 +15,18 @@
|
||||
#include <asm/asm.h>
|
||||
#include <asm/cacheops.h>
|
||||
|
@ -461,9 +464,10 @@ diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kca
|
|||
do {
|
||||
cache64_unroll32(start,Hit_Invalidate_I);
|
||||
start += 0x800;
|
||||
diff -urN linux.old/include/asm-mips/stackframe.h linux.dev/include/asm-mips/stackframe.h
|
||||
--- linux.old/include/asm-mips/stackframe.h 2005-07-05 16:46:49.000000000 +0200
|
||||
+++ linux.dev/include/asm-mips/stackframe.h 2005-07-06 11:23:56.000000000 +0200
|
||||
Index: linux-2.4.35.4/include/asm-mips/stackframe.h
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/include/asm-mips/stackframe.h 2007-12-15 05:19:36.298489571 +0100
|
||||
+++ linux-2.4.35.4/include/asm-mips/stackframe.h 2007-12-15 05:20:14.388660206 +0100
|
||||
@@ -209,6 +209,20 @@
|
||||
|
||||
#endif
|
||||
|
@ -485,10 +489,11 @@ diff -urN linux.old/include/asm-mips/stackframe.h linux.dev/include/asm-mips/sta
|
|||
#define RESTORE_SP \
|
||||
lw sp, PT_R29(sp); \
|
||||
|
||||
diff -urN linux.old/mm/memory.c linux.dev/mm/memory.c
|
||||
--- linux.old/mm/memory.c 2005-04-04 03:42:20.000000000 +0200
|
||||
+++ linux.dev/mm/memory.c 2005-07-06 11:23:56.000000000 +0200
|
||||
@@ -925,6 +925,7 @@
|
||||
Index: linux-2.4.35.4/mm/memory.c
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/mm/memory.c 2007-12-15 05:19:36.306490026 +0100
|
||||
+++ linux-2.4.35.4/mm/memory.c 2007-12-15 05:20:14.388660206 +0100
|
||||
@@ -927,6 +927,7 @@
|
||||
flush_page_to_ram(new_page);
|
||||
flush_cache_page(vma, address);
|
||||
establish_pte(vma, address, page_table, pte_mkwrite(pte_mkdirty(mk_pte(new_page, vma->vm_page_prot))));
|
||||
|
|
|
@ -1,6 +1,7 @@
|
|||
diff -urN linux.old/drivers/mtd/devices/Config.in linux.dev/drivers/mtd/devices/Config.in
|
||||
--- linux.old/drivers/mtd/devices/Config.in 2006-06-22 17:35:39.000000000 +0200
|
||||
+++ linux.dev/drivers/mtd/devices/Config.in 2006-06-21 21:41:24.000000000 +0200
|
||||
Index: linux-2.4.35.4/drivers/mtd/devices/Config.in
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/drivers/mtd/devices/Config.in 2007-12-15 05:19:36.210484556 +0100
|
||||
+++ linux-2.4.35.4/drivers/mtd/devices/Config.in 2007-12-15 05:20:14.656675480 +0100
|
||||
@@ -5,6 +5,7 @@
|
||||
mainmenu_option next_comment
|
||||
|
||||
|
@ -9,9 +10,10 @@ diff -urN linux.old/drivers/mtd/devices/Config.in linux.dev/drivers/mtd/devices/
|
|||
dep_tristate ' Ramix PMC551 PCI Mezzanine RAM card support' CONFIG_MTD_PMC551 $CONFIG_MTD $CONFIG_PCI
|
||||
if [ "$CONFIG_MTD_PMC551" = "y" -o "$CONFIG_MTD_PMC551" = "m" ]; then
|
||||
bool ' PMC551 256M DRAM Bugfix' CONFIG_MTD_PMC551_BUGFIX
|
||||
diff -urN linux.old/drivers/mtd/devices/Makefile linux.dev/drivers/mtd/devices/Makefile
|
||||
--- linux.old/drivers/mtd/devices/Makefile 2006-06-22 17:35:39.000000000 +0200
|
||||
+++ linux.dev/drivers/mtd/devices/Makefile 2006-06-21 21:41:24.000000000 +0200
|
||||
Index: linux-2.4.35.4/drivers/mtd/devices/Makefile
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/drivers/mtd/devices/Makefile 2007-12-15 05:19:36.218485012 +0100
|
||||
+++ linux-2.4.35.4/drivers/mtd/devices/Makefile 2007-12-15 05:20:14.660675705 +0100
|
||||
@@ -3,6 +3,8 @@
|
||||
#
|
||||
# $Id: Makefile,v 1.4 2001/06/26 21:10:05 spse Exp $
|
||||
|
@ -29,9 +31,10 @@ diff -urN linux.old/drivers/mtd/devices/Makefile linux.dev/drivers/mtd/devices/M
|
|||
obj-$(CONFIG_MTD_DOC1000) += doc1000.o
|
||||
obj-$(CONFIG_MTD_DOC2000) += doc2000.o
|
||||
obj-$(CONFIG_MTD_DOC2001) += doc2001.o
|
||||
diff -urN linux.old/drivers/mtd/maps/Config.in linux.dev/drivers/mtd/maps/Config.in
|
||||
--- linux.old/drivers/mtd/maps/Config.in 2006-06-22 17:35:39.000000000 +0200
|
||||
+++ linux.dev/drivers/mtd/maps/Config.in 2006-06-21 21:41:24.000000000 +0200
|
||||
Index: linux-2.4.35.4/drivers/mtd/maps/Config.in
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/drivers/mtd/maps/Config.in 2007-12-15 05:19:44.950982647 +0100
|
||||
+++ linux-2.4.35.4/drivers/mtd/maps/Config.in 2007-12-15 05:20:14.664675934 +0100
|
||||
@@ -48,6 +48,7 @@
|
||||
fi
|
||||
|
||||
|
@ -40,9 +43,10 @@ diff -urN linux.old/drivers/mtd/maps/Config.in linux.dev/drivers/mtd/maps/Config
|
|||
dep_tristate ' Pb1000 MTD support' CONFIG_MTD_PB1000 $CONFIG_MIPS_PB1000
|
||||
dep_tristate ' Pb1500 MTD support' CONFIG_MTD_PB1500 $CONFIG_MIPS_PB1500
|
||||
dep_tristate ' Pb1100 MTD support' CONFIG_MTD_PB1100 $CONFIG_MIPS_PB1100
|
||||
diff -urN linux.old/drivers/mtd/maps/Makefile linux.dev/drivers/mtd/maps/Makefile
|
||||
--- linux.old/drivers/mtd/maps/Makefile 2006-06-22 17:35:39.000000000 +0200
|
||||
+++ linux.dev/drivers/mtd/maps/Makefile 2006-06-21 21:41:24.000000000 +0200
|
||||
Index: linux-2.4.35.4/drivers/mtd/maps/Makefile
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/drivers/mtd/maps/Makefile 2007-12-15 05:19:44.954982876 +0100
|
||||
+++ linux-2.4.35.4/drivers/mtd/maps/Makefile 2007-12-15 05:20:14.664675934 +0100
|
||||
@@ -3,6 +3,8 @@
|
||||
#
|
||||
# $Id: Makefile,v 1.37 2003/01/24 14:26:38 dwmw2 Exp $
|
||||
|
|
|
@ -1,5 +1,7 @@
|
|||
--- linux-2.4.30/drivers/bluetooth/hci_usb.c 2004-08-08 01:26:04.000000000 +0200
|
||||
+++ linux-2.4.30/drivers/bluetooth/hci_usb.c 2005-07-25 20:12:11.000000000 +0200
|
||||
Index: linux-2.4.35.4/drivers/bluetooth/hci_usb.c
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/drivers/bluetooth/hci_usb.c 2007-12-15 05:19:36.182482961 +0100
|
||||
+++ linux-2.4.35.4/drivers/bluetooth/hci_usb.c 2007-12-15 05:20:14.964693031 +0100
|
||||
@@ -259,6 +259,9 @@
|
||||
void *buf;
|
||||
|
||||
|
|
|
@ -1,6 +1,7 @@
|
|||
diff -urN linux.old/arch/mips/lib/ide-std.c linux.dev/arch/mips/lib/ide-std.c
|
||||
--- linux.old/arch/mips/lib/ide-std.c 2003-08-25 13:44:40.000000000 +0200
|
||||
+++ linux.dev/arch/mips/lib/ide-std.c 2005-08-12 23:55:23.886963936 +0200
|
||||
Index: linux-2.4.35.4/arch/mips/lib/ide-std.c
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/arch/mips/lib/ide-std.c 2007-12-15 05:19:36.146480908 +0100
|
||||
+++ linux-2.4.35.4/arch/mips/lib/ide-std.c 2007-12-15 05:20:15.796740447 +0100
|
||||
@@ -31,12 +31,14 @@
|
||||
static ide_ioreg_t std_ide_default_io_base(int index)
|
||||
{
|
||||
|
|
|
@ -1,6 +1,7 @@
|
|||
diff -urN linux.old/drivers/net/b44.c linux.dev/drivers/net/b44.c
|
||||
--- linux.old/drivers/net/b44.c 2006-02-12 13:49:59.000000000 +0100
|
||||
+++ linux.dev/drivers/net/b44.c 2006-03-06 22:37:14.000000000 +0100
|
||||
Index: linux-2.4.35.4/drivers/net/b44.c
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/drivers/net/b44.c 2007-12-15 05:19:36.094477944 +0100
|
||||
+++ linux-2.4.35.4/drivers/net/b44.c 2007-12-15 05:20:16.020753214 +0100
|
||||
@@ -1,7 +1,9 @@
|
||||
/* b44.c: Broadcom 4400 device driver.
|
||||
*
|
||||
|
@ -12,15 +13,13 @@ diff -urN linux.old/drivers/net/b44.c linux.dev/drivers/net/b44.c
|
|||
*
|
||||
* Distribute under GPL.
|
||||
*/
|
||||
@@ -25,6 +27,41 @@
|
||||
@@ -25,6 +27,39 @@
|
||||
|
||||
#include "b44.h"
|
||||
|
||||
+#include <typedefs.h>
|
||||
+#include <bcmdevs.h>
|
||||
+#include <bcmutils.h>
|
||||
+#include <osl.h>
|
||||
+#include <bcmutils.h>
|
||||
+#include <bcmnvram.h>
|
||||
+#include <sbconfig.h>
|
||||
+#include <sbchipc.h>
|
||||
|
@ -400,7 +399,7 @@ diff -urN linux.old/drivers/net/b44.c linux.dev/drivers/net/b44.c
|
|||
bw32(B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
|
||||
(0x0d & MDIO_CTRL_MAXF_MASK)));
|
||||
br32(B44_MDIO_CTRL);
|
||||
@@ -1215,6 +1357,8 @@
|
||||
@@ -1216,6 +1358,8 @@
|
||||
struct b44 *bp = dev->priv;
|
||||
int err;
|
||||
|
||||
|
@ -409,7 +408,7 @@ diff -urN linux.old/drivers/net/b44.c linux.dev/drivers/net/b44.c
|
|||
err = b44_alloc_consistent(bp);
|
||||
if (err)
|
||||
return err;
|
||||
@@ -1235,9 +1379,10 @@
|
||||
@@ -1236,9 +1380,10 @@
|
||||
bp->timer.expires = jiffies + HZ;
|
||||
bp->timer.data = (unsigned long) bp;
|
||||
bp->timer.function = b44_timer;
|
||||
|
@ -421,7 +420,7 @@ diff -urN linux.old/drivers/net/b44.c linux.dev/drivers/net/b44.c
|
|||
|
||||
return 0;
|
||||
|
||||
@@ -1628,7 +1773,7 @@
|
||||
@@ -1638,7 +1783,7 @@
|
||||
u32 mii_regval;
|
||||
|
||||
spin_lock_irq(&bp->lock);
|
||||
|
@ -430,7 +429,7 @@ diff -urN linux.old/drivers/net/b44.c linux.dev/drivers/net/b44.c
|
|||
spin_unlock_irq(&bp->lock);
|
||||
|
||||
data->val_out = mii_regval;
|
||||
@@ -1641,7 +1786,7 @@
|
||||
@@ -1651,7 +1796,7 @@
|
||||
return -EPERM;
|
||||
|
||||
spin_lock_irq(&bp->lock);
|
||||
|
@ -439,7 +438,7 @@ diff -urN linux.old/drivers/net/b44.c linux.dev/drivers/net/b44.c
|
|||
spin_unlock_irq(&bp->lock);
|
||||
|
||||
return err;
|
||||
@@ -1668,21 +1813,52 @@
|
||||
@@ -1678,21 +1823,52 @@
|
||||
static int __devinit b44_get_invariants(struct b44 *bp)
|
||||
{
|
||||
u8 eeprom[128];
|
||||
|
@ -505,7 +504,7 @@ diff -urN linux.old/drivers/net/b44.c linux.dev/drivers/net/b44.c
|
|||
|
||||
/* With this, plus the rx_header prepended to the data by the
|
||||
* hardware, we'll land the ethernet header on a 2-byte boundary.
|
||||
@@ -1692,13 +1868,12 @@
|
||||
@@ -1702,13 +1878,12 @@
|
||||
bp->imask = IMASK_DEF;
|
||||
|
||||
bp->core_unit = ssb_core_unit(bp);
|
||||
|
@ -521,7 +520,7 @@ diff -urN linux.old/drivers/net/b44.c linux.dev/drivers/net/b44.c
|
|||
}
|
||||
|
||||
static int __devinit b44_init_one(struct pci_dev *pdev,
|
||||
@@ -1710,6 +1885,10 @@
|
||||
@@ -1720,6 +1895,10 @@
|
||||
struct b44 *bp;
|
||||
int err, i;
|
||||
|
||||
|
@ -532,9 +531,9 @@ diff -urN linux.old/drivers/net/b44.c linux.dev/drivers/net/b44.c
|
|||
if (b44_version_printed++ == 0)
|
||||
printk(KERN_INFO "%s", version);
|
||||
|
||||
@@ -1819,11 +1998,17 @@
|
||||
|
||||
pci_save_state(bp->pdev, bp->pci_cfg_state);
|
||||
@@ -1834,11 +2013,17 @@
|
||||
*/
|
||||
b44_chip_reset(bp);
|
||||
|
||||
- printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
|
||||
+ printk(KERN_INFO "%s: Broadcom %s 10/100BaseT Ethernet ", dev->name,
|
||||
|
@ -551,9 +550,10 @@ diff -urN linux.old/drivers/net/b44.c linux.dev/drivers/net/b44.c
|
|||
return 0;
|
||||
|
||||
err_out_iounmap:
|
||||
diff -urN linux.old/drivers/net/b44.h linux.dev/drivers/net/b44.h
|
||||
--- linux.old/drivers/net/b44.h 2006-02-12 13:49:59.000000000 +0100
|
||||
+++ linux.dev/drivers/net/b44.h 2006-01-24 20:52:08.000000000 +0100
|
||||
Index: linux-2.4.35.4/drivers/net/b44.h
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/drivers/net/b44.h 2007-12-15 05:19:36.102478402 +0100
|
||||
+++ linux-2.4.35.4/drivers/net/b44.h 2007-12-15 05:20:16.028753670 +0100
|
||||
@@ -229,8 +229,6 @@
|
||||
#define SBIPSFLAG_IMASK4 0x3f000000 /* Which sbflags --> mips interrupt 4 */
|
||||
#define SBIPSFLAG_ISHIFT4 24
|
||||
|
@ -572,10 +572,11 @@ diff -urN linux.old/drivers/net/b44.h linux.dev/drivers/net/b44.h
|
|||
|
||||
/* SW copy of device statistics, kept up to date by periodic timer
|
||||
* which probes HW values. Must have same relative layout as HW
|
||||
diff -urN linux.old/include/linux/pci_ids.h linux.dev/include/linux/pci_ids.h
|
||||
--- linux.old/include/linux/pci_ids.h 2006-02-12 13:49:59.000000000 +0100
|
||||
+++ linux.dev/include/linux/pci_ids.h 2006-01-24 20:52:08.000000000 +0100
|
||||
@@ -1735,6 +1735,7 @@
|
||||
Index: linux-2.4.35.4/include/linux/pci_ids.h
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/include/linux/pci_ids.h 2007-12-15 05:19:36.114479084 +0100
|
||||
+++ linux-2.4.35.4/include/linux/pci_ids.h 2007-12-15 05:20:16.032753896 +0100
|
||||
@@ -1756,6 +1756,7 @@
|
||||
#define PCI_DEVICE_ID_TIGON3_5901_2 0x170e
|
||||
#define PCI_DEVICE_ID_BCM4401 0x4401
|
||||
#define PCI_DEVICE_ID_BCM4401B0 0x4402
|
||||
|
|
|
@ -1,6 +1,7 @@
|
|||
diff -urN linux.old/drivers/pcmcia/yenta.c linux.dev/drivers/pcmcia/yenta.c
|
||||
--- linux.old/drivers/pcmcia/yenta.c 2004-11-17 12:54:21.000000000 +0100
|
||||
+++ linux.dev/drivers/pcmcia/yenta.c 2006-04-11 17:47:45.000000000 +0200
|
||||
Index: linux-2.4.35.4/drivers/pcmcia/yenta.c
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/drivers/pcmcia/yenta.c 2007-12-15 05:19:36.066476349 +0100
|
||||
+++ linux-2.4.35.4/drivers/pcmcia/yenta.c 2007-12-15 05:20:16.268767348 +0100
|
||||
@@ -543,6 +543,9 @@
|
||||
* Probe for usable interrupts using the force
|
||||
* register to generate bogus card status events.
|
||||
|
|
|
@ -1,5 +1,7 @@
|
|||
--- linux-2.4.32.orig/drivers/net/b44.h 2006-09-19 19:56:03.000000000 +0200
|
||||
+++ linux-2.4.32/drivers/net/b44.h 2006-09-19 19:58:01.000000000 +0200
|
||||
Index: linux-2.4.35.4/drivers/net/b44.h
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/drivers/net/b44.h 2007-12-15 05:20:16.028753670 +0100
|
||||
+++ linux-2.4.35.4/drivers/net/b44.h 2007-12-15 05:20:16.480779429 +0100
|
||||
@@ -122,6 +122,7 @@
|
||||
#define RXCONFIG_FLOW 0x00000020 /* Flow Control Enable */
|
||||
#define RXCONFIG_FLOW_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */
|
||||
|
@ -8,8 +10,10 @@
|
|||
#define B44_RXMAXLEN 0x0404UL /* EMAC RX Max Packet Length */
|
||||
#define B44_TXMAXLEN 0x0408UL /* EMAC TX Max Packet Length */
|
||||
#define B44_MDIO_CTRL 0x0410UL /* EMAC MDIO Control */
|
||||
--- linux-2.4.32.orig/drivers/net/b44.c 2006-09-19 19:56:03.000000000 +0200
|
||||
+++ linux-2.4.32/drivers/net/b44.c 2006-09-19 20:08:22.000000000 +0200
|
||||
Index: linux-2.4.35.4/drivers/net/b44.c
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/drivers/net/b44.c 2007-12-15 05:20:16.020753214 +0100
|
||||
+++ linux-2.4.35.4/drivers/net/b44.c 2007-12-15 05:20:16.480779429 +0100
|
||||
@@ -1301,6 +1301,7 @@
|
||||
{
|
||||
struct b44 *bp = dev->priv;
|
||||
|
@ -31,7 +35,7 @@
|
|||
spin_unlock_irq(&bp->lock);
|
||||
|
||||
return 0;
|
||||
@@ -1488,7 +1493,7 @@
|
||||
@@ -1495,7 +1500,7 @@
|
||||
|
||||
val = br32(B44_RXCONFIG);
|
||||
val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
|
||||
|
|
|
@ -1,5 +1,7 @@
|
|||
--- linux.old/net/sched/sch_generic.c 2006-11-24 02:42:23.000000000 +0100
|
||||
+++ linux.dev/net/sched/sch_generic.c 2006-11-24 02:36:58.000000000 +0100
|
||||
Index: linux-2.4.35.4/net/sched/sch_generic.c
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/net/sched/sch_generic.c 2007-12-15 05:20:10.816456638 +0100
|
||||
+++ linux-2.4.35.4/net/sched/sch_generic.c 2007-12-15 05:20:16.704792197 +0100
|
||||
@@ -84,6 +84,11 @@
|
||||
struct sk_buff *skb;
|
||||
|
||||
|
|
|
@ -1,5 +1,7 @@
|
|||
--- linux-2.4.34/drivers/ide/pci/aec62xx.c.old 2006-12-23 22:34:20.000000000 +0200
|
||||
+++ linux-2.4.34/drivers/ide/pci/aec62xx.c 2007-01-14 12:06:05.000000000 +0200
|
||||
Index: linux-2.4.35.4/drivers/ide/pci/aec62xx.c
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/drivers/ide/pci/aec62xx.c 2007-12-15 05:19:35.958470194 +0100
|
||||
+++ linux-2.4.35.4/drivers/ide/pci/aec62xx.c 2007-12-15 05:20:16.928804961 +0100
|
||||
@@ -3,6 +3,8 @@
|
||||
*
|
||||
* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
|
||||
|
@ -13,16 +15,15 @@
|
|||
ide_hwif_t *hwif = HWIF(drive);
|
||||
struct hd_driveid *id = drive->id;
|
||||
|
||||
- if ((id->capability & 1) && drive->autodma) {
|
||||
+#ifndef CONFIG_BCM947XX
|
||||
+ if ((id->capability & 1) && drive->autodma) {
|
||||
if ((id->capability & 1) && drive->autodma) {
|
||||
+#else
|
||||
+ if (1) {
|
||||
+#endif
|
||||
/* Consult the list of known "bad" drives */
|
||||
if (hwif->ide_dma_bad_drive(drive))
|
||||
goto fast_ata_pio;
|
||||
@@ -414,10 +416,60 @@
|
||||
@@ -414,10 +420,60 @@
|
||||
{
|
||||
int bus_speed = system_bus_clock();
|
||||
|
||||
|
@ -83,7 +84,7 @@
|
|||
|
||||
#if defined(DISPLAY_AEC62XX_TIMINGS) && defined(CONFIG_PROC_FS)
|
||||
aec_devs[n_aec_devs++] = dev;
|
||||
@@ -500,6 +552,7 @@
|
||||
@@ -500,6 +556,7 @@
|
||||
|
||||
static void __init init_setup_aec6x80 (struct pci_dev *dev, ide_pci_device_t *d)
|
||||
{
|
||||
|
@ -91,7 +92,7 @@
|
|||
unsigned long bar4reg = pci_resource_start(dev, 4);
|
||||
|
||||
if (inb(bar4reg+2) & 0x10) {
|
||||
@@ -512,6 +565,7 @@
|
||||
@@ -512,6 +569,7 @@
|
||||
strcpy(d->name, "AEC6280R");
|
||||
}
|
||||
|
||||
|
|
|
@ -1,5 +1,7 @@
|
|||
--- linux.old/drivers/ide/pci/pdc202xx_old.c 2006-12-23 21:34:20.000000000 +0100
|
||||
+++ linux.dev/drivers/ide/pci/pdc202xx_old.c 2007-01-24 18:03:28.000000000 +0100
|
||||
Index: linux-2.4.35.4/drivers/ide/pci/pdc202xx_old.c
|
||||
===================================================================
|
||||
--- linux-2.4.35.4.orig/drivers/ide/pci/pdc202xx_old.c 2007-12-15 05:19:35.922468144 +0100
|
||||
+++ linux-2.4.35.4/drivers/ide/pci/pdc202xx_old.c 2007-12-15 05:20:17.136816813 +0100
|
||||
@@ -253,23 +253,23 @@
|
||||
pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
|
||||
|
||||
|
@ -38,4 +40,3 @@
|
|||
switch(dev->device) {
|
||||
case PCI_DEVICE_ID_PROMISE_20267:
|
||||
case PCI_DEVICE_ID_PROMISE_20265:
|
||||
|
||||
|
|
|
@ -1,155 +0,0 @@
|
|||
--- a/arch/mips/bcm947xx/include/sbchipc.h 2007-11-23 12:12:01.000000000 -0500
|
||||
+++ b/arch/mips/bcm947xx/include/sbchipc.h 2007-11-25 06:16:42.000000000 -0500
|
||||
@@ -188,6 +188,7 @@
|
||||
#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
|
||||
#define CAP_ROM 0x00800000 /* Internal boot rom active */
|
||||
#define CAP_BKPLN64 0x08000000 /* 64-bit backplane */
|
||||
+#define CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */
|
||||
|
||||
/* PLL type */
|
||||
#define PLL_NONE 0x00000000
|
||||
@@ -199,6 +200,9 @@
|
||||
#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
|
||||
#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
|
||||
|
||||
+/* watchdog clock */
|
||||
+#define WATCHDOG_CLOCK_5354 32000 /* Hz */
|
||||
+
|
||||
/* corecontrol */
|
||||
#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
|
||||
#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
|
||||
--- a/arch/mips/bcm947xx/include/bcmdevs.h 2007-11-23 12:12:01.000000000 -0500
|
||||
+++ b/arch/mips/bcm947xx/include/bcmdevs.h 2007-11-25 05:58:20.000000000 -0500
|
||||
@@ -121,6 +121,7 @@
|
||||
#define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */
|
||||
#define BCM5350_CHIP_ID 0x5350 /* bcm5350 chipcommon chipid */
|
||||
#define BCM5352_CHIP_ID 0x5352 /* bcm5352 chipcommon chipid */
|
||||
+#define BCM5354_CHIP_ID 0x5354 /* bcm5354 chipcommon chipid */
|
||||
|
||||
#define BCM4320_CHIP_ID 0x4320 /* bcm4320 chipcommon chipid */
|
||||
|
||||
--- a/arch/mips/bcm947xx/sbmips.c 2007-11-23 12:12:02.000000000 -0500
|
||||
+++ b/arch/mips/bcm947xx/sbmips.c 2007-11-25 05:40:40.000000000 -0500
|
||||
@@ -290,6 +290,12 @@
|
||||
n = R_REG(osh, &eir->clockcontrol_n);
|
||||
m = R_REG(osh, &eir->clockcontrol_sb);
|
||||
} else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
|
||||
+ /* 5354 chip uses a non programmable PLL of frequency 240MHz */
|
||||
+ if (sb_chip(sbh) == BCM5354_CHIP_ID) {
|
||||
+ rate = 240000000;
|
||||
+ goto out;
|
||||
+ }
|
||||
+
|
||||
pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
|
||||
n = R_REG(osh, &cc->clockcontrol_n);
|
||||
if ((pll_type == PLL_TYPE2) ||
|
||||
@@ -612,6 +618,15 @@
|
||||
clockcontrol_pci = &eir->clockcontrol_pci;
|
||||
clockcontrol_m2 = &cc->clockcontrol_m2;
|
||||
} else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
|
||||
+
|
||||
+ /* 5354 chipcommon pll setting can't be changed.
|
||||
+ * The PMU on power up comes up with the default clk frequency
|
||||
+ * of 240MHz
|
||||
+ */
|
||||
+ if (sb_chip(sbh) == BCM5354_CHIP_ID) {
|
||||
+ ret = TRUE;
|
||||
+ goto done;
|
||||
+ }
|
||||
pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
|
||||
if (pll_type == PLL_TYPE6) {
|
||||
clockcontrol_n = NULL;
|
||||
--- a/arch/mips/bcm947xx/sbutils.c 2007-11-23 12:12:02.000000000 -0500
|
||||
+++ b/arch/mips/bcm947xx/sbutils.c 2007-11-25 06:22:43.000000000 -0500
|
||||
@@ -791,8 +791,14 @@
|
||||
/* readback */
|
||||
if (regoff >= SBCONFIGOFF)
|
||||
w = R_SBREG(si, r);
|
||||
- else
|
||||
+ else {
|
||||
+ if ((si->sb.chip == BCM5354_CHIP_ID) &&
|
||||
+ (coreidx == SB_CC_IDX) &&
|
||||
+ (regoff == OFFSETOF(chipcregs_t, watchdog))) {
|
||||
+ w = val;
|
||||
+ } else
|
||||
w = R_REG(si->osh, r);
|
||||
+ }
|
||||
|
||||
if (!fast) {
|
||||
/* restore core index */
|
||||
@@ -1902,6 +1908,15 @@
|
||||
n = R_REG(si->osh, &eir->clockcontrol_n);
|
||||
m = R_REG(si->osh, &eir->clockcontrol_sb);
|
||||
} else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
|
||||
+
|
||||
+ if (R_REG(si->osh, &cc->capabilities) & CAP_PMU) {
|
||||
+ if (sb_chip(sbh) == BCM5354_CHIP_ID) {
|
||||
+ /* 5354 has a constant sb clock of 120MHz */
|
||||
+ rate = 120000000;
|
||||
+ goto end;
|
||||
+ } else
|
||||
+ ASSERT(0);
|
||||
+ }
|
||||
pll_type = R_REG(si->osh, &cc->capabilities) & CAP_PLL_MASK;
|
||||
if (pll_type == PLL_NONE) {
|
||||
INTR_RESTORE(si, intr_val);
|
||||
@@ -1929,6 +1944,7 @@
|
||||
rate = rate / 2;
|
||||
}
|
||||
|
||||
+end:
|
||||
/* switch back to previous core */
|
||||
sb_setcoreidx(sbh, idx);
|
||||
|
||||
--- a/arch/mips/bcm947xx/hndchipc.c 2007-11-23 12:12:02.000000000 -0500
|
||||
+++ b/arch/mips/bcm947xx/hndchipc.c 2007-11-25 06:31:15.000000000 -0500
|
||||
@@ -93,6 +93,9 @@
|
||||
chipcregs_t *cc = (chipcregs_t *) regs;
|
||||
uint32 rev, cap, pll, baud_base, div;
|
||||
|
||||
+ /* Default value */
|
||||
+ div = 48;
|
||||
+
|
||||
/* Determine core revision and capabilities */
|
||||
rev = sb_corerev(sbh);
|
||||
cap = R_REG(osh, &cc->capabilities);
|
||||
@@ -108,22 +111,29 @@
|
||||
R_REG(osh, &cc->clockcontrol_m2));
|
||||
div = 1;
|
||||
} else {
|
||||
- /* Fixed ALP clock */
|
||||
- if (rev >= 11 && rev != 15) {
|
||||
- baud_base = 20000000;
|
||||
+/* 5354 chip common uart uses a constant clock
|
||||
+ * frequency of 25MHz */
|
||||
+ if (sb_corerev(sbh) == 20) {
|
||||
+ /* Set the override bit so we don't divide it */
|
||||
+ W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
|
||||
+ baud_base = 25000000;
|
||||
+ } else if (rev >= 11 && rev != 15) {
|
||||
+ /* Fixed ALP clock */
|
||||
+// baud_base = sb_alp_clock(sbh);
|
||||
+ baud_base = 20000000;
|
||||
div = 1;
|
||||
/* Set the override bit so we don't divide it */
|
||||
W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
|
||||
- }
|
||||
+
|
||||
/* Internal backplane clock */
|
||||
- else if (rev >= 3) {
|
||||
- baud_base = sb_clock(sbh);
|
||||
- div = 2; /* Minimum divisor */
|
||||
- W_REG(osh, &cc->clkdiv,
|
||||
+ } else if (rev >= 3) {
|
||||
+ baud_base = sb_clock(sbh);
|
||||
+ div = 2; /* Minimum divisor */
|
||||
+ W_REG(osh, &cc->clkdiv,
|
||||
((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
|
||||
- }
|
||||
+
|
||||
/* Fixed internal backplane clock */
|
||||
- else {
|
||||
+ } else {
|
||||
baud_base = 88000000;
|
||||
div = 48;
|
||||
}
|
|
@ -672,6 +672,8 @@ CONFIG_SERIAL_CONSOLE=y
|
|||
CONFIG_SHAPER=m
|
||||
# CONFIG_SIBYTE_SB1xxx_SOC is not set
|
||||
# CONFIG_SK98LIN is not set
|
||||
# CONFIG_SKGE is not set
|
||||
# CONFIG_SKY2 is not set
|
||||
# CONFIG_SLIP is not set
|
||||
# CONFIG_SMB_FS is not set
|
||||
# CONFIG_SMB_NLS is not set
|
||||
|
@ -722,6 +724,7 @@ CONFIG_WAN_ROUTER=m
|
|||
CONFIG_WATCHDOG=y
|
||||
CONFIG_WATCHDOG_NOWAYOUT=y
|
||||
# CONFIG_WAVELAN is not set
|
||||
# CONFIG_WDT_W83627 is not set
|
||||
# CONFIG_X25 is not set
|
||||
# CONFIG_XFS_DEBUG is not set
|
||||
CONFIG_XFS_FS=m
|
||||
|
|
File diff suppressed because it is too large
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Reference in a new issue