ramips: ramips_esw: coding style cleanup
SVN-Revision: 24334
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48e6a31812
commit
0fcedc7bda
1 changed files with 31 additions and 24 deletions
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@ -45,20 +45,18 @@ ramips_esw_rr(struct rt305x_esw *esw, unsigned reg)
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return __raw_readl(esw->base + reg);
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}
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u32
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static u32
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mii_mgr_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
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u32 write_data)
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{
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unsigned long volatile t_start = jiffies;
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unsigned long t_start = jiffies;
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int ret = 0;
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while(1)
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{
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while (1) {
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if (!(ramips_esw_rr(esw, RT305X_ESW_REG_PCR1) &
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RT305X_ESW_PCR1_WT_DONE))
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break;
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if(time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT))
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{
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if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
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ret = 1;
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goto out;
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}
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@ -72,19 +70,18 @@ mii_mgr_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
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RT305X_ESW_REG_PCR0);
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t_start = jiffies;
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while(1)
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{
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while (1) {
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if (ramips_esw_rr(esw, RT305X_ESW_REG_PCR1) &
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RT305X_ESW_PCR1_WT_DONE)
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break;
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if(time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT))
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{
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if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
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ret = 1;
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break;
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}
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}
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out:
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if(ret)
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if (ret)
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printk(KERN_ERR "ramips_eth: MDIO timeout\n");
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return ret;
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}
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@ -109,20 +106,30 @@ rt305x_esw_hw_init(struct rt305x_esw *esw)
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ramips_esw_wr(esw, 0x00000000, RT305X_ESW_REG_FPA);
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mii_mgr_write(esw, 0, 31, 0x8000);
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for(i = 0; i < 5; i++)
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{
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mii_mgr_write(esw, i, 0, 0x3100); //TX10 waveform coefficient
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mii_mgr_write(esw, i, 26, 0x1601); //TX10 waveform coefficient
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mii_mgr_write(esw, i, 29, 0x7058); //TX100/TX10 AD/DA current bias
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mii_mgr_write(esw, i, 30, 0x0018); //TX100 slew rate control
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for (i = 0; i < 5; i++) {
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/* TX10 waveform coefficient */
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mii_mgr_write(esw, i, 0, 0x3100);
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/* TX10 waveform coefficient */
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mii_mgr_write(esw, i, 26, 0x1601);
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/* TX100/TX10 AD/DA current bias */
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mii_mgr_write(esw, i, 29, 0x7058);
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/* TX100 slew rate control */
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mii_mgr_write(esw, i, 30, 0x0018);
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}
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/* PHY IOT */
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mii_mgr_write(esw, 0, 31, 0x0); //select global register
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mii_mgr_write(esw, 0, 22, 0x052f); //tune TP_IDL tail and head waveform
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mii_mgr_write(esw, 0, 17, 0x0fe0); //set TX10 signal amplitude threshold to minimum
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mii_mgr_write(esw, 0, 18, 0x40ba); //set squelch amplitude to higher threshold
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mii_mgr_write(esw, 0, 14, 0x65); //longer TP_IDL tail length
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mii_mgr_write(esw, 0, 31, 0x8000); //select local register
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/* select global register */
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mii_mgr_write(esw, 0, 31, 0x0);
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/* tune TP_IDL tail and head waveform */
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mii_mgr_write(esw, 0, 22, 0x052f);
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/* set TX10 signal amplitude threshold to minimum */
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mii_mgr_write(esw, 0, 17, 0x0fe0);
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/* set squelch amplitude to higher threshold */
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mii_mgr_write(esw, 0, 18, 0x40ba);
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/* longer TP_IDL tail length */
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mii_mgr_write(esw, 0, 14, 0x65);
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/* select local register */
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mii_mgr_write(esw, 0, 31, 0x8000);
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/* set default vlan */
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ramips_esw_wr(esw, 0x2001, RT305X_ESW_REG_VLANI(0));
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@ -147,7 +154,7 @@ rt305x_esw_probe(struct platform_device *pdev)
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return -ENOMEM;
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}
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esw = kzalloc(sizeof (struct rt305x_esw), GFP_KERNEL);
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esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
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if (!esw) {
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dev_err(&pdev->dev, "no memory for private data\n");
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return -ENOMEM;
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