ramips: add mdio_cfg configuration for the ethernet driver
SVN-Revision: 22211
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9445ce43a6
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0d8c036e56
3 changed files with 86 additions and 0 deletions
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@ -25,6 +25,11 @@ struct ramips_eth_platform_data
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void (*reset_fe)(void);
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int min_pkt_len;
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unsigned long sys_freq;
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int speed;
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int duplex;
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int tx_fc;
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int rx_fc;
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};
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#endif /* _RAMIPS_ETH_PLATFORM_H */
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@ -22,6 +22,7 @@
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#include <linux/init.h>
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#include <linux/skbuff.h>
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#include <linux/etherdevice.h>
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#include <linux/ethtool.h>
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#include <linux/platform_device.h>
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#include <ramips_eth_platform.h>
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@ -77,6 +78,47 @@ ramips_hw_set_macaddr(unsigned char *mac)
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RAMIPS_GDMA1_MAC_ADRL);
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}
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#ifdef CONFIG_RALINK_RT288X
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static void
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ramips_setup_mdio_cfg(struct raeth_priv *re)
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{
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unsigned int mdio_cfg;
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mdio_cfg = RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 |
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RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 |
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RAMIPS_MDIO_CFG_GP1_FRC_EN;
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if (re->duplex == DUPLEX_FULL)
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mdio_cfg |= RAMIPS_MDIO_CFG_GP1_DUPLEX;
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if (re->tx_fc)
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mdio_cfg |= RAMIPS_MDIO_CFG_GP1_FC_TX;
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if (re->rx_fc)
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mdio_cfg |= RAMIPS_MDIO_CFG_GP1_FC_RX;
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switch (re->speed) {
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case SPEED_10:
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mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_10;
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break;
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case SPEED_100:
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mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_100;
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break;
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case SPEED_1000:
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mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_1000;
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break;
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default:
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BUG();
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}
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ramips_fe_wr(mdio_cfg, RAMIPS_MDIO_CFG);
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}
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#else
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static inline void ramips_setup_mdio_cfg(struct raeth_priv *re)
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{
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}
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#endif /* CONFIG_RALINK_RT288X */
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static void
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ramips_cleanup_dma(struct raeth_priv *re)
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{
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@ -334,6 +376,8 @@ ramips_eth_open(struct net_device *dev)
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(unsigned long)dev);
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tasklet_init(&priv->rx_tasklet, ramips_eth_rx_hw, (unsigned long)dev);
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ramips_setup_mdio_cfg(priv);
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ramips_fe_wr(RAMIPS_DELAY_INIT, RAMIPS_DLY_INT_CFG);
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ramips_fe_wr(RAMIPS_TX_DLY_INT | RAMIPS_RX_DLY_INT, RAMIPS_FE_INT_ENABLE);
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ramips_fe_wr(ramips_fe_rr(RAMIPS_GDMA1_FWD_CFG) &
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@ -442,6 +486,11 @@ ramips_eth_plat_probe(struct platform_device *plat)
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ramips_dev->netdev_ops = &ramips_eth_netdev_ops;
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priv = netdev_priv(ramips_dev);
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priv->speed = data->speed;
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priv->duplex = data->duplex;
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priv->rx_fc = data->rx_fc;
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priv->tx_fc = data->tx_fc;
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priv->plat = data;
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err = register_netdev(ramips_dev);
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@ -122,6 +122,33 @@
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#define RAMIPS_RX_CALC_IDX1 (RAMIPS_PDMA_OFFSET + 0x68)
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#define RAMIPS_RX_DRX_IDX1 (RAMIPS_PDMA_OFFSET + 0x6C)
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/* MDIO_CFG register bits */
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#define RAMIPS_MDIO_CFG_AUTO_POLL_EN BIT(29)
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#define RAMIPS_MDIO_CFG_GP1_BP_EN BIT(16)
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#define RAMIPS_MDIO_CFG_GP1_FRC_EN BIT(15)
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#define RAMIPS_MDIO_CFG_GP1_SPEED_10 (0 << 13)
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#define RAMIPS_MDIO_CFG_GP1_SPEED_100 (1 << 13)
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#define RAMIPS_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
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#define RAMIPS_MDIO_CFG_GP1_DUPLEX BIT(12)
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#define RAMIPS_MDIO_CFG_GP1_FC_TX BIT(11)
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#define RAMIPS_MDIO_CFG_GP1_FC_RX BIT(10)
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#define RAMIPS_MDIO_CFG_GP1_LNK_DWN BIT(9)
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#define RAMIPS_MDIO_CFG_GP1_AN_FAIL BIT(8)
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#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
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#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
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#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
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#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
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#define RAMIPS_MDIO_CFG_TURBO_MII_FREQ BIT(5)
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#define RAMIPS_MDIO_CFG_TURBO_MII_MODE BIT(4)
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#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
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#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
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#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
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#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
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#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_0 0
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#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 1
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#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_400 2
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#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_INV 3
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/* uni-cast port */
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#define RAMIPS_GDM1_ICS_EN BIT(22)
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#define RAMIPS_GDM1_TCS_EN BIT(21)
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@ -201,6 +228,11 @@ struct raeth_priv
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spinlock_t page_lock;
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struct ramips_eth_platform_data *plat;
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int speed;
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int duplex;
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int tx_fc;
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int rx_fc;
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};
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#endif /* RAMIPS_ETH_H */
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