ramips: remove interrupt coalescing, it is unnecessary with napi polling and could reduce throughput
Signed-off-by: Felix Fietkau <nbd@openwrt.org> SVN-Revision: 43952
This commit is contained in:
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adaac86c7f
commit
05d4b8c79b
7 changed files with 40 additions and 78 deletions
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@ -140,54 +140,6 @@ static void fe_get_ringparam(struct net_device *dev,
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ring->tx_pending = NUM_DMA_DESC;
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}
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static int fe_get_coalesce(struct net_device *dev,
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struct ethtool_coalesce *coal)
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{
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u32 delay_cfg = fe_reg_r32(FE_REG_DLY_INT_CFG);
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coal->rx_coalesce_usecs = (delay_cfg & 0xff) * FE_DELAY_TIME;
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coal->rx_max_coalesced_frames = ((delay_cfg >> 8) & 0x7f);
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coal->use_adaptive_rx_coalesce = (delay_cfg >> 15) & 0x1;
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coal->tx_coalesce_usecs = ((delay_cfg >> 16 )& 0xff) * FE_DELAY_TIME;
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coal->tx_max_coalesced_frames = ((delay_cfg >> 24) & 0x7f);
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coal->use_adaptive_tx_coalesce = (delay_cfg >> 31) & 0x1;
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return 0;
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}
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static int fe_set_coalesce(struct net_device *dev,
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struct ethtool_coalesce *coal)
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{
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u32 delay_cfg;
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u32 rx_usecs, tx_usecs;
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u32 rx_frames, tx_frames;
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if (!coal->use_adaptive_rx_coalesce || !coal->use_adaptive_tx_coalesce)
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return -EINVAL;
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rx_usecs = DIV_ROUND_UP(coal->rx_coalesce_usecs, FE_DELAY_TIME);
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rx_frames = coal->rx_max_coalesced_frames;
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tx_usecs = DIV_ROUND_UP(coal->tx_coalesce_usecs, FE_DELAY_TIME);
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tx_frames = coal->tx_max_coalesced_frames;
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if (((tx_usecs == 0) && (tx_frames ==0)) ||
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((rx_usecs == 0) && (rx_frames ==0)))
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return -EINVAL;
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if (rx_usecs > 0xff) rx_usecs = 0xff;
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if (rx_frames > 0x7f) rx_frames = 0x7f;
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if (tx_usecs > 0xff) tx_usecs = 0xff;
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if (tx_frames > 0x7f) tx_frames = 0x7f;
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delay_cfg = ((((FE_DELAY_EN_INT | tx_frames) << 8) | tx_usecs) << 16) |
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(((FE_DELAY_EN_INT | rx_frames) << 8) | rx_usecs);
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fe_reg_w32(delay_cfg, FE_REG_DLY_INT_CFG);
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return 0;
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}
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static void fe_get_strings(struct net_device *dev, u32 stringset, u8 *data)
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{
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switch (stringset) {
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@ -243,8 +195,6 @@ static struct ethtool_ops fe_ethtool_ops = {
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.nway_reset = fe_nway_reset,
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.get_link = fe_get_link,
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.get_ringparam = fe_get_ringparam,
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.get_coalesce = fe_get_coalesce,
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.set_coalesce = fe_set_coalesce,
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};
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void fe_set_ethtool_ops(struct net_device *netdev)
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@ -842,8 +842,8 @@ static int fe_poll(struct napi_struct *napi, int budget)
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u32 tx_intr, rx_intr;
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status = fe_reg_r32(FE_REG_FE_INT_STATUS);
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tx_intr = priv->soc->tx_dly_int;
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rx_intr = priv->soc->rx_dly_int;
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tx_intr = priv->soc->tx_int;
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rx_intr = priv->soc->rx_int;
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tx_done = rx_done = 0;
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poll_again:
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@ -907,16 +907,16 @@ static void fe_tx_timeout(struct net_device *dev)
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static irqreturn_t fe_handle_irq(int irq, void *dev)
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{
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struct fe_priv *priv = netdev_priv(dev);
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u32 status, dly_int;
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u32 status, int_mask;
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status = fe_reg_r32(FE_REG_FE_INT_STATUS);
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if (unlikely(!status))
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return IRQ_NONE;
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dly_int = (priv->soc->rx_dly_int | priv->soc->tx_dly_int);
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if (likely(status & dly_int)) {
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fe_int_disable(dly_int);
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int_mask = (priv->soc->rx_int | priv->soc->tx_int);
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if (likely(status & int_mask)) {
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fe_int_disable(int_mask);
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napi_schedule(&priv->rx_napi);
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} else {
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fe_reg_w32(status, FE_REG_FE_INT_STATUS);
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@ -929,11 +929,11 @@ static irqreturn_t fe_handle_irq(int irq, void *dev)
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static void fe_poll_controller(struct net_device *dev)
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{
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struct fe_priv *priv = netdev_priv(dev);
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u32 dly_int = priv->soc->tx_dly_int | priv->soc->rx_dly_int;
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u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
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fe_int_disable(dly_int);
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fe_int_disable(int_mask);
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fe_handle_irq(dev->irq, dev);
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fe_int_enable(dly_int);
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fe_int_enable(int_mask);
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}
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#endif
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@ -1018,9 +1018,7 @@ static int fe_hw_init(struct net_device *dev)
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else
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fe_hw_set_macaddr(priv, dev->dev_addr);
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fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG);
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fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
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fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
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/* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
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if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
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@ -1068,7 +1066,7 @@ static int fe_open(struct net_device *dev)
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netif_carrier_on(dev);
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netif_start_queue(dev);
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fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
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fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
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return 0;
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@ -1083,7 +1081,7 @@ static int fe_stop(struct net_device *dev)
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unsigned long flags;
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int i;
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fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
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fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
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netif_tx_disable(dev);
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@ -79,8 +79,22 @@ enum fe_reg {
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#define FE_TX_DLY_INT BIT(1)
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#define FE_RX_DLY_INT BIT(0)
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#define FE_RX_DONE_INT FE_RX_DONE_INT0
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#define FE_TX_DONE_INT (FE_TX_DONE_INT0 | FE_TX_DONE_INT1 | \
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FE_TX_DONE_INT2 | FE_TX_DONE_INT3)
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#define RT5350_RX_DLY_INT BIT(30)
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#define RT5350_TX_DLY_INT BIT(28)
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#define RT5350_RX_DONE_INT1 BIT(17)
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#define RT5350_RX_DONE_INT0 BIT(16)
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#define RT5350_TX_DONE_INT3 BIT(3)
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#define RT5350_TX_DONE_INT2 BIT(2)
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#define RT5350_TX_DONE_INT1 BIT(1)
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#define RT5350_TX_DONE_INT0 BIT(0)
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#define RT5350_RX_DONE_INT (RT5350_RX_DONE_INT0 | RT5350_RX_DONE_INT1)
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#define RT5350_TX_DONE_INT (RT5350_TX_DONE_INT0 | RT5350_TX_DONE_INT1 | \
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RT5350_TX_DONE_INT2 | RT5350_TX_DONE_INT3)
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/* registers */
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#define FE_FE_OFFSET 0x0000
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@ -367,8 +381,8 @@ struct fe_soc_data
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void *swpriv;
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u32 pdma_glo_cfg;
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u32 rx_dly_int;
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u32 tx_dly_int;
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u32 rx_int;
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u32 tx_int;
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u32 checksum_bit;
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u32 tx_udf_bit;
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};
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@ -225,8 +225,8 @@ static struct fe_soc_data mt7620_data = {
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.port_init = mt7620_port_init,
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.reg_table = mt7620_reg_table,
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.pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
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.rx_dly_int = RT5350_RX_DLY_INT,
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.tx_dly_int = RT5350_TX_DLY_INT,
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.rx_int = RT5350_RX_DONE_INT,
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.tx_int = RT5350_TX_DONE_INT,
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.checksum_bit = MT7620_L4_VALID,
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.tx_udf_bit = MT7620_TX_DMA_UDF,
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.has_carrier = mt7620a_has_carrier,
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@ -247,8 +247,8 @@ static struct fe_soc_data mt7621_data = {
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.switch_config = mt7621_gsw_config,
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.reg_table = mt7621_reg_table,
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.pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
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.rx_dly_int = RT5350_RX_DLY_INT,
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.tx_dly_int = RT5350_TX_DLY_INT,
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.rx_int = RT5350_RX_DONE_INT,
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.tx_int = RT5350_TX_DONE_INT,
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.checksum_bit = MT7621_L4_VALID,
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.tx_udf_bit = MT7621_TX_DMA_UDF,
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.has_carrier = mt7620a_has_carrier,
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@ -65,8 +65,8 @@ struct fe_soc_data rt2880_data = {
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.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
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.checksum_bit = RX_DMA_L4VALID,
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.tx_udf_bit = TX_DMA_UDF,
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.rx_dly_int = FE_RX_DLY_INT,
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.tx_dly_int = FE_TX_DLY_INT,
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.rx_int = FE_RX_DONE_INT,
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.tx_int = FE_TX_DONE_INT,
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.mdio_read = rt2880_mdio_read,
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.mdio_write = rt2880_mdio_write,
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.mdio_adjust_link = rt2880_mdio_link_adjust,
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@ -133,8 +133,8 @@ static struct fe_soc_data rt3050_data = {
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.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
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.checksum_bit = RX_DMA_L4VALID,
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.tx_udf_bit = TX_DMA_UDF,
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.rx_dly_int = FE_RX_DLY_INT,
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.tx_dly_int = FE_TX_DLY_INT,
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.rx_int = FE_RX_DONE_INT,
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.tx_int = FE_TX_DONE_INT,
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};
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static struct fe_soc_data rt5350_data = {
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@ -148,8 +148,8 @@ static struct fe_soc_data rt5350_data = {
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.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
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.checksum_bit = RX_DMA_L4VALID,
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.tx_udf_bit = TX_DMA_UDF,
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.rx_dly_int = RT5350_RX_DLY_INT,
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.tx_dly_int = RT5350_TX_DLY_INT,
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.rx_int = RT5350_RX_DONE_INT,
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.tx_int = RT5350_TX_DONE_INT,
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};
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const struct of_device_id of_fe_match[] = {
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@ -69,8 +69,8 @@ static struct fe_soc_data rt3883_data = {
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.reset_fe = rt3883_fe_reset,
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.fwd_config = rt3883_fwd_config,
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.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
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.rx_dly_int = FE_RX_DLY_INT,
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.tx_dly_int = FE_TX_DLY_INT,
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.rx_int = FE_RX_DONE_INT,
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.tx_int = FE_TX_DONE_INT,
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.checksum_bit = RX_DMA_L4VALID,
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.tx_udf_bit = TX_DMA_UDF,
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.mdio_read = rt2880_mdio_read,
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