brcm47xx-2.6: add a few nops here, some irq saving there, blast the full cache on page icache flushes i really hate the broadcom cpu bugs, but it's much more stable now. PS: A /* Ouch */ in the original source showed me the way ;)
SVN-Revision: 8165
This commit is contained in:
Felix Fietkau
parent
739af29134
commit
0476d261d0
1 changed files with 303 additions and 34 deletions
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@ -1,7 +1,7 @@
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Index: linux-2.6.22-rc6/arch/mips/kernel/genex.S
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Index: linux-2.6.22/arch/mips/kernel/genex.S
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===================================================================
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--- linux-2.6.22-rc6.orig/arch/mips/kernel/genex.S 2007-07-04 01:52:47.812492000 +0200
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+++ linux-2.6.22-rc6/arch/mips/kernel/genex.S 2007-07-04 01:53:01.585352750 +0200
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--- linux-2.6.22.orig/arch/mips/kernel/genex.S 2007-07-26 06:29:25.057170943 +0200
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+++ linux-2.6.22/arch/mips/kernel/genex.S 2007-07-26 06:29:40.890073208 +0200
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@@ -51,6 +51,10 @@
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NESTED(except_vec3_generic, 0, sp)
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.set push
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@ -13,10 +13,10 @@ Index: linux-2.6.22-rc6/arch/mips/kernel/genex.S
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#if R5432_CP0_INTERRUPT_WAR
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mfc0 k0, CP0_INDEX
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#endif
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Index: linux-2.6.22-rc6/arch/mips/mm/c-r4k.c
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Index: linux-2.6.22/arch/mips/mm/c-r4k.c
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===================================================================
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--- linux-2.6.22-rc6.orig/arch/mips/mm/c-r4k.c 2007-07-04 01:53:01.545350250 +0200
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+++ linux-2.6.22-rc6/arch/mips/mm/c-r4k.c 2007-07-04 02:17:11.435962750 +0200
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--- linux-2.6.22.orig/arch/mips/mm/c-r4k.c 2007-07-26 06:29:40.826069560 +0200
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+++ linux-2.6.22/arch/mips/mm/c-r4k.c 2007-07-26 06:32:45.956619550 +0200
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@@ -29,6 +29,9 @@
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#include <asm/cacheflush.h> /* for run_uncached() */
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@ -27,7 +27,19 @@ Index: linux-2.6.22-rc6/arch/mips/mm/c-r4k.c
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/*
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* Special Variant of smp_call_function for use by cache functions:
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*
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@@ -93,6 +96,9 @@
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@@ -85,14 +88,21 @@
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static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
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{
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+ unsigned long flags;
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+
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+ local_irq_save(flags);
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R4600_HIT_CACHEOP_WAR_IMPL;
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blast_dcache32_page(addr);
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+ local_irq_restore(flags);
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}
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static void __init r4k_blast_dcache_page_setup(void)
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{
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unsigned long dc_lsize = cpu_dcache_line_size();
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@ -37,7 +49,7 @@ Index: linux-2.6.22-rc6/arch/mips/mm/c-r4k.c
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if (dc_lsize == 0)
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r4k_blast_dcache_page = (void *)cache_noop;
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else if (dc_lsize == 16)
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@@ -107,6 +113,9 @@
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@@ -107,6 +117,9 @@
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{
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unsigned long dc_lsize = cpu_dcache_line_size();
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@ -47,7 +59,7 @@ Index: linux-2.6.22-rc6/arch/mips/mm/c-r4k.c
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if (dc_lsize == 0)
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r4k_blast_dcache_page_indexed = (void *)cache_noop;
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else if (dc_lsize == 16)
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@@ -121,6 +130,9 @@
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@@ -121,6 +134,9 @@
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{
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unsigned long dc_lsize = cpu_dcache_line_size();
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@ -57,26 +69,274 @@ Index: linux-2.6.22-rc6/arch/mips/mm/c-r4k.c
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if (dc_lsize == 0)
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r4k_blast_dcache = (void *)cache_noop;
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else if (dc_lsize == 16)
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@@ -538,6 +550,9 @@
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r4k_blast_icache();
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else
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protected_blast_icache_range(start, end);
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+
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+ if (bcm4710)
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+ r4k_flush_cache_all();
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@@ -202,8 +218,12 @@
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static void (* r4k_blast_icache_page)(unsigned long addr);
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+static void r4k_flush_cache_all(void);
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static void __init r4k_blast_icache_page_setup(void)
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{
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+#ifdef CONFIG_BCM947XX
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+ r4k_blast_icache_page = (void *)r4k_flush_cache_all;
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+#else
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unsigned long ic_lsize = cpu_icache_line_size();
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if (ic_lsize == 0)
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@@ -214,6 +234,7 @@
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r4k_blast_icache_page = blast_icache32_page;
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else if (ic_lsize == 64)
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r4k_blast_icache_page = blast_icache64_page;
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+#endif
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}
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static void r4k_flush_icache_range(unsigned long start, unsigned long end)
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@@ -618,6 +633,8 @@
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unsigned long addr = (unsigned long) arg;
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@@ -221,6 +242,9 @@
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static void __init r4k_blast_icache_page_indexed_setup(void)
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{
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+#ifdef CONFIG_BCM947XX
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+ r4k_blast_icache_page_indexed = (void *)r4k_flush_cache_all;
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+#else
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unsigned long ic_lsize = cpu_icache_line_size();
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if (ic_lsize == 0)
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@@ -239,6 +263,7 @@
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blast_icache32_page_indexed;
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} else if (ic_lsize == 64)
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r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
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+#endif
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}
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static void (* r4k_blast_icache)(void);
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@@ -322,12 +347,17 @@
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*/
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static inline void local_r4k_flush_cache_all(void * args)
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{
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+ unsigned long flags;
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+
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+ local_irq_save(flags);
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r4k_blast_dcache();
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+ r4k_blast_icache();
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+ local_irq_restore(flags);
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}
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static void r4k_flush_cache_all(void)
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{
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- if (!cpu_has_dc_aliases)
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+ if (!cpu_has_dc_aliases && cpu_use_kmap_coherent)
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return;
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r4k_on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1);
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@@ -335,6 +365,9 @@
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static inline void local_r4k___flush_cache_all(void * args)
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{
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+ unsigned long flags;
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+
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+ local_irq_save(flags);
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r4k_blast_dcache();
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r4k_blast_icache();
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@@ -348,6 +381,7 @@
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case CPU_R14000:
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r4k_blast_scache();
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}
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+ local_irq_restore(flags);
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}
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static void r4k___flush_cache_all(void)
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@@ -358,17 +392,21 @@
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static inline void local_r4k_flush_cache_range(void * args)
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{
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struct vm_area_struct *vma = args;
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+ unsigned long flags;
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if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
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return;
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+ local_irq_save(flags);
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r4k_blast_dcache();
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+ r4k_blast_icache();
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+ local_irq_restore(flags);
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}
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static void r4k_flush_cache_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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- if (!cpu_has_dc_aliases)
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+ if (!cpu_has_dc_aliases && cpu_use_kmap_coherent)
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return;
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r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
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@@ -377,6 +415,7 @@
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static inline void local_r4k_flush_cache_mm(void * args)
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{
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struct mm_struct *mm = args;
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+ unsigned long flags;
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if (!cpu_context(smp_processor_id(), mm))
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return;
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@@ -395,12 +434,15 @@
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return;
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}
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+ local_irq_save(flags);
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r4k_blast_dcache();
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+ r4k_blast_icache();
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+ local_irq_restore(flags);
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}
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static void r4k_flush_cache_mm(struct mm_struct *mm)
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{
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- if (!cpu_has_dc_aliases)
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+ if (!cpu_has_dc_aliases && cpu_use_kmap_coherent)
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return;
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r4k_on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1);
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@@ -420,6 +462,7 @@
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unsigned long paddr = fcp_args->pfn << PAGE_SHIFT;
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int exec = vma->vm_flags & VM_EXEC;
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struct mm_struct *mm = vma->vm_mm;
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+ unsigned long flags;
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pgd_t *pgdp;
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pud_t *pudp;
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pmd_t *pmdp;
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@@ -451,8 +494,9 @@
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* for every cache flush operation. So we do indexed flushes
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* in that case, which doesn't overly flush the cache too much.
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*/
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+ local_irq_save(flags);
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if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
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- if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
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+ if (!cpu_use_kmap_coherent || cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
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r4k_blast_dcache_page(addr);
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if (exec && !cpu_icache_snoops_remote_store)
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r4k_blast_scache_page(addr);
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@@ -460,14 +504,14 @@
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if (exec)
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r4k_blast_icache_page(addr);
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- return;
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+ goto done;
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}
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/*
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* Do indexed flush, too much work to get the (possible) TLB refills
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* to work correctly.
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*/
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- if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
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+ if (!cpu_use_kmap_coherent || cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
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r4k_blast_dcache_page_indexed(cpu_has_pindexed_dcache ?
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paddr : addr);
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if (exec && !cpu_icache_snoops_remote_store) {
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@@ -483,6 +527,8 @@
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} else
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r4k_blast_icache_page_indexed(addr);
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}
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+done:
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+ local_irq_restore(flags);
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}
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static void r4k_flush_cache_page(struct vm_area_struct *vma,
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@@ -499,7 +545,11 @@
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static inline void local_r4k_flush_data_cache_page(void * addr)
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{
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+ unsigned long flags;
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+
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+ local_irq_save(flags);
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r4k_blast_dcache_page((unsigned long) addr);
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+ local_irq_restore(flags);
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}
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static void r4k_flush_data_cache_page(unsigned long addr)
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@@ -542,6 +592,9 @@
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static void r4k_flush_icache_range(unsigned long start, unsigned long end)
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{
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+#ifdef CONFIG_BCM947XX
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+ r4k_flush_cache_all();
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+#else
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struct flush_icache_range_args args;
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args.start = start;
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@@ -549,12 +602,15 @@
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r4k_on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
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instruction_hazard();
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+#endif
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}
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#ifdef CONFIG_DMA_NONCOHERENT
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static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
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{
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+ unsigned long flags;
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+
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/* Catch bad driver code */
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BUG_ON(size == 0);
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@@ -571,18 +627,21 @@
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* subset property so we have to flush the primary caches
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* explicitly
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*/
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+ local_irq_save(flags);
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if (size >= dcache_size) {
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r4k_blast_dcache();
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} else {
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R4600_HIT_CACHEOP_WAR_IMPL;
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blast_dcache_range(addr, addr + size);
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}
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-
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bc_wback_inv(addr, size);
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+ local_irq_restore(flags);
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}
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static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
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{
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+ unsigned long flags;
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+
|
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/* Catch bad driver code */
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BUG_ON(size == 0);
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|
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@@ -594,6 +653,7 @@
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return;
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}
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|
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+ local_irq_save(flags);
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if (size >= dcache_size) {
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r4k_blast_dcache();
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} else {
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@@ -602,6 +662,7 @@
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}
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bc_inv(addr, size);
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+ local_irq_restore(flags);
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}
|
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#endif /* CONFIG_DMA_NONCOHERENT */
|
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|
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@@ -616,8 +677,12 @@
|
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unsigned long dc_lsize = cpu_dcache_line_size();
|
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unsigned long sc_lsize = cpu_scache_line_size();
|
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unsigned long addr = (unsigned long) arg;
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+ unsigned long flags;
|
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|
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+ local_irq_save(flags);
|
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R4600_HIT_CACHEOP_WAR_IMPL;
|
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+ BCM4710_PROTECTED_FILL_TLB(addr);
|
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+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
|
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if (dc_lsize)
|
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protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
|
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if (!cpu_icache_snoops_remote_store && scache_size)
|
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@@ -1144,6 +1161,17 @@
|
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@@ -644,6 +709,7 @@
|
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}
|
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if (MIPS_CACHE_SYNC_WAR)
|
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__asm__ __volatile__ ("sync");
|
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+ local_irq_restore(flags);
|
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}
|
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|
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static void r4k_flush_cache_sigtramp(unsigned long addr)
|
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@@ -1144,6 +1210,17 @@
|
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* silly idea of putting something else there ...
|
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*/
|
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switch (current_cpu_data.cputype) {
|
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|
|
@ -94,7 +354,7 @@ Index: linux-2.6.22-rc6/arch/mips/mm/c-r4k.c
|
|||
case CPU_R4000PC:
|
||||
case CPU_R4000SC:
|
||||
case CPU_R4000MC:
|
||||
@@ -1174,6 +1202,15 @@
|
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@@ -1174,6 +1251,15 @@
|
||||
/* Default cache error handler for R4000 and R5000 family */
|
||||
set_uncached_handler (0x100, &except_vec2_generic, 0x80);
|
||||
|
||||
|
|
@ -110,7 +370,7 @@ Index: linux-2.6.22-rc6/arch/mips/mm/c-r4k.c
|
|||
probe_pcache();
|
||||
setup_scache();
|
||||
|
||||
@@ -1219,5 +1256,13 @@
|
||||
@@ -1219,5 +1305,13 @@
|
||||
build_clear_page();
|
||||
build_copy_page();
|
||||
local_r4k___flush_cache_all(NULL);
|
||||
|
|
@ -124,10 +384,10 @@ Index: linux-2.6.22-rc6/arch/mips/mm/c-r4k.c
|
|||
coherency_setup();
|
||||
+#endif
|
||||
}
|
||||
Index: linux-2.6.22-rc6/arch/mips/mm/tlbex.c
|
||||
Index: linux-2.6.22/arch/mips/mm/tlbex.c
|
||||
===================================================================
|
||||
--- linux-2.6.22-rc6.orig/arch/mips/mm/tlbex.c 2007-07-04 01:53:01.193328250 +0200
|
||||
+++ linux-2.6.22-rc6/arch/mips/mm/tlbex.c 2007-07-04 02:17:26.112880000 +0200
|
||||
--- linux-2.6.22.orig/arch/mips/mm/tlbex.c 2007-07-26 06:29:40.582055658 +0200
|
||||
+++ linux-2.6.22/arch/mips/mm/tlbex.c 2007-07-26 06:32:45.964620005 +0200
|
||||
@@ -1229,6 +1229,10 @@
|
||||
#endif
|
||||
}
|
||||
|
|
@ -139,22 +399,31 @@ Index: linux-2.6.22-rc6/arch/mips/mm/tlbex.c
|
|||
static void __init build_r4000_tlb_refill_handler(void)
|
||||
{
|
||||
u32 *p = tlb_handler;
|
||||
@@ -1243,6 +1247,11 @@
|
||||
@@ -1243,6 +1247,10 @@
|
||||
memset(relocs, 0, sizeof(relocs));
|
||||
memset(final_handler, 0, sizeof(final_handler));
|
||||
|
||||
+#ifdef CONFIG_BCM947XX
|
||||
+ if (current_cpu_data.cputype == CPU_BCM3302)
|
||||
+ i_nop(&p);
|
||||
+ i_nop(&p);
|
||||
+#endif
|
||||
+
|
||||
/*
|
||||
* create the plain linear handler
|
||||
*/
|
||||
Index: linux-2.6.22-rc6/include/asm-mips/r4kcache.h
|
||||
@@ -1736,6 +1744,9 @@
|
||||
memset(labels, 0, sizeof(labels));
|
||||
memset(relocs, 0, sizeof(relocs));
|
||||
|
||||
+#ifdef CONFIG_BCM947XX
|
||||
+ i_nop(&p);
|
||||
+#endif
|
||||
if (bcm1250_m3_war()) {
|
||||
i_MFC0(&p, K0, C0_BADVADDR);
|
||||
i_MFC0(&p, K1, C0_ENTRYHI);
|
||||
Index: linux-2.6.22/include/asm-mips/r4kcache.h
|
||||
===================================================================
|
||||
--- linux-2.6.22-rc6.orig/include/asm-mips/r4kcache.h 2007-07-04 01:52:47.840493750 +0200
|
||||
+++ linux-2.6.22-rc6/include/asm-mips/r4kcache.h 2007-07-04 01:53:01.673358250 +0200
|
||||
--- linux-2.6.22.orig/include/asm-mips/r4kcache.h 2007-07-26 06:29:25.085172538 +0200
|
||||
+++ linux-2.6.22/include/asm-mips/r4kcache.h 2007-07-26 06:29:40.938075943 +0200
|
||||
@@ -17,6 +17,20 @@
|
||||
#include <asm/cpu-features.h>
|
||||
#include <asm/mipsmtregs.h>
|
||||
|
|
@ -357,10 +626,10 @@ Index: linux-2.6.22-rc6/include/asm-mips/r4kcache.h
|
|||
+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
|
||||
|
||||
#endif /* _ASM_R4KCACHE_H */
|
||||
Index: linux-2.6.22-rc6/include/asm-mips/stackframe.h
|
||||
Index: linux-2.6.22/include/asm-mips/stackframe.h
|
||||
===================================================================
|
||||
--- linux-2.6.22-rc6.orig/include/asm-mips/stackframe.h 2007-07-04 01:52:47.852494500 +0200
|
||||
+++ linux-2.6.22-rc6/include/asm-mips/stackframe.h 2007-07-04 01:53:01.697359750 +0200
|
||||
--- linux-2.6.22.orig/include/asm-mips/stackframe.h 2007-07-26 06:29:25.093172994 +0200
|
||||
+++ linux-2.6.22/include/asm-mips/stackframe.h 2007-07-26 06:29:40.962077312 +0200
|
||||
@@ -350,6 +350,10 @@
|
||||
.macro RESTORE_SP_AND_RET
|
||||
LONG_L sp, PT_R29(sp)
|
||||
|
|
|
|||
Loading…
Reference in a new issue