2018-08-22 09:22:30 +00:00
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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2018-08-09 13:59:41 +00:00
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@@ -134,7 +134,7 @@
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#define QCA955X_PCI_CTRL_SIZE 0x100
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#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
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-#define QCA955X_GMAC_SIZE 0x40
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+#define QCA955X_GMAC_SIZE 0x64
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#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
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#define QCA955X_WMAC_SIZE 0x20000
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#define QCA955X_EHCI0_BASE 0x1b000000
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@@ -1269,7 +1269,11 @@
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*/
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#define QCA955X_GMAC_REG_ETH_CFG 0x00
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+#define QCA955X_GMAC_REG_SGMII_RESET 0x14
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#define QCA955X_GMAC_REG_SGMII_SERDES 0x18
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+#define QCA955X_GMAC_REG_MR_AN_CONTROL 0x1c
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+#define QCA955X_GMAC_REG_MR_AN_STATUS 0x20
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+#define QCA955X_GMAC_REG_SGMII_DEBUG 0x58
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#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
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#define QCA955X_ETH_CFG_MII_GE0 BIT(1)
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@@ -1291,6 +1295,18 @@
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#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
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#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
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+#define QCA955X_SGMII_RESET_RX_CLK_N_RESET 0x0
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+#define QCA955X_SGMII_RESET_RX_CLK_N BIT(0)
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+#define QCA955X_SGMII_RESET_TX_CLK_N BIT(1)
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+#define QCA955X_SGMII_RESET_RX_125M_N BIT(2)
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+#define QCA955X_SGMII_RESET_TX_125M_N BIT(3)
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+#define QCA955X_SGMII_RESET_HW_RX_125M_N BIT(4)
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+
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+#define QCA955X_MR_AN_CONTROL_PHY_RESET BIT(15)
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+#define QCA955X_MR_AN_CONTROL_AN_ENABLE BIT(12)
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+
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+#define QCA955X_MR_AN_STATUS_AN_ABILITY BIT(3)
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+
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#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
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#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
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#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
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