32 lines
1.2 KiB
Diff
32 lines
1.2 KiB
Diff
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From 67373874e07eb8c54ab27f8fe9998690e50b1e91 Mon Sep 17 00:00:00 2001
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From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Date: Thu, 6 Jun 2013 11:21:23 +0200
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Subject: [PATCH 021/203] arm: mvebu: armada-xp-db: ensure PCIe range is
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specified
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The ranges DT entry needed by the PCIe controller is defined at the
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SoC .dtsi level. However, some boards have a NOR flash, and to support
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it, they need to override the SoC-level ranges property to add an
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additional range. Since PCIe and NOR support came separately, some
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boards were not properly changed to include the PCIe range in their
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ranges property at the .dts level.
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This commit fixes those platforms.
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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---
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arch/arm/boot/dts/armada-xp-db.dts | 1 +
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1 file changed, 1 insertion(+)
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--- a/arch/arm/boot/dts/armada-xp-db.dts
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+++ b/arch/arm/boot/dts/armada-xp-db.dts
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@@ -31,6 +31,7 @@
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soc {
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ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
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+ 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
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0xf0000000 0 0xf0000000 0x1000000>; /* Device Bus, NOR 16MiB */
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internal-regs {
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